A charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a blocking layer and a preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology and proposes a charge-trapping flash memory device based on a hafnium-aluminum oxide composite dielectric barrier layer and a method for preparing the same. The device comprises a Si substrate, a tunneling layer of an Al2O3 thin film, a storage layer of a Si3N4 thin film, a barrier layer, and an Al electrode layer. The tunneling layer, storage layer, and barrier layer are sequentially deposited on the surface of the Si substrate, and an Al electrode layer is evaporated on the surface of the barrier layer. The barrier layer comprises a hafnium-aluminum oxide composite dielectric film formed by periodically overlapping deposition of HfO2 and Al2O3. The present invention forms HfO2-Al2O3 atomic stack structures with different Hf / Al element ratios through periodic overlapping deposition of HfO2 and Al2O3. This growth method is conducive to element diffusion and defect filling between Hf-O and Al-O. By controlling the Hf / Al element ratio, the dielectric constant of the barrier layer can be improved. Under the same operating voltage, the voltage acting on the tunneling layer is higher, and more charge is injected into / erased from the storage layer, which increases the storage window size of the device to a certain extent. The retention and fatigue characteristics are not deteriorated compared with devices with Al2O3 as the barrier layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer and a preparation method thereof. Background Art

[0002] Currently, the basic storage unit of 3D NAND Flash is a charge-trap memory, with an ONO-type structure: a tunneling layer of SiO2, a storage layer of Si3N4, and a barrier layer of SiO2. By varying the amount of charge in the storage layer, the threshold voltage of the charge-trap memory transistor is altered, enabling information storage. The SiO2 barrier layer, with its larger bandgap relative to the Si3N4 storage layer, prevents the trapped charge in the storage layer from leaking to the gate, causing charge loss.

[0003] However, with the development of Moore's Law, 3D NAND Flash has encountered certain problems in increasing device storage density while reducing size. First, as the size of the barrier layer decreases, the barrier layer's effectiveness in preventing the charge trapped in the storage layer from leaking to the gate decreases, which can easily cause problems such as gate leakage or back-gate injection, seriously affecting the reliability of the device. Secondly, as the size of the storage layer decreases, the number of traps that capture charge in the storage layer decreases. To a certain extent, this reduces the storage window size of the charge-trapping memory, affecting the improvement of the memory storage density and, in turn, the development of multi-value storage. Finally, as the size of the tunneling layer decreases, the quality of the tunneling layer film is likely to deteriorate. After multiple programming / erase operations, the charge frequently passes through the tunneling layer, which can easily cause damage to the tunneling layer film and reduce the reliability of the device.

[0004] To address the challenges and problems brought about by the reduction of memory size, one approach is to use high dielectric constant, i.e., high-k materials, instead of SiO2 and Si3N4 for charge trapping memory. According to the formula of equivalent oxide thickness EOT = (ε ox / ε k )×d kWith the same equivalent oxide thickness, high-k material films can be made physically thicker. Therefore, introducing high-k materials is an effective solution to a series of problems brought about by downsizing. Current research on the use of high-k materials in charge trap memories focuses on replacing SiO2 with Al2O3 as a barrier or tunneling layer, and replacing Si3N4 with single or composite high-k materials such as ZrO2, Al2O3, and TiO2 as a storage layer. Replacing SiO2 with Al2O3 as a barrier layer has shown some success, but the dielectric constant of Al2O3 remains relatively low, leaving significant room for improvement. Therefore, a charge trap memory with a high dielectric constant, a large memory window under certain programming / erase conditions, low backgate injection / leakage currents, excellent retention / fatigue performance, and high reliability is needed. Summary of the Invention

[0005] In view of this, the present invention proposes a charge trapping memory with high dielectric constant, large storage window under certain programming / erase operations, small back gate injection / leakage current, excellent retention / fatigue performance and high reliability, and a preparation method thereof.

[0006] The technical solution of the present invention is implemented as follows: On the one hand, the present invention provides a charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer, the memory comprising: a Si substrate, a tunneling layer, a storage layer, a barrier layer, and an Al electrode layer;

[0007] The tunneling layer, the storage layer, and the barrier layer are sequentially deposited on the surface of the Si substrate, and an Al electrode layer is evaporated on the surface of the barrier layer;

[0008] The tunneling layer is an Al2O3 film, the storage layer is a Si3N4 film, and the barrier layer is a hafnium aluminum oxide composite dielectric film formed by periodically overlapping and depositing HfO2 and Al2O3.

[0009] On the basis of the above technical solution, preferably, the hafnium aluminum oxide composite dielectric film is Hf m Al n O y , the atomic ratio m / n of Hf / Al is 1 / 8~2, and y is 1.5-2.

[0010] On the basis of the above technical solution, preferably, the barrier layer is Hf 0.11 Al 0.89 O 1.56 , Hf 0.33 Al 0.67 O 1.67 and Hf 0.67 Al 0.33 O 1.84 A type of composite dielectric film.

[0011] Based on the above technical solution, preferably, the thickness of the tunneling layer is 2-10 nm, the thickness of the storage layer is 5-20 nm, the thickness of the barrier layer is 10-100 nm, and the thickness of the Al electrode layer is 100 nm.

[0012] On the other hand, the present invention also provides a method for preparing a charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a blocking layer, comprising the following steps:

[0013] S1, clean the Si substrate and blow dry it with nitrogen;

[0014] S2, preparation of tunneling layer Al2O3 film: using atomic layer deposition method, trimethylaluminum and water as precursors, Al2O3 film is deposited on the surface of Si substrate at a deposition temperature of 100-300°C;

[0015] S2, preparation of the storage layer Si3N4 film: using the atomic layer deposition method, bis(diethylamino)silane and N2 plasma as precursors, the Si3N4 film is deposited on the surface of the tunneling layer at a deposition temperature of 300-400°C;

[0016] S3, barrier layer Hf m Al n O y Preparation of thin films: The precursors for HfO2 growth are hafnium tetradimethylamino and water, and the precursors for Al2O3 growth are trimethylaluminum and water; overlapping deposition growth of HfO2 and Al2O3 is a cycle, and multiple cycles are repeated to obtain Hf m Al n O y Thin films, deposition temperature is 200-300℃;

[0017] S4, high temperature annealing: placing the Si substrate with the tunneling layer, storage layer and barrier layer deposited thereon in a rapid thermal annealing furnace for annealing, then cooling and removing the substrate;

[0018] S5, Al electrode layer evaporation: Al electrode is evaporated on the surface of the barrier layer, and then the metal electrode is annealed.

[0019] On the basis of the above technical solution, preferably, in step S4, the annealing temperature is 400-800° C., and the annealing treatment is performed for 50-60 seconds in a N 2 atmosphere.

[0020] Based on the above technical solution, preferably, in step S5, the annealing temperature is 200-300° C. and the time is 20-30 min.

[0021] On the basis of the above technical solution, preferably, Hf is grown 0.11 Al 0.89 O1.56 When the composite dielectric film is grown, one layer of HfO2 and four layers of Al2O3 are grown by overlapping deposition, and the cycle is repeated 26 times.

[0022] On the basis of the above technical solution, preferably, Hf is grown 0.33 Al 0.67 O 1.67 When the composite dielectric film is formed, one cycle is composed of depositing and growing one layer of HfO2 and one layer of Al2O3, and the cycle is repeated for 65 cycles.

[0023] On the basis of the above technical solution, preferably, Hf is grown 0.67 Al 0.33 O 1.84 When the composite dielectric film is formed, the deposition growth of 4 layers of HfO2 and 1 layer of Al2O3 is considered as one cycle, and the cycle is repeated 26 times.

[0024] The charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer and the preparation method thereof of the present invention have the following beneficial effects compared to the prior art:

[0025] (1) The present invention proposes a hafnium aluminum oxide (Hf) with Al2O3 as a tunneling layer, Si3N4 as a storage layer, and Hf-O and Al-O overlapping deposition in different proportions. m Al n O y ) composite dielectric serves as a barrier layer for charge-trapping memory. Both the tunneling and barrier layers of this device utilize high-k dielectric materials, which improves the overall dielectric constant of the functional layer and enhances the gate's ability to control channel carriers. This increased dielectric constant of the barrier layer allows for a higher voltage applied to the tunneling layer at a given gate operating voltage, facilitating more charge FN tunneling into and out of the memory layer.

[0026] (2) In the growth and processing of the barrier layer film, the ALD film deposition process is adopted to form an HfO2-Al2O3 atomic stacking structure with different Hf / Al element ratios by periodically overlapping and depositing Hf-O and Al-O with different atomic sizes. This growth method is conducive to the diffusion of elements between Hf-O and Al-O and the filling of defects. The present invention can improve the dielectric constant of the barrier layer by controlling the Hf / Al element ratio. Under the same operating voltage, the voltage acting on the tunneling layer is higher, and more charges are injected into / erased from the storage layer, which increases the storage window size of the device to a certain extent. The retention and fatigue characteristics are not worse than those of devices with Al2O3 as the barrier layer. (3) In the charge capture memory structure of this patent, a hafnium aluminum oxide composite medium is used as the barrier layer, and then a high-temperature rapid thermal annealing process is performed to form Hf m Al n Oy Composite dielectric film. High temperature rapid thermal annealing treatment eliminates lattice damage during the growth of the barrier film, reduces the number of interface / body traps, and reduces the number of oxygen vacancies, which are beneficial to reducing the leakage channel of the barrier film and improving the performance of the barrier film in blocking charge leakage. At the same time, high temperature annealing is conducive to the fusion of Hf-O and Al-O elements to form Hf m Al n O y Composite dielectrics, compared to traditional Al2O3 or SiO2, this dielectric material retains a wide bandgap energy level while having a higher dielectric constant and a stable and dense lattice structure.

[0027] (4) This patent proposes to form Hf by periodically overlapping deposition of Hf-O and Al-O through ALD process m Al n O y Composite dielectric film is used as a barrier layer to prepare charge trapping memory. Controlling the Hf / Al element ratio can increase the memory window size of the device, and the retention and fatigue characteristics are not worse than those of devices with Al2O3 as a barrier layer. 0.33 Al 0.67 O 1.67 Devices using thin films as barrier layers have a large storage window and optimal fatigue and retention properties.

[0028] (5) The device fabrication process for the charge trapping memory device proposed in the present invention is simple. The thin film growth adopts the ALD process, and the growth process of the three functional layers can be completed in the same device. This helps to avoid the introduction of impurities on the film surface during the transfer process of film growth, which reduces the film quality and increases the adverse effects of leakage. At the same time, the continuous deposition of the three functional layers helps to reduce interface defects and improve device performance. In addition, the use of the ALD process to deposit the film ensures that the thickness and composition of the prepared film are uniform and stable, and the film quality is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 Prepare a flow chart for the memory of the present invention;

[0031] Figure 2 For different proportions of Hf m Aln O y Thin film bandgap diagram;

[0032] Figure 3 Figure 1 shows the storage window and retention performance of devices at different annealing temperatures. Figure a shows the storage window, and Figure b shows the retention performance.

[0033] Figure 4 For different proportions of Hf m Al n O y Storage window diagram of device with composite dielectric as barrier layer, a is Al2O3, b is Hf 0.11 Al 0.89 O 1.56 , c is Hf 0.33 Al 0.67 O 1.67 , d is Hf 0.67 Al 0.33 O 1.84 ;

[0034] Figure 5 For different proportions of Hf m Al n O y Comparison of storage window sizes of devices with composite dielectrics as barrier layers;

[0035] Figure 6 For different proportions of Hf m Al n O y Fatigue characteristics of devices with composite dielectrics as barrier layers, a is Al2O3, b is Hf 0.11 Al 0.89 O 1.56 , c is Hf 0.33 Al 0.67 O 1.67 , d is Hf 0.67 Al 0.33 O 1.84 ;

[0036] Figure 7 For different proportions of Hf m Al n O y The storage window of the device with composite dielectric as barrier layer changes with the number of programming / erasing times;

[0037] Figure 8 For different proportions of Hf m Al n O y The room temperature maintenance characteristics of the device with composite dielectric as barrier layer, a is Al2O3, b is Hf 0.11 Al 0.89 O 1.56 , c is Hf0.33 Al 0.67 O 1.67 , d is Hf 0.67 Al 0.33 O 1.84 ;

[0038] Figure 9 For different proportions of Hf m Al n O y 100℃ high temperature retention characteristics of devices with composite dielectrics as barrier layers; a is Al2O3, b is Hf 0.11 Al 0.89 O 1.56 , c is Hf 0.33 Al 0.67 O 1.67 , d is Hf 0.67 Al 0.33 O 1.84 . DETAILED DESCRIPTION

[0039] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] Example 1

[0041] The method for preparing a charge-trapping flash memory device based on a hafnium aluminum oxide composite dielectric as a blocking layer in this embodiment includes the following steps:

[0042] S1, cleaning Si substrate

[0043] A Si substrate with a resistivity of 1-10 ohms is used, and the Si wafer is cleaned using a standard RCA cleaning process to remove organic and inorganic impurities on the Si wafer surface and obtain a clean surface.

[0044] The cleaning method involves ultrasonic cleaning with acetone and then ethanol solutions. The wafer is then rinsed with deionized water and placed in a solution of 29% NH₄OH (mass fraction): 30% H₂O₂ (mass fraction): H₂O = 1:1:5 (volume ratio) at 80°C for 10 minutes. The wafer is then rinsed repeatedly with deionized water. The wafer is then placed in a solution of 37% HCl (mass fraction): 30% H₂O₂ (mass fraction): H₂O = 1:1:6 (volume ratio) at 80°C for 10 minutes. The wafer is then rinsed repeatedly with deionized water. The wafer, which has undergone two soakings, is then immersed in a 5% diluted HF solution (HF:H₂O = 10:70) for 1 minute to remove the natural oxide layer on the wafer surface. Finally, the wafer is rinsed repeatedly with deionized water to remove any residual HF solution on the wafer surface. The wafer is then blown dry with nitrogen.

[0045] S2, Preparation of tunneling layer Al2O3 film

[0046] Al2O3 thin films were grown using a thermal atomic layer deposition (TALD) system. A cleaned Si substrate was placed in the TALD chamber to grow a 3nm thick Al2O3 film. The Al2O3 growth temperature was 200°C, and the precursors used were trimethylaluminum (TMA) and water (H2O).

[0047] One Al2O3 growth cycle is (TMA-N2-H2O-N2), corresponding to a time of (0.02s-15s-0.015s-15s). The Al2O3 growth thickness in one cycle is 0.1nm, so a 3nm Al2O3 tunneling layer film requires 30 ALD growth cycles.

[0048] S3, preparation of storage layer Si3N4 film:

[0049] Si3N4 thin films were grown using plasma-enhanced atomic layer deposition (PEALD). A Si substrate with an Al2O3 tunneling layer was placed in a PEALD chamber to grow a 6nm Si3N4 film. The Si3N4 growth temperature was 300°C, and the precursors were bis(diethylamino)silane (BDEAS) and N2 plasma.

[0050] One Si3N4 growth cycle is (BDEAS-Ar-N2 Plasma-Ar), corresponding to a time of (0.2s-15s-15s-15s). The Si3N4 growth thickness in one cycle is 0.02nm, so a 6nm Si3N4 storage layer film requires 300 ALD growth cycles.

[0051] S4, barrier layer Hf 0.33 Al 0.67 O1.67 Film preparation

[0052] The HfO2 and Al2O3 thin films were grown using a thermal atomic layer deposition device (TALD). The Si substrate with the Al2O3 tunneling layer and Si3N4 storage layer was placed in the TALD chamber to grow 13nm HfO2 and Al2O3 thin films. 0.33 Al 0.67 O 1.67 The growth temperature of the film is 200℃.

[0053] The precursors for Al2O3 growth are trimethylaluminum (TMA) and water (H2O). One Al2O3 growth cycle is (TMA-N2-H2O-N2) with a duration of (0.02s-15s-0.015s-15s). The Al2O3 thickness grown in one cycle is 0.1nm.

[0054] The precursors for HfO2 growth are tetrakis(dimethylamino)hafnium (TDMAHf) and water (H2O). One HfO2 growth cycle is (TDMAHf-N2-H2O-N2) with a duration of (0.15s-15s-0.015s-15s). The thickness of the HfO2 grown in one cycle is 0.1nm.

[0055] Hf 0.33 Al 0.67 O 1.67 The growth cycle is {(TDMAHf-N2-H2O-N2)+(TMA-N2-H2O-N2)}×65, and the time is {(0.15s-15s-0.015s-15s)-(0.02s-15s-0.015s-15s)}×65, that is, the deposition and growth of one layer of HfO2 and one layer of Al2O3 is one cycle, and the cycle is 65 cycles.

[0056] S5, high temperature annealing

[0057] The device with three dielectric films, namely the tunneling layer, storage layer and barrier layer deposited by ALD, was placed in a rapid thermal annealing furnace, annealed at 800°C for 60s, and then naturally cooled to room temperature (20-30°C) and taken out.

[0058] S6, Al electrode layer evaporation

[0059] The memory device of the present invention has no special requirements for the preparation of metal electrodes. This embodiment only provides a method for evaporating a circular Al electrode with a diameter of 100 μm and a thickness of 100 nm.

[0060] First, AZ5214 photoresist was spin-coated on the device surface at 4000 rpm for 60 seconds and baked at 110°C for 10 minutes. A 100 μm diameter circular electrode mask was then used for exposure on a photolithography machine for 5.5 seconds and development for 70 seconds. Excess developer was removed with deionized water, and the photolithographic device was then deposited with a 100 nm thick Al electrode in a thermal evaporator. After deposition, excess photoresist was removed with acetone. Finally, the device with the Al electrode was annealed at 300°C for 20 minutes in an annealing furnace to improve the contact properties between the metal Al electrode and the dielectric.

[0061] Example 2

[0062] The difference between Example 2 and Example 1 is that the barrier layer is Hf 0.11 Al 0.89 O 1.56 film.

[0063] Hf 0.11 Al 0.89 O 1.56 The growth cycle is: {(TDMAHf-N2-H2O-N2) + (TMA-N2-H2O-N2) × 4} × 26, and the time is {(0.15s-15s-0.015s-15s)-(0.02s-15s-0.015s-15s) × 4} × 26. That is, the deposition and growth of one layer of HfO2 and four layers of Al2O3 is one cycle, and the cycle is repeated 26 times.

[0064] Example 3

[0065] The difference between Example 3 and Example 1 is that the barrier layer is Hf 0.67 Al 0.33 O 1.84 film.

[0066] Hf 0.67 Al 0.33 O 1.84 The growth cycle is: {(TDMAHf-N2-H2O-N2) × 4 + (TMA-N2-H2O-N2)} × 26, and the time is {(0.15s-15s-0.015s-15s) × 4 - (0.02s-15s-0.015s-15s)} × 26. That is, the deposition and growth of four layers of HfO2 and one layer of Al2O3 constitutes one cycle, and the cycle is repeated 26 times.

[0067] Example 4

[0068] The difference between Example 4 and Example 1 is that the annealing temperature is 400° C., and the rest of the contents are the same.

[0069] Example 5

[0070] The method for preparing a charge-trapping flash memory device based on a hafnium aluminum oxide composite dielectric as a blocking layer in this embodiment includes the following steps:

[0071] S1, cleaning the Si substrate, the method is the same as that in Example 1.

[0072] S2, Preparation of tunneling layer Al2O3 film

[0073] The Al2O3 film growth precursor is the same as that in Example 1, with a thickness of 2 nm and a growth temperature of 100°C.

[0074] The Al2O3 growth cycle is (TMA-N2-H2O-N2) × 20, corresponding to a time of (0.02s-15s-0.015s-15s) × 20. The Al2O3 growth thickness in one cycle is 0.1nm, so a 2nm Al2O3 tunneling layer film requires 20 ALD cycles.

[0075] S3, Preparation of storage layer Si3N4 film

[0076] The Si3N4 thin film growth precursor is the same as that in Example 1, with a thickness of 5 nm and a Si3N4 growth temperature of 350°C.

[0077] The Si3N4 growth cycle is (BDEAS-Ar-N2 Plasma-Ar) × 250, corresponding to a time of (0.2s-15s-15s-15s) × 250. The Si3N4 growth thickness in one cycle is 0.02nm, so a 5nm Si3N4 storage layer film requires 250 ALD cycles.

[0078] S4, barrier layer Hf 0.33 Al 0.67 O 1.67 Film preparation

[0079] The precursors and growth cycles of HfO2 and Al2O3 were the same as those in Example 1. 0.33 Al 0.67 O 1.67 The film thickness is 10 nm and the growth temperature is 250 °C.

[0080] Hf 0.33 Al 0.67 O 1.67 The growth cycle is {(TDMAHf-N2-H2O-N2)+(TMA-N2-H2O-N2)}×50, and the time is {(0.15s-15s-0.015s-15s)-(0.02s-15s-0.015s-15s)}×50, that is, the deposition and growth of one layer of HfO2 and one layer of Al2O3 is one cycle, and the cycle is 50 cycles.

[0081] S5, high temperature annealing

[0082] The device with three dielectric films, namely the tunneling layer, storage layer and barrier layer, deposited by ALD, was placed in a rapid thermal annealing furnace, annealed at 600°C for 50s, and then naturally cooled to room temperature (20-30°C) and taken out.

[0083] S6, Al electrode layer evaporation, the method is the same as that in Example 1.

[0084] The device with the evaporated Al electrode was annealed in an annealing furnace at 200°C for 30 minutes to improve the contact characteristics between the metal Al electrode and the dielectric.

[0085] Example 6

[0086] The method for preparing a charge-trapping flash memory device based on a hafnium aluminum oxide composite dielectric as a blocking layer in this embodiment includes the following steps:

[0087] S1, cleaning the Si substrate, the method is the same as that in Example 1.

[0088] S2, preparation of tunneling layer Al2O3 film: the Al2O3 film growth precursor is the same as that in Example 1, the thickness is 10 nm, and the growth temperature is 300°C.

[0089] The Al2O3 growth cycle is (TMA-N2-H2O-N2) × 100, corresponding to a time of (0.02s-15s-0.015s-15s) × 100. The Al2O3 growth thickness in one cycle is 0.1nm, so a 10nm Al2O3 tunneling layer film requires 100 ALD cycles.

[0090] S3, Preparation of storage layer Si3N4 film

[0091] The Si3N4 thin film growth precursor is the same as that in Example 1, with a thickness of 20 nm and a Si3N4 growth temperature of 400°C.

[0092] The Si3N4 growth cycle is (BDEAS-Ar-N2 Plasma-Ar) × 1000, corresponding to a time of (0.2s-15s-15s-15s) × 1000. The Si3N4 growth thickness in one cycle is 0.02nm, so a 20nm Si3N4 storage layer film requires 1000 ALD growth cycles.

[0093] S4, barrier layer Hf 0.33 Al 0.67 O 1.67 Film preparation

[0094] The precursors and growth cycles of HfO2 and Al2O3 were the same as those in Example 1. 0.33Al 0.67 O 1.67 The film thickness is 100 nm and the growth temperature is 300 °C.

[0095] Hf 0.33 Al 0.67 O 1.67 The growth cycle is {(TDMAHf-N2-H2O-N2)+(TMA-N2-H2O-N2)}×500, and the time is {(0.15s-15s-0.015s-15s)-(0.02s-15s-0.015s-15s)}×500, that is, the deposition and growth of one layer of HfO2 and one layer of Al2O3 is one cycle, and the cycle is 500 cycles.

[0096] S5, high temperature annealing

[0097] The device with three dielectric films, namely the tunneling layer, storage layer and barrier layer deposited by ALD, was placed in a rapid thermal annealing furnace, annealed at 800°C for 60s, and then naturally cooled to room temperature (20-30°C) and taken out.

[0098] S6, Al electrode layer evaporation, the method is the same as that in Example 1.

[0099] The device with the evaporated Al electrode was annealed in an annealing furnace at 250° C. for 25 minutes to improve the contact characteristics between the metal Al electrode and the dielectric.

[0100] Changing the thickness of the three films in Examples 5 and 6 has no effect on the Hf and Al atomic ratios mentioned in the patent. However, varying the thickness of the three films does affect the overall storage performance of the device. Reducing the film thickness in Example 5 results in a smaller device storage window, worsening fatigue and retention characteristics. Increasing the film thickness in Example 6 improves the device's fatigue and retention characteristics, but reduces programming / erase speeds and increases the required programming / erase voltage.

[0101] Comparative Example 1

[0102] The difference between Comparative Example 1 and Example 1 is that the barrier layer is an Al2O3 film, and the rest of the contents are the same as Example 1.

[0103] The Al2O3 growth cycle is: (TMA-N2-H2O-N2)×130, and the time is (0.02s-15s-0.015s-15s)×130, that is, 130 layers of Al2O3 are cyclically deposited and grown.

[0104] Comparative Example 2

[0105] The difference between Comparative Example 2 and Example 1 is that step S5, the high-temperature annealing step, is missing, and the rest of the contents are the same as Example 1.

[0106] XPS spectroscopy was used to analyze the O 1s The inelastic peak loss is used to calculate the film band gap width. The results are shown in Figure 2 As shown in the figure, the band gap of ALD-grown Al2O3 is calculated to be 8.56eV by XPS test, and the Hf containing 11% Hf element 0.11 Al 0.89 O 1.56 The band gap of the medium is 8.42eV, and the Hf containing 33% Hf element 0.33 Al 0.67 O 1.67 The band gap of the medium is 8.08eV. As the proportion of Hf element increases, Hf m Al n O y The band gap of the film is reduced, which is consistent with the theory, but Hf 0.33 Al 0.67 O 1.67 The band gap of the film is also greater than 8eV, which means that the ALD-grown Hf m Al n O y The film has a large bandgap.

[0107] From the storage window curve (see Figure 4 ) It can be seen that the memory window of the device with Al2O3 as the barrier layer reaches 7.5V at a ±10V program / erase operating voltage. As the Hf / Al element ratio increases, the device memory window size increases significantly and finally saturates, indicating that the increase in Hf element content has a significant effect on improving the device memory window. When the Hf element content reaches 33%, the device memory window size reaches 8.8V at a ±10V program / erase operating voltage, which is a 17.3% improvement over the device with Al2O3 as the barrier layer. The memory window reaches 10.7V at a ±15V program / erase operating voltage, which is a 33.75% improvement compared to the device with Al2O3 as the barrier layer (8V memory window @ ±15V operating voltage). This is because the patent proposes using a hafnium aluminum oxide composite dielectric as a barrier layer. By introducing the Hf element, the dielectric constant of the barrier layer is increased. At the same operating voltage, the voltage acting on the tunneling layer is higher, more charge is injected into / erased from the memory layer, and the device memory window size is improved to a certain extent.

[0108] Figure 5 Shows different Hf m Al n O y The trend of the storage window of the device with the operating voltage as the film is used as a barrier layer. 0.11 Al 0.89 O1.56 The storage window size of the device as a barrier layer changes little with the operating voltage. As the proportion of Hf elements increases, the Hf 0.33 Al 0.67 O 1.67 or Hf 0.67 Al 0.33 O 1.84 For devices with a blocking layer, the storage window size increases significantly with voltage, and the slope of the curve increases. This facilitates the device's multi-value storage function, controlling the amount of charge in the storage layer by applying different operating voltages.

[0109] Figure 6 It can be seen that the charge trapping memory of this patent has excellent fatigue performance. With the introduction of a small amount of Hf element, that is, when the Hf / Al element ratio is low, the Hf 0.11 Al 0.89 O 1.56 or Hf 0.33 Al 0.67 O 1.67 Compared with the device with Al2O3 as the barrier layer, the fatigue properties of the three devices are better. After 5000 times of ±10V / 1s pulse voltage operation, the program / erase flat band voltage changes little compared with the pre-operation and there is no significant change. 0.67 Al 0.33 O 1.84 The fatigue characteristics of the device with a blocking layer are poor. After 5000 ±10V / 1s pulse voltage operations, its programming / erasing flat band voltage changes significantly from that before the operation, and the storage window is greatly reduced. Therefore, in order to obtain better fatigue characteristics, it is necessary to control the blocking layer Hf m Al n O y The Hf element content of the film is less than 33%.

[0110] Figure 7 Display different Hf m Al n O y The storage window of the device with thin film as the barrier layer changes with the number of pulse voltages. 0.67 Al 0.33 O 1.84 The storage window of the thin film as a barrier layer device is severely reduced. This is because after multiple pulse voltage operations, the functional layer film is damaged. Therefore, the barrier layer Hf m Al n O y The Hf element in the film is below 33%, which can better ensure that the device can withstand more pulse voltage operations.

[0111] Figure 8 and 9 To maintain device performance, Figure 8 At room temperature, Figure 9 Combining the two to maintain the performance curve, Hf 0.33 Al 0.67 O 1.67 As a barrier layer, the film maintains the best performance under room temperature and high temperature conditions. Under room temperature conditions, the charge loss is expected to be the least after 10 years, which is 9.04%. Under high temperature conditions of 100℃, the charge loss is expected to be 12.44% after 10 years, which is the best reliability. This is because Hf 0.33 Al 0.67 O 1.67 The film adopts an atomic stacking structure during the growth process, that is, a cycle of Hf-O film is grown and then a cycle of Al-O film is grown. This step is repeated to prepare the barrier layer Hf 0.33 Al 0.67 O 1.67 This growth method is conducive to the mixing of Hf-O and Al-O elements. After high temperature annealing, it reduces the defects in the film, improves the quality of the barrier film, and reduces the current leakage channel. Therefore, Hf 0.33 Al 0.67 O 1.67 Devices with thin films as barrier layers retain performance better.

[0112] like Figure 3 As shown, compared with Comparative Example 2, the device that underwent high-temperature rapid thermal annealing had a larger storage window and maintained the best performance (see Examples 4 and 5). This is because the high temperature repairs the lattice defects generated during the film growth process, and the Hf-O and Al-O in the barrier layer film are better mixed at high temperature, reducing defects within the film, reducing current leakage channels, and better blocking charge leakage in the storage layer. Therefore, simultaneous high-temperature rapid thermal annealing of the device's three functional layers (tunnel layer, storage layer, and barrier layer) can improve film quality and further enhance the device's storage performance.

[0113] The device without annealing (Comparative Example 2) has the largest storage window. As the annealing temperature increases, the device storage window first becomes smaller and then increases (see Figure a). In the retention characteristic curve, the device without annealing has the worst retention performance, especially in the programmed state, where the charge loss is the largest over time (see Figure b). As the annealing temperature increases, the device retention performance improves. This is because without annealing, the barrier layer Hf m Al n O yThe interface traps of the film are more charged, and these traps store a part of the charge, making the storage window of the device larger. However, the retention characteristic curve shows that the energy level of these interface traps is shallow, and the stored charge is very easy to leak, resulting in the loss of stored charge. Therefore, high temperature annealing can improve the barrier layer Hf m Al n O y The film's lattice damage is reduced, the number of shallow interface traps is reduced, and its barrier effect is improved. At the same time, the three functional layers of the device are annealed simultaneously, which is beneficial to improving the film interface contact characteristics and, to a certain extent, improving the reliability of the memory device.

[0114] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a blocking layer, characterized by: The memory comprises: a Si substrate, a tunneling layer, a storage layer, a barrier layer and an Al electrode layer; The tunneling layer, the storage layer, and the barrier layer are sequentially deposited on the surface of the Si substrate, and an Al electrode layer is evaporated on the surface of the barrier layer; The tunneling layer is an Al2O3 film, the storage layer is a Si3N4 film, and the barrier layer is a hafnium aluminum oxide composite dielectric film formed by periodically overlapping deposition and growth of HfO2 and Al2O3; The hafnium aluminum oxide composite dielectric film is Hf m Al n O y , the atomic ratio m / n of Hf / Al is 1 / 8~2, and y is 1.5-2.

2. The charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 1, characterized in that: The barrier layer is Hf 0.11 Al 0.89 O 1.56 , Hf 0.33 Al 0.67 O 1.67 and Hf 0.67 Al 0.33 O 1.84 A type of composite dielectric film.

3. The charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 1, characterized in that: The thickness of the tunneling layer is 2-10 nm, the thickness of the storage layer is 5-20 nm, the thickness of the barrier layer is 10-100 nm, and the thickness of the Al electrode layer is 100 nm.

4. The method for preparing a charge-trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 2, wherein: The following steps are involved: S1, clean the Si substrate and blow dry it with nitrogen; S2, preparation of tunneling layer Al2O3 film: using atomic layer deposition method, trimethylaluminum and water as precursors, Al2O3 film is deposited on the surface of Si substrate at a deposition temperature of 100-300°C; S2, preparation of the storage layer Si3N4 film: using the atomic layer deposition method, bis(diethylamino)silane and N2 plasma as precursors, the Si3N4 film is deposited on the surface of the tunneling layer at a deposition temperature of 300-400°C; S3, barrier layer Hf m Al n O y Preparation of thin films: The precursors for HfO2 growth are hafnium tetradimethylamino and water, and the precursors for Al2O3 growth are trimethylaluminum and water; overlapping deposition growth of HfO2 and Al2O3 is a cycle, and multiple cycles are repeated to obtain Hf m Al n O y Thin films, deposition temperature is 200-300℃; S4, high temperature annealing: placing the Si substrate with the tunneling layer, storage layer and barrier layer deposited thereon in a rapid thermal annealing furnace for annealing, then cooling and removing the substrate; S5, Al electrode layer evaporation: Al electrode is evaporated on the surface of the barrier layer, and then the metal electrode is annealed.

5. The method for preparing a charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 4, characterized in that: In step S4, the annealing temperature is 400-800° C., and the annealing treatment is performed for 50-60 seconds in a N 2 atmosphere.

6. The method for preparing a charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 4, characterized in that: In step S5, the annealing temperature is 200-300° C. and the time is 20-30 minutes.

7. The method for preparing a charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 4, characterized in that: Growth Hf 0.11 Al 0.89 O 1.56 When the composite dielectric film is grown, one layer of HfO2 and four layers of Al2O3 are grown by overlapping deposition, and the cycle is repeated 26 times.

8. The method for preparing a charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 4, characterized in that: Growth Hf 0.33 Al 0.67 O 1.67 When the composite dielectric film is formed, one cycle is composed of depositing and growing one layer of HfO2 and one layer of Al2O3, and the cycle is repeated for 65 cycles.

9. The method for preparing a charge trapping flash memory based on a hafnium aluminum oxide composite dielectric as a barrier layer according to claim 4, characterized in that: Growth Hf 0.67 Al 0.33 O 1.84 When the composite dielectric film is formed, the deposition growth of 4 layers of HfO2 and 1 layer of Al2O3 is considered as one cycle, and the cycle is repeated 26 times.

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