Gate-source, gate-drain, short-gate-length fully self-aligned method and its applications

Abstract

The application discloses a full self-alignment method of gate source, gate drain and short gate length and application thereof. The preparation method of the semiconductor radio frequency device comprises the following steps: forming a support structure for defining the gate source, the gate drain and the short gate length on an epitaxial wafer by using the full self-alignment method of the gate source, the gate drain and the short gate length, and manufacturing a source electrode, a drain electrode and a gate electrode matched with the epitaxial wafer, wherein the source electrode and the drain electrode are respectively located on two sides of the support structure, and the gate electrode is located on the support structure. The full self-alignment method provided by the embodiment of the application has a simple working process, and the source, the gate and the drain can be accurately self-aligned only by using the support structure formed by photoetching and film plating processes.

Description

Technical Field

[0001] This invention specifically relates to a fully self-aligned method for gate source, gate drain, and short gate length, and its application, belonging to the field of micro-nano manufacturing technology. Background Technology

[0002] In the manufacturing process of GaN HEMT RF devices, to improve device performance, the devices need to be scaled down to a smaller size. Most devices use a T-type gate, with a gate cap of approximately 300nm~800nm ​​and a gate root typically below 150nm or even below 100nm. Furthermore, to improve device performance, different dimensions of the gate-source and gate-drain spacing must be designed. This poses a significant challenge to the alignment of the gate and source / drain electrodes. Both ultraviolet lithography and electron beam lithography inevitably introduce errors during alignment and overlay, and these errors can have a significant impact on device performance when the device is made smaller.

[0003] To address the overlay misalignment issue, a small number of researchers have explored self-aligned processes. In 2013, HRL Laboratories in the United States fabricated a self-aligned RF GaN HEMT, the structure of which is shown below. Figure 1a , Figure 1b As shown. The GaN RF device based on self-aligned gate-end technology, fabricated by the Hong Kong University of Science and Technology in 2013, has the following process flow and device structure: Figure 2 As shown.

[0004] Current self-aligned technologies primarily focus on making the gate shorter and more stable, while a complete self-aligned process for the gate-source, gate-drain, and short gate lengths remains undeveloped. The self-aligned gate-end process described above can define the gate length without relying on electron beam lithography, and the gate and source / drain are self-aligned. However, its gate length is defined by wet etching (reaching 210nm in the paper), making further reduction difficult, and it's challenging to reproduce stably in actual production. Furthermore, the absence of a gate channel region between the gate-source and gate-drain electrodes negatively impacts the device's breakdown voltage and increases parasitic capacitance. Summary of the Invention

[0005] The main objective of this invention is to provide a fully self-aligned method for gate source, gate drain, and short gate length, and its application, thereby overcoming the shortcomings of the prior art.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0007] The first aspect of this invention provides a fully self-aligned method for a gate source, gate drain, and short gate length, comprising:

[0008] A first support material is formed on the surface of the epitaxial wafer;

[0009] A patterned first mask is formed on the surface of the first support material layer, and the first support material not covered by the first mask is removed, thereby forming a first support layer. The first support layer has a first sidewall and a second sidewall disposed opposite to each other in a selected direction.

[0010] Remove the first mask and form a continuous second support material on the surface of the epitaxial wafer and the first support layer;

[0011] The second support material distributed on the first sidewall of the first support layer is removed by etching, and the remaining second support material serves as the second support layer. The second support layer has a third sidewall on the side facing away from the first sidewall along a selected direction.

[0012] A continuous third support material is formed on the surfaces of the epitaxial wafer, the first support layer, and the second support layer;

[0013] The third support material distributed on the third sidewall of the second support layer and the second sidewall of the first support layer is removed by etching. The remaining third support material on the third sidewall of the second support layer serves as the third support layer, and the remaining third support material on the second sidewall of the first support layer serves as the fourth support layer. The first support layer, the second support layer, the third support layer, and the fourth support layer together form a support structure.

[0014] The regions on both sides of the epitaxial wafer located on the support structure are respectively the source region and the drain region. The region where the second support layer is located is the gate root region of the gate. The region where the third support layer is located, and the regions where the third support layer and the first support layer are located, correspond to the gate source region and the other corresponds to the gate drain region. The first support material, the third support material and the second support material have corrosion selectivity.

[0015] A second aspect of the present invention provides a method for fabricating a semiconductor radio frequency device, comprising: forming a support structure defining the gate source, gate drain, and short gate length on an epitaxial wafer using the aforementioned gate-source, gate-drain, and short gate length self-alignment method; and fabricating a source, drain, and gate that match the epitaxial wafer, wherein the source and drain are respectively located on both sides of the support structure, and the gate is located on the support structure.

[0016] Compared with the prior art, the advantages of the present invention include: the fully self-aligned method provided by the embodiments of the present invention has a simple workflow, and the source, gate and drain can be accurately self-aligned by only the support structure formed by photolithography, coating and other processes. Attached Figure Description

[0017] Figure 1a , Figure 1bThis is a schematic diagram of the structure of a self-aligned radio frequency GaN HEMT fabricated by HRL Laboratories in the United States in 2013;

[0018] Figure 2 This is a process flow diagram of GaN RF devices based on self-aligned gate-end technology;

[0019] Figure 3 This is a schematic diagram of the process flow of a fully self-aligned technology provided in a typical embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the device spacing obtained by the fully self-aligned technology in a typical embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the process flow for different ohmic contact processes in a typical embodiment of the present invention. Detailed Implementation

[0022] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0023] In radio frequency devices fabricated using either electron beam lithography or self-aligned techniques, the distances between the gate and the source / drain electrodes are defined by the overlay between two lithography steps. When device dimensions shrink to 1.5 μm or even less than 1 μm, the overlay error of the lithography machine will significantly impact device performance (an overlay accuracy deviation of 150 nm can potentially cause a 300 nm positional shift in the gate). Therefore, accurately defining the gate length, gate-source spacing, and gate-drain spacing of small-size HEMTs is crucial. In the fabrication process of small-size devices, lithography inevitably leads to overlay errors. This invention uses sidewall technology to define the dimensions of each part, thus avoiding the problem of overlay errors.

[0024] The first aspect of this invention provides a fully self-aligned method for a gate source, gate drain, and short gate length, comprising:

[0025] A first support material is formed on the surface of the epitaxial wafer;

[0026] A patterned first mask is formed on the surface of the first support material layer, and the first support material not covered by the first mask is removed, thereby forming a first support layer. The first support layer has a first sidewall and a second sidewall disposed opposite to each other in a selected direction.

[0027] Remove the first mask and form a continuous second support material on the surface of the epitaxial wafer and the first support layer;

[0028] The second support material distributed on the first sidewall of the first support layer is removed by etching, and the remaining second support material serves as the second support layer. The second support layer has a third sidewall on the side facing away from the first sidewall along a selected direction.

[0029] A continuous third support material is formed on the surfaces of the epitaxial wafer, the first support layer, and the second support layer;

[0030] The third support material distributed on the third sidewall of the second support layer and the second sidewall of the first support layer is removed by etching. The remaining third support material on the third sidewall of the second support layer serves as the third support layer, and the remaining third support material on the second sidewall of the first support layer serves as the fourth support layer. The first support layer, the second support layer, the third support layer, and the fourth support layer together form a support structure.

[0031] The regions on both sides of the epitaxial wafer located on the support structure are respectively the source region and the drain region. The region where the second support layer is located is the gate root region of the gate. The region where the third support layer is located, and the regions where the third support layer and the first support layer are located, correspond to the gate source region and the other corresponds to the gate drain region. The first support material, the third support material and the second support material have corrosion selectivity.

[0032] Furthermore, the fully self-aligned method for the gate source, gate drain, and short gate length specifically includes:

[0033] The second support material is etched using an anisotropic etching process until the surface of the epitaxial wafer is reached, thereby removing the second support material distributed on the first sidewall and the second sidewall of the first support layer.

[0034] A second mask is applied to the surface of the second support material remaining on the first sidewall of the first support layer, and the second support material distributed on the second sidewall of the first support layer is removed, thereby forming the second support layer;

[0035] And, remove the second mask covering the second support layer.

[0036] Furthermore, the fully self-aligned method for the gate source, gate drain, and short gate length specifically includes:

[0037] The third support material is etched using an anisotropic etching process until the surface of the epitaxial wafer is reached, thereby removing the third support material distributed on the third sidewall of the second support layer and the second sidewall of the first support layer, and forming the third support layer and the fourth support layer.

[0038] Furthermore, the first and second sidewalls of the first support layer are perpendicular to the surface of the epitaxial sheet.

[0039] Furthermore, the first and third support materials are insulating materials, and the second support material is either an insulating material or a metallic material. For example, the insulating material may be silicon oxide or silicon nitride, etc.

[0040] Furthermore, the thickness of the second support layer in the selected direction is the gate length, and one of the thicknesses of the third support layer in the selected direction, the fourth support layer, and the first support layer in the selected direction is the gate-source spacing, and the other is the gate-drain spacing.

[0041] A second aspect of the present invention provides a method for fabricating a semiconductor radio frequency device, comprising: forming a support structure defining the gate source, gate drain, and short gate length on an epitaxial wafer using the aforementioned gate-source, gate-drain, and short gate length self-alignment method; and fabricating a source, drain, and gate that match the epitaxial wafer, wherein the source and drain are respectively located on both sides of the support structure, and the gate is located on the support structure.

[0042] In a more specific embodiment, the second support material is a metallic material, the second support layer serves as the gate root, and the preparation method further includes:

[0043] Metal is deposited on the top surface of the epitaxial wafer and the support structure, and the metal on the epitaxial wafer forms an ohmic contact with the epitaxial wafer. The metal on the top surface of the support structure serves as a gate cap, which is electrically connected to the gate root. The metals on both sides of the support structure serve as the source and drain, respectively.

[0044] In another more specific embodiment, the method for fabricating the semiconductor radio frequency device specifically includes:

[0045] An ohmic contact layer is formed in the region on both sides of the support structure of the epitaxial wafer;

[0046] Remove the second support layer;

[0047] A gate metal is deposited on the top surface of the support structure and between the first support layer and the third support layer. The gate metal located between the first support layer and the third support layer serves as the gate root, and the gate metal located on the top surface of the support structure serves as the gate cap. The gate cap and the gate root are electrically connected to form a gate.

[0048] Ohmic metal is deposited on the ohmic contact layer as the source and drain.

[0049] Furthermore, the method for fabricating the semiconductor radio frequency device specifically includes:

[0050] An ohmic contact layer is formed in the surface portion of the epitaxial wafer located on both sides of the support structure by ion implantation.

[0051] Alternatively, the surface portion of the epitaxial wafer located on both sides of the support structure can be etched away, and then an ohmic contact layer can be epitaxially grown on both sides of the support structure.

[0052] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor epitaxy, photolithography, etching, metal deposition, ion implantation processes and equipment used in the embodiments of the present invention can all be known in the art, and the photoresist, epitaxial structure materials, electrode materials, etc. used can also be known in the art.

[0053] Example 1

[0054] Please see Figure 3 A method for fabricating a GaN-based HEMT radio frequency device includes the following steps:

[0055] 1) The fully automated alignment technology process includes:

[0056] (a) Provide a HEMT wafer containing an AlGaN / GaN heterojunction.

[0057] (b) A layer of SiO2 is deposited on the surface of the HEMT wafer as a first support material.

[0058] (c) A patterned photoresist or metal mask (e.g., a Ni mask, which can achieve better sidewall steepness) is formed on the first support material as the first mask.

[0059] (d) Etching away the first support material not covered by the first mask, and forming a steep sidewall with the remaining first support material, and removing the first mask, with the remaining first support material serving as a first support layer, the first support layer having a first sidewall and a second sidewall disposed opposite to each other along a selected direction, the selected direction being the lateral direction of the HEMT wafer.

[0060] (e) A layer of W metal is deposited on the surface of the HEMT wafer and the first support layer as a second support material using CVD (chemical vapor deposition) process, and the W metal is conformally covered to the first sidewall and the second sidewall of the first support layer.

[0061] (f) The second support material is etched using an anisotropic etching process until the surface of the HEMT wafer is reached, so as to remove the second support material covering the surface of the HEMT wafer and the top surface of the first support layer, while the second support material covering the first sidewall and the second sidewall of the first support layer is retained.

[0062] (g) By photolithography, a second support material located on the first sidewall of the first support layer is covered by photoresist or other materials as a second mask. The second support material covered on the second sidewall of the first support layer is removed by a wet etching process. After that, the second mask is removed. The second support material left on the first sidewall of the first support layer is used as the second support layer. The side of the second support layer facing away from the first sidewall of the first support layer in a selected direction is the third sidewall.

[0063] (h) A continuous SiO2 layer is deposited on the surface of the HEMT wafer, the first support layer, and the second support layer as a third support material.

[0064] (i) An anisotropic etching process is used to etch the third support material until the surface of the HEMT wafer is reached, so as to remove the third support material covering the surface of the HEMT wafer and the top surface of the first support layer and the second support layer, while the third support material covering the second sidewall of the first support layer and the third sidewall of the second support layer is retained. The third support material remaining on the third sidewall of the second support layer serves as the third support layer, and the third support material remaining on the second sidewall of the first support layer serves as the fourth support layer. The first support layer, the second support layer, the third support layer, and the fourth support layer together form a support structure.

[0065] In this design, the regions on either side of the support structure of the HEMT wafer serve as the source and drain regions, respectively. The region containing the second support layer serves as the gate root region of the gate. The region containing the third support layer, and one of the regions containing the third support layer and the first support layer, corresponds to the gate-source region, and the other corresponds to the gate-drain region. That is, as shown... Figure 4 As shown, in the selected direction, the thickness of the second support layer is the gate length Lg, the thickness of the third support layer is the gate-source distance Lgs, and the sum of the thicknesses of the fourth support layer and the first support layer in the selected direction is the gate-drain distance Lgd.

[0066] 2) such as Figure 5 As shown, the process flow for fabricating ohmic contacts includes:

[0067] (j) Low-temperature alloy ohmic contact: Metal is deposited directly on the surface of the HEMT wafer and the top surface of the support structure, and the metal distributed on the surface of the HEMT wafer is subjected to low-temperature annealing so that the metal and the HEMT wafer form an ohmic contact. The metal on the surface of the HEMT wafer located on both sides of the support structure serves as the source and drain, respectively. The metal distributed on the top of the support structure serves as the gate cap, and the second support layer serves as the gate root. The gate cap and the gate root are in electrical contact and together form the gate.

[0068] Example 2

[0069] The fabrication method of a GaN-based HEMT RF device in Example 2 is exactly the same as the fully self-aligned technology process in Example 1. The main difference between the two is the process flow for fabricating the ohmic contact.

[0070] The ohmic contact fabrication process in this embodiment employs ion implantation to form the ohmic contact layer, specifically including:

[0071] (j) Using the support structure as a mask, ion implantation is performed on the source and drain regions (regions on both sides of the support structure) of the HEMT wafer to transform the surface portion of the HEMT wafer in the source and drain regions into an ohmic contact layer.

[0072] (k) The second support layer is removed by wet etching, and the source and drain regions of the HEMT wafer are annealed and activated.

[0073] (l) Photolithography defines the position of the gate cap, and gate metal is deposited between the first support layer and the third support layer and on the top surface of the support structure. The gate metal between the first support layer and the third support layer is used as the gate root, and the gate metal on the top surface of the support structure is used as the gate cap.

[0074] (m) Photolithography defines the location of the ohmic contacts, and ohmic metal is deposited in the source and drain regions of the HEMT wafer as the source and drain.

[0075] Example 3

[0076] The fabrication method of a GaN-based HEMT RF device in Example 3 is basically the same as that in Example 1, with the main difference being:

[0077] In this embodiment, the first and third support materials are SiN, and the second support material is SiO2. To be compatible with the regrowth ohmic contact process, the process flow remains the same, but the materials need to be changed. However, the first, second, and third support materials include, but are not limited to, SiN and SiO2, and any other two non-metallic materials that can be selectively etched away are acceptable.

[0078] The ohmic contact fabrication process in this embodiment uses a growth method to form the ohmic contact layer, specifically including:

[0079] (j) Using the support structure as a mask, the source and drain regions (regions on both sides of the support structure) of the HEMT wafer are etched to remove the surface portion of the HEMT wafer in the source and drain regions.

[0080] (k) Secondary epitaxial growth of n in the source / drain region of the HEMT wafer + -GaN as an ohmic contact layer;

[0081] (l) The second support layer is removed by wet etching process, and the source and drain regions of the HEMT wafer are annealed and activated;

[0082] (m) The position of the gate cap is defined by a patterned photolithography on the surface of the HEMT wafer and the support structure, and gate metal is deposited between the first support layer and the third support layer and on the top surface of the support structure. The gate metal between the first support layer and the third support layer is used as the gate root, and the gate metal on the top surface of the support structure is used as the gate cap.

[0083] (n) Photolithography defines the location of the ohmic contacts, and ohmic metal is deposited in the source and drain regions of the HEMT wafer as the source and drain.

[0084] This invention provides a method for fabricating a semiconductor radio frequency device. Steep sidewalls are fabricated through a single photolithography and etching process. A support structure is then fabricated using a coating / anisotropic etching method to define Lg and Lgs. Finally, the fabricated support structure serves as a mask to define source-drain ohmic contacts. This invention also provides a fully self-aligned method where the first and third support materials exhibit etching selectivity with the second support material (defining the length of Lg) to ensure compatibility with the final ohmic contacts. The support structure formed by this fully self-aligned method can accurately achieve source, gate, and drain self-alignment.

[0085] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for full self-alignment of gate-source, gate-drain, short gate length, characterized in that, The method comprises the following steps: forming a first support material layer on the surface of the epitaxial wafer; forming a patterned first mask on the surface of the first support material layer, removing the first support material not covered by the first mask, thereby forming a first support layer having a first sidewall and a second sidewall arranged back to back along a selected direction; removing the first mask and forming a continuous second support material layer on the surface of the epitaxial wafer and the first support layer; etching and removing the second support material distributed outside the first sidewall of the first support layer, and the remaining second support material serving as a second support layer having a third sidewall on the side opposite to the first sidewall along the selected direction; forming a continuous third support material layer on the surface of the epitaxial wafer, the first support layer and the second support layer; etching and removing the third support material distributed outside the third sidewall of the second support layer and the second sidewall of the first support layer, the third support material remaining on the third sidewall of the second support layer serving as a third support layer, and the third support material remaining on the second sidewall of the first support layer serving as a fourth support layer, the first support layer, the second support layer, the third support layer and the fourth support layer collectively forming a support structure; wherein the regions on both sides of the support structure are respectively used as a source region and a drain region, the region where the second support layer is located is used as a gate root region of a gate, one of the region where the third support layer is located, the third support layer and the region where the first support layer is located corresponds to a gate-source region, and the other corresponds to a gate-drain region, the first support material, the third support material and the second support material have etching selectivity.

2. The gate-source, gate-drain, short-gate-length fully self-aligned method of claim 1, wherein, The method comprises the following steps: applying an anisotropic etching process to etch the second support material until the surface of the epitaxial wafer is reached, thereby removing the second support material distributed outside the first sidewall and the second sidewall of the first support layer; applying a second mask to the surface of the second support material remaining on the first sidewall of the first support layer, and removing the second support material distributed on the second sidewall of the first support layer, thereby forming the second support layer; and removing the second mask covering the second support layer.

3. The gate-source, gate-drain, short-gate-length fully self-aligned method of claim 1, wherein, The method comprises the following steps: applying an anisotropic etching process to etch the third support material until the surface of the epitaxial wafer is reached, thereby removing the third support material distributed outside the third sidewall of the second support layer and the second sidewall of the first support layer, and forming the third support layer and the fourth support layer.

4. The gate-source, gate-drain, short-gate-length fully self-aligned method of claim 1, wherein: The first sidewall and the second sidewall of the first support layer are perpendicular to the surface of the epitaxial wafer.

5. The gate-source, gate-drain, short-gate-length fully self-aligned method of claim 1, wherein: The first support material and the third support material are insulating materials, and the second support material is an insulating material or a metal material.

6. The gate-source, gate-drain, short-gate-length fully self-aligned method of claim 1, wherein: The thickness of the second support layer in the selected direction is a gate length, and one of the thickness of the third support layer in the selected direction, the thickness of the fourth support layer in the selected direction and the thickness of the first support layer in the selected direction is a gate-source distance, and the other is a gate-drain distance.

7. A method of fabricating a semiconductor radio frequency device, characterized by, The method comprises the following steps: The gate-source, gate-drain, short-gate-length full self-alignment method defined in any one of claims 1-6 is used to form a support structure defining a gate-source, gate-drain, short-gate-length on an epitaxial wafer, and a source, a drain and a gate are made to match the epitaxial wafer, the source and the drain are respectively located on two sides of the support structure, and the gate is located on the support structure.

8. The method of claim 7, wherein: The second support material is a metal material, the second support layer is used as a gate root, and the preparation method further comprises: Depositing a metal on the top surface of the epitaxial wafer and the support structure, and making the metal on the epitaxial wafer form an ohmic contact with the epitaxial wafer, the metal on the top surface of the support structure is used as a gate cap, the gate cap is electrically connected with the gate root, and the metals on the two sides of the support structure are respectively used as a source and a drain.

9. The method of claim 7, wherein the semiconductor radio frequency device is a high electron mobility transistor. Specifically comprising: forming an ohmic contact layer on the regions of the epitaxial wafer located on the two sides of the support structure; removing the second support layer; depositing a gate metal on the top surface of the support structure and between the first support layer and the third support layer, the gate metal between the first support layer and the third support layer is used as a gate root, the gate metal on the top surface of the support structure is used as a gate cap, the gate cap is electrically connected with the gate root and forms a gate; depositing an ohmic metal on the ohmic contact layer as a source and a drain.

10. The method of claim 9, wherein the semiconductor radio frequency device is a high electron mobility transistor. Specifically comprising: using ion implantation to convert the surface layer of the regions of the epitaxial wafer located on the two sides of the support structure to form an ohmic contact layer; or, etching to remove the surface layer of the regions of the epitaxial wafer located on the two sides of the support structure, and then epitaxially growing an ohmic contact layer on the regions on the two sides of the support structure.

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