Method for manufacturing embedded siGe epitaxy

Abstract

The application provides a preparation method of embedded SiGe epitaxy, which comprises the following steps: firstly, growing a SiGe epitaxial buffer layer with a stepwise increase distribution of concentration and low concentration Ge in the groove along the epitaxial growth direction, so as to effectively reduce the lattice mismatch between the silicon substrate and the SiGe epitaxial buffer layer, and to provide a good deposition basis for the deposition of the subsequent material layer; in addition, the first SiGe epitaxial seed layer with the required thickness is obtained by adopting the way of recycling of the epitaxial growth step combined with the rinsing step, so that the first SiGe epitaxial seed layer with excellent film quality can be formed, and the unnecessary small particles in the non-groove area are also effectively removed, thereby reducing or even inhibiting the shoulder defects; finally, the second SiGe epitaxial seed layer is used as another part of the stress layer of the channel, and after the second SiGe epitaxial seed layer is formed, the hydrochloric acid rinsing with a rinsing time of no more than 5 seconds is performed once again, so that the regeneration of the unnecessary small particles in the non-groove area is further reduced.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and in particular to a method for preparing embedded SiGe epitaxy. Background Technology

[0002] With the development of semiconductor technology, the critical dimension (CD) of devices is becoming smaller and smaller. When the process node of devices reaches below 28nm, the gate structure in the process node will adopt a high dielectric constant metal gate (HKMG) and the source and drain regions will adopt embedded epitaxial layers. The embedded epitaxial layer (EPI) is used to change the stress in the channel region, thereby improving the carrier mobility in the channel region and thus improving the performance of the device. In the fabrication of PMOS devices, SiGe is usually selected as the embedded epitaxial layer material. This process occurs after the gate structure is completed, and the specific steps include: depositing a silicon nitride (Si3N4) layer using reduced pressure chemical vapor deposition (LPCVD) as a barrier layer for the epitaxial growth of SiGe strained material; removing the Si3N4 layer in the PMOS region by photolithography and etching; selectively etching the silicon substrate to form grooves in the PMOS source and drain; and selectively epitaxially growing a single-crystal SiGe strained material film on the silicon substrate of the PMOS source and drain grooves by epitaxial technology, while performing P-type ion doping.

[0003] The tiny particles generated during existing embedded germanium-silicon epitaxial processes are a key factor limiting the efficiency of large-scale production. These particles mainly form on the sidewalls and top of the gate structure (often referred to as shoulder defects), affecting device reliability. To ensure high-quality SiGe epitaxial layers while effectively controlling these shoulder defects (such as…),… Figure 1 As shown in the diagram, in SiGe epitaxial technology, the control of carrier gas and precursor flow rates is extremely critical, but it faces several limitations. For example, precise control is challenging, reaction kinetics are complex, and the interaction of temperature and pressure all affect the quality of the SiGe epitaxial layer. Furthermore, hydrochloric acid (HCl) rinsing presents many challenges in reducing defects. For instance, the sensitivity to dosage and time, interface quality control, and the dynamic balance between the immediate effects of HCl and the epitaxial growth rate all influence the growth efficiency and quality of the SiGe epitaxial layer. Therefore, existing technologies struggle to effectively control shoulder defects while ensuring high-quality SiGe epitaxial layers. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating embedded SiGe epitaxy, which solves the problem in the prior art that it is difficult to effectively control shoulder defects while ensuring a high-quality SiGe epitaxial layer when fabricating embedded SiGe epitaxy for PMOS devices.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating embedded SiGe epitaxy, the method comprising:

[0006] S1. A silicon substrate is provided, on which a gate structure of a semiconductor device is formed, and an etch barrier layer is covered on the surface of the silicon substrate and the surface of the gate structure.

[0007] S2. Based on the etching barrier layer, the silicon substrates on both sides of the gate structure are etched to form grooves;

[0008] S3. Filling the groove with a P-type doped embedded epitaxial layer includes the following steps:

[0009] S31. Selective epitaxial growth is performed to form a P-type doped SiGe epitaxial buffer layer on the inner surface of the groove; wherein the concentration of Ge in the SiGe epitaxial buffer layer increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 10 at% to 30 at%.

[0010] S32. A P-type doped first SiGe epitaxial seed layer is formed on the surface of the SiGe epitaxial buffer layer; wherein the concentration of Ge in the first SiGe epitaxial seed layer increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 30 at% to 50 at%, and the upper surface of the first SiGe epitaxial seed layer is not higher than the lower surface of the gate structure.

[0011] The method for forming the first SiGe epitaxial seed layer is as follows: an epitaxial growth step, selectively epitaxially growing a p-type doped first SiGe epitaxial seed layer, the thickness of which is... The rinsing step involves rinsing the first SiGe epitaxial seed layer with hydrochloric acid for no more than 5 seconds; the epitaxial growth step and the rinsing step are repeated multiple times as a cycle unit until the first SiGe epitaxial seed layer of the required thickness is reached.

[0012] S33. Perform selective epitaxial growth to form a P-type doped second SiGe epitaxial seed layer on the surface of the first SiGe epitaxial seed layer; wherein, the concentration of Ge in the second SiGe epitaxial seed layer decreases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 20 at% to 50 at%, and the upper surface of the second SiGe epitaxial seed layer is not lower than the lower surface of the gate structure.

[0013] S34. Rinse the second SiGe epitaxial seed layer with hydrochloric acid for no more than 5 seconds.

[0014] S35. Perform selective epitaxial growth to form a P-type doped silicon capping layer on the surface of the second SiGe epitaxial seed layer.

[0015] Optionally, in the method of forming the first SiGe epitaxial seed layer in step S32, the epitaxial growth step and the rinsing step are cycled 1 to 4 times as a cycle unit.

[0016] Optionally, the dopant ion of the P-type doped embedded epitaxial layer is boron.

[0017] Furthermore, in step S33, the initial concentration of Ge and the initial concentration of P-type doping during the selective epitaxial growth of the second SiGe epitaxial seed layer are the same as the final concentration of Ge and the final concentration of P-type doping during the formation of the first SiGe epitaxial seed layer in step S32.

[0018] Furthermore, the doping concentration of the SiGe epitaxial buffer layer is 1E18 to 1E20; the doping concentration of the first SiGe epitaxial seed layer is 1E20 to 9E20; the doping concentration of the second SiGe epitaxial seed layer is 1E19 to 9E20; and the doping concentration of the silicon cap layer is 1E20 to 6E20.

[0019] Optionally, in step S32, the concentration of hydrochloric acid used in the rinsing step of the method for forming the first SiGe epitaxial seed layer is 1% to 20%; in step S34, the concentration of hydrochloric acid used to rinse the second SiGe epitaxial seed layer is 1% to 20%.

[0020] Optionally, the thickness of the SiGe epitaxial buffer layer is The thickness of the first SiGe epitaxial seed layer is The thickness of the second SiGe epitaxial seed layer is The thickness of the silicon cap layer is

[0021] Optionally, the etching barrier layer is a silicon nitride etching barrier layer.

[0022] Optionally, the silicon source precursor used in forming the SiGe epitaxial buffer layer, the first SiGe epitaxial seed layer and the second SiGe epitaxial seed layer is SiH2Cl2, and the germanium source precursor used is GeH4; the silicon source precursor used in forming the silicon capping layer is SiH2Cl2 and SiH4.

[0023] Optionally, the carrier gas flow rate used when selectively epitaxially growing the SiGe epitaxial buffer layer, the first SiGe epitaxial seed layer, the second SiGe epitaxial seed layer, and the silicon capping layer is 1 standard liter / min to 200 standard liters / min, and the precursor flow rate is 1 standard liter / min to 200 standard liters / min.

[0024] As described above, the embedded SiGe epitaxial fabrication method of the present invention first grows a low-concentration SiGe epitaxial buffer layer with a stepped growth distribution along the epitaxial growth direction in the trench, thereby effectively reducing the lattice mismatch between the silicon substrate and the SiGe epitaxial buffer layer, providing an excellent deposition basis for subsequent material layer deposition. Furthermore, by using a cycle of epitaxial growth steps combined with rinsing steps, a first SiGe epitaxial seed layer of the required thickness is obtained. Since this first SiGe epitaxial seed layer is a high-concentration Ge layer, it is mainly used as part of the stress layer of the channel. Due to the high Ge concentration, this stage is most prone to unnecessary nucleation in non-trench regions (sidewalls and / or top of the gate). By growing a thickness of [missing information] in each cycle... The first SiGe epitaxial seed layer is formed and then rinsed with hydrochloric acid for no more than 5 seconds to achieve an excellent dynamic balance between the immediate etching effect of hydrochloric acid and the epitaxial growth thickness. This ensures that the interface of the first SiGe epitaxial seed layer formed in each cycle is not damaged after hydrochloric acid rinsing, resulting in an excellent growth interface without affecting growth efficiency. At the same time, it can effectively suppress or even remove unnecessary nucleation generated in non-groove areas. After multiple cycles, because the unnecessary nucleation generated in non-groove areas is continuously suppressed, it is difficult for it to grow larger, thus ultimately forming a first SiGe epitaxial seed layer with excellent film quality. At the same time, unnecessary microparticles in non-groove areas are also effectively removed, reducing or even suppressing shoulder defects. Finally, the second SiGe epitaxial seed layer is used as another part of the channel stress layer. After the second SiGe epitaxial seed layer is formed, it is rinsed with hydrochloric acid for no more than 5 seconds to further reduce the regeneration of unnecessary microparticles in non-groove areas. Attached Figure Description

[0025] Figure 1 The image shown is an SEM image of an embedded SiGe epitaxial layer formed in the prior art.

[0026] Figures 2 to 8 The diagram shows a cross-sectional view of each step in the fabrication method of embedded SiGe epitaxy according to the present invention.

[0027] Component designation explanation

[0028] 10 Silicon substrate

[0029] 11 Gate Structure

[0030] 12 Etching Barrier Layer

[0031] 13 Grooves

[0032] 14 Embedded Epitaxial Layer

[0033] 140 SiGe Epitaxial Buffer Layer

[0034] 141 First SiGe Epitaxial Seed Layer

[0035] 142 First SiGe Epitaxial Seed Layer

[0036] 143 Second SiGe Epitaxial Seed Layer

[0037] 144 Silicon cap layer

[0038] 20. Shoulder defects Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please see Figures 2 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] This embodiment provides a method for fabricating embedded SiGe epitaxy, the method comprising the following steps:

[0042] S1. A silicon substrate is provided, on which a gate structure of a semiconductor device is formed, and an etch barrier layer is covered on the surface of the silicon substrate and the surface of the gate structure.

[0043] S2. Based on the etching barrier layer, the silicon substrates on both sides of the gate structure are etched to form grooves;

[0044] S3. Filling the groove with a P-type doped embedded epitaxial layer includes the following steps:

[0045] S31. Selective epitaxial growth is performed to form a P-type doped SiGe epitaxial buffer layer on the inner surface of the groove; wherein the concentration of Ge in the SiGe epitaxial buffer layer increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 10 at% to 30 at%.

[0046] S32. A P-type doped first SiGe epitaxial seed layer is formed on the surface of the SiGe epitaxial buffer layer; wherein the concentration of Ge in the first SiGe epitaxial seed layer increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 30 at% to 50 at%, and the upper surface of the first SiGe epitaxial seed layer is not higher than the lower surface of the gate structure.

[0047] The method for forming the first SiGe epitaxial seed layer is as follows: an epitaxial growth step, selectively epitaxially growing a p-type doped first SiGe epitaxial seed layer, the thickness of which is... The rinsing step involves rinsing the first SiGe epitaxial seed layer with hydrochloric acid for no more than 5 seconds; the epitaxial growth step and the rinsing step are repeated multiple times as a cycle unit until the first SiGe epitaxial seed layer of the required thickness is reached.

[0048] S33. Perform selective epitaxial growth to form a P-type doped second SiGe epitaxial seed layer on the surface of the first SiGe epitaxial seed layer; wherein, the concentration of Ge in the second SiGe epitaxial seed layer decreases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 20 at% to 50 at%, and the upper surface of the second SiGe epitaxial seed layer is not lower than the lower surface of the gate structure.

[0049] S34. Rinse the second SiGe epitaxial seed layer with hydrochloric acid for no more than 5 seconds.

[0050] S35. Perform selective epitaxial growth to form a P-type doped silicon capping layer on the surface of the second SiGe epitaxial seed layer.

[0051] It should be noted that in this embodiment, the concentration of Ge refers to the atomic percentage of Ge atoms in the total amount of Ge atoms and Si atoms in the formed SiGe material.

[0052] The embedded SiGe epitaxial fabrication method of this embodiment first grows a low-concentration SiGe epitaxial buffer layer with a stepped growth distribution along the epitaxial growth direction in the trench. This effectively reduces the lattice mismatch between the silicon substrate and the SiGe epitaxial buffer layer, providing an excellent deposition foundation for subsequent material layer deposition. Furthermore, a first SiGe epitaxial seed layer of the required thickness is obtained by cyclically combining epitaxial growth steps with rinsing steps. Since this first SiGe epitaxial seed layer is a high-concentration Ge layer, it is mainly used as part of the channel stress layer. Due to the high Ge concentration, this stage is most prone to unnecessary nucleation in non-trench regions (gate sidewalls and / or top). By growing a thickness of [missing information] in each cycle... The first SiGe epitaxial seed layer is formed and then rinsed with hydrochloric acid for no more than 5 seconds to achieve an excellent dynamic balance between the immediate etching effect of hydrochloric acid and the epitaxial growth thickness. This ensures that the interface of the first SiGe epitaxial seed layer formed in each cycle is not damaged after hydrochloric acid rinsing, resulting in an excellent growth interface without affecting growth efficiency. At the same time, it can effectively suppress or even remove unnecessary nucleation generated in non-groove areas. After multiple cycles, because the unnecessary nucleation generated in non-groove areas is continuously suppressed, it is difficult for it to grow larger, thus ultimately forming a first SiGe epitaxial seed layer with excellent film quality. At the same time, unnecessary microparticles in non-groove areas are also effectively removed, reducing or even suppressing shoulder defects. Finally, the second SiGe epitaxial seed layer is used as another part of the channel stress layer. After the second SiGe epitaxial seed layer is formed, it is rinsed with hydrochloric acid for no more than 5 seconds to further reduce the regeneration of unnecessary microparticles in non-groove areas.

[0053] The method for fabricating embedded SiGe epitaxy in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0054] like Figure 2 As shown, step S1 is performed first, providing a silicon substrate 10, on which a gate structure 11 of a semiconductor device is formed, and an etch barrier layer 12 is covered on the surface of the silicon substrate 10 and the surface of the gate structure 11.

[0055] The gate structure 11 includes a gate dielectric layer and a gate polysilicon layer stacked sequentially. As an example, the sidewalls of the gate structure 11 may also be formed with sidewall structures, which is a conventional arrangement in the art and is not excessively limited herein.

[0056] As an example, the material of the etch barrier layer 12 can be any suitable material to facilitate the subsequent formation of grooves on both sides of the gate structure 11, while also serving as a non-growth layer for subsequent embedded epitaxial layer growth. In this embodiment, the etch barrier layer 12 is selected as a silicon nitride etch barrier layer.

[0057] like Figure 3 As shown, then step S2 is performed, in which the silicon substrate 10 on both sides of the gate structure 11 is etched to form a groove 13 based on the etch barrier layer 12.

[0058] The shape of the groove 13 is not excessively restricted. For example, the cross-section of the groove 13 can be U-shaped, Σ-shaped (i.e., diamond-shaped), or other desired shapes. Depending on the shape of the groove 13, the method of forming the groove 13 may also differ. For example, the groove 13 can be formed by wet etching, dry etching, or a combination of wet and dry etching. The specific method chosen depends on existing conventional techniques and is not excessively limited here. Furthermore, the size of the groove 13 is also set according to actual needs.

[0059] like Figures 4 to 8 As shown, step S3 is then performed, in which a P-type doped embedded epitaxial layer 14 is filled into the groove 13. The embedded epitaxial layer 14 is formed by a subsequently formed SiGe epitaxial buffer layer 140, a first SiGe epitaxial seed layer 141, a second SiGe epitaxial seed layer 143, and a silicon capping layer 144. The specific method for forming the embedded epitaxial layer 14 includes the following steps:

[0060] like Figure 4 As shown, step S31 is performed first, in which a P-type doped SiGe epitaxial buffer layer 140 is formed on the inner surface of the groove 13 by selective epitaxial growth; wherein, the concentration of Ge in the SiGe epitaxial buffer layer 140 increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 10 at% to 30 at%.

[0061] The type of dopant ion used for P-type doping is not overly restricted, as long as it can achieve P-type conductivity. For example, it can be boron, aluminum, gallium, or indium, etc. In this embodiment, boron ions are preferred.

[0062] As an example, the doping concentration of the SiGe epitaxial buffer layer 140 is 1E18 to 1E20. This SiGe epitaxial buffer layer 140 serves as a lattice-matching layer between the stress layer formed subsequently by epitaxy and the semiconductor substrate. A low Ge content is selected, and the Ge content increases in a stepwise manner along the epitaxial growth direction to achieve excellent lattice matching between the SiGe epitaxial buffer layer 140 and the silicon substrate 10. Simultaneously, it also ensures excellent lattice matching between the SiGe epitaxial buffer layer 140 and the subsequently formed first SiGe epitaxial seed layer 141. Furthermore, the stepwise increase in Ge content along the epitaxial growth direction allows for gradual changes in the lattice structure of the SiGe epitaxial buffer layer 140, ultimately forming a SiGe epitaxial buffer layer 140 with superior performance, providing an excellent deposition basis for subsequent material layer deposition.

[0063] As an example, the thickness of the SiGe epitaxial buffer layer 140 is selected as follows:

[0064] As an example, the silicon source precursor used to form the SiGe epitaxial buffer layer 140 is SiH2Cl2, the germanium source precursor is GeH4, and the carrier gas used is H2 and / or N2.

[0065] like Figure 5 and Figure 6 As shown, step S32 is then performed to form a P-type doped first SiGe epitaxial seed layer 141 on the surface of the SiGe epitaxial buffer layer 140; wherein, the concentration of Ge in the first SiGe epitaxial seed layer 141 increases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 30 at% to 50 at%, and the upper surface of the first SiGe epitaxial seed layer 141 is not higher than the lower surface of the gate structure 11.

[0066] The method for forming the first SiGe epitaxial seed layer 141 is as follows: Figure 5 As shown, in the epitaxial growth step, a p-type doped first SiGe epitaxial seed layer 142 is selectively grown epitaxially. The thickness of the first SiGe epitaxial seed layer 142 is... In the rinsing step, the first SiGe epitaxial seed layer 142 is rinsed with hydrochloric acid for no more than 5 seconds; Figure 6 As shown, the epitaxial growth step and the rinsing step are cycled multiple times as a cycle unit until the first SiGe epitaxial seed layer 141 of the required thickness is reached.

[0067] like Figure 5As shown above, since the first SiGe epitaxial seed layer 141 is a high-concentration Ge layer and is also part of the main layer used as the channel stress layer, the high Ge concentration makes it the stage most prone to unnecessary nucleation in the non-recessed region (sidewalls and / or top of the gate). Therefore, the first SiGe epitaxial seed layer 141 is prepared by cyclic growth using epitaxy + rinsing, with a thickness of [missing information] in each cycle. The first SiGe epitaxial seed layer 142 is combined with hydrochloric acid rinsing for no more than 5 seconds to achieve an excellent dynamic balance between the immediate etching effect of hydrochloric acid and the epitaxial growth thickness. This ensures that the interface of the first SiGe epitaxial seed layer 142 formed in each cycle is not damaged after hydrochloric acid rinsing, resulting in an excellent growth interface without affecting growth efficiency. At the same time, unnecessary nucleation generated in non-groove areas can be effectively suppressed or even removed. After multiple cycles, because unnecessary nucleation generated in non-groove areas is continuously suppressed, it is difficult for the nuclei to grow larger, thus ultimately forming a first SiGe epitaxial seed layer 141 with excellent film quality. At the same time, unnecessary microparticles in non-groove areas are also effectively removed, reducing or even suppressing shoulder defects.

[0068] As a preferred example, in this method for forming the first SiGe epitaxial seed layer 141, the epitaxial growth step and the rinsing step are repeated 1 to 4 times as cyclic units, that is, a total of 2 to 5 cycles. If the number of cycles is too few, the effect of suppressing nucleation and reducing defects will not be achieved. If the number of cycles is too many, the multiple rinsing processes will cause surface damage to the formed SiGe epitaxial layer, and will also damage areas outside the SiGe epitaxial layer, such as the channel region, resulting in a decrease in device performance.

[0069] As another preferred example, the concentration of hydrochloric acid used in the rinsing step of the method for forming the first SiGe epitaxial seed layer 141 in step S32 is 1% to 20%, for example, it can be 1%, 5%, 8%, 11%, 14%, 17%, 20%, etc.

[0070] As an example, the thickness of the first SiGe epitaxial seed layer 141 is selected as follows:

[0071] As an example, the silicon source precursor used to form the first SiGe epitaxial seed layer 141 is SiH2Cl2 and / or SiH4, the germanium source precursor is GeH4, and the carrier gas used is H2 and / or N2.

[0072] As an example, the doping concentration of the first SiGe epitaxial seed layer 141 is 1E20 to 9E20.

[0073] The type of dopant ion used for P-type doping is not overly restricted, as long as it can achieve P-type conductivity. For example, it can be boron, aluminum, gallium, or indium, etc. In this embodiment, boron ions are preferred.

[0074] like Figure 7 As shown, step S33 is then performed to selectively epitaxially grow a P-type doped second SiGe epitaxial seed layer 143 on the surface of the first SiGe epitaxial seed layer 141; wherein, the concentration of Ge in the second SiGe epitaxial seed layer 143 decreases in a stepwise manner along the growth direction, and the concentration of Ge ranges from 20 at% to 50 at%, and the upper surface of the second SiGe epitaxial seed layer 143 is not lower than the lower surface of the gate structure 11. That is, the concentration of Ge in the first SiGe epitaxial seed layer 141 gradually increases along the growth direction, while the concentration of Ge in the second SiGe epitaxial seed layer 143 gradually decreases along the growth direction. This method allows the lattice constants of the formed first SiGe epitaxial seed layer 141 and second SiGe epitaxial seed layer 143 to change gradually. The middle region in the thickness direction of these two layers is the region with the maximum Ge concentration, which provides the main stress effect for the channel. On both sides of the thickness direction of these two layers are the regions with the minimum Ge concentration, which can have good lattice matching with the corresponding silicon material, thereby ensuring the formation of a high-quality SiGe epitaxial seed layer.

[0075] As a preferred example, in step S33, the initial concentrations of Ge and P-type doping during the selective epitaxial growth of the second SiGe epitaxial seed layer 143 are the same as the final concentrations of Ge and P-type doping during the formation of the first SiGe epitaxial seed layer 141 in step S32. That is, the initial concentrations of Ge and P-type doping during the selective epitaxial growth of the second SiGe epitaxial seed layer 143 are based on the final concentrations of Ge and P-type doping during the formation of the first SiGe epitaxial seed layer 141 in step S32. This further improves the lattice matching between the first SiGe epitaxial seed layer 141 and the second SiGe epitaxial seed layer 143.

[0076] As an example, the thickness of the second SiGe epitaxial seed layer 143 is selected as follows:

[0077] As an example, the silicon source precursor used to form the second SiGe epitaxial seed layer 143 is SiH2Cl2, the germanium source precursor is GeH4, and the carrier gas used is H2 and / or N2.

[0078] As an example, the doping concentration of the second SiGe epitaxial seed layer 143 is 1E19 to 9E20.

[0079] The type of dopant ion used for P-type doping is not overly restricted, as long as it can achieve P-type conductivity. For example, it can be boron, aluminum, gallium, or indium, etc. In this embodiment, boron ions are preferred.

[0080] Next, in step S34, the second SiGe epitaxial seed layer 143 is rinsed with hydrochloric acid for no more than 5 seconds. Since the second SiGe epitaxial seed layer 143 is another part of the main layer of the channel stress layer, the concentration of Ge is relatively high. Rinsing the second SiGe epitaxial seed layer 143 with hydrochloric acid for no more than 5 seconds can further reduce the unnecessary regeneration of microparticles in non-recessed areas.

[0081] As a preferred example, the concentration of hydrochloric acid used in this step S34 rinsing is 1% to 20%, for example, it can be 1%, 5%, 8%, 11%, 14%, 17%, 20%, etc.

[0082] like Figure 8 As shown, step S35 is performed last to selectively epitaxially grow a P-type doped silicon capping layer 144 on the surface of the second SiGe epitaxial seed layer 143. This silicon capping layer 144 can reduce the contact resistance between the source and drain.

[0083] As an example, the silicon source precursor used to form the silicon capping layer 144 is a mixed gas of SiH2Cl2 and SiH4, and the carrier gas used is H2 and / or N2.

[0084] As an example, the doping concentration of the silicon capping layer 144 is 1E20 to 6E20.

[0085] As an example, the thickness of the silicon cap layer 144 is chosen to be...

[0086] The type of dopant ion used for P-type doping is not overly restricted, as long as it can achieve P-type conductivity. For example, it can be boron, aluminum, gallium, or indium, etc. In this embodiment, boron ions are preferred.

[0087] like Figure 8 As shown, through steps S31 to S35, an embedded epitaxial layer 14 consisting of a SiGe epitaxial buffer layer 140, a first SiGe epitaxial seed layer 141, a second SiGe epitaxial seed layer 143, and a silicon capping layer 144 has been formed.

[0088] As a preferred example, the carrier gas flow rate used during the selective epitaxial growth of the SiGe epitaxial buffer layer 140, the first SiGe epitaxial seed layer 141, the second SiGe epitaxial seed layer 143, and the silicon capping layer 144 is 1 standard liter / min to 200 standard liters / min, for example, 1 standard liter / min, 40 standard liters / min, 80 standard liters / min, 120 standard liters / min, 160 standard liters / min, 200 standard liters / min, etc.; the precursor flow rate is 1 standard liter / min to 200 standard liters / min, for example, 1 standard liter / min, 40 standard liters / min, 80 standard liters / min, 120 standard liters / min, 160 standard liters / min, 200 standard liters / min, etc. In this embodiment, H2 is preferred as the carrier gas. To achieve high-quality embedded epitaxy, balancing the carrier gas and precursor flow rates is crucial. Ideally, the carrier gas flow rate should be set to 1 to 200 standard liters per minute (SPM) and the precursor flow rate should also be set to 1 to 200 SPM. This allows for a dynamic balance between the carrier and precursor flow rates, optimizing deposition selectivity, reducing deposition on non-silicon surfaces, improving the uniformity of the epitaxial layer, and ensuring thickness control.

[0089] In summary, this invention provides a method for fabricating embedded SiGe epitaxy. First, a low-concentration SiGe epitaxial buffer layer with a stepped growth distribution along the epitaxial growth direction is grown in the trench to effectively reduce the lattice mismatch between the silicon substrate and the SiGe epitaxial buffer layer, thus providing an excellent deposition foundation for subsequent material layers. Furthermore, a first SiGe epitaxial seed layer of the required thickness is obtained by combining epitaxial growth steps with rinsing steps in a cyclic manner. Since this first SiGe epitaxial seed layer is a high-concentration Ge layer, it is mainly used as part of the stress layer of the channel. Due to the high Ge concentration, this stage is most prone to unnecessary nucleation in non-trench regions (sidewalls and / or top of the gate). By growing a thickness of [missing information] in each cycle... The first SiGe epitaxial seed layer is combined with a hydrochloric acid rinse of no more than 5 seconds to achieve an excellent dynamic balance between the immediate etching effect of hydrochloric acid and the epitaxial growth thickness. This ensures that the interface of the first SiGe epitaxial seed layer formed in each cycle is not damaged after hydrochloric acid rinsing, resulting in an excellent growth interface without affecting growth efficiency. Simultaneously, it effectively suppresses or even removes unnecessary nucleation in non-groove regions. After multiple cycles, because unnecessary nucleation in non-groove regions is continuously suppressed, it is difficult for the nuclei to grow larger, ultimately forming a first SiGe epitaxial seed layer with excellent film quality. Unnecessary microparticles in non-groove regions are also effectively removed, reducing or even suppressing shoulder defects. Finally, the second SiGe epitaxial seed layer is used as another part of the channel stress layer. After the formation of the second SiGe epitaxial seed layer, another hydrochloric acid rinse of no more than 5 seconds is performed to further reduce the regeneration of unnecessary microparticles in non-groove regions. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of preparing embedded SiGe epitaxy, characterized by, The preparation method comprises: S1, providing a silicon substrate on which a gate structure of a semiconductor device is formed, and a surface of the silicon substrate and a surface of the gate structure are covered with an etching barrier layer; S2, etching the silicon substrate on both sides of the gate structure based on the etching barrier layer to form a groove; S3, filling a P-doped embedded epitaxial layer in the groove, comprising the following steps: S31, selectively epitaxially growing a P-doped SiGe epitaxial buffer layer on the inner side surface of the groove; wherein the concentration of Ge in the SiGe epitaxial buffer layer increases in a stepped manner along the growth direction, and the concentration range of Ge is 10at%~30at%; S32, forming a P-doped first SiGe epitaxial seed layer on the surface of the SiGe epitaxial buffer layer; wherein the concentration of Ge in the first SiGe epitaxial seed layer decreases in a stepped manner along the growth direction, and the concentration range of Ge is 30at%~50at%, and the upper surface of the first SiGe epitaxial seed layer is not higher than the lower surface of the gate structure; The method for forming the first SiGe epitaxial seed layer comprises: an epitaxial growth step of selectively epitaxially growing a P-doped first SiGe epitaxial seed sub-layer, the thickness of the first SiGe epitaxial seed sub-layer being 40Å~100Å; a rinsing step of rinsing the first SiGe epitaxial seed sub-layer with hydrochloric acid, the rinsing time being not more than 5 seconds; and the epitaxial growth step and the rinsing step are taken as a cycle unit and cycled for multiple times until the first SiGe epitaxial seed layer with the required thickness is obtained; S33, selectively epitaxially growing a P-doped second SiGe epitaxial seed layer on the surface of the first SiGe epitaxial seed layer; wherein the concentration of Ge in the second SiGe epitaxial seed layer decreases in a stepped manner along the growth direction, and the concentration range of Ge is 20at%~50at%, and the upper surface of the second SiGe epitaxial seed layer is not lower than the lower surface of the gate structure; S34, rinsing the second SiGe epitaxial seed layer with hydrochloric acid, the rinsing time being not more than 5 seconds; S35, selectively epitaxially growing a P-doped silicon cap layer on the surface of the second SiGe epitaxial seed layer.

2. The method of claim 1, wherein: In the method for forming the first SiGe epitaxial seed layer in step S32, the epitaxial growth step and the rinsing step are taken as a cycle unit and cycled for 1~4 times.

3. The method of claim 1, wherein: The doping ions of the P-doped embedded epitaxial layer are boron.

4. The method of claim 1, 2 or 3, wherein: In step S33, the initial concentration of Ge and the initial concentration of P-type doping when the second SiGe epitaxial seed layer is selectively epitaxially grown are the same as the final concentration of Ge and the final concentration of P-type doping when the first SiGe epitaxial seed layer is formed in step S32.

5. The method of claim 1, wherein: The thickness of the SiGe epitaxial buffer layer is 100Å~300Å; the thickness of the first SiGe epitaxial seed layer is 200Å~400Å; the thickness of the second SiGe epitaxial seed layer is 100Å~200Å; and the thickness of the silicon cap layer is 80Å~300Å.

6. The method of claim 1, wherein: The etching stop layer is a silicon nitride etching stop layer.

7. The method of claim 1, wherein: The silicon source precursor used in forming the SiGe epitaxial buffer layer, the first SiGe epitaxial seed layer and the second SiGe epitaxial seed layer is SiH2Cl2, and the germanium source precursor used is GeH4; the silicon source precursor used in forming the silicon cap layer is SiH2Cl2 and SiH4.

8. The method of claim 1, wherein: The carrier gas flow rate used in the selective epitaxial growth of the SiGe epitaxial buffer layer, the first SiGe epitaxial seed layer, the second SiGe epitaxial seed layer and the silicon cap layer is 1 standard liter / minute to 200 standard liters / minute, and the precursor flow rate is 1 standard liter / minute to 200 standard liters / minute.

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