Optoelectronic device

Abstract

An apparatus includes an assembly of pixels, where a first pixel generates event-based data elements and a second pixel generates light intensity data elements. Each of the first and second pixels includes a portion of the layer that forms a photodiode. The first integrated circuit chip includes a first substrate and a first interconnection network, and the second integrated circuit chip includes a second substrate and a second interconnection network. The first integrated circuit chip and the second integrated circuit chip are attached to each other through the first interconnection network and the second interconnection network. The layer having the photodiode is located on a first surface of the second substrate opposite a second surface of the second substrate having the second interconnect network thereon.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2310461 filed on September 29, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to optoelectronic devices. Background Art

[0004] Like a standard camera, an event-based camera comprises a plurality of pixels, each pixel being configured to transmit a value corresponding to a position in an observed scene. However, in contrast to a standard camera (i.e. a camera having each of its pixels configured to periodically transmit a light intensity value corresponding to that position), an event-based camera is configured to transmit information indicating a change in light intensity. An event-based camera is thus configured to transmit an event-based image of a scene. A standard camera is thus configured to transmit a light intensity image of a scene. Thus, a standard camera is a synchronous camera, making it possible to obtain a series of images comprising as many intensity values ​​as pixels at a frame rate. An event-based camera is a synchronous camera or an asynchronous camera, providing, for each pixel, information indicating a change in brightness at a corresponding position in the scene. When the scene is stationary, a standard camera keeps transmitting all intensity values ​​periodically, while an event-based camera does not transmit a value, thereby indicating a lack of change.

[0005] There is a need in the art to overcome all or part of the disadvantages of known optoelectronic devices. Summary of the invention

[0006] In one embodiment, a device includes at least one pixel component, the component including at least a first pixel and at least a second pixel, the first pixel generating an event-based data element, the second pixel generating a light intensity data element, each of the first pixel and the second pixel including a portion of a layer, the portion forming a photodiode, the device also includes a first integrated circuit chip and a second integrated circuit chip, the first integrated circuit chip including a first substrate and a first interconnection network, the second integrated circuit chip including a second substrate and a second interconnection network, the first integrated circuit chip and the second integrated circuit chip are attached to each other through their first interconnection network and the second interconnection network, and the layer is located on a first surface of the second substrate, and the first surface is opposite to a second surface of the second substrate having the second interconnection network located thereon.

[0007] According to an embodiment, the device is an event-based camera.

[0008] According to an embodiment, the first integrated circuit chip includes at least a portion of a control circuit for at least a first pixel, and the second integrated circuit chip includes at least a control circuit for a second pixel.

[0009] According to an embodiment, at least a part of the control circuit of the first pixel is in the second integrated circuit chip.

[0010] According to an embodiment, the first integrated circuit chip and the second integrated circuit chip are attached by molecular bonds.

[0011] According to an embodiment, a device comprises an assembly of a plurality of pixels arranged in an array.

[0012] According to an embodiment, each component comprises four second pixels surrounding a first pixel.

[0013] According to an embodiment, each component comprises eight second pixels surrounding a first pixel.

[0014] According to an embodiment, each component includes three second pixels and one first pixel arranged in an array.

[0015] According to an embodiment, the layer is continuous.

[0016] According to an embodiment, the layer completely covers the first surface of the second substrate.

[0017] According to an embodiment, the material of the layer is homogeneous.

[0018] According to an embodiment, the layer is in contact with the second substrate.

[0019] According to an embodiment, the layer is a layer of quantum dots or colloidal quantum dots.

[0020] According to an embodiment, the layer is made of a lead-based or tin-based photosensitive perovskite material, or of a bulk heterojunction formed of a photosensitive organic semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above features and advantages, and others, will be described in detail in the remainder of the disclosure of specific embodiments given in an illustrative and non-limiting manner with reference to the accompanying drawings, in which:

[0022] Figure 1 A cross-sectional view of an embodiment of an optoelectronic device is shown;

[0023] Figure 2 Shows Figure 1 A perspective view of an embodiment of the present invention;

[0024] Figure 3 An example of a pixel control circuit is shown;

[0025] Figure 4AAn alternative arrangement of pixel components is shown; and

[0026] Figure 4B Another alternative arrangement of pixel components is shown. DETAILED DESCRIPTION

[0027] In the various figures, similar features have been indicated by similar reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties.

[0028] For clarity, only the steps and elements useful for the understanding of the embodiments are described and illustrated in detail.

[0029] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0030] In the following description, when referring to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or referring to terms defining relative positions (such as terms "above", "below", "above", "below", etc.), or referring to terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise specifically stated, they refer to the orientation of the drawings.

[0031] Unless specifically stated otherwise, the expressions “about”, “approximately”, “substantially” and “in the order of” mean plus or minus 10%, preferably plus or minus 5%.

[0032] Figure 1 A cross-sectional view of an embodiment of an optoelectronic device is shown. Figure 2 Shows Figure 1 More specifically, Figure 1 Shown along Figure 2 Cross-sectional view of the device in plane AA.

[0033] Figure 1 and Figure 2An assembly 10 of pixels of an optoelectronic device is shown. The assembly 10 corresponds, for example, to a portion of an image capture device, for example of a camera. The assembly 10 comprises at least one pixel 12 and at least one pixel 14. More specifically, the assembly 10 comprises at least one event-based camera pixel 12 and at least one standard camera pixel 14. The pixel 14 is, for example, a pixel of the “global shutter” type, or a pixel of the “rolling shutter” type. The assembly 10 thus enables event-based data and standard brightness data to be obtained. The camera is thus an event-based camera, or a neuromorphic camera.

[0034] exist Figure 1 and Figure 2 In the example of FIG. 1 , the component 10 comprises only one pixel 14 and four pixels 12. The pixel 14 is surrounded by the pixels 12. The device, ie for example a camera, comprises a plurality of components 10, preferably arranged in an array.

[0035] The device includes a first integrated circuit chip 16 and a second integrated circuit chip 18. The first integrated circuit chip 16 includes a semiconductor substrate 20 and an interconnection network 22. The substrate 20 includes an upper surface 20a and a lower surface 20b. Similarly, the interconnection network includes an upper surface 22a and a lower surface 22b. The interconnection network 22 is bonded to the substrate 20. More specifically, the lower surface 22b of the interconnection network 22 is bonded to the upper surface 20a of the substrate 20.

[0036] The substrate 20 is made of silicon, for example. Figure 1 and Figure 2 Electronic components not shown in the figure are formed inside and on the top of the substrate 20. For example, the electronic components are formed on the upper surface of the substrate 20.

[0037] The substrate 20 includes at least a portion of the control circuitry of the pixel 14. In other words, at least a portion of the electronic components that form the control circuitry of the pixel 14 are located inside and on top of the substrate 20. For example, the substrate includes synchronous or asynchronous readout circuitry, amplifiers, logic circuitry, and storage cells of the pixel 14. Certain components may be common to multiple pixels.

[0038] The interconnection network 22 includes a stack of insulating layers, metal tracks 24 located in the insulating layers, and conductive vias 26 located in the insulating layers and coupling the conductive tracks together. The lower layers in the stack of insulating layers are located in contact with the substrate 20, and specifically in contact with the upper surface of the substrate 20. The upper layer of the stack, i.e., the insulating layer of the interconnection network that is farthest from the substrate 20, for example includes a metal track 28. The track 28 is flush with the upper surface 22a of the interconnection network.

[0039] Similarly, the second integrated circuit chip 18 includes a semiconductor substrate 28 and an interconnection network 30. The substrate 28 includes an upper surface 28a and a lower surface 28b. Similarly, the interconnection network includes an upper surface 30a and a lower surface 30b. The interconnection network 30 is bonded to the substrate 28. More specifically, the lower surface 30b of the interconnection network 30 is bonded to the upper surface 28a of the substrate 28.

[0040] The substrate 28 is made of silicon, for example. Figure 1 and Figure 2 Electronic components not shown in the figure are formed inside and on the top of the substrate 28. For example, the electronic components are formed on the upper surface of the substrate 28.

[0041] The substrate 28 (preferably completely) comprises the control circuitry of the pixels 12. In particular, the substrate 28 preferably comprises the readout circuitry of the pixels 12. The substrate 28 comprises, for example, a part of the control circuitry of the pixels 14.

[0042] The interconnection network 30 includes a stack of insulating layers, metal tracks 32 located in the insulating layers, and conductive vias 34 located in the insulating layers and coupling the conductive tracks together. The lower layers in the stack of insulating layers are located in contact with the substrate 28, and specifically in contact with the upper surface of the substrate 28. The upper layer of the stack, i.e., the insulating layer of the interconnection network that is farthest from the substrate 28, includes, for example, metal tracks 36. Tracks 36 are flush with the upper surface 30a of the interconnection network.

[0043] Chips 16 and 18 are attached to each other. More specifically, nets 22 and 30 are attached to each other. More specifically, upper surface 22a of net 22 and upper surface 30a of net 30 are attached to each other. Figure 1 and Figure 2 In the example of , chips 16 and 18 are attached by molecular bonds. Therefore, tracks 28 and 36 are placed so as to contact each other. Alternatively, chips 16 and 18, more specifically upper surfaces 22a and 30a, can be attached in another way, such as by solder balls, such as solder balls between tracks 28 and 36.

[0044] Chips 16 and 18 are thus electrically coupled. In other words, substrates 20 and 28 are electrically coupled by means of vias 26 , tracks 24 , tracks 28 , tracks 36 , tracks 32 , and vias 34 .

[0045] Component 10 also includes layer 40. Layer 40 includes, for example, quantum dots (QD). Layer 40 includes, for example, colloidal quantum dots (CQD). Alternatively, layer 40 can be made of a lead-based or tin-based photosensitive perovskite material. In other words, layer 40 is made of, for example, a material having a formula of ABX3 type, wherein element A is among the following elements: methylammonium, formamidinium, or cesium, wherein element B is among the following elements: lead or tin, and wherein element X is a halide, i.e., an element among the following elements: iodine, chlorine, or bromine. The quantum dots of layer 40 can be made of perovskite, for example, made of a lead-based or tin-based photosensitive perovskite as described above, or passivated with a lead-based or tin-based photosensitive perovskite. Layer 40 can also be a bulk heterojunction formed by a photosensitive organic semiconductor such as PDPP3T and fullerene. Layer 40 is located on chip 18, more specifically on substrate 28, more specifically on lower surface 28b of substrate 28. Layer 40 is, for example, in contact with at least a portion of substrate 28. In other words, layer 40 and substrate 28 are not separated by an interconnection network.

[0046] Layer 40 is a continuous layer. Layer 40 preferably completely covers surface 28b. In other words, layer 40 preferably does not include an opening exposing surface 28b. Layer 40 is common to assembly 10 of pixels. Preferably, layer 40 is common to all pixels of the device.

[0047] The layer 40 includes quantum dots. The quantum dots of the layer 40 are, for example, located in a layer made of a material other than a semiconductor material, for example, made of an electrically insulating material, for example, made of a resin.

[0048] By quantum dots, it is meant that each quantum dot forms a confinement domain in all dimensions (i.e. in the three dimensions of space) by quantum effects. Each quantum dot therefore preferably has a size in all directions in the order of tens of nanometers, in other words, less than 100 nm, preferably in the range of from 2 nm to 15 nm.

[0049] Each quantum dot includes a core made of a semiconductor material (e.g., made of lead sulfide). The core preferably has a size in all directions on the order of tens of nanometers, in other words, less than 100 nm. Each quantum dot also includes a ligand extending from the core. The ligand is preferably made of an organic aliphatic molecule or a metal-organic and inorganic molecule.

[0050] Due to their net charge and their dipole moment, the ligands modify the effective doping of the quantum dot layer and its electron affinity. For example, the ligands of the quantum dots of layer 40 may be molecules acting as N-type dopants, for example organic molecules such as thiolates.

[0051] The layer 40 forms a photodiode. In other words, when light at the operating wavelength of the layer 40 is absorbed by the layer 40 depending on the quantum dots, the layer 40 generates electric charges in the layer.

[0052] The material forming the quantum dots and the size of each quantum dot (especially the size of the semiconductor core) determine the absorption wavelength of the quantum dots, i.e. the operating wavelength of the photodiode. The operating wavelength corresponds, for example, to the near infrared, i.e. to a wavelength in the range from 700 nm to 1.6 mm. The operating wavelength may also correspond to the mid-infrared, i.e. to a wavelength in the range from 1.6 μm to 4 μm, or to the visible light range, i.e. to a wavelength in the range from 300 nm to 700 nm.

[0053] It is possible to select the operating wavelength in a wavelength range that is larger than the possible wavelength range of a standard photodiode (i.e. a photodiode that does not include a quantum dot layer). In fact, the quantum dot layer corresponds to an absorption curve with a peak that is significantly located at a wavelength that depends on the material of the quantum dots and can be any wavelength in a wavelength range that includes at least a wavelength from 300 nm to 4 μm.

[0054] For example, layer 40 includes a single type of quantum dots. In other words, all quantum dots of layer 40 have, for example, a core made of the same material and ligands made of the same material. Preferably, layer 40 is homogeneous. In other words, the composition of layer 40 is preferably the same throughout layer 40.

[0055] Layer 40 includes different regions 42, 44. Each pixel 14 includes region 44. Each pixel 12 includes region 42. Each region 42 is a portion of layer 40 that generates charge for a corresponding pixel 12. Similarly, each region 44 is a portion of layer 40 that generates charge for a corresponding pixel 14.

[0056] Each pixel comprises, for example, a mechanism for attracting the charges generated in the entire area. For example, each pixel comprises a first layer for extracting electrons, called an electrode, respectively holes (not shown), in contact with the lower surface of layer 40. Each pixel comprises, for example, a second layer for extracting holes, called an electrode, respectively electrons, in contact with the upper surface of layer 40. The second extraction layer is transparent for the operating wavelength of the pixel covered by the second layer. The first and second extraction layers are made, for example, of doped silicon, for example, in the case of the first layer, formed by a doped region of substrate 28, or by a metal oxide, for example, by TiO x 、ZnO、AZO、IGZO、MoO x 、CoO、CuO x NiO x For example, each pixel includes a mechanism for attracting charge toward the circuitry corresponding to the pixel located in substrates 20 and 28.

[0057] Thus, during operation of the device, electric charge is generated throughout the layer 40. The electric charge located in each region 42, 44 is attracted by the described mechanism towards the circuit corresponding to the pixel associated with the region 42, 44.

[0058] Region 42 has a shape of, for example, a rectangle, preferably a square, with a tapered angle. The tapered angles of the four regions 42 face the same point, i.e., the center of the assembly, so that the portion of layer 40 located between the tapered angles and at the center of the assembly forms region 44. Therefore, region 42 includes, in the same pixel row, two parallel sides, one shorter than the other, the short sides touching each other. Similarly, region 42 includes, in the same pixel column, i.e., in a direction relative to the row direction, two parallel sides, one shorter than the other, the short sides touching each other. Each region 42 also includes a side coupled to the shorter side of the region 42, the side corresponding to a side of region 44. Region 44 is therefore a quadrilateral in the top view. Therefore, region 44 is completely surrounded by region 42.

[0059] The components 10 are arranged in an array in a device, for example. Preferably, each component 10 comprises pixels separated from pixels of other components. Thus, each pixel 14 is separated from a pixel 14 of another component, for example, by pixels 12 of two components 10.

[0060] In the operating mode of the device, the pixels can be operated in a non-simultaneous manner to be able to generate event-based images and light intensity images at different times. When only event-based images are generated, only the event-based sensor is operated and then all charges are collected by the charge extraction layer located in the corresponding pixel. This is allowed by the continuity of layer 40, etc. This enables the sensitivity and speed of the event-based sensor to be improved without losing spatial and spectral aliasing information.

[0061] In another operating mode, the event-based sensor is turned off and the charge photogenerated in the event-based pixels is distributed between adjacent pixels.

[0062] In another operating mode, both types of sensors can also be operated simultaneously, with the electric field generated by each electrode allowing charge collection without electrical crosstalk between pixels.

[0063] Figure 3 An example of a pixel control circuit is shown. More specifically, Figure 3 Pixel 12 and pixel 14 are schematically shown.

[0064] Pixel 12 includes a photodiode 50. Photodiode 50 corresponds to portion 42 of layer 40 associated with said pixel 12. Photodiode 50 includes a terminal (eg, cathode) coupled (preferably connected) to a node to which bias voltage Vbias is applied, for example via a doped well of substrate 28 of chip 18.

[0065] The pixel 12 also includes control circuitry for the pixel 12. The control circuitry for the pixel 12 includes control circuitry 52 (RS / GS) for the photodiode 50. Each photodiode 50, i.e., each pixel 12, for example, includes circuitry 52. ​​Circuitry 52 is located in the substrate 28, preferably completely in the substrate 28. The pixel photodiode 50 is coupled (preferably connected) to the circuitry 52.

[0066] The circuit 54 is located in the substrate 28. The circuit 54 is an analog-to-digital converter (ADC). The circuit 54 is preferably completely in the substrate 28. The circuit 54 is, for example, common to a plurality of pixels 12, for example, common to all pixels 12 of the assembly 10, for example, common to only the pixels 12 of the assembly 10. The circuit 54 is, for example, coupled (preferably connected) to the circuit 52.

[0067] Circuit 56 is located in substrate 28. Circuit 56 is a pixel readout (RO) circuit, such as a readout circuit of assembly 10. Circuit 56 is preferably entirely in substrate 28. Circuit 56 is, for example, common to a plurality of pixels 12, such as common to all pixels 12 of assembly 10, such as common to only pixels 12 of assembly 10. Circuit 56 is, for example, coupled (preferably connected) to circuit 54. Circuit 56 delivers a value representing the brightness of one or more pixels 12 (e.g., pixels 12 of assembly 10) on output 58.

[0068] Pixel 14 includes a photodiode 60. Photodiode 60 corresponds to portion 44 of layer 40 associated with said pixel 14. Photodiode 60 includes a terminal (e.g., cathode) coupled (preferably connected) to a node to which bias voltage Vbias is applied, e.g., via a doped well of substrate 28 of chip 18.

[0069] The pixel 14 includes a control circuit for the pixel 14. The control circuit for the pixel 14 includes, for example, a circuit (log) 62 having a function that applies a logarithm to the value obtained by the photodiode 60. The circuit 62 is, for example, coupled (preferably connected) to the anode of the photodiode 60. The circuit 62 is, for example, located in the substrate 28, preferably completely located in the substrate 28.

[0070] Pixel 14 includes circuit (SF) 64. Circuit 64 is an amplifier (e.g., common drain type) including, for example, a source-follower circuit. Circuit 64 is, for example, coupled (preferably connected) to circuit 62. Circuit 64 is, for example, located in substrate 28, preferably completely located in substrate 28.

[0071] The control circuitry of the pixel 14 also includes other components located in the substrate 20. The control circuitry of the pixel 14 includes, for example, an amplifier (A) 66 coupled (preferably connected) to the circuitry 64. The control circuitry of the pixel 14 also includes a logic circuit 68, such as a high pass filter, associated with a memory 70. The circuitry 68 is coupled (preferably connected) to the amplifier 66 to receive as input a signal amplified by the amplifier 66. The memory circuit (MEM) 70 is configured to contain the value obtained by the logic circuit 68.

[0072] Similarly, the control circuitry of pixel 14 includes another logic circuit 72, such as a high pass filter, associated with a memory circuit (MEM) 74. Circuit 72 is coupled (preferably connected) to amplifier 66 to receive as input the signal amplified by amplifier 66. Memory 74 is configured to contain the value obtained by logic circuit 72.

[0073] According to an embodiment, the amplifier 66 is configured to be reset, for example, depending on the output values ​​of the circuits 68 and 72. For example, the pixel 14 may include a logic circuit (not shown), such as an OR gate. The logic circuit is, for example, in the first integrated circuit chip 16. The logic circuit includes, for example, an input coupled (preferably connected) to the output of the circuit 68, another input coupled (preferably connected) to the output of the circuit 72, and an output coupled (preferably connected) to the input of the amplifier 66. For example, when this logic circuit (not explicitly shown) delivers a first binary value, the amplifier 66 is reset.

[0074] Pixel 14 also includes data processing circuit (DP) 76 and readout circuit (RO) 78. Circuit 76 is, for example, coupled (preferably connected) to memories 70 and 74, and circuit 78 is, for example, coupled (preferably connected) to circuit 76. Circuits 76 and 78 are, for example, common to multiple pixels 14.

[0075] Thus, substrate 28 includes the control circuit of pixel 12, preferably the entire control circuit of pixel 12. Substrate 20 preferably does not include components of the control circuit of pixel 12. Substrate 20 includes at least a portion of the control circuit of pixel 14. Substrate 28 may, for example, include a portion of the control circuit of pixel 14. Components of the control circuit located in different substrates are coupled to each other via interconnection networks 22 and 30. In particular, components of the control circuit of pixel 14 located on substrates 20 and 28 are coupled together via interconnection networks 22 and 30.

[0076] Figure 4A An alternative arrangement of pixel components is shown. More specifically, Figure 4A Components of pixels 12 and 14 are shown (such as Figure 1 and Figure 2 Component) of layer 40 top view.

[0077] exist Figure 4A In the example of , the pixel assembly includes one pixel 14 and three pixels 12, the pixels being arranged in an array. The assembly thus includes a column of two pixels 12 and a column including one pixel 14 and one pixel 12.

[0078] The pixel components are arranged in an array, for example, with other identical components. Each pixel 14 is therefore surrounded by pixels 12 of the component and nearby components.

[0079] Figure 4B Another alternative arrangement of pixel components is shown. More specifically, Figure 4B Components of pixels 12 and 14 are shown (such as Figure 1 and Figure 2 Component) of layer 40 top view.

[0080] exist Figure 4B In the example of , the pixel assembly includes one pixel 14 and eight pixels 12, and the pixels are arranged in an array. The assembly thus includes two columns of three pixels 12 and one column including one pixel 14 and two pixels 12, in such a way that the pixel 14 is surrounded by the pixel 12.

[0081] The pixel components are arranged in an array, for example, with other identical components. Each pixel 14 is thus separated from nearby pixels 14 by at least two pixels 12 .

[0082] An advantage of the described embodiments is that the size of the pixel is not limited by the distances required by via fabrication methods, as is the case in devices where the photodiode is coupled to the substrate via an interconnect network.

[0083] Another advantage of the described embodiments is that dividing the control circuitry over multiple chips enables pixels to be placed closer to each other.

[0084] Another advantage of the previously described embodiments is that the device can deliver event-based images and light intensity images, for example non-simultaneously, with event-based pixels and standard pixels being independently readable.

[0085] Another advantage of the described embodiment is that it is possible to form a full screen through the use of a quantum dot layer. In other words, charges can be generated over the entire surface of the screen. There are no areas between pixels where charges cannot be generated.

[0086] Another advantage of the described embodiment is that, depending on the choice of quantum dots, the range of possible wavelengths is more significant.

[0087] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0088] Finally, based on the indication of the functions given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A device comprising: A component of a pixel, wherein the component of the pixel comprises: a first pixel configured to generate an event-based data element, and a second pixel, the second pixel being configured to generate a light intensity data element, Each of the first and second pixels includes a portion of a layer, the portion forming a photodiode; a first integrated circuit chip, the first integrated circuit chip comprising a first substrate and a first interconnect network; a second integrated circuit chip, the second integrated circuit chip comprising a second substrate and a second interconnect network; wherein the first integrated circuit chip and the second integrated circuit chip are attached to each other via the first interconnect network and the second interconnect network; and Wherein the layer is located on a first surface of the second substrate, the first surface being opposite to a second surface of the second substrate having a second interconnect network located thereon.

2. The device of claim 1, wherein the device is an event-based camera.

3. The device according to claim 1: wherein the first integrated circuit chip includes at least a portion of a control circuit for the first pixel; and The second integrated circuit chip includes a control circuit for the second pixel.

4. The device of claim 3, wherein another portion of the control circuitry of the first pixel is in the second integrated circuit chip. 5 . The apparatus of claim 1 , wherein the first integrated circuit chip and the second integrated circuit chip are attached at the first interconnection network and the second interconnection network by molecular bonds.

6. The device of claim 1, comprising an assembly of a plurality of pixels arranged in an array.

7. The apparatus of claim 6, wherein each pixel assembly comprises four second pixels surrounding one first pixel.

8. The apparatus of claim 6, wherein each pixel assembly comprises eight second pixels surrounding one first pixel.

9. The device of claim 6, wherein the components of each pixel include three second pixels and one first pixel arranged in an array.

10. The device of claim 1, wherein the layer is continuous. The device of claim 1 , wherein the layer completely covers the first side of the second substrate.

12. The device of claim 1, wherein the material of the layer is homogeneous.

13. The device of claim 1, wherein the layer is in contact with the second substrate.

14. The device of claim 1, wherein the layer is made of quantum dots.

15. The device of claim 1, wherein the layer is made of colloidal quantum dots.

16. The device of claim 1, wherein the layer is made of a photosensitive perovskite material based on one of lead or tin.

17. The device of claim 1, wherein the layer is made of a bulk heterojunction formed of a photosensitive organic semiconductor.

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