LED epitaxial wafer and preparation method thereof, LED chip

Abstract

The present invention relates to the field of optoelectronic technology, and discloses an LED epitaxial wafer and a preparation method thereof, comprising the following steps: S1, providing a substrate; S2, sequentially depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate; wherein the P-type GaN layer is prepared by the following method: Step 1, growing a P-type GaN sublayer; Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer; repeating Step 1 and Step 2 at least once to complete the growth of the P-type GaN layer. The LED epitaxial wafer provided by the present invention can improve the luminous efficiency.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to an LED epitaxial wafer and a preparation method thereof, and an LED chip. Background Art

[0002] LED chips are semiconductor electronic components that can emit light. They are small in size, high in brightness, and low in energy consumption. They are widely used in lighting and other fields. LED chips are obtained by splitting LED epitaxial wafers. LED epitaxial wafers include a substrate and a GaN epitaxial layer grown on the substrate.

[0003] At present, sapphire, silicon or silicon carbide are commonly used as substrates. With the continuous expansion of the application field of LED chips, the performance requirements of chips are getting higher and higher, especially the brightness requirements. The luminous efficiency of chips mainly depends on the epitaxy, so how to further improve the luminous efficiency of epitaxial wafers has become the current technical bottleneck. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for preparing an LED epitaxial wafer, which improves the luminous efficiency.

[0005] The technical problem to be solved by the present invention is also to provide an LED epitaxial wafer with good light-emitting performance.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an LED epitaxial wafer, comprising the following steps:

[0007] S1. providing a substrate;

[0008] S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence;

[0009] Wherein, the P-type GaN layer is prepared by the following method:

[0010] Step 1, growing a P-type GaN sublayer;

[0011] Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer;

[0012] Repeat step 1 and step 2 at least once to complete the growth of the P-type GaN layer.

[0013] In some embodiments, step 1 and step 2 are repeated 1 to 10 times.

[0014] In some embodiments, the annealing treatment takes 10 seconds to 30 seconds.

[0015] In some embodiments, the flow rate of the TMIn is 100 sccm to 500 sccm.

[0016] In some embodiments, the growth temperature of the P-type GaN layer is 800° C. to 1000° C., and the growth pressure is 100 torr to 500 torr.

[0017] In some embodiments, the P-type GaN layer has a thickness of 5 nm to 100 nm.

[0018] In some embodiments, the thickness of the P-type GaN sublayer is 1 nm to 20 nm.

[0019] In some embodiments, the P-type GaN sublayer is prepared by the following method:

[0020] The growth temperature of the reaction chamber is 800° C. to 1000° C., the growth pressure is 100 torr to 500 torr, N2 is introduced as a carrier gas, TEGa is used as a Ga source, NH3 is used as a N source, and Cp2Mg is used as a doping source to react and grow a P-type GaN sublayer.

[0021] In order to solve the above problems, the present invention provides an LED epitaxial wafer, and the LED epitaxial wafer is prepared by the LED epitaxial wafer preparation method.

[0022] Correspondingly, the present invention further provides an LED chip, wherein the LED chip includes the LED epitaxial wafer.

[0023] The implementation of the present invention has the following beneficial effects:

[0024] The light-emitting principle of LED is that electrons and holes recombine and emit light at the MQW, and the electron concentration is much greater than the hole concentration. Therefore, increasing the hole concentration can improve the recombination efficiency and the luminescence efficiency. The holes are provided by the P-type doped GaN layer. Usually, the P-type doping is obtained by doping Mg, and Mg atoms are particularly easy to form Mg-H complexes with H atoms, which will greatly affect the hole concentration. The preparation method provided by the present invention anneals the P-type GaN sublayer by passing N2 and TMIn. On the one hand, high-temperature annealing can break the Mg-H bond to obtain holes, thereby increasing the hole concentration. On the other hand, an appropriate amount of TMIn is passed into the annealing layer, and TMIn will decompose In atoms. In atoms can capture free H atoms, reduce Mg-H complexes, and increase hole concentration. In the preparation process of the P-type GaN layer of the present invention, the growth of the P-type doped GaN layer and the annealing treatment occur alternately, which can increase the hole concentration, and finally increase the recombination probability of electrons and holes in the multi-quantum well layer, and improve the luminescence efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic structural diagram of the LED epitaxial wafer provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0031] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0032] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0033] To solve the above problems, the present invention provides a method for preparing an LED epitaxial wafer, such as Figure 1 As shown, the following steps are included:

[0034] S1, providing a substrate 100;

[0035] S2, sequentially depositing a buffer layer 200, an N-type GaN layer 300, a multi-quantum well layer 400, and a P-type GaN layer 500 on the substrate 100;

[0036] Wherein, the P-type GaN layer is prepared by the following method:

[0037] Step 1, growing a P-type GaN sublayer;

[0038] Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer;

[0039] Repeat step 1 and step 2 at least once to complete the growth of the P-type GaN layer.

[0040] The light-emitting principle of LED is that electrons and holes recombine and emit light at the MQW, and the electron concentration is much greater than the hole concentration. Therefore, increasing the hole concentration can improve the recombination efficiency and the luminescence efficiency. The holes are provided by the P-type doped GaN layer. Usually, the P-type doping is obtained by doping Mg, and Mg atoms are particularly easy to form Mg-H complexes with H atoms, which will greatly affect the hole concentration. The preparation method provided by the present invention anneals the P-type GaN sublayer by passing N2 and TMIn. On the one hand, high-temperature annealing can break the Mg-H bond to obtain holes, thereby increasing the hole concentration. On the other hand, an appropriate amount of TMIn is passed into the annealing layer, and TMIn will decompose In atoms. In atoms can capture free H atoms, reduce Mg-H complexes, and increase hole concentration. In the preparation process of the P-type GaN layer of the present invention, the growth of the P-type doped GaN layer and the annealing treatment occur alternately, which can increase the hole concentration, and finally increase the recombination probability of electrons and holes in the multi-quantum well layer, and improve the luminescence efficiency.

[0041] Specifically, the method for preparing the LED epitaxial wafer comprises the following steps:

[0042] S1, providing a substrate 100;

[0043] In some embodiments, the substrate 100 may be selected from one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate. Preferably, the substrate 100 is a sapphire substrate, which is a commonly used GaN-based LED substrate material. The sapphire substrate has a mature preparation process, a low price, is easy to clean and handle, and has good stability at high temperatures.

[0044] S2, sequentially depositing a buffer layer 200, an N-type GaN layer 300, a multi-quantum well layer 400, and a P-type GaN layer 500 on the substrate 100;

[0045] Specifically, the above step S2 specifically includes the following steps:

[0046] S21 , depositing the buffer layer 200 on the substrate 100 .

[0047] In some embodiments, an AlN buffer layer is deposited in an applied material PVD process. The AlN buffer layer provides nucleation centers with the same orientation as the substrate, releases the stress caused by the lattice mismatch between GaN and the substrate and the thermal stress caused by the mismatch in thermal expansion coefficients, provides a flat nucleation surface for further growth, reduces the contact angle of nucleation growth, and enables the island-like grown GaN grains to be connected into a surface within a smaller thickness, thus transforming into two-dimensional epitaxial growth.

[0048] S22 , depositing the N-type GaN layer 300 on the buffer layer 200 .

[0049] In some embodiments, the temperature of the reaction chamber is controlled at 1000° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Ga source, and a Si source are introduced to grow the N-type GaN layer.

[0050] S23 , depositing the multi-quantum well layer 400 on the N-type GaN layer 300 .

[0051] In some embodiments, the multi-quantum well layer is an alternately stacked InGaN quantum well layer and a GaN quantum barrier layer, with a stacking period number of 1 to 20. The growth temperature of the InGaN quantum well layer is 790°C to 810°C, the thickness is 2nm to 5nm, and the growth pressure is 50torr to 300torr; the growth temperature of the GaN quantum barrier layer is 800°C to 900°C, the thickness is 5nm to 15nm, and the growth pressure is 50torr to 300torr.

[0052] S24 , depositing the P-type GaN layer 500 on the multi-quantum well layer 400 .

[0053] The P-type GaN layer is prepared by the following method:

[0054] Step 1, growing a P-type GaN sublayer;

[0055] Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer;

[0056] Repeat step 1 and step 2 at least once to complete the growth of the P-type GaN layer.

[0057] In some embodiments, step 1 and step 2 are repeated 1 to 10 times. Exemplarily, step 1 and step 2 are repeated 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 times.

[0058] In some embodiments, the annealing treatment time is 10s to 30s. Exemplary annealing treatment time is 12s, 14s, 16s, 18s, 20s, 22s, 24s, 26s, 28s, but is not limited to the above.

[0059] In some embodiments, the flow rate of TMIn is 100 sccm to 500 sccm. Exemplary flow rates of TMIn are 130 sccm, 160 sccm, 200 sccm, 230 sccm, 260 sccm, 300 sccm, 330 sccm, 360 sccm, 400 sccm, 430 sccm, 460 sccm, but are not limited to the above.

[0060] In some embodiments, the growth temperature of the P-type GaN layer is 800° C. to 1000° C., and the growth pressure is 100 torr to 500 torr. Preferably, the growth temperature of the P-type GaN layer is 850° C. to 950° C., and the growth pressure is 150 torr to 450 torr.

[0061] In some embodiments, the thickness of the P-type GaN layer is 5nm to 100nm. The exemplary thickness of the P-type GaN layer is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, not limited to the above. In some embodiments, the thickness of the P-type GaN sublayer is 1nm to 20nm. The exemplary thickness of the P-type GaN sublayer is 12nm, 14nm, 16nm, 18nm, not limited to the above.

[0062] In some embodiments, the P-type GaN sublayer is prepared by the following method:

[0063] The growth temperature of the reaction chamber is 800° C. to 1000° C., the growth pressure is 100 torr to 500 torr, N2 is introduced as a carrier gas, TEGa is used as a Ga source, NH3 is used as a N source, and Cp2Mg is used as a doping source to react and grow a P-type GaN sublayer.

[0064] Accordingly, the present invention also provides an LED chip, which includes the above-mentioned LED epitaxial wafer. The LED epitaxial wafer is the basic material for manufacturing LED chips, and the quality and characteristics of the LED epitaxial wafer directly affect the performance and output of the final LED chip.

[0065] The present invention is further described below with specific embodiments:

[0066] Example 1

[0067] This embodiment provides a method for preparing an LED epitaxial wafer, comprising the following steps:

[0068] S1. providing a substrate;

[0069] S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence;

[0070] Wherein, the P-type GaN layer is prepared by the following method:

[0071] Step 1, growing a P-type GaN sublayer;

[0072] Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer;

[0073] Repeat step 1 and step 2 for 5 times to complete the growth of the P-type GaN layer.

[0074] The thickness of the P-type GaN layer is 50 nm, the annealing time is 20 s, and the flow rate of TMIn is 300 sccm.

[0075] Example 2

[0076] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the embodiment 1 in that the annealing treatment time is 10 seconds, and the rest is the same as the embodiment 1.

[0077] Example 3

[0078] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the first embodiment in that the annealing time is 30 seconds, and the rest is the same as the first embodiment.

[0079] Example 4

[0080] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the first embodiment in that the flow rate of TMIn is 100 sccm, and the rest is the same as the first embodiment.

[0081] Example 5

[0082] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the first embodiment in that the flow rate of TMIn is 200 sccm, and the rest is the same as the first embodiment.

[0083] Example 6

[0084] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the first embodiment in that the flow rate of TMIn is 400 sccm, and the rest is the same as the first embodiment.

[0085] Example 7

[0086] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from the first embodiment in that the flow rate of TMIn is 500 sccm, and the rest is the same as the first embodiment.

[0087] Example 8

[0088] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from Embodiment 1 in that: Step 1 and Step 2 are repeated once in total, and the rest is the same as Embodiment 1.

[0089] Example 9

[0090] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from Embodiment 1 in that: Step 1 and Step 2 are repeated 3 times in total, and the rest is the same as Embodiment 1.

[0091] Example 10

[0092] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from Embodiment 1 in that: Step 1 and Step 2 are repeated 7 times in total, and the rest is the same as Embodiment 1.

[0093] Embodiment 11

[0094] This embodiment provides a method for preparing an LED epitaxial wafer, which is different from Embodiment 1 in that: Step 1 and Step 2 are repeated 10 times in total, and the rest is the same as Embodiment 1.

[0095] Comparative Example 1

[0096] This comparative example provides a method for preparing an LED epitaxial wafer, which is different from Example 1 in that the annealing time is 5 seconds, and the rest is the same as Example 1.

[0097] Comparative Example 2

[0098] This comparative example provides a method for preparing an LED epitaxial wafer, which is different from Example 1 in that the annealing time is 35 seconds, and the rest is the same as Example 1.

[0099] Comparative Example 3

[0100] This comparative example provides a method for preparing an LED epitaxial wafer, which is different from Example 1 in that the flow rate of TMIn is 50 sccm, and the rest is the same as Example 1.

[0101] Comparative Example 4

[0102] This comparative example provides a method for preparing an LED epitaxial wafer, which is different from Example 1 in that the flow rate of TMIn is 600 sccm, and the rest is the same as Example 1.

[0103] Comparative Example 5

[0104] This comparative example provides a method for preparing an LED epitaxial wafer, which is different from Example 1 in that: Step 1 and Step 2 are repeated 12 times in total, and the rest is the same as Example 1.

[0105] Comparative Example 1

[0106] This comparative example provides a method for preparing an LED epitaxial wafer, comprising the following steps:

[0107] S1. providing a substrate;

[0108] S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence;

[0109] Wherein, the P-type GaN layer is prepared by the following method:

[0110] The growth temperature of the reaction chamber is 800° C. to 1000° C., the growth pressure is 100 torr to 500 torr, N2 is introduced as a carrier gas, TEGa is used as a Ga source, NH3 is used as a N source, and Cp2Mg is used as a doping source to react and grow a P-type GaN layer.

[0111] The LED epitaxial wafers prepared in Examples 1 to 11, Comparative Examples 1 to 5 and Comparative Example 1 were used to prepare LED chips using the same chip process conditions. The chip size was 22 mil*35 mil, and the test current was 60 mA. The specific test results are shown in Table 1.

[0112] Table 1 Performance test results of LED chips prepared in Examples 1 to 11, Comparative Examples 1 to 5 and Comparative Example 1

[0113]

[0114] The preparation method provided by the present invention anneals the P-type GaN sublayer by introducing N2 and TMIn. On the one hand, high-temperature annealing can break the Mg-H bond to obtain holes, thereby increasing the hole concentration. On the other hand, an appropriate amount of TMIn is introduced into the annealing layer, and TMIn decomposes In atoms, which can capture free H atoms, reduce Mg-H complexes, and increase the hole concentration. In the preparation process of the P-type GaN layer of the present invention, the growth of the P-type doped GaN layer and the annealing treatment occur alternately, which can increase the hole concentration, and ultimately increase the recombination probability of electrons and holes in the multi-quantum well layer, thereby improving the luminous efficiency.

[0115] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0116] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for preparing an LED epitaxial wafer, characterized in that: The following steps are involved: S1. providing a substrate; S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence; Wherein, the P-type GaN layer is prepared by the following method: Step 1, growing a P-type GaN sublayer; Step 2, introducing N2 and TMIn to anneal the P-type GaN sublayer; Repeat step 1 and step 2 at least once to complete the growth of the P-type GaN layer.

2. The method for preparing an LED epitaxial wafer according to claim 1, wherein: Repeat steps 1 and 2 1 to 10 times.

3. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that: The annealing treatment time is 10s to 30s.

4. The method for preparing an LED epitaxial wafer according to claim 1, wherein: The flow rate of TMIn is 100 sccm to 500 sccm.

5. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that: The growth temperature of the P-type GaN layer is 800° C. to 1000° C., and the growth pressure is 100 torr to 500 torr.

6. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that: The thickness of the P-type GaN layer is 5nm-100nm.

7. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that: The thickness of the P-type GaN sublayer is 1 nm to 20 nm.

8. The method for preparing an LED epitaxial wafer according to claim 1, characterized in that: The P-type GaN sublayer is prepared by the following method: The growth temperature of the reaction chamber is 800° C. to 1000° C., the growth pressure is 100 torr to 500 torr, N2 is introduced as a carrier gas, TEGa is used as a Ga source, NH3 is used as a N source, and Cp2Mg is used as a doping source to react and grow a P-type GaN sublayer.

9. An LED epitaxial wafer, characterized in that: The LED epitaxial wafer is prepared by the method for preparing an LED epitaxial wafer according to any one of claims 1 to 8.

10. An LED chip, characterized in that: The LED chip comprises the LED epitaxial wafer as claimed in claim 9.

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