Gate tube and manufacturing method thereof

Abstract

The invention relates to a gate tube and a manufacturing method thereof. The gate tube includes: a first electrode; the gate layer is arranged on the first electrode, and the bottom surface of the gate layer is in contact with the first electrode; a second electrode disposed on the gate layer, a top surface of the gate layer being in contact with the second electrode; and the passivation layer at least covers the side wall of the gate layer, the thermal conductivity of the passivation layer is smaller than that of the gate layer, and the conductivity of the passivation layer is smaller than that of the gate layer. The passivation layer can prevent heat from being transmitted to the external environment from the gate tube, so that the temperature of the gate layer can be increased more quickly, the gate tube can reach the starting temperature more quickly, the starting time of the gate tube is shortened, the starting voltage of the gate tube is reduced, the reading voltage of the gate tube is also reduced, and the leakage current of the gate tube is reduced; in addition, the passivation layer is low in heat conductivity and has good insulation performance, the electric leakage risk of the gate tube can be further reduced, current is prevented from flowing among different devices, and therefore electric crosstalk among the devices is avoided.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a gate tube and a manufacturing method thereof. Background Art

[0002] In the context of the big data era, the vigorous development of cutting-edge technologies such as smart cities and autonomous driving has put forward more stringent requirements for data storage devices, including faster data access speeds, lower energy consumption, and higher storage capacity. However, current traditional storage technologies face many challenges and are difficult to meet these requirements. Traditional memories are difficult to match the data processing speed of the processor in terms of read and write speeds, which has become a key factor restricting the improvement of the overall performance of the system. Traditional memories such as DRAM need to continuously refresh the charge when working, which not only leads to higher energy consumption, but also increases the complexity and maintenance cost of the system. In addition, with the continuous reduction of process nodes, the production cost and process complexity of memory have risen sharply, further limiting the improvement of storage density.

[0003] As a nonlinear threshold switching device, the gate transistor has attracted much attention due to its simple structure, low energy consumption, easy integration and flexible design. When the gate transistor forms a storage unit with the memory and realizes three-dimensional integration, it provides a new solution for storage and neuromorphic computing systems.

[0004] However, although the gate tube has the advantages of low power consumption, high switching speed and high-density integration, it will have a leakage current of uA level in the non-conducting state. This leakage current problem will not only lead to a significant increase in energy consumption in large-scale integrated circuits, but may also affect the non-volatile characteristics of the memory, causing the memory to lose stored data when there is no power. In addition, in order to reduce the leakage current, a more complex manufacturing process may be required, which will undoubtedly increase the production cost and process complexity, thereby limiting the development and application of the gate tube. Summary of the invention

[0005] Based on this, it is necessary to provide a gate tube and a manufacturing method thereof to address the problems of gate tube leakage current, high production cost and high process complexity in the prior art.

[0006] In a first aspect, the present disclosure provides a gating tube, the gating tube comprising:

[0007] a first electrode;

[0008] A gating layer, disposed on the first electrode, wherein a bottom surface of the gating layer contacts the first electrode;

[0009] A second electrode is disposed on the gating layer, and a top surface of the gating layer is in contact with the second electrode;

[0010] A passivation layer at least covers a side wall of the gating layer, wherein the thermal conductivity of the passivation layer is smaller than the thermal conductivity of the gating layer, and the electrical conductivity of the passivation layer is smaller than the electrical conductivity of the gating layer.

[0011] Optionally, the passivation layer further covers a top surface of the gating layer that is not covered by the second electrode.

[0012] Optionally, the passivation layer also covers a bottom surface of the gating layer that is not covered by the first electrode.

[0013] Optionally, the thermal conductivity of the passivation layer is 0.1 W / m·K-25 W / m·K; the electrical conductivity of the passivation layer is 10 - 8 S / m to 10 -16 S / m;

[0014] The material of the passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0015] Optionally, the gate tube is arranged on a substrate, and the top surface of the substrate is covered with a first dielectric layer;

[0016] The first electrode is arranged in the first dielectric layer, and extends from the top surface of the first dielectric layer to the top surface of the substrate; the gating layer and the second electrode are sequentially stacked on a side of the first electrode away from the substrate.

[0017] Optionally, an insulating layer is provided on a side of the first dielectric layer away from the substrate, the insulating layer covers a side wall of the gating layer and a side wall of the second electrode, and the insulating layer is separated from the gating layer by the passivation layer.

[0018] In a second aspect, the present disclosure provides a method for manufacturing a gating tube, comprising:

[0019] Providing a substrate, wherein the substrate is covered with a first dielectric layer;

[0020] forming a first hole on the first dielectric layer, and forming a first electrode in the first hole;

[0021] forming a gating layer on the first electrode layer, wherein a bottom surface of the gating layer contacts the first electrode;

[0022] forming a passivation layer, wherein the passivation layer at least covers the sidewalls of the gating layer and the top surface of the gating layer; and the conductivity of the passivation layer is less than the conductivity of the gating layer;

[0023] removing at least a portion of the passivation layer on the top surface of the gating layer to expose at least a portion of the top surface of the gating layer;

[0024] A second electrode is formed, the second electrode covering the exposed top surface of the gate layer, the second electrode being in contact with the top surface of the gate layer.

[0025] Optionally, before forming the first hole, a first passivation layer is formed, the first passivation layer covers the top surface of the first dielectric layer, and the first passivation layer and the first dielectric layer are etched to form the first hole; a portion of the bottom surface of the gating layer is connected to the first passivation layer, and the gating layer and the first dielectric layer are separated by the first passivation layer;

[0026] After forming the gate layer, a second passivation layer is formed to cover the sidewalls and the top surface of the gate layer.

[0027] Optionally, it also includes:

[0028] forming an insulating layer, the insulating layer covering the gating layer, the insulating layer and the gating layer being separated by the passivation layer;

[0029] The insulating layer is etched to expose a portion of the top surface of the gating layer to form a second hole, and the second electrode is formed in the second hole.

[0030] Optionally, the thermal conductivity of the passivation layer is 0.1 W / m·K-25 W / m·K; the electrical conductivity of the passivation layer is 10 - 8 S / m to 10 -16 S / m;

[0031] The material of the passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0032] The gate tube and its manufacturing method disclosed in the present invention are provided with a passivation layer on the side wall of the gate layer. On the one hand, the passivation layer has a smaller thermal conductivity than the gate layer, and the passivation layer can prevent heat from being transferred from the gate tube to the external environment, so that the gate layer can be heated up faster, the gate tube can reach the opening temperature faster, and the opening time of the gate tube is shortened; at the same time, because the heat is not easy to dissipate, the gate tube can reach the opening condition at a lower voltage, the opening voltage of the gate tube is reduced, and the reading voltage of the gate tube is also reduced accordingly, which is beneficial to reducing the leakage current of the gate tube; on the other hand, the passivation layer has a low thermal conductivity and good insulation performance, which can further reduce the leakage risk of the gate tube, avoid the current flowing between different devices, and thus avoid electrical crosstalk between devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a schematic structural diagram of a gating tube provided in an embodiment;

[0035] Figure 2 is a schematic structural diagram of a gating tube provided in yet another embodiment;

[0036] Figure 3 It is a schematic diagram of the structure of a gating tube provided in another embodiment;

[0037] Figure 4 is a process flow chart of a method for manufacturing a gating tube provided in an embodiment;

[0038] Figure 5 is a schematic structural diagram of a substrate provided in an embodiment;

[0039] Figure 6 is a schematic diagram of a structure after a first passivation layer is formed provided in an embodiment;

[0040] Figure 7 A schematic diagram of a structure after a first hole is formed provided in an embodiment;

[0041] Figure 8 A schematic diagram of a structure after a first electrode is formed in a first hole provided in an embodiment;

[0042] Fig. 9 A schematic diagram of a structure after a gating layer is formed on a first electrode provided in an embodiment;

[0043] Fig.10 is a schematic diagram of a structure after forming a second passivation layer provided in an embodiment;

[0044] Fig.11 is a schematic diagram of a structure after an insulating layer is formed provided in an embodiment;

[0045] Fig.12 It is a schematic diagram of the structure after forming the second hole provided in one embodiment.

[0046] Description of reference numerals:

[0047] 10. gating tube; 11. first electrode; 12. gating layer; 13. second electrode; 14. passivation layer; 141. first passivation layer; 142. second passivation layer; 15. insulating layer; 151. first insulating layer; 152. second insulating layer; 20. substrate; 20a. front device layer; 30. first dielectric layer; 101. first hole; 102. second hole. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] According to an exemplary embodiment, the present disclosure provides a gate tube 10, referring to Figure 1 , Figure 2 or Figure 3 As shown, the gate tube 10 includes a first electrode 11, a gate layer 12 and a second electrode 13; the gate layer 12 is arranged on the first electrode 11, and the bottom surface of the gate layer 12 is in contact with the first electrode 11; the second electrode 13 is arranged on the gate layer 12, and the top surface of the gate layer 12 is in contact with the second electrode 13; the passivation layer 14 at least covers the side wall of the gate layer 12, the thermal conductivity of the passivation layer 14 is less than the thermal conductivity of the gate layer 12, and the electrical conductivity of the passivation layer 14 is less than the electrical conductivity of the gate layer 12.

[0051] In the gate tube 10 of the present embodiment, a passivation layer 14 is provided on the side wall of the gate layer 12. On the one hand, the passivation layer 14 has a smaller thermal conductivity than the gate layer 12, and the passivation layer 14 can prevent heat from being transferred from the gate tube 10 to the external environment, so that the gate layer 12 can be heated up faster, and the gate tube 10 can reach the opening temperature faster, thereby shortening the opening time of the gate tube 10; at the same time, since heat is not easy to dissipate, the gate tube 10 can reach the opening condition at a lower voltage, the opening voltage of the gate tube 10 is reduced, and the reading voltage of the gate tube 10 is also reduced accordingly, which is beneficial to reducing the leakage current of the gate tube 10; on the other hand, the passivation layer 14 has a low thermal conductivity and good insulation performance, which can further reduce the leakage risk of the gate tube 10, avoid the current flowing between different devices, and thus avoid electrical crosstalk between devices.

[0052] In some embodiments, reference Figure 1 , Figure 2 or Figure 3 As shown, the passivation layer 14 also covers the top surface of the gating layer 12 that is not covered by the second electrode 13. In this way, the passivation layer 14 can prevent the top surface of the gating layer 12 from transferring heat outward, further limit the heat loss of the gating layer 12, further improve the heating rate of the gating layer 12, shorten the opening time of the gating tube 10, reduce the opening voltage and reading voltage of the gating tube 10, reduce the leakage current of the gating tube 10, and optimize the switching performance of the gating tube 10; at the same time, the passivation layer 14 covers the top surface of the gating layer 12, and also enhances the protective effect of the passivation layer 14 on the gating layer 12, which can further reduce the risk of electrical crosstalk or short circuit between the gating layer 12 and other devices.

[0053] In some embodiments, reference Figure 2 or Figure 3 As shown, the passivation layer 14 also covers the bottom surface of the gating layer 12 that is not covered by the first electrode 11. In this way, the passivation layer 14 can provide more comprehensive protection for the gating layer 12, optimize the thermal management of the gating layer 12, and further optimize the switching performance of the gating transistor 10. At the same time, the passivation layer 14 can reduce the risk of electrical crosstalk or short circuit between the gating layer 12 and other devices.

[0054] In some embodiments, the thermal conductivity of the passivation layer 14 is 0.1 W / m·K-25 W / m·K; illustratively, the thermal conductivity of the passivation layer 14 may be 0.1 W / m·K, 1 W / m·K, 3 W / m·K, 5 W / m·K, 8 W / m·K, 10 W / m·K, 12 W / m·K, 13 W / m·K, 15 W / m·K, 18 W / m·K, 20 W / m·K, 22 W / m·K or 25 W / m·K.

[0055] The conductivity of the passivation layer 14 is 10 -8 S / m to 10 -16 S / m. For example, the conductivity of the passivation layer 14 can be 10 -8 S / m, 10 -9 S / m, 10 -10 S / m, 10 -11 S / m, 10 -12 S / m, 10 -13 S / m, 10 -14 S / m, 10 -15 S / m or 10 -16 S / m.

[0056] In some embodiments, the material of the passivation layer 14 includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0057] It is understood that the passivation layer 14 may include a single-layer structure or a multi-layer structure stacked on the surface of the gate layer 12 .

[0058] In one example, the passivation layer 14 includes a silicon oxide layer. In another example, the passivation layer 14 includes a silicon oxide layer and a silicon nitride layer sequentially covering the surface of the gate layer 12. In yet another example, the passivation layer 14 includes a silicon oxide layer, a silicon nitride layer, and a silicon carbide layer sequentially covering the surface of the gate layer 12.

[0059] In some embodiments, the material of the gate layer 12 may include at least one of niobium oxide (NbOx), vanadium oxide (VOx), OTS materials such as aluminum telluride, boron telluride, germanium selenide, germanium sulfide, antimony telluride, GeSeAsIn, GeSeAsN, and GeSeCN.

[0060] The material of the first electrode 11 may include at least one of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), ruthenium (Ru), ruthenium oxide (RuO), iridium (Ir), iridium oxide (IrO2), indium tin oxide (ITO), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), titanium aluminum nitride (TiAlN), hafnium (Hf) or copper (Cu).

[0061] The selection range of the material of the second electrode 13 is the same as that of the first electrode 11 , and will not be described in detail herein.

[0062] In some embodiments, reference Figure 1 , Figure 2 or Figure 3 As shown, the gate tube 10 is arranged on the substrate 20, and the top surface of the substrate 20 is covered with a first dielectric layer 30. The first electrode 11 is arranged in the first dielectric layer 30, and the first electrode 11 extends from the top surface of the first dielectric layer 30 to the top surface of the substrate 20; the gate layer 12 and the second electrode 13 are sequentially stacked on the side of the first electrode 11 away from the substrate 20.

[0063] Among them, the substrate 20 can be a semiconductor substrate, which is made of semiconductor materials. The semiconductor material can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as III-V group compounds such as gallium arsenide.

[0064] Reference Figure 1 , Figure 2 or Figure 3As shown, the substrate 20 includes one or more stacked front device layers 20a, and the front device layer 20a can be formed in the substrate 20 or arranged on the substrate 20. Among them, a variety of semiconductor devices and a variety of metal interconnect structures can be arranged in each front device layer 20a. Among them, the semiconductor device can include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device. The first dielectric layer 30 is arranged above the substrate 20, and the first dielectric layer 30 covers the front device layer 20a formed on the substrate 20.

[0065] In this embodiment, a memory is formed on the substrate 20, such as a resistive random access memory (RRAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM), a magnetoresistive random access memory (MRAM) or other types of memory.

[0066] In some embodiments, the gate tube 10 is arranged in one-to-one correspondence with the memory on the substrate 20, the first electrode 11 of the gate tube 10 extends from the top surface of the first dielectric layer 30 toward the substrate 20, the first electrode 11 of the gate tube 10 is electrically connected to the corresponding memory, and the gate tube 10 and the corresponding memory are integrated to form a storage unit of 1S1R architecture. For example, the gate tube 10 can be connected in series with new types of memory such as resistive random access memory (RRAM), phase change memory (PCRAM), magnetoresistive memory (MRAM) and ferroelectric memory (FeRAM) to form a storage unit.

[0067] In some embodiments, the memory is arranged in multiple columns along a direction perpendicular to the substrate 20, the gate tube 10 is arranged one by one with the multiple columns of memory on the substrate 20, the first electrode 11 of the gate tube 10 extends from the top surface of the first dielectric layer 30 toward the substrate 20, the first electrode 11 of the gate tube 10 is connected to the gate wire of the corresponding column of memory, and the gate tube 10 is used to control the gating of each corresponding column of memory. For example, the gate tube 10 can be connected to the NAND string to control the gating of a string of NAND strings.

[0068] In some embodiments, reference Figure 1 , Figure 2 or Figure 3 As shown, an insulating layer 15 is provided on one side of the first dielectric layer 30 away from the substrate 20, and the insulating layer 15 covers the sidewalls of the gate layer 12 and the sidewalls of the second electrode 13, and the insulating layer 15 is separated from the gate layer 12 by the passivation layer 14. The insulating layer 15 is filled between adjacent gate tubes 10, and is used for electrical insulation between adjacent gate tubes 10, so as to avoid electrical crosstalk or short circuit between adjacent gate tubes 10.

[0069] For example, the material of the insulating layer 15 may include a low-K material with a low dielectric constant, such as porous silicon oxide, porous silicon oxycarbon hydride, silicate glass, borophosphosilicate glass or silicon carbon nitride.

[0070] For example, the insulating layer 15 may include a single layer or a multi-layer structure.

[0071] In some embodiments, reference Figure 3 As shown, the insulating layer 15 includes a first insulating layer 151 and a second insulating layer 152 sequentially stacked on the first dielectric layer 30 , the first insulating layer 151 is filled between the gate layers 12 of adjacent gate tubes 10 , and the second insulating layer 152 is filled between the second electrodes 13 of adjacent gate tubes 10 .

[0072] In some embodiments, the passivation layer 14 is further disposed between the insulating layer 15 and the first dielectric layer 30 to enhance the electrical insulation effect between devices.

[0073] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a gate tube, such as Figure 4 As shown, the method for making a gating tube comprises the following steps:

[0074] Step S10: providing a substrate 20, wherein the substrate 20 is covered with a first dielectric layer 30;

[0075] Step S20: forming a first hole 101 on the first dielectric layer 30 and forming a first electrode 11 in the first hole 101;

[0076] Step S30: forming a gating layer 12 on the first electrode 11 layer, wherein the bottom surface of the gating layer 12 is in contact with the first electrode 11;

[0077] Step S40: forming a passivation layer 14, wherein the passivation layer 14 at least covers the sidewalls of the gate layer 12 and the top surface of the gate layer 12; the conductivity of the passivation layer 14 is less than the conductivity of the gate layer 12;

[0078] Step S50: removing at least a portion of the passivation layer 14 on the top surface of the gate layer 12 to expose at least a portion of the top surface of the gate layer 12;

[0079] Step S60 : forming a second electrode 13 , wherein the second electrode 13 covers the exposed top surface of the gate layer 12 , and the second electrode 13 is in contact with the top surface of the gate layer 12 .

[0080] The manufacturing method of the gate tube of the present embodiment forms a passivation layer 14 covering the side wall of the gate layer 12. On the one hand, the passivation layer 14 has a smaller thermal conductivity than the gate layer 12, and the passivation layer 14 can prevent heat from being transferred from the gate tube 10 to the external environment, so that the gate layer 12 can be heated up faster, and the gate tube 10 can reach the opening temperature faster, thereby shortening the opening time of the gate tube 10; at the same time, since heat is not easy to dissipate, the gate tube 10 can reach the opening condition at a lower voltage, the opening voltage of the gate tube 10 is reduced, and the reading voltage of the gate tube 10 is also reduced, which is beneficial to reducing the leakage current of the gate tube 10; on the other hand, the passivation layer 14 has a low thermal conductivity and good insulation performance, which can further reduce the leakage risk of the gate tube 10, avoid the current flowing between different devices, and thus avoid electrical crosstalk between devices.

[0081] In step S10, referring to Figure 5 The substrate 20 may be a semiconductor substrate, which is made of a semiconductor material, and the semiconductor material may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may be other materials with semiconductor properties, such as III-V compounds such as gallium arsenide.

[0082] The substrate 20 includes one or more stacked front device layers 20a, which can be formed in the substrate 20 or arranged on the substrate 20. In each semiconductor device layer, a variety of semiconductor devices and a variety of metal interconnect structures can be arranged. In particular, the semiconductor device can include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device. The first dielectric layer 30 is arranged above the substrate 20, and the first dielectric layer 30 covers the front device layer 20a formed on the substrate 20.

[0083] In this embodiment, a memory is formed on the substrate 20 , such as RRAM, DRAM, SRAM, flash EPROM, FeRAM, PCRAM, MRAM or other types of memory.

[0084] In step S20, referring to Figure 6 , Figure 7First, a photoresist layer is formed on the top surface of the first dielectric layer 30, and an exposure-development process is performed on the photoresist layer, and the patterned photoresist defines the pattern of the first electrode 11. The first dielectric layer 30 is etched according to the patterned photoresist layer to form a first hole 101, and the first hole 101 exposes the top surface of the corresponding memory of the front device layer 20a.

[0085] Then, refer to Figure 8 The conductive material may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or electroplating process, and the conductive material fills the first hole 101 and covers the top surface of the first dielectric layer 30 .

[0086] Then, the conductive material on the first dielectric layer 30 is removed by chemical mechanical polishing (CMP), and the first electrode 11 is formed in the first hole 101 .

[0087] The material of the first electrode 11 may include at least one of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, ruthenium, ruthenium oxide, iridium, iridium oxide, indium tin oxide, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, hafnium or copper.

[0088] For example, the thickness of the first electrode 11 is 10 nm-500 nm.

[0089] In step S30, a gate material layer may be formed by PVD, CVD or ALD deposition, and the gate material layer covers the top surface of the first dielectric layer 30 and the first electrode 11. Then, a photoresist layer is formed on the gate material layer, and the patterned photoresist defines the pattern of the gate layer 12. The gate material layer is etched according to the patterned photoresist layer. Fig. 9 , forming a gate layer 12 which is in contact with the top surface of the first electrode 11 .

[0090] In this embodiment, refer to Fig. 9 The projection of the gating layer 12 formed on the substrate 20 covers the projection of the first electrode 11 formed on the substrate 20 , and the gating layer 12 also covers a portion of the first dielectric layer 30 around the first electrode 11 .

[0091] The material of the gate layer 12 may include at least one of niobium oxide, vanadium oxide, and an OTS material such as aluminum telluride, boron telluride, germanium selenide, germanium sulfide, antimony telluride, GeSeAsIn, GeSeAsN, and GeSeCN.

[0092] In some embodiments, the gating layer 12 has a thickness of 5 nm to 200 nm.

[0093] In step S40, referring to Fig.10 The passivation layer 14 may be formed by atmospheric pressure chemical vapor deposition (APCVD), PECVD, or low pressure chemical vapor deposition (LPCVD). The passivation layer 14 covers the sidewalls and the top surface of the gate layer 12 .

[0094] In some embodiments, the thermal conductivity of the passivation layer 14 is 0.1 W / m·K-25 W / m·K; illustratively, the thermal conductivity of the passivation layer 14 may be 0.1 W / m·K, 1 W / m·K, 3 W / m·K, 5 W / m·K, 8 W / m·K, 10 W / m·K, 12 W / m·K, 13 W / m·K, 15 W / m·K, 18 W / m·K, 20 W / m·K, 22 W / m·K or 25 W / m·K.

[0095] The conductivity of the passivation layer 14 is 10 -8 S / m to 10 -16 S / m. For example, the conductivity of the passivation layer 14 can be 10 -8 S / m, 10 -9 S / m, 10 -10 S / m, 10 -11 S / m, 10 -12 S / m, 10 -13 S / m, 10 -14 S / m, 10 -15 S / m or 10 -16 S / m.

[0096] In some embodiments, the material of the passivation layer 14 includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

[0097] In this embodiment, after step S40 and before step S50, the following steps are further performed:

[0098] Reference Fig.11 , step S40 - 1 : forming an insulating layer 15 , the insulating layer 15 covers the gate layer 12 , and the insulating layer 15 is separated from the gate layer 12 by the passivation layer 14 .

[0099] APCVD, PECVD or LPCVD may be used to deposit an insulating material to cover the passivation layer 14 and fill the region between the gate layers 12 to form the insulating layer 15 .

[0100] For example, the material of the insulating layer 15 may include a low-K material with a low dielectric constant, such as porous silicon oxide, porous silicon oxycarbon hydride, silicate glass, borophosphosilicate glass or silicon carbon nitride.

[0101] For example, the insulating layer 15 may include a single layer or a multi-layer structure.

[0102] In some embodiments, reference Figure 3 A first insulating layer 151 and a second insulating layer 152 are sequentially deposited on the first dielectric layer 30 , wherein the first insulating layer 151 is filled between the gate layers 12 of adjacent gate tubes 10 , and the second insulating layer 152 is formed above the gate layer 12 .

[0103] In step S50, referring to Fig.12 , removing at least a portion of the passivation layer 14 on the top surface of the gating layer 12 to expose at least a portion of the top surface of the gating layer 12, the following implementations may be adopted:

[0104] A photoresist layer is formed on the top surface of the insulating layer 15, and the patterned photoresist layer defines the pattern of the second electrode 13. The insulating layer 15 is etched according to the patterned photoresist layer.

[0105] The insulating layer 15 is etched to expose a portion of the top surface of the gate layer 12, to form a first hole 101, and a second electrode 13 is formed in the first hole 101. Specifically, after the insulating layer 15 is etched according to the patterned photoresist layer, the passivation layer 14 exposed by the first hole 101 is further etched, and the first hole 101 is extended to the top surface of the gate layer 12, so that the second electrode 13 formed in the first hole 101 is in contact with the top surface of the gate layer 12.

[0106] In step S60, referring to Figure 2 As shown, the conductive material may be deposited by PVD, CVD, PECVD, ALD or electroplating process, and the conductive material fills the first hole 101 and covers the top surface of the insulating layer 15. The second electrode 13 is formed after the top surface of the insulating layer 15 is removed by CMP.

[0107] The selection range of the material of the second electrode 13 is the same as that of the first electrode 11 , and will not be described in detail herein.

[0108] For example, the thickness of the second electrode 13 is 10 nm-500 nm.

[0109] In this embodiment, the projection of the second electrode 13 formed on the substrate 20 falls on the inner side of the projection of the gating layer 12 formed on the substrate 20 , and part of the top surface of the gating layer 12 is covered by the first passivation layer 141 .

[0110] In some embodiments, reference Figure 6 Combined with Figure 2 , Figure 10-12 As shown, before forming the first hole 101, a first passivation layer 141 is formed, the first passivation layer 141 covers the top surface of the first dielectric layer 30, and the first passivation layer 141 and the first dielectric layer 30 are etched to form the first hole 101; a portion of the bottom surface of the gating layer 12 is connected to the first passivation layer 141, and the gating layer 12 is separated from the first dielectric layer 30 by the first passivation layer 141; after forming the gating layer 12, a second passivation layer 142 is formed to cover the sidewalls and top surface of the gating layer 12.

[0111] In this way, the bottom surface of the gating layer 12 other than the contact with the first electrode 11 is connected to the first passivation layer 141, and the gating layer 12 is separated from the first dielectric layer 30 by the first passivation layer 141. The passivation layer 14 can provide more comprehensive protection for the gating layer 12, optimize the thermal management of the gating layer 12, and further optimize the switching performance of the gating tube 10. At the same time, the passivation layer 14 can reduce the risk of electrical crosstalk or short circuit between the gating layer 12 and other devices.

[0112] The gate tube provided by the present disclosure is provided with a passivation layer covering the wall of the gate layer. The passivation layer can reduce the leakage current of the gate tube in the high resistance state, and the passivation layer can isolate or weaken the abnormal flow path of the current of the gate tube. The passivation layer significantly improves the current control ability of the device in the off state, thereby reducing unnecessary energy consumption; at the same time, the passivation layer has good thermal insulation properties, which can hinder the transfer of heat from the gate layer to the external environment, improve the thermal stability of the gate layer, and when the gate tube is turned on, the heat inside the gate layer is more effectively retained inside the gate layer, so that the temperature rise rate of the gate layer is accelerated, so that the gate tube can reach its turn-on threshold voltage faster, thereby significantly improving the response speed of the gate tube. The gate tube provided by the present disclosure achieves faster switching speed and lower power consumption while ensuring a high switching ratio. This is of great significance for improving the efficiency and performance of the entire electronic system, and can meet the demand for a new generation of electronic devices in the field of integrated circuits along the development process of Moore's Law.

[0113] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A gating tube, characterized in that: The gating tube comprises: a first electrode; A gating layer, disposed on the first electrode, wherein a bottom surface of the gating layer contacts the first electrode; A second electrode is disposed on the gating layer, and a top surface of the gating layer is in contact with the second electrode; A passivation layer at least covers a side wall of the gating layer, wherein the thermal conductivity of the passivation layer is smaller than the thermal conductivity of the gating layer, and the electrical conductivity of the passivation layer is smaller than the electrical conductivity of the gating layer.

2. The gating tube according to claim 1, characterized in that: The passivation layer also covers a top surface of the gating layer that is not covered by the second electrode.

3. The gating tube according to claim 1, characterized in that: The passivation layer also covers the bottom surface of the gating layer not covered by the first electrode.

4. The gating tube according to claim 1, characterized in that: The thermal conductivity of the passivation layer is 0.1W / m·K-25W / m·K; the electrical conductivity of the passivation layer is 10 -8 S / m to 10 -16 S / m; The material of the passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

5. The gating tube according to any one of claims 1 to 4, characterized in that: The gate tube is arranged on a substrate, and the top surface of the substrate is covered with a first dielectric layer; The first electrode is disposed in the first dielectric layer, and the first electrode extends from the top surface of the first dielectric layer to the top surface of the substrate; The gating layer and the second electrode are sequentially stacked on a side of the first electrode away from the substrate.

6. The gating tube according to claim 5, characterized in that: An insulating layer is disposed on a side of the first dielectric layer away from the substrate, the insulating layer covers the sidewall of the gating layer and the sidewall of the second electrode, and the insulating layer is separated from the gating layer by the passivation layer.

7. A method for manufacturing a gate tube, characterized in that: include: Providing a substrate, wherein the substrate is covered with a first dielectric layer; forming a first hole on the first dielectric layer, and forming a first electrode in the first hole; forming a gating layer on the first electrode layer, wherein a bottom surface of the gating layer contacts the first electrode; forming a passivation layer, wherein the passivation layer at least covers the sidewalls of the gating layer and the top surface of the gating layer; The conductivity of the passivation layer is less than the conductivity of the gating layer; removing at least a portion of the passivation layer on the top surface of the gating layer to expose at least a portion of the top surface of the gating layer; A second electrode is formed, the second electrode covering the exposed top surface of the gate layer, the second electrode being in contact with the top surface of the gate layer.

8. The method for manufacturing a gate tube according to claim 7, characterized in that: Before forming the first hole, a first passivation layer is formed, the first passivation layer covers the top surface of the first dielectric layer, and the first passivation layer and the first dielectric layer are etched to form the first hole; a part of the bottom surface of the gating layer is connected to the first passivation layer, and the gating layer and the first dielectric layer are separated by the first passivation layer; After forming the gate layer, a second passivation layer is formed to cover the sidewalls and the top surface of the gate layer.

9. The method for manufacturing a gate tube according to claim 8, characterized in that: Also includes: forming an insulating layer, the insulating layer covering the gating layer, the insulating layer and the gating layer being separated by the passivation layer; The insulating layer is etched to expose a portion of the top surface of the gating layer to form a second hole, and the second electrode is formed in the second hole.

10. The method for manufacturing a gate tube according to claim 7, characterized in that: The thermal conductivity of the passivation layer is 0.1W / m·K-25W / m·K; the electrical conductivity of the passivation layer is 10 -8 S / m to 10 -16 S / m; The material of the passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, nitrogen-doped silicon carbide, aluminum oxide, and tantalum oxide.

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