CrSi thin-film resistor preparation method, resistance device preparation method and resistance device

Abstract

The invention discloses a CrSi thin-film resistor preparation method, a resistance device preparation method and a resistance device, and relates to the technical field of semiconductor manufacturing. The preparation method of the CrSi thin-film resistor comprises the following steps: depositing a CrSi thin-film layer on an NDC film layer of a wafer; a SiON film layer is deposited on the CrSi thin film layer, and the CrSi thin film layer is covered with the SiON film layer; carrying out high-temperature annealing treatment on the CrSi thin film layer; metal electrode contact holes are etched in the SiON film layer and the CrSi film layer through dry etching; depositing a TIN film layer on the front surface of the wafer, wherein the TIN film layer covers the SiON film layer, the CrSi film layer and the metal electrode contact hole; and etching the TIN film layer into a metal electrode by adopting dry etching. Through the technical means, when the CrSi thin film layer is subjected to high-temperature annealing, the SiON film layer prevents Cr atoms from diffusing outwards, dry etching is carried out on the CrSi thin film layer and the TIN film layer, and the problems that the Cr atoms pollute etching liquid and the two ends of the CrSi thin film layer are exposed due to TIN side digging are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a CrSi thin film resistor, a method for manufacturing a resistor device, and a resistor device. Background Art

[0002] CrSi thin film resistors refer to resistor materials composed of chromium (Cr) and silicon (Si). CrSi thin film resistors are widely used in various electronic devices due to their high performance and high stability, such as smart devices, wearable technology and IoT devices. With the continuous advancement of science and technology and the growing demand for high-performance resistors in smart devices, the application prospects of CrSi thin film resistors will be broader. With the decreasing process nodes of integrated circuits and the continuous improvement of device performance by advanced processes, the preparation of CrSi thin film resistors has received more and more attention.

[0003] In the prior art, the preparation process of CrSi thin film resistors is as follows: depositing a CrSi thin film layer on NDC and etching a resistor pattern; high temperature annealing; depositing TIN on CrSi; depositing SiON on the TIN layer and etching a metal electrode contact hole pattern; using wet etching to etch the TIN into a metal electrode pattern; depositing oxide and making wiring holes. There are three serious Cr pollution processes in this process flow: First, during high-temperature annealing, the CrSi film layer is directly exposed to high temperature, causing the Cr atoms in the CrSi film layer to diffuse violently in the annealing machine chamber; second, during wet etching of TIN, the wafer is sent into a container containing etching solution for reaction. During the reaction, TIN is etched away in large quantities, exposing a large area of ​​CrSi film layer. Moreover, due to the anisotropy of the reaction between the etching solution and the film layer, TIN will have side digging, further increasing the exposed area of ​​CrSi film layer, and a large number of Cr atoms will quickly enter the etching solution. Later, when other devices enter the container for reaction, the Cr atoms in the etching solution will adhere to the surface of the device or diffuse into the inside, causing heavy metal pollution; third, after the preparation of TIN metal electrodes, wiring holes and upper film layers, the CrSi film layer will be exposed in a cavity due to TIN side digging. In this case, the Cr atoms in the exposed CrSi film layer will enter the air through diffusion, causing heavy metal pollution to the machines and containers used for transmission, loading and subsequent process steps. Therefore, the existing preparation process will cause pollution to the equipment, environment and other resistor devices in production when preparing CrSi thin film resistors, seriously affecting the production efficiency and safety of the resistor devices. Summary of the invention

[0004] The present application provides a method for preparing a CrSi thin film resistor, a method for preparing a resistor device, and a resistor device, which solves the problem in the prior art that Cr atoms in the CrSi thin film resistor diffuse outward to cause heavy metal pollution, and improves the production efficiency and safety of the resistor device.

[0005] In a first aspect, the present application provides a method for preparing a CrSi thin film resistor, comprising:

[0006] Depositing a CrSi thin film layer on the NDC film layer of the wafer;

[0007] Depositing a SiON film layer on the CrSi film layer, wherein the SiON film layer covers the CrSi film layer;

[0008] Performing high temperature annealing treatment on the CrSi thin film layer;

[0009] Etching metal electrode contact holes on the SiON film layer and the CrSi film layer by dry etching;

[0010] Depositing a TIN film layer on the front side of the wafer, wherein the TIN film layer covers the SiON film layer, the CrSi thin film layer and the metal electrode contact hole;

[0011] The TIN film layer is etched into a metal electrode by dry etching.

[0012] Optionally, depositing a CrSi thin film layer on the NDC film layer of the wafer includes:

[0013] The CrSi thin film layer is deposited on the NDC film layer of the wafer using a physical vapor deposition process.

[0014] Optionally, after the high temperature annealing, the method further comprises:

[0015] The SiON film layer and the CrSi film layer are etched into a resistance pattern by dry etching.

[0016] Optionally, the step of etching the SiON film layer and the CrSi film layer into a resistance pattern by dry etching includes:

[0017] Coating a layer of photoresist on the SiON film layer;

[0018] Developing the photoresist above the SiON film layer based on the resistance pattern mask to expose a portion of the SiON film layer;

[0019] The exposed SiON film layer and the corresponding CrSi film layer thereunder are etched by a plasma etching process, so that the remaining SiON film layer and the CrSi film layer form a resistance pattern.

[0020] Optionally, etching metal electrode contact holes on the SiON film layer and the CrSi film layer by dry etching includes:

[0021] Coating a layer of photoresist on the SiON film layer;

[0022] Developing the photoresist above the SiON film layer based on the contact hole pattern mask to expose a portion of the SiON film layer;

[0023] The exposed SiON film layer and the corresponding CrSi film layer thereunder are etched by a plasma etching process to form metal electrode contact holes on the SiON film layer and the CrSi film layer.

[0024] Optionally, the step of etching the TIN film layer into a metal electrode by dry etching includes:

[0025] Coating a layer of photoresist on the TIN film layer;

[0026] Developing the photoresist above the TIN film layer based on the metal electrode pattern mask to expose a portion of the TIN film layer;

[0027] The exposed TIN film layer is etched by a plasma etching process, so that the remaining TIN film layer forms a metal electrode.

[0028] Optionally, the metal electrode wraps both ends of the CrSi thin film layer.

[0029] Optionally, after etching the TIN film layer into a metal electrode by dry etching, the method further comprises:

[0030] An NDC film layer is deposited on the front side of the wafer.

[0031] In a second aspect, the present application provides a method for preparing a resistor device, including the method for preparing a CrSi thin film resistor as described in the first aspect.

[0032] In a third aspect, the present application provides a resistor device, which is prepared using the resistor device preparation method as described in the second aspect.

[0033] In the present application, a CrSi thin film layer is deposited on the NDC film layer of the wafer; a SiON film layer is deposited above the CrSi thin film resistor, and the SiON film layer covers the CrSi thin film layer; the CrSi thin film resistor is subjected to high temperature annealing treatment; a metal electrode contact hole is etched on the SiON film layer and the CrSi thin film layer by dry etching; a TIN film layer is deposited on the front of the wafer, and the TIN film layer covers the SiON film layer, the CrSi thin film layer and the metal electrode contact hole; and the TIN film layer is etched into a metal electrode by dry etching. Through the above technical means, the upper surface of the CrSi thin film layer is completely covered by the SiON film layer. When the CrSi thin film layer is subjected to high temperature annealing, the SiON film layer can effectively prevent the Cr atoms in the CrSi thin film layer from diffusing outward, thereby reducing the risk of heavy metal pollution. The CrSi thin film layer is dry-etched to avoid the problem of Cr atoms in the CrSi thin film layer contaminating the etching solution, and the TIN film layer is dry-etched to avoid the problem of TIN side digging and causing the two ends of the CrSi thin film layer to be exposed, further reducing the risk of heavy metal pollution and improving the production efficiency and safety of resistor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of a conventional CrSi thin film resistor provided in an embodiment of the present application during high temperature annealing;

[0035] Figure 2 It is a schematic diagram of the structure of a conventional CrSi thin film resistor provided in an embodiment of the present application when etching the TIN layer;

[0036] Figure 3 This is a schematic diagram of the structure of a conventional CrSi thin film resistor after being manufactured provided in an embodiment of the present application;

[0037] Figure 4 It is a flow chart of a method for preparing a CrSi thin film resistor provided in an embodiment of the present application;

[0038] Figure 5 It is a schematic diagram of the structure after a CrSi thin film layer is deposited on a wafer provided in an embodiment of the present application;

[0039] Figure 6 It is a schematic diagram of the structure of a SiON film layer deposited on a wafer provided in an embodiment of the present application;

[0040] Figure 7 It is a schematic diagram of the structure in which the SiON film layer and the CrSi film layer of the wafer provided in the embodiment of the present application are etched into a resistance pattern;

[0041] Figure 8 It is a schematic diagram of the structure of etching metal electrode contact holes in a wafer provided in an embodiment of the present application;

[0042] Fig. 9It is a schematic diagram of the structure of a TIN film layer deposited on a wafer provided in an embodiment of the present application;

[0043] Fig.10 It is a schematic diagram of the structure of the TIN film layer of the wafer provided in the embodiment of the present application to form a metal electrode;

[0044] Fig.11 is a schematic diagram of the structure of the third NDC film layer deposited on a wafer provided in an embodiment of the present application;

[0045] Fig.12 is a schematic diagram of the structure of the CrSi thin film resistor provided in an embodiment of the present application;

[0046] In the figure, 11, substrate; 12, interlayer dielectric layer; 13, NDC film layer; 14, BD film layer; 15, first metal layer; 16, CrSi thin film layer; 17, SiON film layer; 18, metal electrode contact hole; 19, TIN film layer; 20, metal through hole; 21, second metal layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0048] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0049] In the more common existing implementation method, the preparation process of CrSi thin film resistors is: depositing CrSi thin film resistors on NDC and etching resistor patterns; high temperature annealing; depositing TIN on CrSi; depositing SiON on the TIN layer and etching the pattern of metal electrode contact holes; using wet etching to etch the TIN into the pattern of metal electrodes; depositing oxide and making wiring holes. There are three serious Cr contamination processes in this process flow, namely high temperature annealing, wet etching of TIN, and after the resistor is made. Figure 1 Schematic diagram of the structure of the conventional CrSi thin film resistor during high temperature annealing provided in the embodiment of the present application. Figure 1 As shown, during high-temperature annealing, CrSi is exposed to high temperature without any shielding, causing Cr atoms to diffuse violently in the annealing machine cavity. Figure 2 Schematic diagram of the structure of the conventional CrSi thin film resistor provided in the embodiment of the present application when etching the TIN layer. Figure 2 As shown in the figure, when wet etching is used to etch TIN, the wafer is sent into a container containing etching solution for reaction. During the reaction, a large amount of TIN is etched away, and a large area of ​​CrSi thin film layer below is leaked. A large number of Cr atoms in the CrSi thin film layer will quickly enter the etching solution. When other devices enter the container containing the etching solution for reaction, the Cr atoms remaining in the etching solution will adhere to the device surface or diffuse into the device, causing serious heavy metal pollution to other devices. In addition, due to the anisotropy of the reaction between the etching solution and the film layer, TIN will have side digging phenomenon (such as Figure 2 The TIN film layer shown is recessed inward), further increasing the exposed area of ​​the CrSi film layer, thereby further increasing the risk of heavy metal pollution. Figure 3 Schematic diagram of the structure of the conventional CrSi thin film resistor provided in the embodiment of the present application. Figure 3 As shown in the figure, although the two sides of the CrSi thin film layer are covered by the BD film layer, the side digging problem of TIN will cause the two ends of the upper surface of the CrSi thin film layer to be uncovered and exposed in a hole. The Cr atoms in the exposed CrSi thin film layer will diffuse into the air, causing heavy metal pollution to the machines and containers used in the transmission, loading and subsequent process steps. Therefore, the existing preparation process will cause pollution to the equipment, environment and other resistor devices in production when preparing CrSi thin film resistors, seriously affecting the production efficiency and safety of resistor devices.

[0050] To solve the above problems, the present embodiment provides a method for preparing a CrSi thin film resistor, a method for preparing a resistor device, and a resistor device, so as to deposit a SiON film layer on the CrSi thin film layer, so as to prevent Cr atoms from diffusing outward through the SiON film layer when the CrSi thin film layer is subjected to high-temperature annealing, and to perform dry etching on the CrSi thin film layer and the TIN film layer, so as to avoid the problem of Cr atoms contaminating the etching solution and the problem of TIN side digging causing the two ends of the CrSi thin film layer to be exposed, thereby improving the production efficiency and safety of the resistor device.

[0051] Figure 4 A flow chart of a method for preparing a CrSi thin film resistor provided in an embodiment of the present application is given. Figure 4 As shown, the CrSi thin film resistor preparation method includes:

[0052] S110 , depositing a CrSi thin film layer 16 on the NDC film layer 13 of the wafer.

[0053] Exemplarily, before depositing the CrSi thin film layer 16, the wafer is formed by stacking a substrate 11, an interlayer dielectric layer (ILD TEOS) 12, an underlying NDC film layer 13, a BD film layer 14 and a second NDC film layer 13, and a first metal layer 15 is formed between the interlayer dielectric layer 12, the underlying NDC film layer 13 and the BD film layer 14. Before depositing the CrSi thin film layer 16, a silicon dioxide material is first deposited on the substrate 11 to form an interlayer dielectric layer 12, a nitrogen-doped silicon carbide material is deposited on the interlayer dielectric layer 12 to form an underlying NDC film layer 13, a SiCOH material is deposited on the underlying NDC film layer 13 to form a BD film layer 14, a pattern of a first metal layer 15 is etched on the BD film layer 14, the underlying NDC film layer 13 and the interlayer dielectric layer 12, and then a copper material is deposited in the pattern of the first metal layer 15 etched in the BD film layer 14, the underlying NDC film layer 13 and the interlayer dielectric layer 12, so that the copper material deposited between the interlayer dielectric layer 12, the underlying NDC film layer 13 and the BD film layer 14 forms a first metal layer 15. Then, a nitrogen-doped silicon carbide material is deposited on the BD film layer 14 and the first metal layer 15 to form a second NDC film layer 13. A CrSi material is deposited on the second NDC film layer 13 to form a CrSi thin film layer 16 . The CrSi thin film layer 16 completely covers the second NDC film layer 13 .

[0054] For example, Figure 5 1 is a schematic diagram of the structure of a wafer after a CrSi thin film layer 16 is deposited according to an embodiment of the present application. Figure 5 As shown, the CrSi thin film layer 16 covers the second NDC film layer 13 , and a BD film layer 14 , a bottom NDC film layer 13 , an interlayer dielectric layer 12 and a substrate 11 are sequentially formed below the second NDC film layer 13 .

[0055] Optionally, a CrSi thin film layer 16 is deposited on the NDC film layer 13 of the wafer using a physical vapor deposition process. Physical vapor deposition (PVD) uses physical methods, such as evaporation, sputtering, or ion implantation, to convert CrSi into atoms, molecules, or ions, which are deposited on the surface of the second NDC film layer 13 of the wafer to form the CrSi thin film layer 16.

[0056] S120 , depositing a SiON film layer 17 on the CrSi film layer 16 , wherein the SiON film layer 17 covers the CrSi film layer 16 .

[0057] Exemplarily, SiON material is deposited on the CrSi thin film layer 16 of the wafer to form a SiON film layer 17 , and the SiON film layer 17 covers the CrSi thin film layer 16 .

[0058] For example, Figure 6 Schematic diagram of the structure of the wafer deposited SiON film 17 provided in the embodiment of the present application. Figure 6 As shown, the SiON film layer 17 covers the CrSi film layer 16. It should be noted that since the current passes through the CrSi film layer 16, the type of material deposited on the CrSi film layer 16 does not affect the use of the CrSi film layer 16. That is, no matter whether the SiON film layer 17 is similar to Figure 1 The structure of the conventional CrSi thin film resistor shown in FIG. 1 is formed on the CrSi thin film layer 16, or as Figure 6 The embodiment shown is formed on the CrSi film layer 16, which will not affect the conductive function of the CrSi film layer 16. However, when the SiON film layer 17 provided in this embodiment is covered on the CrSi film layer 16, when the CrSi film layer 16 is subjected to high-temperature annealing, the SiON film layer 17 can effectively prevent the Cr atoms in the CrSi film layer 16 from diffusing outward, thereby reducing the risk of heavy metal pollution.

[0059] S130 , performing high temperature annealing treatment on the CrSi thin film layer 16 .

[0060] For example, since there are defects in the CrSi thin film layer 16 during deposition, the CrSi thin film layer 16 may be subjected to high temperature annealing to repair the defects of the CrSi thin film layer 16 and improve the resistance quality of the CrSi thin film layer 16. During the high temperature annealing process, although the CrSi thin film layer 16 is subjected to high temperature, since the CrSi thin film layer 16 is covered with the SiON film layer 17, the SiON film layer 17 can prevent the Cr atoms in the CrSi thin film layer 16 from diffusing outward, thereby reducing the risk of heavy metal pollution.

[0061] Optionally, different types of CrSi thin film resistors have different resistance pattern requirements for the CrSi thin film layer 16. After the CrSi thin film layer 16 is subjected to high temperature annealing, the SiON film layer 17 and the CrSi thin film layer 16 may be etched into a resistance pattern by dry etching. Exemplarily, when the resistance pattern is a long strip pattern, the SiON film layer 17 and the CrSi thin film layer 16 are etched into a long strip pattern by dry etching, that is, the SiON film layer 17 and the CrSi thin film layer 16 retained on the wafer are long strip patterns. Figure 7 1 is a schematic diagram of the structure of the SiON film layer 17 and the CrSi film layer 16 of the wafer provided in the embodiment of the present application being etched into a resistance pattern. Figure 7 As shown, after both ends of the SiON film layer 17 and the CrSi film layer 16 are etched away, the remaining middle portion forms a resistance pattern corresponding to the CrSi thin film resistor.

[0062] In this embodiment, when etching the SiON film layer 17 and the CrSi film layer 16 into a resistor pattern, a layer of photoresist may be coated on the SiON film layer 17; the photoresist on the SiON film layer 17 is developed based on the resistor pattern mask to expose a portion of the SiON film layer 17; the exposed SiON film layer 17 and the corresponding CrSi film layer 16 below are etched using a plasma etching process, so that the remaining SiON film layer 17 and the CrSi film layer 16 form a resistor pattern. Exemplarily, a layer of photoresist is coated on the upper surface of the wafer, that is, the upper surface of the SiON film layer 17, and the photoresist on the SiON film layer 17 is exposed through a preset resistor pattern mask, so that the exposed photoresist is eliminated and the corresponding SiON film layer 17 below is exposed, and the exposed portion of the SiON film layer 17 does not belong to the resistor portion. The exposed SiON film layer 17 and the corresponding CrSi film layer 16 below are etched using a plasma etching process, and the SiON film layer 17 and the CrSi film layer 16 corresponding to the resistor pattern are retained. Finally, the remaining photoresist on the SiON film layer 17 is removed.

[0063] It should be noted that when etching the SiON film layer 17 and the CrSi film layer 16 into a resistor pattern, dry etching is used. The problem of the CrSi film layer 16 coming into contact with the etching solution during wet etching, causing the Cr atoms in the CrSi film layer 16 to contaminate the etching solution and the container, will not occur, thereby effectively reducing the risk of heavy metal pollution.

[0064] S140 , etching metal electrode contact holes 18 on the SiON film layer 17 and the CrSi film layer 16 by dry etching.

[0065] Exemplarily, dry etching is used to etch metal electrode contact holes 18 on the SiON film layer 17 and the CrSi film layer 16 forming the resistor pattern. When etching the CrSi film layer 16, only the upper half of the corresponding etching area will be etched but not completely etched, that is, the NCD film layer below the corresponding etching area of ​​the CrSi film layer 16 will not be exposed. Figure 8 1 is a schematic diagram of the structure of the wafer etching metal electrode contact hole 18 provided in the embodiment of the present application. Figure 8 As shown, two metal electrode contact holes 18 are formed between the SiON film layer 17 and the CrSi film layer 16. The bottom of the metal electrode contact holes 18 contacts the CrSi film layer 16. Subsequently, TIN material can be deposited in the metal electrode contact holes 18 to form metal electrodes.

[0066] It should be noted that when the CrSi thin film layer 16 is dry-etched, the CrSi thin film layer 16 will not come into contact with the etching solution used in wet etching, so there will be no problem of Cr atoms in the CrSi thin film layer 16 contaminating the etching solution and the container, effectively reducing the risk of heavy metal pollution.

[0067] Optionally, when etching the metal electrode contact hole 18 on the SiON film layer 17 and the CrSi film layer 16, a layer of photoresist may be coated on the SiON film layer 17; the photoresist on the SiON film layer 17 is developed based on the contact hole pattern mask to expose a portion of the SiON film layer 17; and the exposed SiON film layer 17 and the corresponding CrSi film layer 16 below are etched using a plasma etching process to form the metal electrode contact hole 18 on the SiON film layer 17 and the CrSi film layer 16. For example, refer to Figure 7 A layer of photoresist is coated on the upper surface of the wafer, i.e., the upper surface of the SiON film layer 17 and the upper surfaces of the second NDC film layer 13 exposed on both sides. The photoresist on the upper surface of the wafer is exposed through a preset contact hole pattern mask so that the exposed photoresist is removed and the corresponding SiON film layer 17 below is exposed. At this time, the area of ​​the exposed SiON film layer 17 is the area where the metal electrode contact hole 18 is to be etched in the SiON film layer 17. The exposed SiON film layer 17 and the corresponding CrSi film layer 16 below are etched using a plasma etching process so that the etched area forms a metal electrode contact hole 18. Finally, the residual photoresist on the SiON film layer 17 and the second NDC film layer 13 is removed.

[0068] S150 , depositing a TIN film layer 19 on the front side of the wafer, wherein the TIN film layer 19 covers the SiON film layer 17 , the CrSi thin film layer 16 and the metal electrode contact hole 18 .

[0069] Exemplarily, a TIN (titanium nitride) material is deposited on the front side, ie, the upper surface, of the wafer to form a TIN film layer 19 . Fig. 9 Schematic diagram of the structure of the wafer-deposited TIN film layer 19 provided in the embodiment of the present application. Fig. 9 As shown, the TIN film layer 19 covers the SiON film layer 17 , the CrSi thin film layer 16 and the metal electrode contact hole 18 .

[0070] S160, using dry etching to etch the TIN film layer 19 into a metal electrode.

[0071] Exemplarily, a dry etching process is used to etch the SiON film layer 17, the CrSi film layer 16 and the TIN film layer 19 deposited on the metal electrode contact hole 18 into a metal electrode. When etching the TIN film layer 19, the TIN material at both ends of the CrSi film layer 16 will be retained so that the finally formed metal electrode will wrap the side walls at both ends of the CrSi film layer 16. The side walls at both ends of the CrSi film layer 16 will not be exposed to the air, thereby preventing the Cr atoms in the CrSi film layer 16 from diffusing into the air and contaminating the machines and devices involved in the subsequent processes. Fig.10 1 is a schematic diagram of the structure of the TIN film layer 19 of the wafer provided in the embodiment of the present application forming a metal electrode. Fig.10 As shown, the middle and both ends of the TIN film layer 19 are etched away, exposing the SiON film layer 17 and the second NDC film layer 13 underneath. The remaining TIN film layer 19 forms a metal electrode, which wraps the two ends of the CrSi film layer 16 to prevent the side walls of the two ends of the CrSi film layer 16 from being exposed to the air.

[0072] It should be noted that since the TIN film layer 19 is dry-etched, the dry etching can accurately etch the two ends of the TIN film layer 19, and the remaining TIN material wraps the side walls of the two ends of the CrSi film layer 16. The TIN film layer 19 will not have the side digging phenomenon during wet etching, so there is no exposure of the side walls of the two ends of the CrSi film layer 16, which effectively reduces the risk of heavy metal pollution.

[0073] Optionally, when etching the TIN film layer 19, a layer of photoresist may be coated on the TIN film layer 19; the photoresist on the TIN film layer 19 is developed based on the metal electrode pattern mask to expose part of the TIN film layer 19; and the exposed TIN film layer 19 is etched using a plasma etching process so that the remaining TIN film layer 19 forms a metal electrode. Exemplarily, a layer of photoresist is coated on the upper surface of the wafer, i.e., the upper surface of the TIN film layer 19, and the photoresist on the upper surface of the TIN film layer 19 is exposed through a preset metal electrode pattern mask so that the exposed photoresist is eliminated to expose the corresponding TIN film layer 19 below, and the exposed portion of the TIN film layer 19 does not belong to the metal electrode portion. The exposed TIN film layer 19 is etched using a plasma etching process so that the remaining TIN film layer 19 forms a metal electrode, and finally the residual photoresist on the TIN film layer 19 is removed.

[0074] It should be noted that in order to ensure that the metal electrode can wrap the two ends of the CrSi thin film layer 16, the photoresist above the two sides of the outer wall of the CrSi thin film layer 16 will be retained after the photoresist is exposed, so that the corresponding TIN material below can be protected from being etched away by the photoresist, thereby successfully retaining the TIN material that can wrap the two ends of the CrSi thin film layer 16.

[0075] Furthermore, after the TIN film layer 19 is etched into a metal electrode, an NDC film layer 13 is deposited on the front side of the wafer. The deposited NDC film layer 13 can be regarded as the third NDC film layer 13 on the wafer. Fig.11 1 is a schematic diagram of the structure of the third NDC film layer 13 deposited on a wafer according to an embodiment of the present application. Fig.11 As shown, the third NDC film layer 13 covers the metal electrode and contacts the second NDC film layer 13 exposed at both ends. The third NDC film layer 13 and the second NDC film layer 13 can completely wrap the metal electrode.

[0076] Afterwards, SiCOH material is deposited on the third NDC film layer 13 to form a BD film layer 14. The BD film layer 14 above the third NDC film layer 13 can be regarded as the second BD film layer 14. Contact holes are etched on the second BD film layer 14 and the third NDC film layer 13. The bottom of the contact hole contacts the TIN film layer 19. Copper material is deposited in the contact hole to form a metal through hole 20. The second metal layer 21 pattern is etched on both sides of the second BD film layer 14. Copper material is deposited in the second metal layer 21 pattern etched in the second BD film layer 14 to form the second metal layer 21. The preparation of the CrSi thin film resistor is completed. Fig.12 Schematic diagram of the structure of the CrSi thin film resistor provided in the embodiment of the present application. Fig.12As shown, a second BD film layer 14 is formed above the third NDC film layer 13, and a metal through hole 20 is formed between the second BD film layer 14 and the third NDC film layer 13. The metal through hole 20 connects the TIN film layer 19 below the third NDC film layer 13 and the second metal layer 21 above the second BD film layer 14.

[0077] On the basis of the above-mentioned embodiments, the embodiments of the present application also provide a method for preparing a resistor device and a resistor device prepared by the method for preparing a resistor device, and the method for preparing a resistor device includes the method for preparing a CrSi thin film resistor as described in the above-mentioned embodiments. In the process of preparing the resistor device in this embodiment, the method for preparing the CrSi thin film resistor provided in the above-mentioned embodiment is used to deposit a SiON film layer 17 on the upper surface of the CrSi thin film layer 16, so that when the CrSi thin film layer 16 is subjected to high-temperature annealing, the Cr atoms in the CrSi thin film layer 16 diffuse outward through the SiON film layer 17, thereby reducing the risk of heavy metal pollution. The CrSi thin film layer 16 is dry-etched to avoid the problem of Cr atoms in the CrSi thin film layer 16 contaminating the etching solution, and the TIN film layer 19 is dry-etched to avoid the problem of TIN side digging and causing the two ends of the CrSi thin film layer 16 to be exposed, further reducing the risk of heavy metal pollution and improving the production efficiency and safety of the resistor device.

[0078] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the protection scope of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for preparing a CrSi thin film resistor, characterized in that: include: Depositing a CrSi thin film layer on the NDC film layer of the wafer; Depositing a SiON film layer on the CrSi film layer, wherein the SiON film layer covers the CrSi film layer; Performing high temperature annealing treatment on the CrSi thin film layer; Etching metal electrode contact holes on the SiON film layer and the CrSi film layer by dry etching; Depositing a TIN film layer on the front side of the wafer, wherein the TIN film layer covers the SiON film layer, the CrSi thin film layer and the metal electrode contact hole; The TIN film layer is etched into a metal electrode by dry etching.

2. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: The step of depositing a CrSi thin film layer on the NDC film layer of the wafer comprises: The CrSi thin film layer is deposited on the NDC film layer of the wafer using a physical vapor deposition process.

3. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: After the high temperature annealing, the method further comprises: The SiON film layer and the CrSi film layer are etched into a resistance pattern by dry etching.

4. The method for preparing a CrSi thin film resistor according to claim 3, characterized in that: The step of etching the SiON film layer and the CrSi film layer into a resistance pattern by dry etching comprises: Coating a layer of photoresist on the SiON film layer; Developing the photoresist above the SiON film layer based on the resistance pattern mask to expose a portion of the SiON film layer; The exposed SiON film layer and the corresponding CrSi film layer thereunder are etched by a plasma etching process, so that the remaining SiON film layer and the CrSi film layer form a resistance pattern.

5. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: The step of etching metal electrode contact holes on the SiON film layer and the CrSi film layer by dry etching comprises: Coating a layer of photoresist on the SiON film layer; Developing the photoresist above the SiON film layer based on the contact hole pattern mask to expose a portion of the SiON film layer; The exposed SiON film layer and the corresponding CrSi film layer thereunder are etched by a plasma etching process to form metal electrode contact holes on the SiON film layer and the CrSi film layer.

6. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: The step of etching the TIN film layer into a metal electrode by dry etching comprises: Coating a layer of photoresist on the TIN film layer; Developing the photoresist above the TIN film layer based on the metal electrode pattern mask to expose a portion of the TIN film layer; The exposed TIN film layer is etched by a plasma etching process, so that the remaining TIN film layer forms a metal electrode.

7. The method for preparing a CrSi thin film resistor according to claim 1, characterized in that: The metal electrodes wrap both ends of the CrSi thin film layer.

8. The method for preparing a CrSi thin film resistor according to claim 6, characterized in that: After the TIN film layer is etched into a metal electrode by dry etching, the method further comprises: An NDC film layer is deposited on the front side of the wafer.

9. A method for preparing a resistor device, characterized in that: The invention comprises a method for preparing a CrSi thin film resistor as described in any one of claims 1 to 8.

10. A resistor device, characterized in that: The resistor device is prepared using the resistor device preparation method as claimed in claim 9.

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