Memory device clock mapping

Abstract

An example memory device includes clock circuitry. The clock circuitry may generate first and second clock signals based on a system clock signal, wherein the first and second clock signals are out of phase with each other. The apparatus may include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus may include processing circuitry to provide an odd-numbered clock signal and an even-numbered clock signal based on the first and second clock signals and the detection result. The processing circuitry may provide the odd-numbered clock signal and the even-numbered clock signal that are out-of-phase or in-phase with the first clock signal and the second clock signal depending on the detection result.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. application serial number 17 / 897,957, filed on August 29, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to memory devices. More specifically, embodiments relate to clock circuitry in memory devices. Background Art

[0004] A memory device is a semiconductor circuit that provides electronic storage of data for a host system, such as a computer or other electronic device. Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when not powered and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM)).

[0005] Some memory devices use circuitry to align output data with the system clock. However, as the system clock frequency increases, this alignment becomes increasingly difficult. Consequently, there is a general need to improve memory device operation at ever-increasing system clock speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter subscripts may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0007] Figure 1 An example block diagram of a memory device is generally illustrated.

[0008] Figure 2 A system clock signal and first and second internal clock signals for a memory device are generally described.

[0009] Figure 3 An example of a signal diagram for a self-refresh exit operation is generally illustrated.

[0010] Figure 4 An example of clock signal switching is generally described.

[0011] Figure 5 A signal diagram including a command lock signal and a clock swap signal is generally described.

[0012] Figure 6A An example of clock divider circuitry is generally described.

[0013] Figure 6B Examples of clock switching circuitry and control logic are generally described.

[0014] Figure 6C An example of clock switching circuitry is generally described.

[0015] Figure 7A and 7B An example of a portion of command decoding circuitry is generally described.

[0016] Figure 8A An example of command lock timing circuitry is generally described.

[0017] Figure 8B A signal diagram generally illustrates a signal including a command lock window.

[0018] Figure 9 A signal diagram generally illustrates an example of a delay locked loop (DLL) that is reset after a self-refresh event.

[0019] Figure 10 An example of a method for determining clock signal timing using NOP signal detection is generally described.

[0020] Figure 11 A block diagram illustrating an example machine with which, in which, or by which any one or more of the techniques discussed herein may be implemented. DETAILED DESCRIPTION

[0021] The following description and drawings sufficiently illustrate specific embodiments to enable one skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The embodiments recited in the claims encompass all available equivalents of the claims.

[0022] Figure 1 A simplified block diagram generally illustrating various features of memory device 100. Figure 1The block diagram may be a functional block diagram illustrating various functions of the memory device 100. According to one embodiment, the memory device 100 may be a random access memory (RAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including a double data rate SRAM device), a holographic RAM (HRAM) flash memory, and / or a phase change memory (PCM) device, and / or other chalcogenide-based memory, such as a self-select memory (SSM). Furthermore, the memory cells of the memory device may each have a corresponding logical storage device (e.g., a capacitor, a resistor, or a chalcogenide device).

[0023] In one example, memory device 100 includes cells or an array of cells arranged according to a planar architecture, wherein discrete cells or memory elements are positioned at the intersections of word lines (WLs) and bit lines (BLs). In some examples, memory elements comprising chalcogenide materials may be disposed at these WL and BL intersections and may function as both a selector and a memory element. In a two-dimensional array, alternating stacks of WLs and BLs may be arranged or layered to provide a 3D memory array.

[0024] The memory device 100 may include memory partitions 102, and each memory partition 102 may include one or more cell arrays (i.e., memory arrays), for example including chalcogenide materials. Various configurations, organizations, and sizes of the memory partitions 102 on the memory device 100 may be used depending on the application and design of the overall system. For example, each of the memory partitions 102 may include a corresponding different die in a stacked memory device. In such a device, at least one die may be a primary die that interfaces with a host or memory controller 108 using an inter-device bus 110, and one or more other dies may be secondary dies that interface with the primary die using an intra-package bus 124. The array may also be subdivided into multiple individually addressable portions (e.g., into multiple channels, banks, ranks, etc.). Alternatively, the memory system may include multiple memory devices, such as Figure 1 1. Memory device 100 of a system, wherein each memory device represents an individually addressable sub-portion (e.g., a rank, etc.) of the system's memory capacity. Thus, a memory device, or a memory system having multiple memory devices, ranks, channels, banks, or the like, may include multiple terminals (e.g., clock terminals, CMD / ADD terminals, I / O terminals, etc.) dedicated to one or more (but less than all) individually addressable portions. For example, a multi-channel memory device may include multiple terminals, each terminal corresponding to one of multiple channels of the memory.

[0025] Memory device 100 may include a command interface 104 and an input / output interface 106. Command interface 104 may receive various signals from an external host device, such as a processor or controller (e.g., memory controller 108) external to memory device 100. In some embodiments, an inter-device bus 110 (or a signal path or group of signal paths) may individually or in combination allow for bidirectional transmission of signals between command interface 104 and a processor or controller (e.g., memory controller 108).

[0026] In an example, the memory device 100 may include a second bus 112 (or a signal path or another group of signal paths) that, individually or in combination, may allow for bidirectional transmission of signals (including, for example, data signals) between the input / output interface 106 and, for example, a processor or controller, such as the memory controller 108. Thus, the processor or controller, such as the memory controller 108, may provide various signals to the memory device 100 to facilitate the transmission and receipt of data to be written to or read from the memory device 100.

[0027] In an example, the command decoder 120 can decode a command (e.g., a read command, a write command, a register file command, an activate command, etc.) and provide access to a specific one of the memory partitions 102 corresponding to the command, for example, via an intra-package bus 124. The command decoder 120 can transmit various signals to one or more registers 126 via a bus path (e.g., one or more global patch lines). In an example, the memory device 100 can include various other decoders, such as row decoders and column decoders, to facilitate access to the various memory partitions 102. In one embodiment, each memory partition 102 can include a respective control block 128 that provides decoding (e.g., row and / or column decoding) as well as other features (e.g., timing control and data control) to facilitate execution of commands to and from the respective memory partition 102.

[0028] In an example, the command decoder 120 or other components in the memory device 100 may provide register commands to one or more of the registers 126, which may be used in the operation of each of the memory partitions 102, each control block 128, and the like. For example, one of the registers 126 may define various modes of programmable operation and / or configuration of the memory device 100. The registers 126 may be included in a semiconductor device to define the operation of various types of memory components, such as DRAM, synchronous DRAM, chalcogenide memory (e.g., PCM), or other types of memory. The registers 126 may receive various signals from the command decoder 120 via a patch cord that may include a common data path, a common address path, a common write command signal path, or a common read command signal path. The patch cord may traverse the memory device 100 and couple to each register 126.

[0029] Registers 126 may be accessible or otherwise accessible by memory controller 108. Registers 126 may be dispersed across memory device 100 and may represent or contain information such as configuration settings for memory device 100 and / or specific components therein, status information about memory device 100 and / or specific components therein, memory device 100 parameters and / or specific parameters of components of memory device 100, or predetermined patterns that may be written across the memory device (e.g., in one or more of memory partitions 102). Thus, while Figure 1 1 , it should be understood that additional and / or alternative registers may be located elsewhere in the memory device and may be accessed by the memory controller 108 (i.e., when in operation, the registers are accessed by the memory controller 108). Such accesses by the memory controller 108 may include, for example, reading of the registers (e.g., a read access) and / or writing to the registers (e.g., a write access).

[0030] In an example, the memory device 100 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor and / or by a memory controller 108. In one example, the command / address signals are clocked to the command interface 104 using a clock signal. The command interface 104 may include a command / address input circuit 116 configured to receive and transmit commands through a command decoder 120 to provide access to the memory partitions 102. The command interface 104 may receive a memory select signal that enables the memory device 100 to process commands with respect to the incoming command / address signals. Access to a specific memory partition 102 within the memory device 100 may be encoded in the command.

[0031] The command interface 104 can be configured to receive various other command signals. For example, a reset command can be used to reset the command interface 104, status registers, state machines, and the like, such as during power-up or standby exit. Various signals can be provided to facilitate testing of the memory device 100. For example, a test signal can be used to place the memory device 100 in a test mode for connection capability testing. The command interface 104 can be used to provide an alarm signal or other warning signal to the system processor or controller for certain detectable errors. In some embodiments, the input / output interface 106 can additionally or alternatively transmit an alarm signal, such as a thermal alarm.

[0032] In an example, the command interface 104 may include or utilize circuits such as a clock input circuit 114 and a command / address input circuit 116 to ensure proper handling of received signals. The command interface 104 may receive one or more clock signals from an external device such as the memory controller 108. The command interface 104 may receive commands (e.g., read commands, write commands, etc.) that may be entered, for example, on the positive edge of the clock signal and may receive data that may be transmitted or received, for example, on the positive and / or negative edges of the clock signal. In some examples, commands may have variable clock lengths (e.g., commands may be received using one or more clocks).

[0033] Clock input circuit 114 can receive one or more clock signals and generate an internal clock signal CLK therefrom. In some embodiments, internal clock signal CLK is supplied to internal clock generator 118, such as a delay-locked loop (DLL) circuit. Internal clock generator 118 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. Phase-controlled internal clock signal LCLK can be provided to, for example, input / output interface 106 and can be used as a timing signal for determining the output timing of read data.

[0034] The internal clock signal CLK may be provided to various other components within the memory device 100 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 120. The command decoder 120 may receive command signals from a command bus 122 and may decode the command signals to provide various internal commands. For example, the command decoder 120 may use the internal bus to provide a command signal to the internal clock generator 118 to coordinate the generation of the phase-controlled internal clock signal LCLK. In some examples, the phase-controlled internal clock signal LCLK may be used to clock data through the input / output interface 106. In some examples, the frequency of the internal clock signal CLK may be less than the frequency of the clock signal used by the memory controller 108 to communicate via the inter-device bus 110.

[0035] For example, by transmitting and receiving data signals through input / output interface 106, data can be sent to and from memory device 100 using the command and clock signals discussed above. More specifically, data can be sent to and retrieved from memory partition 102 via data path 130, which can include, for example, multiple bidirectional data buses. For example, data I / O signals can be transmitted to and received from input / output interface 106 in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into high and low bytes; however, this segmentation is not typically used for other memory device types.

[0036] Various other components such as power supply circuits (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 100), etc. may be incorporated with the memory device 100. Therefore, it should be understood that only the following examples are provided. Figure 1 The block diagram is used to highlight certain functional features of the memory device 100 to assist in the subsequent detailed description.

[0037] As previously mentioned herein, the memory device 100 can use various internal clock signals. DRAM memory devices, in particular, use an internal clock generator 118 (e.g., DLL) to align output data with the system clock. In some previous systems and designs, the clock frequency was slow enough that the incoming system clock signal was used to capture commands and addresses and serve as an input to the internal clock generator 118 to generate output timings on either the rising or falling edge. However, as clock speeds increase, memory devices are unable to use the full clock frequency to capture memory commands and addresses. Therefore, some memory systems can be adapted for these faster speeds by generating multiple internal clock signals that switch at half the frequency of the system clock. Then, depending on which rising edge of the even or odd external clock signal such commands are aligned to, either an "even" clock signal (e.g., CLKE) or an "odd" clock signal (e.g., CLKO) can be used to capture commands and addresses. Both the even and odd clock signals can, in turn, be used by the internal clock generator 118 to generate the output control clock signal. Thus, in effect, the timing of the output bits can be controlled by two different clocks.

[0038] Figure 2 A system clock signal and first and second internal clock signals, such as used in a memory device, are generally described. Figure 2 The example of shows the alignment of rising edges of the first and second internal clock signals relative to the edges of the external clock.

[0039] exist Figure 2In the example of FIG1 , an external clock signal is shown at external clock signal 200. A chip select (CS) signal for a command (in the example, a no operation or "NOP") is shown at signal 202. A first internal clock signal having a rising edge during odd cycles of external clock signal 200 is shown at first clock signal 204. A second internal clock signal having a rising edge during even cycles of external clock signal 200 is shown at second clock signal 206. First clock signal 204 and second clock signal 206 have a frequency that is half the frequency of system clock 200. A rising edge of external clock signal 200 has a rising edge at either a rising edge of first clock signal 204 or a rising edge of second clock signal 206, and an external user may not be able to detect which of the internal signal's rising edges will coincide with (e.g., mirror) any given rising edge of external clock signal 200. In some examples, the first and second clock signal paths may be physically distinct paths, which in turn may affect edge timing and cause distortion or inconsistency in the output data of memory device 100.

[0040] To address these and other issues, embodiments herein provide systems and methods that allow devices and users of the memory device 100 to map the external clock signal 200 to a specific internal divided clock signal, such as the first clock signal 204 or the second clock signal 206. In this example, external users and systems can read the output data, analyze the duty cycle, and adjust the system clock to correct for duty cycle distortion that may result from having odd and even clock paths.

[0041] Figure 3 An example of a signal diagram for a self-refresh exit operation of a memory device is generally described. Figure 3 In some examples, a self-refresh entry / self-refresh exit (SRE / SRX) operation is performed, and after the operation, the memory device 100 (or more specifically, the memory controller 108) may change one of the clocks (e.g., the first clock signal 204 ( Figure 2 )) is aligned with the first NOP issued for SRX, as described below.

[0042] exist Figure 3 In the example of , signal 300 illustrates an external clock signal (e.g., similar to external clock signal 200 ( Figure 2 )). Signal 302 is a chip select (CS) signal and signals 304 and 306 are command signals. A self-refresh operation is provided, and the self-refresh operation may include a self-refresh entry (SRE, Figure 3(not shown) and self-refresh exit (SRX) operation 308. Figure 3 In the example of FIG. 3 , a self-refresh exit may include three NOP command strings 310, which may be set to start, for example, on the first odd-numbered clock cycle tc+1 of the external clock signal 300, which may correspond to the NOP command mapped to the first command pipeline. After this point, DCA training may be performed. The chip select (CS) signal 302 is shown as low for three cycles corresponding to the three NOP command strings 310. Although three NOP command strings 310 are described, this is for example purposes only and embodiments are not limited thereto.

[0043] In an example, a first NOP command in commands 310 can be detected in the DRAM using detection circuitry. When the first NOP command is received, the NOP command arrives from a second (e.g., "even") command path or pipeline, or from a first (e.g., "odd") command path or pipeline. The first and second command paths can be identical or substantially identical, but based on clock signals that are offset by half a cycle from each other, such that the clock signals are out of phase with each other.

[0044] In an example, the detection circuitry provides a detection result indicating that a first NOP command (or other command associated with exiting a self-refresh operation) arrives at the first command pipeline or the second command pipeline. If the NOP command arrives at the first command pipeline, then no clock swap adjustment is indicated, for example, because the first command pipeline may correspond to the NOP command coinciding with an "odd" cycle of the external clock (e.g., at tc+1). The example may then proceed with DCA training.

[0045] Otherwise, if a NOP command arrives in the second command pipeline, a clock swap adjustment may be indicated, and a "clock swap" signal or indicator may be set for later processing as described herein. The example may then proceed with DCA training. In the event of any subsequent SRE / SRX sequence, the internal clock may be mapped to that which existed during DCA training. However, if any subsequent "soft" reset occurs, a pair of SRE / SRX commands may be issued to ensure that the internal clock is mapped as described above.

[0046] In an example, the clock switching operation may include the following. First, an external clock (eg, external clock signal 200 ( Figure 2 ) or clock signal 300( Figure 3)) is divided into four phases (e.g., I (0 degrees), IB (90 degrees phase shift relative to I), Q (180 degrees phase shift relative to I), and QB (270 degrees phase shift relative to I)). When the "clock swap" signal, or the "clock swap" signal is set to "high," the output of the clock divider can be swapped, for example, by inverting the output from the clock divider. When the output is inverted, instead of outputting the I phase, the Q phase is output; similarly, instead of outputting IB, QB is output. A multiplexer (mux) can be used for the swapping, as provided in the circuit diagram later in this document.

[0047] Reference again Figure 2 , Figure 2 The NOP command is illustrated to occur in coordination with the rising edge of the first clock signal 204 (eg, when the CS signal 202 is asserted). In this example, no "clock swap" is indicated.

[0048] In contrast, Figure 4 Clock swapping according to some embodiments is illustrated. In an example, an external clock signal 402 is provided. When a NOP command occurs (e.g., when the CS signal 404 is asserted), the clock signal with the corresponding rising edge may be the second (e.g., "even") clock signal 406, as shown at point 407. Thus, the clocks may be swapped at 408, for example, by delaying the edge of each of the even and odd clock signals by one full system (external) clock cycle. In an example, the delay may be achieved by "swapping" the (I, Q) and (IB, QB) phases in pairs.

[0049] Figure 5 A signal diagram including a command lock signal and a clock swap signal is generally illustrated. In the example of swapping clock signals, a command decode lock signal 500 can be generated in coordination with a clock swap event. Lock signal 500 can be used to enforce a lock window 512, or a time interval during which no operations or commands are executed, for example to protect circuitry that may be adversely affected by irregular clock signal patterns during a clock swap event. For example, adjacent flip-flops (flip-flops) connected to or controlled by the divided clock signal can be disabled during a "swap" event. Figure 5 ) or other adjacent elements perform operations during the lockout window.

[0050] exist Figure 5In the example of FIG. 5 , a self-refresh exit (SRX) command is received at signal 501. An external clock is shown at signal 502. Four phase signals of the first and second internal clocks are shown at 504 (I phase or 0 degrees), 506 (Q phase or 180 degrees), 508 (IB phase or 90 degrees), and 510 (QB phase or 270 degrees). Lock signal 500 goes high, or is enabled, while swapping occurs at lock window 512, during which signals 504 and 506 are swapped, and signals 508 and 510 are swapped.

[0051] Figure 6A An example of a clock divider circuit system 600 is generally described. In this example, four signals are provided, each separated by a phase or a number of degrees, for example, 90 degrees or a fraction of a clock period. Pin 602 provides I phase or 0 degrees, pin 604 provides Q phase or 180 degrees, pin 606 provides IB phase or 90 degrees, and pin 608 provides QB phase or 270 degrees. The different phase signals are provided based on the system clock signal CLKT.

[0052] Figure 6B An example of clock switching circuitry and control logic is generally described. The example includes clock switching circuitry 612, which can provide signal switching when indicated for I-phase and Q-phase signals. Clock switching circuitry 614 can provide signal switching when indicated for IB-phase and QB-phase signals.

[0053] Figure 6C An example of a clock switching circuit system is generally described. In the example, Figure 6C Additional details regarding clock swapping circuitry according to some embodiments are provided. For example, swap 616 (if high) indicates that swapping should not occur, and swap signal 618 (if high) indicates that swapping should occur. The circuitry in block 620 includes a multiplexer (mux) for performing signal swapping operations and is configured to provide outputs including a pair of internal clock signals 622 and 624, which can be swapped signals or the original non-swapped signals.

[0054] Figure 7A and 7BAn example of a portion of command decoding circuitry is generally described. The decoding circuitry can be configured to recognize NOP commands on first and second command paths (e.g., such as may be associated with self-refresh entry and / or exit operations). In an example, block 702 includes an even decoder configured to detect commands arriving via the second (or "even") pipeline. For example, block 702 may include circuitry configured to recognize NOP commands on the second command pipeline and provide an output signal or a NOPE command when one or more NOP commands are recognized in the second command pipeline. In an example, block 704 includes an odd decoder configured to detect commands arriving via the first (or "odd") pipeline. For example, block 704 may include circuitry configured to recognize NOP commands on the first command pipeline and provide an output signal or a NOPO command when one or more NOP commands are recognized in the first command pipeline. In an example, blocks 702 and 704 may include different instances of the same circuitry but applied to different pipelines.

[0055] exist Figure 7A In an example, block 706 includes command decoder circuitry configured to monitor or capture NOP command information for the first and second pipelines and to monitor or capture information regarding a self-refresh exit (SRX) command. For example, receiving an exit command can have the same or similar effect as a NOP command in terms of triggering clock swap detection and / or implementing an event. In an example, block 706 includes logic configured to identify whether multiple NOP commands have been received. In some examples, clock swapping can be inhibited unless or until a specified number of discrete NOP commands (e.g., three consecutive NOP commands in a particular pipeline) are received.

[0056] exist Figure 7B In the illustrated portion of the command decoding circuitry, a NOP command may be configured to detect which of the first and second command pipelines arrives first or earliest. Based on the detection result on the self-refresh exit NOP command signal, a signal may be generated indicating whether a clock shift is required according to various embodiments.

[0057] In an example, the input lanes 708 / 710 pair is coupled to an arbiter circuitry that detects the pipeline carrying the first NOP command of the SRX routine. The input lanes 708 / 710 pair can be configured to receive output signals, such as NOPE and NOPO commands, from portions of the decoder circuitry illustrated in the examples of, for example, blocks 702 and 704, respectively. The arbiter circuitry can, for example, mask the NOPE command when a NOPO command is captured earlier, or can mask the NOPO command when a NOPE command is captured earlier. Figure 7B In the example of FIG. 7 , the clock swap indicator signal 712 may be switched based on a detection result indicating whether a clock swap is required.

[0058] Figure 8A An example of a command lock timing circuit system is generally described. At the input of the lock timing circuit system, the circuit system can be configured to receive a self-refresh, NOP and / or power-on reset signal. In response, the circuit system can provide a CLKSWAP_START signal to set the flip-flop 804. The output of the flip-flop can be processed or delayed (for example, using one or more signal delay elements) and can be fed back to the flip-flop 804 via the feedback path 806, thereby forming a timeout mechanism. The timeout can be configured so that the signal flow will settle to a final state within a specified command lock window, for example, corresponding to a specific number of clock cycles. The lock window can have a sufficient duration or interval length so that the clock swap event can be completed. In an example, a power-on reset signal can be introduced at the middle portion of the feedback path 806 to skip some or all delay elements.

[0059] Figure 8B Generally illustrates the signal diagram including the command lock window. Figure 8B In an example, the command lock window may be triggered at 810, for example, in coordination with the entry of a self-refresh or the initiation of a self-refresh routine. In an example, a clock swap event may occur during the lock window 812. Irregular clock signals during the clock swap event may result in erroneous commands, and thus, for example, during the lock window 812, commands arriving during the clock swap event may be intentionally paused or discarded. In an example, the number of cycles used to implement the clock swap may be less than the number of cycles in the lock window 812. After the self-refresh routine is completed, the internal clock generator 118 (e.g., Figure 1 DLL shown in ).

[0060] Figure 9 A signal diagram generally illustrates an example of a delay locked loop (DLL) that is reset after a self-refresh event. In an example, a self-refresh routine may be initiated at time 900 (e.g., at SRE) and the self-refresh routine may end at time 902 (e.g., at SRX). In an example, during some portion of the self-refresh routine, clock synchronization (e.g., with a system clock) may be lost and may be reestablished later, e.g., after the self-refresh routine. Figure 9 In an example, a clock swap event 904 may be initiated at or in coordination with a self-refresh exit command. A DLL reset command signal 906 may be asserted (e.g., after a self-refresh exit) and the clock signals may be resynchronized. For example, a DLL reset interval may be initiated in coordination with a self-refresh exit routine. Coarse lock may be established within a number of clock cycles (e.g., a number of clock cycles typically exceeding the number of cycles used for a self-refresh routine and / or clock swap events). At time 908, DLL lock may be achieved and the system may continue normal command processing operations.

[0061] According to various examples, a clock swap event can be performed at the earliest possible logic point, such as upon receipt of a system clock signal or shortly thereafter (e.g., in a memory chip). Downstream circuitry, such as including internal clock generator 118, can then receive and use the correctly aligned clock signal output from the clock swap circuit.

[0062] Figure 10 An example of a method 1000 for determining clock signal timing using NOP command signal detection is generally described. In method 1000, an internal clock signal can be provided, for example, using an internal clock generator 118 (e.g., a DLL) circuitry to align output data with a system clock. At operation 1002, method 1000 includes generating a first clock signal and a second clock signal based on the system clock signal. In an example, the first and second clock signals can be out of phase with each other.

[0063] At decision operation 1004, method 1000 may include determining whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or the second clock signal. In an example, the initial operation of the self-refresh exit operation may include a no operation (NOP) command, or a series of multiple temporally adjacent NOP commands on one or more corresponding command buses (e.g., in a memory device). In an example, reference may be made to Figure 3 To understand operation 1004, Figure 3 The command associated with exiting from the self-refresh operation may include a NOP command 306, but embodiments are not limited to NOP commands. In an example, various command detection circuit systems (e.g., using at least one of the commands referenced herein) may be used. Figure 6A and 6B In an example, the NOP command detection circuitry may be configured to provide a detection result, such as a signal that may include information about whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first or second clock signal.

[0064] If, at decision operation 1004, the NOP command coincides with a rising edge of the first clock signal (e.g., corresponding to the first command pipeline), method 1000 may continue with operation 1006. If, at decision operation 1004, the NOP command coincides with a rising edge of the second clock signal (e.g., corresponding to the second command pipeline), method 1000 may continue with operation 1008.

[0065] In an example of method 1000, the detection result can be used to switch the behavior of a clock switching circuit. The clock switching circuit can receive the detection result and the first and second clock signals and, in response, can provide an odd clock signal and an even clock signal corresponding to the first and second clock signals, respectively. The timing or phase of the odd and even clock signals can depend on the value of the detection result. For example, at operation 1006, method 1000 can include providing the even and odd clock signals that are out of phase with the first and second clock signals, respectively. At operation 1008, method 1000 can include providing the even and odd clock signals that are in phase with the first and second clock signals, respectively.

[0066] Figure 11 A block diagram illustrates an example machine (e.g., a host system) 1100 that may include one or more memory devices and / or memory systems (e.g., that may include or use clock shifting circuitry as described herein). The machine 1100 may benefit from enhanced memory performance resulting from the use of one or more of the described memory devices and / or memory systems, thereby facilitating improved performance of the machine 1100 (with respect to many such machines or systems, efficient reading and writing of memory may facilitate improved performance of a processor or other component of the machine), as further described below.

[0067] In some embodiments, the machine 1100 may be a standalone device or may be connected (e.g., using a network) to other machines. In a networked deployment, the machine 1100 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, the machine 1100 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1100 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any other machine capable of executing instructions (sequentially or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute an instruction set (or multiple instruction sets) to perform any one or more of the methodologies discussed herein, such as in cloud computing, software as a service (SaaS), or other computer cluster configurations.

[0068] As described herein, examples may include or be operable by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity comprising hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership can be flexible over time and with the variability of the underlying hardware. A circuit system includes components that can perform specific tasks individually or in combination during operation. In an example, the hardware of a circuit system may be immutably designed to perform a specific operation (e.g., hard-wired). In an example, the hardware of a circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include computer-readable media that has been physically modified (e.g., magnetic properties, electrical properties, removable placement, etc.) to encode instructions for a specific operation. When the physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor, or vice versa. The instructions enable participating hardware (e.g., execution units or loading mechanisms) to generate components of the circuit system in the hardware via variable connections to perform portions of a specific task when in operation. Thus, the computer-readable media is communicatively coupled to other components of the circuit system during device operation. In an example, any one of the physical components can be used in more than one component of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system, or reused by a third circuit in the second circuit system at a different time.

[0069] A machine (e.g., a computer system, a host system, etc.) 1100 may include a processing device 1102 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 1104 (e.g., read-only memory (ROM), dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1106 (e.g., static random access memory (SRAM), etc.), and a storage system 1108, some or all of which may communicate with each other via a communication interface (e.g., a bus) 1130. In one example, the main memory 1104 includes one or more memory devices as described in the examples above.

[0070] The processing device 1102 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a combination of instruction sets. The processing device 1102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1102 may be configured to execute instructions 1124 for performing the operations and steps discussed herein. The computer system 1100 may further include a network interface device 1120 for communicating via a network 1126.

[0071] The storage system 1108 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1124 or software embodying any one or more of the methodologies or functionality described herein. The instructions 1124 may also reside, completely or at least partially, within the main memory 1104 or the processing device 1102 during execution thereof by the computer system 1100, the main memory 1104 and the processing device 1102 also constituting machine-readable storage media.

[0072] The term "machine-readable storage medium" should be taken to include a single medium or multiple media that stores one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium with a plurality of particles having a constant (e.g., stationary) mass. Thus, a centralized machine-readable medium does not transitorily propagate signals. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), and flash memory devices; magnetic disks, such as internal and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0073] The machine 1100 may further include a display unit 1110, an alphanumeric input device 1112 (e.g., a keyboard), and a user interface (UI) navigation device 1114 (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touch screen display. The machine 1100 may include a signal generating device 1118 (e.g., a speaker), or one or more sensors 1116, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 1100 may include an output controller 1128 (e.g., a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC)), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0074] Instructions 1124 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage system 1108, which can be accessed by main memory 1104 for use by processing device 1102. Main memory 1104 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of memory than storage system 1108 (e.g., SSD), which is suitable for long-term storage, including when in a "power-off" condition. Instructions 1124 or data used by a user or machine 1100 are typically loaded into main memory 1104 for use by processing device 1102. When main memory 1104 is full, virtual space from storage system 1108 can be allocated to supplement main memory 1104; however, because storage system 1108 devices are typically slower than main memory 1104, with write speeds typically at least half the read speed, using virtual memory can significantly reduce the user experience (compared to main memory 1104 (e.g., DRAM)) due to storage system latency. Furthermore, using storage system 1108 for virtual storage may significantly reduce the usable lifespan of storage system 1108 .

[0075] The instructions 1124 may further be transmitted or received via the network interface device 1120 using a transmission medium via the network 1126 using any of a number of transmission protocols, such as frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network such as the Internet, a mobile telephone network such as a cellular network, a plain old telephone (POTS) network, and a wireless data network such as a wireless network known as a cellular network. The Institute of Electrical and Electronics Engineers (IEEE) 1102.15 series of standards, known as 16 family of standards), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, and the like. In an example, network interface device 1120 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to network 1126. In an example, network interface device 1108 may include multiple antennas to communicate wirelessly using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1100, including digital or analog communication signals or other intangible media to facilitate communication of such software.

[0076] In order to better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are set forth below as digital recognition examples.

[0077] Example 1 includes an apparatus comprising: clock circuitry configured to generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other; and detection circuitry configured to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. Example 1 may further include processing circuitry configured to receive the first and second clock signals and the detection result and, in response, provide an odd clock signal and an even clock signal corresponding to the first and second clock signals, respectively, and provide the odd clock signal and the even clock signal out of phase with the first and second clock signals when the detection result coincides with the rising edge of the first clock signal, and provide the odd clock signal and the even clock signal in phase with the first and second clock signals when the detection result coincides with the rising edge of the second clock signal.

[0078] In Example 2, the subject matter of Example 1 may include or use duty cycle adjustment (DCA) circuitry configured to alter a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

[0079] In Example 3, the subject matter of any one or more of Examples 1-2 may include the odd clock signal and the even clock signal each at a frequency of approximately half the frequency of the system clock signal of the apparatus and 180 degrees out of phase with each other.

[0080] In Example 4, the subject matter of any one or more of Examples 1 to 3 may include or use a command processor configured to process commands for the device based on instructions on a command bus, and the command processor may be configured to initiate a command lock for commands on the command bus in coordination with the self-refresh exit operation.

[0081] In Example 5, the subject matter of any one or more of Examples 1-4 can include providing the odd clock signal and the even clock signal out of phase with the first clock signal comprising swapping outputs of a clock divider pair.

[0082] In Example 6, the subject matter of any one or more of Examples 1-5 may include the self-refresh exit operation comprising a self-refresh entry (SRE) command and a self-refresh exit (SRX).

[0083] In Example 7, the subject matter of Example 6 may include the initial operation of the self-refresh exit operation comprising a no operation (NOP) command or a sequenced string of multiple NOP commands.

[0084] In Example 8, the subject matter of any one or more of Examples 1-7 includes a memory device including the clock circuitry, the detection circuitry, and / or the processing circuitry.

[0085] In Example 9, the subject matter of Example 8 may include the memory device comprising a dynamic random access memory (DRAM) device.

[0086] Example 10 is a clock commutation circuit for a memory device, the clock commutation circuit comprising: a commutation signal generator configured to provide a commutation signal indicating an earlier arrival of an instruction (e.g., a NOP instruction or a command) on a first command bus or a second command bus; and a multiplexing circuit configured to receive an input clock signal from a clock divider circuit and the commutation signal from the commutation signal generator, and selectively provide odd and even clock signals that are in phase with or out of phase with the input clock signal based on the commutation signal.

[0087] In Example 11, the subject matter of Example 10 may include or use the clock divider circuit to receive a system clock signal, and the input clock signal has a frequency lower than a frequency of the system clock signal.

[0088] In Example 12, the subject matter of any one or more of Examples 10-11 may include or use the first and second command buses, wherein the first and second command buses are configured to transmit memory commands for the memory device.

[0089] In Example 13, the subject matter of any one or more of Examples 10-12 may include the instruction on the first command bus or the second command bus comprising an instruction subsequent to a self-refresh command.

[0090] Example 14 is a method comprising: generating a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other; providing a detection result indicating whether the initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; receiving the first clock signal and the second clock signal and the detection result and, in response, providing an odd clock signal and an even clock signal corresponding to the first clock signal and the second clock signal, respectively; and providing the odd clock signal and the even clock signal that are out of phase with the first clock signal and the second clock signal when the detection result coincides with the rising edge of the first clock signal, and providing the odd clock signal and the even clock signal that are in phase with the first clock signal and the second clock signal when the detection result coincides with the rising edge of the second clock signal.

[0091] In Example 15, the subject matter of Example 14 may include initiating a duty cycle adjustment (DCA) routine to alter a duty cycle timing characteristic of at least one of the first clock signal and the second clock signal.

[0092] In Example 16, the subject matter of any one or more of Examples 14-15 can include the odd clock signal and the even clock signal each being at a frequency of approximately half the frequency of a system clock and being 180 degrees out of phase with each other.

[0093] In Example 17, the subject matter of any one or more of Examples 14-16 can include enabling a command lock for commands on a command bus of the memory device in coordination with the self-refresh exit operation.

[0094] In Example 18, the subject matter of any one or more of Examples 14-17 can include providing the odd clock signal and the even clock signal out of phase with the first clock signal and the second clock signal, including swapping outputs of a clock divider.

[0095] In Example 19, the subject matter of any one or more of Examples 14-18 includes the self refresh exit operation comprising a self refresh entry (SRE) command and a self refresh exit (SRX).

[0096] In Example 20, the subject matter of Example 19 may include the initial operation of the SRX command comprising a no operation (NOP) command or a sequenced string of multiple NOP commands.

[0097] Example 21 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-20.

[0098] Example 22 is an apparatus comprising means for implementing any of Examples 1-20.

[0099] Example 23 is a system for implementing any of Examples 1-20.

[0100] Example 24 is a method for implementing any of Examples 1-20.

[0101] Each of these non-limiting examples can stand on its own or can be combined with one or more of the other examples in various permutations or combinations.

[0102] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. Furthermore, the inventors also contemplate examples using any combination or arrangement of the elements (or one or more aspects thereof) shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0103] All publications, patents, and patent files cited in this file are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of any inconsistency between the usages in this file and those so incorporated by reference, the usage in the incorporated references should be considered supplementary to that in this file; for irreconcilable inconsistencies, the usage in this file controls.

[0104] In this file, independent of any other examples or uses of "at least one" or "one or more", the terms "a / an" as commonly used in patent files are used to include one or more than one. In this file, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article or process that includes elements other than the elements listed after the term in the claim is still considered to be within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0105] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0106] This detailed description is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0107] It will be understood that when an element is referred to as being “on,” “connected to,” or “coupled with” another element, it can be directly on, connected, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled with” another element, there are no intervening elements or layers present. If two elements are shown in a drawing with a line connecting them, the two elements may be coupled or directly coupled unless otherwise indicated.

[0108] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, higher-level language code, or the like. This code may include computer-readable instructions for performing the various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, a hard disk, a removable disk, a removable optical disk (such as a compact disk and a digital video disk), a cassette tape, a memory card or stick, a random access memory (RAM), a read-only memory (ROM), and the like.

[0109] The above description is intended to be illustrative and non-restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments after reviewing the above description. The description abstract is provided to comply with 37 CFR § 1.72 (b) to allow the reader to quickly determine the essence of the technical disclosure. The description abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be interpreted as an expectation that unclaimed disclosed features are essential to any claim. The fact is that the subject matter of the present invention may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims together with the full range of equivalents authorized by these claims.

Claims

1. A device comprising: a clock circuit system configured to generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other; detection circuitry configured to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; and A processing circuit system configured to: receiving the first clock signal and the second clock signal and the detection result and in response, providing an odd clock signal and an even clock signal corresponding to the first clock signal and the second clock signal, respectively; and When the detection result coincides with the rising edge of the first clock signal, the odd clock signal and the even clock signal are provided which are out of phase with the first clock signal and the second clock signal, and when the detection result coincides with the rising edge of the second clock signal, the odd clock signal and the even clock signal are provided which are in phase with the first clock signal and the second clock signal.

2. The apparatus of claim 1, further comprising duty cycle adjustment (DCA) circuitry configured to alter a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

3. The apparatus of claim 1, wherein the odd clock signal and the even clock signal are each at a frequency of approximately half the frequency of the system clock signal of the apparatus and are 180 degrees out of phase with each other.

4. The apparatus of claim 1 , further comprising a command processor configured to process commands for the apparatus based on instructions on a command bus, wherein the command processor is configured to enable a command lock for commands on the command bus in coordination with the self-refresh exit operation.

5. The apparatus of claim 1, wherein the instructions to provide the odd clock signal and the even clock signal out of phase with the first clock signal comprise swapping outputs of a pair of clock dividers.

6. The apparatus of claim 1, wherein the self-refresh exit operation comprises a self-refresh entry (SRE) command and a self-refresh exit (SRX) command. 7 . The apparatus of claim 6 , wherein the initial operation of the self-refresh exit operation comprises a no operation (NOP) command.

8. The apparatus of claim 1, further comprising a memory device including the clock circuitry, the detection circuitry, and the processing circuitry.

9. The apparatus of claim 8, wherein the memory device comprises a dynamic random access memory (DRAM) device.

10. A clock switching circuit for a memory device, the clock switching circuit comprising: a swap signal generator configured to provide a swap signal indicating an earlier arrival of a command on the first command bus or the second command bus; and A multiplexing circuit is configured to receive an input clock signal from a clock divider circuit and the swap signal from the swap signal generator and selectively provide odd and even clock signals that are in phase with or out of phase with the input clock signal based on the swap signal.

11. The clock swapping circuit of claim 10, further comprising the clock divider circuit configured to receive a system clock signal, wherein the input clock signal has a lower frequency than a frequency of the system clock signal.

12. The clock swapping circuit of claim 10, further comprising the first command bus and the second command bus, wherein the first command bus and the second command bus are configured to transmit memory commands for the memory device. 13 . The clock swapping circuit of claim 10 , wherein the command on the first command bus or the second command bus comprises a command after a self-refresh exit command.

14. A method comprising: generating a first clock signal and a second clock signal based on a system clock signal, wherein the first clock signal and the second clock signal are out of phase with each other; providing a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; receiving the first clock signal and the second clock signal and the detection result and in response, providing an odd clock signal and an even clock signal corresponding to the first clock signal and the second clock signal, respectively; and When the detection result coincides with the rising edge of the first clock signal, the odd clock signal and the even clock signal are provided which are out of phase with the first clock signal and the second clock signal, and when the detection result coincides with the rising edge of the second clock signal, the odd clock signal and the even clock signal are provided which are in phase with the first clock signal and the second clock signal.

15. The method of claim 14, further comprising initiating a duty cycle adjustment (DCA) to alter a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

16. The method of claim 14, wherein the odd clock signal and the even clock signal are each at a frequency of approximately half the frequency of a system clock and are 180 degrees out of phase with each other.

17. The method of claim 14, further comprising initiating a command lock for commands on a command bus in coordination with the self-refresh exit operation.

18. The method of claim 14, wherein providing the odd and even clock signals out of phase with the first and second clock signals comprises swapping outputs of clock dividers.

19. The method of claim 14, wherein the self-refresh exit operation comprises a self-refresh entry (SRE) command and a self-refresh exit (SRX) command.

20. The method of claim 19, wherein the initial operation of the SRX comprises a no operation (NOP) command.

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