Storage device

Abstract

Provided is a memory device capable of achieving miniaturization or high integration. The memory device includes a memory cell and a first insulator. The memory cell includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductor, a second insulator on the first conductor, and a second conductor on the second insulator. The first insulator is disposed on the second conductor. The transistor includes a second conductor, a third conductor on the first insulator, an oxide semiconductor, a third insulator on the oxide semiconductor, and a fourth conductor on the third insulator. The first insulator and the third conductor are provided with an opening that reaches the second conductor. A portion of the oxide semiconductor is disposed in the opening. The oxide semiconductor has a region in contact with the top surface of the second conductor, a region in contact with the side surface of the third conductor, and a region in contact with a part of the top surface of the third conductor. An angle formed by a side surface of the first insulator located at the opening and a top surface of the first conductor is 45 degrees or more and less than 90 degrees.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a storage device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also a form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), CPU (Central Processing Unit), memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer to form a chip and having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0006] In addition, a technology for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply described as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known, and oxide semiconductors have attracted attention as other materials.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. [Prior technical literature] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Non-patent literature]

[0010] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention Technical problem to be solved by the invention

[0011] One of the purposes of one embodiment of the present invention is to provide a storage device that can achieve miniaturization or high integration. Another purpose of one embodiment of the present invention is to provide a storage device with a high operating speed. Another purpose of one embodiment of the present invention is to provide a storage device with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a storage device with small unevenness in the electrical characteristics of transistors. Another purpose of one embodiment of the present invention is to provide a storage device with high reliability. Another purpose of one embodiment of the present invention is to provide a storage device with a large on-state current. Another purpose of one embodiment of the present invention is to provide a storage device with low power consumption. Another purpose of one embodiment of the present invention is to provide a novel storage device. Another purpose of one embodiment of the present invention is to provide a method for manufacturing a novel storage device.

[0012] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc. Solutions to technical problems

[0013] One embodiment of the present invention is a memory device, which includes a memory cell and a first insulator. The memory cell includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductor, a second insulator on the first conductor, and a second conductor on the second insulator. The first insulator is arranged on the first conductor, the second insulator, and the second conductor. The transistor includes a second conductor, a third conductor on the first insulator, an oxide semiconductor, a third insulator, and a fourth conductor. An opening portion reaching the second conductor is provided in the first insulator and the third conductor. At least a portion of the oxide semiconductor is arranged in the opening portion. The oxide semiconductor has a region in contact with the top surface of the second conductor in the opening portion, a region in contact with the side surface of the third conductor in the opening portion, and a region in contact with at least a portion of the top surface of the third conductor. The third insulator is arranged on the oxide semiconductor in such a manner that at least a portion of it is located in the opening portion. The fourth conductor is arranged on the third insulator in such a manner that at least a portion of it is located in the opening portion. The angle formed by the side surface of the first insulator in the opening portion and the top surface of the first conductor is greater than 45 degrees and less than 90 degrees.

[0014] In addition, one embodiment of the present invention is a storage device, which includes a storage unit and a first insulator. The storage unit includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductor, a second insulator on the first conductor, and a second conductor on the second insulator. The first insulator is arranged on the first conductor, the second insulator, and the second conductor. The transistor includes a second conductor, a third conductor on the first insulator, an oxide semiconductor, a third insulator, and a fourth conductor. An opening portion reaching the second conductor is provided in the first insulator and the third conductor. At least a portion of the oxide semiconductor is arranged in the opening portion. The oxide semiconductor has a region in contact with the top surface of the second conductor in the opening portion, a region in contact with the side surface of the third conductor in the opening portion, and a region in contact with at least a portion of the top surface of the third conductor. The third insulator is arranged on the oxide semiconductor in such a manner that at least a portion of it is located in the opening portion. The fourth conductor is arranged on the third insulator in such a manner that at least a portion of it is located in the opening portion. The shape of the bottom of the fourth conductor located in the opening portion is needle-shaped.

[0015] In the above-mentioned memory device, the channel length of the transistor is preferably smaller than at least the channel width of the transistor.

[0016] In the above-mentioned memory device, the second insulator preferably includes a material having ferroelectricity.

[0017] In the above-mentioned memory device, the second insulator preferably includes a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

[0018] In the above memory device, the oxide semiconductor preferably contains any one or more selected from In, Ga, and Zn.

[0019] In addition, in the above-mentioned storage device, preferably, the first insulator includes a stacked body, the stacked body includes a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer contains silicon and nitrogen, the second layer contains silicon and oxygen, and the third layer contains silicon and nitrogen.

[0020] Furthermore, in the above-mentioned storage device, preferably, the fourth conductor extends in a first direction, and the third conductor extends in a second direction orthogonal to the first direction.

[0021] In the above-mentioned storage device, it is preferable that the storage device further includes a plurality of layers including storage cells, and the plurality of layers are stacked. Effects of the Invention

[0022] According to one embodiment of the present invention, a storage device that can be miniaturized or highly integrated can be provided. In addition, a storage device with a high operating speed can be provided. In addition, a storage device with high reliability can be provided. In addition, a storage device with small unevenness in the electrical characteristics of transistors can be provided. In addition, a storage device with good electrical characteristics can be provided. In addition, a storage device with a large on-state current can be provided. In addition, a storage device with low power consumption can be provided. In addition, a novel storage device can be provided. In addition, a method for manufacturing a novel storage device can be provided.

[0023] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A is a plan view showing an example of a storage device. Figures 1B to 1D is a cross-sectional view showing an example of a storage device. Figure 1E This is a circuit diagram for explaining an example of the structure of a storage device. Figure 2A and Figure 2B is a cross-sectional view showing an example of a storage device. Figure 3A and Figure 3B is a cross-sectional view showing an example of a storage device. Figure 4 is a cross-sectional view showing an example of a storage device. Figure 5A and Figure 5B is a cross-sectional view showing an example of a storage device. Figure 5C is a plan view showing an example of a storage device. Fig. 6A and Figure 6B is a cross-sectional view showing an example of a storage device. Figure 6C is a plan view showing an example of a storage device. FIG. 7A to FIG. 7C is a cross-sectional view showing an example of a storage device. Fig. 8A and Figure 8B is a cross-sectional view showing an example of a storage device. Fig. 9A is a plan view showing an example of a storage device. Fig. 9B and Fig. 9C is a cross-sectional view showing an example of a storage device. FIG. 10A to FIG. 10Cis a cross-sectional view showing an example of a storage device. FIG. 11A to FIG. 11C is a cross-sectional view showing an example of a storage device. FIG. 12A to FIG. 12C is a cross-sectional view showing an example of a storage device. FIG. 13A to FIG. 13C is a cross-sectional view showing an example of a storage device. Fig.14A is a plan view showing an example of a storage device. FIG. 14B to FIG. 14D is a cross-sectional view showing an example of a storage device. Fig.15A and Fig. 15B is a cross-sectional view showing an example of a storage device. Fig.16A and Fig. 16B is a cross-sectional view showing an example of a storage device. Fig.17A is a plan view showing an example of a storage device. FIG. 17B to FIG. 17D is a cross-sectional view showing an example of a storage device. Fig.18A This is a plan view showing an example of a method for manufacturing a storage device. Fig.18B and Fig.18C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.19A This is a plan view showing an example of a method for manufacturing a storage device. Fig.19B and Fig.19C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig. 20A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 20B and Fig. 20C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.21A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 21B and Fig. 21C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.22A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 22B and Fig. 22C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.23A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 23B and Fig.23C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.24A This is a plan view showing an example of a method for manufacturing a storage device. Fig. 24B and Fig.24C is a cross-sectional view showing an example of a method for manufacturing a storage device. Fig.25A is a plan view showing an example of a storage device. Fig.25B is a cross-sectional view showing an example of a storage device. Fig.26A is a plan view showing an example of a storage device. Fig.26B is a cross-sectional view showing an example of a storage device. Fig.27A is a plan view showing an example of a storage device. Fig.27B is a cross-sectional view showing an example of a storage device. Fig.28A and Fig.28B is a plan view showing an example of a storage device. FIG. 29A to FIG. 29E It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 30A to FIG. 30D This is a cross-sectional view of a metal oxide according to one embodiment of the present invention. FIG. 31A to FIG. 31D It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 32A to FIG. 32C It is a cross-sectional view explaining a method for depositing a metal oxide according to one embodiment of the present invention. Fig.33 is a block diagram illustrating a structural example of a storage device. Fig.34A It is a perspective schematic diagram illustrating a structural example of a storage device. Fig.34B is a circuit diagram illustrating a structural example of a storage device. Fig.35A and Fig.35B is a schematic diagram illustrating a configuration example of a storage device. Fig.36 is a circuit diagram illustrating a structural example of a storage device. Fig.37A and Fig.37B FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention. Fig.38A and Fig.38B This is a diagram for explaining an example of an electronic component. FIG. 39A to FIG. 39E is a schematic diagram of a storage device according to one embodiment of the present invention. FIG. 40A to FIG. 40H FIG. 1 is a diagram showing an electronic device according to one embodiment of the present invention. Fig.41 is a diagram showing an example of space equipment. Modes for Carrying Out the Invention

[0025] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0026] In addition, in the drawings, the size, thickness of the layer or the area are sometimes exaggerated for obvious reasons. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the shapes or numerical values ​​shown in the drawings are not limited. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally thinned due to treatments such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in the drawings, the same symbols are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0027] In addition, in particular, in a plan view (also referred to as a “top view”) or a perspective view, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0028] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0029] In addition, in this specification, for the sake of convenience, words and phrases indicating configuration such as "upper" and "lower" are used to describe the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited, and the words and phrases can be appropriately changed according to the situation.

[0030] For example, in this specification, etc., X and Y are connected, which means that X and Y are electrically connected. Here, X and Y are electrically connected, which means that an electric signal can be transmitted between X and Y when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between X and Y. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Here, X and Y are directly connected, which means that X and Y can transmit an electric signal between X and Y through wiring (or electrodes) without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

[0031] In addition, in this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. Furthermore, a transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., a channel formation region refers to a region where current mainly flows.

[0032] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0033] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase, the crystallinity may decrease, etc. may occur. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, sometimes the mixing of impurities leads to oxygen vacancies (also called V O : The formation of oxygenvacancy).

[0034] Note that in this specification, etc., oxynitride refers to a substance containing more oxygen than nitrogen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, oxynitride refers to a substance containing more nitrogen than oxygen in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.

[0035] In this specification, the term "insulator" may be referred to as an insulating film or insulating layer, the term "conductor" may be referred to as a conductive film or conductive layer, and the term "semiconductor" may be referred to as a semiconductor film or semiconductor layer.

[0036] In addition, in this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0037] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be referred to as "potential". Note that the ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc., etc., also changes according to the change of the reference potential.

[0038] In this specification and the like, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol for identification such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0039] Note that in this specification, etc., "high consistency" refers to a structure in which the height from the reference surface (for example, a flat surface such as a substrate surface) in a cross section is equal. For example, in the manufacturing process of a storage device, a flattening process (typically a CMP process) is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface treated by CMP is equal to the reference surface. Note that depending on the processing device, processing method or material of the processed surface during the CMP process, the heights of multiple layers are sometimes different. In this specification, etc., "high consistency" also includes the above situation. For example, in the case of a layer having two heights relative to the reference surface (referred to as the first layer and the second layer here), when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is less than 20nm, it is also referred to as "high consistency".

[0040] Note that in this specification, etc., "end alignment" refers to a situation where at least a portion of the contours of stacked layers overlap when viewed from above. For example, this includes a situation where the upper layer and the lower layer are processed by using the same mask pattern or a portion of them are processed by using the same mask pattern. However, strictly speaking, sometimes the contours do not overlap and the contour of the upper layer is located on the inside of the contour of the lower layer or the contour of the upper layer is located on the outside of the contour of the lower layer. These situations can also be said to be "end alignment".

[0041] Note that, in general, it is difficult to clearly distinguish between “completely consistent” and “substantially consistent.” Therefore, in this specification and the like, “consistent” includes both completely consistent and substantially consistent.

[0042] Note that in this specification, etc., the normally-on characteristic refers to a state in which a channel exists and current flows through a transistor even when no voltage is applied to the gate. Also, the normally-off characteristic refers to a state in which current does not flow through a transistor when no voltage is applied to the gate or when a ground potential is supplied to the gate.

[0043] In addition, in this specification, off-state current may be referred to as leakage current. In addition, in this specification, off-state current may refer to current flowing between a source and a drain when a transistor is in an off state, for example.

[0044] (Implementation Method 1) In this embodiment, refer to Figures 1A to 28B An example of a memory device according to one embodiment of the present invention and a method for manufacturing the same will be described. A memory device according to one embodiment of the present invention includes a transistor and a capacitor.

[0045] <Configuration Example of Storage Device> Reference Figures 1A to 1D The structure of a memory device including a transistor and a capacitor is described. Figures 1A to 1D 1 and 2 are a plan view and a cross-sectional view of a memory device including a transistor 200 and a capacitor 100 . Figure 1A is a plan view of the storage device. In addition, Figures 1B to 1D is a cross-sectional view of the storage device. Figure 1B It is along Figure 1A A cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Figure 1C It is along Figure 1A A cross-sectional view of the portion along the dashed line A3-A4 in FIG. Figure 1D is a cross-sectional view of a portion of transistor 200. Note that Figure 1A In the plan view, some components are omitted for clarity.

[0046] Note that arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings of this specification. Note that in this specification, "X direction" refers to the direction along the X axis, and sometimes the forward and reverse directions are not distinguished except for the cases clearly stated. The same is true for "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. Specifically, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, the X direction, Y direction, or Z direction is sometimes referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction".

[0047] Figures 1A to 1D The illustrated memory device includes an insulator 140 on a substrate (not shown), a memory cell 150 on the insulator 140, an insulator 280, and an insulator 283 on the memory cell 150. The insulator 140, the insulator 280, and the insulator 283 are used as interlayer films.

[0048] The memory cell 150 includes a capacitor 100 on an insulator 140 and a transistor 200 on the capacitor 100 .

[0049] The capacitor 100 includes a conductor 110 on an insulator 140, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130. In the capacitor 100, the conductor 120 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 110 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 130 is used as a dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0050] The insulator 280 is disposed on the capacitor 100 . That is, the insulator 280 is disposed on the conductor 110 , the insulator 130 , and the conductor 120 . In other words, the conductor 120 is disposed under the insulator 280 .

[0051] The transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. In the transistor 200, the oxide semiconductor 230 is used as a semiconductor layer, the conductor 260 is used as a gate electrode, the insulator 250 is used as a gate insulator, the conductor 120 is used as one of a source electrode and a drain electrode, and the conductor 240 is used as the other of the source electrode and the drain electrode.

[0052] like Figure 1B and Figure 1CAs shown, an opening 290 that reaches the conductor 120 is provided in the insulator 280 and the conductor 240. At least a portion of the oxide semiconductor 230 is disposed in the opening 290. In addition, the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 in the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a portion of the top surface of the conductor 240. The insulator 250 is disposed so that at least a portion thereof is located in the opening 290. The conductor 260 is disposed so that at least a portion thereof is located in the opening 290. In addition, as Figure 1B and Figure 1C As shown, the conductor 260 is preferably provided in a manner embedded in the opening 290 .

[0053] The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 and a region in contact with a portion of the top surface of the conductor 240 in the opening 290. In this way, since the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240, the area in contact between the oxide semiconductor 230 and the conductor 240 can be increased.

[0054] like Figures 1A to 1C As shown, the transistor 200 overlaps the capacitor 100. In particular, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200 and is used as the upper electrode of the capacitor 100, so the transistor 200 and the capacitor 100 share a part of the structure. By adopting this structure, the transistor 200 and the capacitor 100 can be arranged in a manner that does not significantly increase the occupied area when viewed from above. As a result, the occupied area of ​​the memory cell 150 can be reduced, so the memory cell 150 can be arranged at a high density to increase the storage capacity of the memory device. In other words, a high integration of the memory device can be achieved.

[0055] Figure 1E 2 is a circuit diagram of a storage device shown in this embodiment. Figure 1E As shown, Figures 1A to 1D The structure shown is used as a memory cell of a memory device. The memory cell includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

[0056] One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitor C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitor C is connected to the wiring PL.

[0057] Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. Figures 1A to 1C As shown in FIG. 1 , it is preferred that the conductor 260 extends in the Y direction and the conductor 240 extends in the X direction. By adopting this structure, the wiring BL and the wiring WL intersect each other. Figure 1A The wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited thereto. For example, the wiring PL may be parallel to the wiring WL (conductor 260) or the wiring BL (conductor 240).

[0058] Note that the storage unit will be described in detail in a later embodiment.

[0059] [Capacitor 100] The capacitor 100 includes a conductor 110 , an insulator 130 , and a conductor 120 .

[0060] The conductor 110 is provided on the insulator 140. The conductor 110 is used as the wiring PL, and can be provided in a planar shape, for example. As the conductor 110, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 110, for example, a highly conductive conductive material such as tungsten can be used. By using a highly conductive conductive material in this way, the conductivity of the conductor 110 can be improved, so that the conductor 110 can fully function as the wiring PL.

[0061] In addition, as the conductor 110, it is preferable to stack a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, it is also possible to have a structure in which titanium nitride is stacked on tungsten. Or, for example, it is also possible to have a structure in which a first titanium nitride, tungsten, and a second titanium nitride are stacked in sequence. By adopting such a structure, when an oxide insulator is used as the insulator 130, it is possible to suppress the conductor 110 from being excessively oxidized by the insulator 130.

[0062] The insulator 130 is provided on the conductor 110. It is preferable to use a material having a high relative dielectric constant, that is, a so-called high-k material, as described in [Insulator] described later as the insulator 130. By using the high-k material as the insulator 130, the thickness of the insulator 130 can be increased to a degree that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0063] In addition, as the insulator 130, it is preferred to stack an insulating layer composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic destruction of the capacitor 100 can be suppressed.

[0064] In addition, a material having ferroelectricity may be used as the insulator 130. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0065] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the atomic number ratio of the element M1, the element M2 and the element M3 can be appropriately set.

[0066] In addition, as a material that can have ferroelectricity, SrTaO 2 N、BaTaO 2 N and other perovskite-type oxynitrides, κ-type alumina GaFeO 3 wait.

[0067] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0068] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulator 130 can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0069] Metal oxides containing one or both of hafnium and zirconium are preferred because they can have ferroelectricity even if they are processed into a thin film of a few nm. Here, the thickness of the insulator 130 can be less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and further preferably less than 10 nm (typically, more than 2 nm and less than 9 nm). For example, the thickness is preferably more than 8 nm and less than 12 nm. By using a ferroelectric layer that can be thin-filmed, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that in this specification, etc., a material that can have ferroelectricity and is formed in a layered state is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0070] In addition, a metal oxide containing one or both of hafnium and zirconium is preferred because it can have ferroelectricity even when its area is small. For example, even if the area (occupied area) of the ferroelectric layer in top view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following may also have ferroelectric properties. In addition, sometimes the ferroelectric layer has an area (occupied area) of 10000nm when viewed from above. 2 Below or 1000nm 2 The area occupied by the capacitor 100 can be reduced by reducing the area of ​​the ferroelectric layer.

[0071] Ferroelectrics are insulators that are polarized internally when exposed to an external electric field and that maintain polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses the material as a dielectric. Nonvolatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, and the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0072] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 130 is any one or more selected from the group consisting of cubic system, tetragonal system, orthorhombic system, monoclinic system and hexagonal system. In addition, the insulator 130 may also have an amorphous structure. At this time, the insulator 130 may also have a composite structure of an amorphous structure and a crystal structure.

[0073] Alternatively, a structure may be adopted in which the side end of the insulator 130 is aligned with the side end of the conductor 110. With such a structure, the insulator 130 and the conductor 110 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0074] Alternatively, the insulator 130 may cover the side end portion of the conductor 110. This can prevent the conductor 110 and the conductor 120 from being short-circuited.

[0075] The conductor 120 is provided in a manner of contacting a portion of the top surface of the insulator 130. Here, the electrostatic capacitance of the capacitor 100 depends on the area of ​​the conductor 120, so the area of ​​the island-shaped conductor 120 may be appropriately set according to the design value of the capacitor 100. For example, by increasing the area of ​​the island-shaped conductor 120, the electrostatic capacitance of the capacitor 100 can be increased. By increasing the electrostatic capacitance per unit area of ​​the capacitor 100 in this way, the read operation of the storage device can be stabilized.

[0076] Note that in this specification and the like, an island shape refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0077] The side ends of the conductor 120 are located inside the side ends of the conductor 110 in both the X direction and the Y direction. When the insulator 130 covers the side ends of the conductor 110 , the side ends of the conductor 120 may be located outside the side ends of the conductor 110 .

[0078] As the conductor 120, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 120, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, for example, there can also be a structure in which tantalum nitride is stacked on titanium nitride. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230. By adopting such a structure, excessive oxidation of the conductor 120 due to the oxide semiconductor 230 can be suppressed. In addition, when an oxide insulator is used for the insulator 130, excessive oxidation of the conductor 120 due to the insulator 130 can be suppressed. Alternatively, as the conductor 120, for example, there can be a structure in which tungsten is stacked on titanium nitride.

[0079] [Transistor 200] like Figures 1A to 1C As shown, the transistor 200 may include a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 arranged in contact with a top surface of the conductor 120 exposed in an opening 290, a side surface of the insulator 280 in the opening 290, a side surface of the conductor 240 in the opening 290, and at least a portion of a top surface of the conductor 240, an insulator 250 arranged in contact with the top surface of the oxide semiconductor 230, and a conductor 260 arranged in contact with the top surface of the insulator 250.

[0080] At least a part of the components of the transistor 200 is disposed in the opening 290 . Here, the bottom of the opening 290 is the top surface of the conductor 120 , and the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240 .

[0081] The sidewall of the opening 290 preferably has a tapered shape. By making the sidewall of the opening 290 have a tapered shape, the coverage of the oxide semiconductor 230 or the insulator 250 can be improved, thereby reducing defects such as voids. For example, the angle formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 ( Figure 1B The angle θ) shown is preferably greater than 45 degrees and less than 90 degrees. Alternatively, it is preferably greater than 45 degrees and less than 75 degrees. Alternatively, it is preferably greater than 45 degrees and less than 65 degrees.

[0082] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to a substrate surface or a formed surface. For example, a region having an angle (hereinafter sometimes referred to as a taper angle) formed by the inclined side surface and the substrate surface is less than 90°. Note that the side surface and the substrate surface of a component do not necessarily have to be completely flat, and may be a nearly planar shape with a slight curvature or a nearly planar shape with a slight convexity.

[0083] Figure 1B and Figure 1C The shape of the opening 290 shown is a truncated cone. In this case, the shape of the opening 290 when viewed from above is circular, and the shape of the opening 290 when viewed from a cross section is trapezoidal. In addition, the area of ​​the upper bottom surface of the truncated cone (for example, the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone (the top surface of the conductor 120 exposed in the opening 290). In this case, the maximum diameter of the opening 290 can be calculated based on the upper bottom surface of the truncated cone. Note that Figure 1D It is a cross-sectional view along the XY plane including the conductor 240 .

[0084] Note that this embodiment shows an example in which the shape of the opening 290 when viewed from above is circular, but the present invention is not limited to this. For example, the shape of the opening 290 when viewed from above may also be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 290 may be appropriately calculated based on the shape of the uppermost portion of the opening 290. For example, when the shape of the opening when viewed from above is a quadrangle, the maximum width of the opening 290 is preferably the length of the diagonal line of the uppermost portion of the opening 290.

[0085] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 arranged in the opening 290 reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided so as to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fit into the recess of the insulator 250 reflecting the shape of the opening 290.

[0086] like Figure 1B and Figure 1C As shown in FIG. 1 , the bottom of the conductor 260 located in the opening 290 has a flat region. Note that depending on the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view), the thickness of the insulator 280, the thickness of the oxide semiconductor 230, and the thickness of the insulator 250, etc., the bottom of the conductor 260 located in the opening 290 may not have a flat region. For example, Figure 2A and Figure 2B As shown, sometimes the bottom of the conductor 260 located in the opening 290 has a needle-like shape. Figure 2A and Figure 2B The plan view of the storage device shown can be referred to Figure 1A The cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to Figure 1D .

[0087] Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top (closer to the bottom of the conductor 260 located in the opening 290). In addition, the top of the needle-like shape may be an acute angle or a curved shape that bulges downward. In addition, the shape of the needle-like shape with an acute angle at the top may also be called a V-shape.

[0088] The region of the conductor 260 located in the opening 290 facing the oxide semiconductor 230 through the insulator 250 is used as a gate electrode. Therefore, the conductor 260 that is embedded in the opening 290 and has a needle-like bottom shape can also be called a needle-shaped gate. Figure 1B and Figure 1C As shown, even if the bottom of the conductor 260 is in a shape having a flat region, the conductor 260 may sometimes be referred to as a needle-shaped gate.

[0089] exist Figure 1B and Figure 1C In the embodiment, although the side surface of the conductor 240 in the opening 290 is consistent with the side surface of the insulator 280 in the opening 290, the present invention is not limited thereto. Figure 3A and Figure 3B As shown, the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 may also be discontinuous. In addition, the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may also be different from each other. Note that Figure 3A and Figure 3B The plan view of the storage device shown can be referred to Figure 1A The cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to Figure 1D .

[0090] Here, if Figure 3A As shown, the angle formed by the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is called angle θ2. At this time, angle θ2 is preferably smaller than angle θ. By adopting this structure, the coverage of the side surface of the conductor 240 in the opening 290 by the oxide semiconductor 230 is improved, thereby reducing defects such as voids.

[0091] Here, Figure 4 Show Figure 1B FIG. 2 is an enlarged view of the oxide semiconductor 230 and its vicinity. Figure 4 As shown, the oxide semiconductor 230 includes a region 230i, and regions 230na and 230nb provided so as to sandwich the region 230i.

[0092] The region 230na is a region in the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na is used as one of the source region and the drain region of the transistor 200. The region 230nb is a region in the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb is used as the other of the source region and the drain region of the transistor 200. Figure 1D As shown, the conductor 240 is in contact with the entire periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 may be formed on the entire periphery of the portion of the oxide semiconductor 230 formed in the same layer as the conductor 240.

[0093] The region 230i is a region between the region 230na and the region 230nb in the oxide semiconductor 230. At least a portion of the region 230i is used as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region between the conductor 120 and the conductor 240 of the oxide semiconductor 230. In addition, it can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that contacts the insulator 280 or a region near the insulator 280.

[0094] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120. Figure 4 , the dotted double arrow indicates the channel length L of the transistor 200. When viewed from a cross section, the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact. That is, the channel length L is equivalent to the length of the side surface of the opening 290 side of the insulator 280 when viewed from a cross section.

[0095] In the existing transistor, the channel length is set according to the exposure limit of the photolithography method, but in the present invention, the channel length can be set according to the thickness of the insulator 280 and the angle θ formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 110. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of the photolithography method (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 200 becomes larger, so that the frequency characteristics can be improved. As a result, the read speed and write speed of the memory cell 150 can be improved, so a memory device with a high operating speed can be provided.

[0096] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. Therefore, compared with a conventional transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane, the occupied area of ​​the transistor 200 can be reduced. Thus, the memory device can be highly integrated, so that the memory capacity per unit area can be increased.

[0097] In addition, Figure 1D Similarly, on the XY plane including the channel formation region of the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in concentric circles. Therefore, the side surface of the conductor 260 arranged in the center is opposite to the side surface of the oxide semiconductor 230 via the insulator 250. In other words, the entire circle of the oxide semiconductor 230 becomes the channel formation region when viewed from above. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (the maximum diameter when the shape of the opening 290 when viewed from above is circular). Figure 4 In FIG. 1 , a double-pointed dashed double arrow indicates the maximum width D of the opening 290 . By increasing the maximum width D of the opening 290 , the channel width per unit area can be increased, thereby increasing the on-state current.

[0098] In addition, the length of the outer periphery of the oxide semiconductor 230 may be calculated, for example, from a region facing the conductor 240 or a position at half the thickness of the insulator 280. Note that, as required, the perimeter of any position of the opening 290 may be set as the channel width of the transistor 200. For example, the perimeter of the lowermost portion of the opening 290 may be set as the channel width, or the perimeter of the uppermost portion of the opening 290 may be set as the channel width.

[0099] When the opening 290 is formed by photolithography, the maximum width D of the opening 290 is set according to the exposure limit of the photolithography. In addition, the maximum width D of the opening 290 is set according to the thickness of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width D of the opening 290 is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, for example. Note that in the case where the shape of the opening 290 when viewed from above is circular, the maximum width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width can be calculated as "D×π".

[0100] In addition, in the memory device of one embodiment of the present invention, the channel length of the transistor 200 is preferably at least smaller than the channel width of the transistor 200. The channel length of the transistor 200 of one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, and preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, of the channel width of the transistor 200. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0101] In addition, by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. As a result, the distance between the conductor 260 and the oxide semiconductor 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor 230 substantially uniformly.

[0102] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, it is preferred that the number of oxygen vacancies is small or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source region and the drain region. In addition, hydrogen near an oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0103] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V O The resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0104] like Figure 1B and Figure 1C As shown, a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Figure 1B 2 shows a structure in which the oxide semiconductor 230 is separated in the X direction, but the present invention is not limited thereto. Figure 5A As shown in FIG. 1 , the oxide semiconductor 230 may also extend in the X direction. Figure 5A The structure shown is also separated in the Y direction (refer to Figure 5B ). Here, Figure 5C Show Figure 5A and Figure 5BIn addition, the cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to. Figure 1D .

[0105] also, Figure 1C 2 shows a structure in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240. Note that the present invention is not limited to this. Figure 6B As shown, a structure may be adopted in which the side end of the oxide semiconductor 230 is aligned with the side end of the conductor 240. Alternatively, a structure may be adopted in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240.

[0106] In addition, Figure 6B In the structure shown, the oxide semiconductor 230 may be Fig. 6A As shown, they are separated in the X direction and can also be Figure 5A Likewise, it extends in the X direction. Here, Figure 6C Show Fig. 6A and Figure 6B In addition, the cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to. Figure 1D .

[0107] The band gap of the metal oxide used as the oxide semiconductor 230 is preferably greater than 2 eV, and more preferably greater than 2.5 eV. By using a metal oxide with a large band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, the frequency of refresh operation required for a general DRAM is about 1 time / 60 msec, and the frequency of refresh operation of a memory device of one embodiment of the present invention can be about 1 time / 10 sec, that is, 10 times or more or 100 times the frequency of the refresh line operation can be achieved. In addition, by using a memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0108] Note that as the oxide semiconductor 230 , a single layer or a stacked layer of a metal oxide described in [Metal Oxide] to be described later can be used.

[0109] As the oxide semiconductor 230, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0110] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0111] As an analysis of the composition of the metal oxide used for the oxide semiconductor 230, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0112] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content in the metal oxide after formation is sometimes reduced to about 50% of the zinc content in the sputtering target.

[0113] The oxide semiconductor 230 preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide semiconductor 230 .

[0114] The CAAC-OS preferably has a plurality of layered crystal regions and the c-axis thereof is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 230 preferably has layered crystals that are roughly parallel to the side walls of the opening 290, and in particular, layered crystals that are roughly parallel to the side surfaces of the insulator 280. By adopting such a structure, the layered crystals of the oxide semiconductor 230 are roughly parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.

[0115] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0116] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0117] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 230, oxygen can be suppressed from being extracted from the oxide semiconductor 230 by the source electrode or the drain electrode. Therefore, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so that the transistor 200 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

[0118] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0119] Note that Figures 1B to 1DThe oxide semiconductor 230 is shown as a single-layer structure, but the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted.

[0120] For example, FIG. 7A to FIG. 7C As shown, the oxide semiconductor 230 may have a stacked-layer structure of an oxide semiconductor 230 a and an oxide semiconductor 230 b on the oxide semiconductor 230 a .

[0121] The conductivity of the material used for the oxide semiconductor 230 a is preferably different from the conductivity of the material used for the oxide semiconductor 230 b .

[0122] For example, the oxide semiconductor 230a may use a material having a higher conductivity than the oxide semiconductor 230b. By using a material having a higher conductivity for the conductor 120 used as a source electrode or a drain electrode and the oxide semiconductor 230a in contact with the conductor 240, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor having a large on-state current.

[0123] Here, when a material with high conductivity is used for an oxide semiconductor 230b disposed on one side of a conductor 260 used as a gate electrode, the threshold voltage of the transistor is sometimes caused to drift, so that the drain current (hereinafter also recorded as the cut-off current) flowing when the gate voltage is 0V becomes larger. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage is sometimes reduced. Therefore, the oxide semiconductor 230b preferably uses a material with a lower conductivity than the oxide semiconductor 230a. Thus, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cut-off current can be realized. Note that sometimes the cut-off current is recorded as normally closed.

[0124] As described above, by making the oxide semiconductor 230 have a stacked structure and using a material having higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally-off transistor with a large on-state current can be realized. Thus, a semiconductor device having both low power consumption and high performance can be realized.

[0125] In addition, the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b. By increasing the carrier concentration of the oxide semiconductor 230a, the conductivity becomes higher, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. By reducing the carrier concentration of the oxide semiconductor 230b, the conductivity becomes lower, thereby realizing a normally-off transistor.

[0126] Here, although an example is shown in which a material having a higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a, one embodiment of the present invention is not limited thereto. The oxide semiconductor 230a may also use a material having a lower conductivity than the oxide semiconductor 230b. The carrier concentration of the oxide semiconductor 230a may be lower than the carrier concentration of the oxide semiconductor 230b.

[0127] The band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0128] The band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. In addition, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, thereby realizing a normally closed transistor.

[0129] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0130] As described above, the band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from the composition of the second metal oxide, the band gap can be controlled. For example, the content of element M of the first metal oxide is preferably lower than the content of element M of the second metal oxide. Specifically, in the case where the first metal oxide and the second metal oxide use In-M-Zn oxide, the composition of the first metal oxide can be set to In:M:Zn=1:1:1 [atomic number ratio] or thereabouts, and the composition of the second metal oxide can be set to In:M:Zn=1:3:2 [atomic number ratio] or thereabouts. As element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0131] The first metal oxide may not contain the element M. For example, the first metal oxide used for the oxide semiconductor 230a may be an In-Zn oxide, and the second metal oxide used for the oxide semiconductor 230b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide may be set to In:Zn=1:1 [atomic ratio] or thereabouts or In:Zn=4:1 [atomic ratio] or thereabouts, and the composition of the second metal oxide may be set to In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts.

[0132] Here, although an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, one embodiment of the present invention is not limited thereto. The content of the element M of the first metal oxide may also be higher than the content of the element M of the second metal oxide. In addition, as long as the composition of the first metal oxide and the second metal oxide is different, the content of elements other than the element M of the first metal oxide and the second metal oxide may also be different.

[0133] The thickness of the oxide semiconductor 230 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm, and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0134] The thickness of each layer constituting the oxide semiconductor 230 (here, the oxide semiconductor 230a and the oxide semiconductor 230b) may be determined so that the thickness of the oxide semiconductor 230 is within the above range. The thickness of the oxide semiconductor 230a may be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the required range. In addition, the thickness of the oxide semiconductor 230b may be determined so that the threshold voltage of the transistor is within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

[0135] FIG. 7A to FIG. 7C Although the example in which the oxide semiconductor 230 has a stacked-layer structure of two layers of the oxide semiconductor 230 a and the oxide semiconductor 230 b is shown, the present invention is not limited thereto and the oxide semiconductor 230 may have a stacked-layer structure of three or more layers.

[0136] A single layer or a stack of insulators described in [Insulator] described later can be used as the insulator 250. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0137] In addition, a material having a high relative dielectric constant, that is, a so-called high-k material described in [Insulator] described later, may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0138] The thickness of the insulator 250 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulator 250 may be a region having the above thickness.

[0139] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0140] like Figure 1B and Figure 1C As shown, a portion of the insulator 250 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. At this time, the insulator 250 preferably covers the side end of the oxide semiconductor 230. Thus, the conductor 260 and the oxide semiconductor 230 can be prevented from being short-circuited. In addition, the insulator 250 preferably covers the side end of the conductor 240. Thus, the conductor 260 and the conductor 240 can be prevented from being short-circuited.

[0141] Notice, Figures 1B to 1D The insulator 250 is shown to have a single-layer structure, but the present invention is not limited thereto. The insulator 250 may also have a stacked-layer structure.

[0142] For example, FIG. 7A to FIG. 7C As shown, the insulator 250 may also have a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0143] The insulator 250b preferably uses a material with a low relative dielectric constant as described in [Insulator] to be described later. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 250b contains at least oxygen and silicon. By adopting this structure, the parasitic capacitance generated between the conductor 260 and the conductor 240 can be reduced. In addition, it is preferred that the impurity concentration of water, hydrogen, etc. in the insulator 250b is reduced.

[0144] The insulator 250a preferably uses an insulator having oxygen barrier properties as described in [Insulator] to be described later. The insulator 250a has a region in contact with the oxide semiconductor 230. When the insulator 250a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the oxide semiconductor 230 during heat treatment or the like. Therefore, the formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. As a result, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved. As the insulator 250a, for example, aluminum oxide is preferably used. In this case, the insulator 250a contains at least oxygen and aluminum.

[0145] The insulator 250c preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has high hydrogen barrier properties and is therefore preferably used for the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.

[0146] The insulator 250c may also have oxygen barrier properties. The insulator 250c is provided between the insulator 250b and the conductor 260. Thus, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260 and oxidation of the conductor 260 can be suppressed. In addition, a reduction in the amount of oxygen supplied to the region 230i can be suppressed.

[0147] In addition, an insulator may be provided between the insulator 250b and the insulator 250c. The insulator preferably uses an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By providing the insulator, hydrogen contained in the oxide semiconductor 230 can be captured or fixed more efficiently. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced. As the insulator, for example, hafnium oxide is preferably used. In this case, the insulator contains at least oxygen and hafnium. In addition, the insulator may also have an amorphous structure.

[0148] In order to realize the miniaturization of transistor 200, the thickness of insulators 250a to 250c is preferably thin, and it is preferable to set their thicknesses within the above range. Typically, the thicknesses of insulator 250a, insulator 250b, insulator having the function of capturing or fixing hydrogen, and insulator 250c are set to 1nm, 2nm, 2nm, and 1nm, respectively. By adopting such a structure, even if transistor 200 is miniaturized or highly integrated, it can have good electrical characteristics.

[0149] exist FIG. 7A to FIG. 7C The insulator 250 has a three-layer laminated structure of insulators 250a to 250c, but the present invention is not limited thereto. The insulator 250 may also have a laminated structure of two or more layers. At this time, each layer included in the insulator 250 is preferably appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.

[0150] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 260. For example, a highly conductive material such as tungsten can be used as the conductor 260.

[0151] In addition, as the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide) can be cited. Thus, the decrease in the conductivity of the conductor 260 can be suppressed.

[0152] In addition, the conductor 260 may also have a laminated structure. FIG. 7A to FIG. 7C As shown in FIG. 1 , the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a. In this case, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By stacking tungsten in this way, the conductivity of the conductor 260 may be improved, and the conductor 260 may fully function as the wiring WL.

[0153] exist FIG. 7A to FIG. 7CThe conductor 260 has a two-layer laminate structure of the conductor 260a and the conductor 260b, but the present invention is not limited thereto. The conductor 260 may also have a three-layer or more laminate structure.

[0154] exist Figure 1B and Figure 1C The conductor 260 is provided in a manner embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the concave portion is located in the opening 290. In this case, the concave portion may be filled with an inorganic insulating material or the like.

[0155] In addition, if Figure 1B and Figure 1C As shown, a portion of the conductor 260 is preferably located outside the opening 290, that is, on the conductor 240 and the insulator 280. Figure 1B As shown, the side end of the conductor 260 is preferably located inside the side end of the oxide semiconductor 230. This can prevent the conductor 260 from being short-circuited with the oxide semiconductor 230. In addition, the side end of the conductor 260 may be consistent with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.

[0156] The conductor 120 may be provided in the manner described in [Capacitor 100 ].

[0157] in addition, Figure 1B and Figure 1C The top surface of the conductor 120 is flattened, but the present invention is not limited thereto. Fig. 8A and Figure 8B As shown, a structure in which a concave portion overlapping the opening 290 is formed on the top surface of the conductor 120 may be adopted. By adopting a structure in which at least a portion of the oxide semiconductor 230, the insulator 250, and the conductor 260 are formed in a manner embedded in the concave portion, the gate electric field of the conductor 260 can be easily applied to the conductor 120 near the oxide semiconductor 230.

[0158] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 240. For example, a highly conductive material such as tungsten can be used as the conductor 240.

[0159] As with the conductor 260, the conductor 240 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting such a structure, excessive oxidation of the conductor 240 due to the oxide semiconductor 230 can be suppressed.

[0160] Alternatively, for example, tungsten may be stacked on titanium nitride. By stacking tungsten in this manner, the conductivity of the conductor 240 can be improved, and the conductor 240 can fully function as the wiring BL.

[0161] When the oxide semiconductor 230 is in contact with the conductor 120, a metal compound or oxygen vacancy is formed, and the region 230na of the oxide semiconductor 230 is reduced in resistance. By reducing the resistance of the oxide semiconductor 230 in contact with the conductor 120, the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced. Similarly, when the oxide semiconductor 230 is in contact with the conductor 240, the region 230nb of the oxide semiconductor 230 is reduced in resistance. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0162] Note that when the region 230na is made low-resistance and has high conductivity, the region 230na may be used as the upper electrode of the capacitor 100. In this case, 9A to 9C As shown, the conductor 120 may not be provided. By not providing the conductor 120, the manufacturing process of the storage device can be simplified. 9A to 9C The cross-sectional view of the memory device shown in the XY plane including the conductor 240 can be referred to as Figure 1D .

[0163] Insulator 140 and insulator 280 are used as interlayer films, so their relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulator 140 and insulator 280, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0164] In addition, the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0165] In addition, as the insulator 280 disposed near the channel formation region, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is preferably used. By heat-treating the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H. Thus, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

[0166] Note that Figure 1B and Figure 1CThe insulator 280 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 280 may also have a stacked-layer structure.

[0167] For example, Fig. 10A and Fig. 10B As shown, the insulator 280 may also have a stacked structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b. Fig. 10C yes Fig. 10A and Fig. 10B The memory device is shown in a cross-sectional view along the XY plane including the conductor 240 .

[0168] The insulator 280b preferably uses an insulator containing oxygen. The insulator 280b preferably has a region having a higher oxygen content than at least one of the insulator 280a and the insulator 280c. In particular, the insulator 280b preferably has a region having a higher oxygen content than the insulator 280a and the insulator 280c, respectively. When the oxygen content of the insulator 280b is high, an i-type region is easily formed in the region in contact with the insulator 280b in the oxide semiconductor 230 and in the vicinity thereof.

[0169] The insulator 280 b is preferably a film that releases oxygen by heating. Since the insulator 280 b releases oxygen due to heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, especially to the channel formation region of the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0170] For example, oxygen can be supplied to the insulator 280 b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulator 280 b by sputtering in an oxygen atmosphere. The oxide film can then be removed.

[0171] The insulator 280b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD) method. In particular, when the sputtering method is used, a deposition method that does not use hydrogen gas as a deposition gas is used for deposition, thereby achieving a film with a very low hydrogen content. Therefore, the semiconductor 230 can be suppressed from being supplied with hydrogen and the electrical characteristics of the transistor 200 can be stabilized.

[0172] When the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and VO The influence of H on the power supply characteristics and reliability is particularly great. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, oxygen vacancies and V can be suppressed at least in the region of the oxide semiconductor 230 that is in contact with the insulator 280 b. O H increases. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0173] Insulator 280a and insulator 280b preferably use an insulator having oxygen barrier properties as described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of oxygen in insulator 280b to the substrate side through insulator 280a and to the insulator 250 side through insulator 280c due to heating. In other words, by clamping insulator 280b above and below using insulator 280a and insulator 280c, which are not easy to diffuse oxygen, oxygen in insulator 280b can be confined. Thus, oxygen can be effectively supplied to oxide semiconductor 230.

[0174] In addition, due to the oxygen in the insulator 280b, the conductor 120 and the conductor 240 are oxidized, and sometimes the resistance becomes higher. By providing the insulator 280a between the insulator 280b and the conductor 120, it is possible to suppress the conductor 120 from being oxidized and the resistance from becoming higher. In addition, by providing the insulator 280c between the insulator 280b and the conductor 240, it is possible to suppress the conductor 240 from being oxidized and the resistance from becoming higher. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and the oxygen vacancies in the oxide semiconductor 230 can be reduced.

[0175] In addition, in the oxide semiconductor 230, the amount of oxygen supplied to the region in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in contact with the insulator 280b. As a result, the region in contact with the insulator 280a and the region in contact with the insulator 280c of the oxide semiconductor 230 are sometimes reduced in resistance. That is, by adjusting the thickness of the insulator 280a, the range of the region 230na used as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb used as the other of the source region and the drain region can be controlled.

[0176] As described above, since the source region and the drain region can be controlled by the thickness of the insulator 280 a and the insulator 280 c , the thickness of the insulator 280 a and the insulator 280 c may be appropriately set according to the characteristics required for the transistor 200 .

[0177] For example, Fig. 10A and Fig. 10BAs shown, the thickness of the insulator 280a and the thickness of the insulator 280c may also be substantially the same. Fig.11A and Fig. 11B As shown, the thickness of the insulator 280c may also be smaller than the thickness of the insulator 280a. Fig.11A and Fig. 11B The structure shown can make the region 230na close to the bottom of the conductor 260 in the opening 290. In this case, it can be said that the range of the region 230i is reduced. As a result, the on-state current of the transistor 200 can be increased. Note that Fig. 11C yes Fig.11A and Fig. 11B The memory device is shown in a cross-sectional view along the XY plane including the conductor 240 .

[0178] In addition, Fig.11A and Fig. 11B 2 shows a structure in which an insulator 280c is provided on the planarized insulator 280b, but the present invention is not limited thereto. Fig. 12A and Fig. 12B As shown, insulator 280c may be deposited without performing a planarization process on insulator 280b. By not performing a planarization process, the manufacturing cost can be reduced while the yield rate can be improved. In addition, insulator 280a, insulator 280b, and insulator 280c may be deposited continuously without being exposed to the atmospheric environment. By depositing without being exposed to the atmospheric environment, impurities or moisture from the atmospheric environment may be prevented from adhering to insulators 280a to 280c, thereby keeping the vicinity of the interface between insulator 280a and insulator 280b and the vicinity of the interface between insulator 280b and insulator 280c clean. Note that Fig. 12C yes Fig. 12A and Fig. 12B The memory device is shown in a cross-sectional view along the XY plane including the conductor 240 .

[0179] Insulator 280a and insulator 280c preferably use an insulator having hydrogen barrier properties described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through insulator 280a or insulator 280c to oxide semiconductor 230. Since silicon nitride film and silicon oxynitride film have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, respectively, they can be applied to insulator 280a and insulator 280c. Note that insulator 280a and insulator 280c can use the same material or different materials.

[0180] The thickness of insulator 280a is preferably smaller than the thickness of insulator 280c. In addition, the thickness of insulator 280c is preferably smaller than the thickness of insulator 280b. The thickness of insulator 280a and insulator 280c is preferably greater than 1 nm and less than 15 nm, more preferably greater than 2 nm and less than 10 nm, further preferably greater than 3 nm and less than 7 nm, and further preferably greater than 3 nm and less than 5 nm. The thickness of insulator 280b is preferably greater than 3 nm and less than 30 nm, more preferably greater than 5 nm and less than 20 nm, and further preferably greater than 7 nm and less than 15 nm. By setting the thickness of insulators 280a to 280c within the above range, oxygen vacancies in the oxide semiconductor 230, especially oxygen vacancies in the channel formation region, can be reduced.

[0181] For example, it is preferable that the insulator 280a and the insulator 280c use silicon nitride, and the insulator 280b use silicon oxide. In this case, the insulator 280a and the insulator 280c contain at least silicon and nitrogen. In addition, the insulator 280b contains at least silicon and oxygen.

[0182] Notice, Fig. 10A and Fig. 10B The insulator 280 is shown to have a three-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 280 may have a two-layer stacked structure or a four-layer stacked structure or more.

[0183] The insulator 283 preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 250 to the oxide semiconductor 230. Since the silicon nitride film and the silicon oxynitride film have the characteristics of less release of impurities (for example, water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 283.

[0184] In addition, Figure 1B , etc. show a structure in which the insulator 250 is provided in contact with the top surface and the side surface of the oxide semiconductor 230. Note that the present invention is not limited to this. A structure may be provided between the oxide semiconductor 230 and the insulator 250.

[0185] For example, FIG. 13A to FIG. 13C As shown, an insulator 252 may be provided between the oxide semiconductor 230 and the insulator 250. The insulator 252 serves as a part of the gate insulator of the transistor 200. In other words, the insulator 252 and the insulator 250 serve as the gate insulator of the transistor 200.

[0186] The insulator 252 is preferably formed at the same time as the oxide semiconductor 230. At this time, the side end of the insulator 252 is aligned with the side end of the oxide semiconductor 230. After the oxide semiconductor film to be the oxide semiconductor 230 is deposited, the insulating film to be the insulator 252 is deposited on the oxide semiconductor film in contact with the oxide semiconductor film without performing an etching process or the like, so that the top surface of the oxide semiconductor film can be protected by the insulating film. Therefore, it is possible to suppress the diffusion of impurities into the oxide semiconductor 230 constituting the transistor, so that the electrical characteristics and reliability of the transistor can be improved.

[0187] Figure 1C The structure in which the conductor 240 is provided on the insulator 280 is shown. In addition, a structure in which the insulator 250 has a region in contact with the top surface of the insulator 280 in a region not overlapping with the conductor 240 is also shown. Note that the present invention is not limited to this.

[0188] For example, FIG. 14B to FIG. 14D As shown, the conductor 240 may be embedded in the insulator 281. In this case, the height of the top surface of the conductor 240 is preferably consistent with the height of the top surface of the insulator 281. By adopting this structure, the physical distance from the conductor 260 to the conductor 240 (especially the side end of the conductor 240) can be increased, and the conductor 260 and the conductor 240 can be prevented from short-circuiting. Note that Fig.14A yes FIG. 14B to FIG. 14D A plan view of the storage device is shown.

[0189] Since the insulator 281 is used as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 281, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used.

[0190] <Constituent Materials of Storage Device> Next, constituent materials that can be used for the storage device are described.

[0191] [Substrate] As a substrate for forming the transistor 200 and the capacitor 100, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0192] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0193] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin filmization of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferred to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0194] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0195] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0196] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0197] In addition, an insulator such as a gate insulator that contacts the semiconductor layer or an insulator that is disposed near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen contacts the semiconductor layer, or when an insulator having a region containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0198] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0199] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0200] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0201] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0202] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise specified, impurities recorded as corresponding substances refer to impurities in the channel formation region or the semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 In addition, oxygen, which is recorded as a corresponding substance, refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0203] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0204] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, oxides of strontium and ruthenium, or oxides of lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even after absorbing oxygen, and are therefore preferred.

[0205] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0206] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0207] In addition, when a metal oxide is used in the channel formation region of the transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0208] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0209] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0210] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the metal oxide used for the semiconductor layer of the transistor has fewer lattice defects.

[0211] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0212] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0213] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0214] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having a nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxide of the metal oxide having an a-like structure is higher than that of the metal oxide having a nc structure and the metal oxide having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0215] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0216] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0217] Here, the metal oxide having a channel formation region preferably adopts a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure stacked with multiple layers (for example, a first layer, a second layer, and a third layer). In other words, the crystal has a layered crystal structure (also called a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors, CAAC-OS (c-axis alignedcrystalline oxide semiconductor), and the like.

[0218] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0219] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. In addition, the second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. In addition, the third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0220] As the crystal structure of the above crystal, for example, YbFe 2 O 4 Type structure, Yb 2 Fe 3 O 7 type structures, their deformed structures, etc.

[0221] Furthermore, it is preferred that the first to third layers are all composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0222] By adopting the above structure, the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0223] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or a semi-metal element with a high bonding energy with oxygen, for example, a metal element or a semi-metal element with a higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" recorded in this specification, etc. sometimes include semi-metal elements.

[0224] As a metal oxide semiconductor of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide) and the like containing silicon may be mentioned.

[0225] By increasing the atomic number ratio of indium relative to the total atomic number of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0226] Note that the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0227] In addition, the metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0228] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0229] In addition, by increasing the atomic number ratio of the element M relative to the total atomic number of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0230] In addition, by increasing the atomic number ratio of In relative to the total atomic number of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0231] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0232] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. In the method for depositing a metal oxide according to one embodiment of the present invention, since the ALD method is used, the metal oxide having the layered crystal structure can be easily formed.

[0233] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0234] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit very thin films; it can deposit structures with high aspect ratios; it can deposit in a manner with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of these elements can be performed using XPS or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0235] The ALD method is different from a deposition method in which particles released from a target material are deposited. It is a film-forming method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0236] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0237] [[Transistor including an oxide semiconductor]] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor is described. Hereinafter, a transistor using an oxide semiconductor in a semiconductor layer may be referred to as an OS transistor, and a transistor using silicon in a semiconductor layer may be referred to as a Si transistor.

[0238] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0239] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Above. Note that, when the purpose is to reduce the carrier concentration of the oxide semiconductor film, it is sufficient to reduce the impurity concentration in the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0240] Since the defect state density of a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is low, the trap state density may also be low.

[0241] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0242] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0243] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor whose band gap is larger than that of silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0244] In addition, in Si transistors, the short channel effect (also called Short Channel Effect: SCE) appears as the miniaturization of transistors develops. Therefore, the miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, OS transistors use oxide semiconductors as semiconductor materials with large band gaps, which can suppress the short channel effect. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0245] In addition, the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0246] In addition, as an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0247] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region of OS transistors and the characteristic length between the drain region and the channel formation region are smaller. Therefore, compared with Si transistors, OS transistors have a higher ability to resist short channel effects. That is to say, in the case of manufacturing transistors with short channel lengths, OS transistors are more preferred than Si transistors.

[0248] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in a short channel transistor, the lower end of the conduction band of the channel formation region decreases due to the conduction-band-lowering (CBL) effect, and thus the energy difference between the lower end of the conduction band of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Therefore, the OS transistor can also be regarded as a channel formation region becoming n-type. - type region and the source region and drain region become n+ n + / n - / n + Accumulation type junction-less transistor structure or n + / n - / n + Accumulation-type non-junction transistor structure.

[0249] Since the OS transistor has the above structure, it can have good electrical characteristics even if the OS transistor is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, a short channel effect occurs in Si transistors, so it is sometimes difficult to set the gate length to less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be suitable for transistors with short channel lengths. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is working.

[0250] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0251] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a short channel length.

[0252] [[Impurities in metal oxides]] Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0253] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×1018 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0254] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0255] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, thereby sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0256] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0257] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0258] [Other semiconductor materials] The oxide semiconductor 230 may be referred to as a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0259] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0260] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0261] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0262] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0263] As the semiconductor layer, for example, a transition metal chalcogenide that can be used as a semiconductor is preferably used. Specific examples of the transition metal chalcogenide that can be used as the semiconductor layer include molybdenum sulfide (typically MoS 2 ), Molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ) etc. By using the above transition metal chalcogenide in the semiconductor layer, a memory device having a large on-state current can be provided.

[0264] <Variation Example 1 of Storage Device> Note that Figure 1B In the embodiment, the opening 290 is provided so that the sidewall of the opening 290 has a tapered shape, but the present invention is not limited thereto. For example, the sidewall of the opening 290 may be perpendicular to the top surface of the conductor 110 or may have an inverse tapered shape.

[0265] exist Fig.15A and Fig. 15B In the storage device shown, the side wall of the opening 290 is perpendicular to the top surface of the conductor 110. In this case, the opening 290 has a cylindrical shape. By adopting this structure, the storage device can be miniaturized or highly integrated. In addition, Fig.15A and Fig. 15B The plan view of the storage device shown can be referred to Figure 1A The cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to Figure 1D .

[0266] exist Fig.16A and Fig. 16B In the storage device shown, the side wall of the opening 290 has an inverse tapered shape. Fig.16A and Fig. 16B The plan view of the storage device shown can be referred to Figure 1A The cross-sectional view of the storage device including the conductor 240 on the XY plane can be referred to Figure 1D .

[0267] Here, the inverse cone shape refers to a shape having a side or upper portion protruding more than the bottom in a direction parallel to the substrate. At this time, the shape of the opening 290 is a truncated cone shape. In this case, the opening 290 has a circular shape when viewed from above, and has a trapezoidal shape when viewed from a cross section. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductor 120 exposed in the opening 290). By adopting this structure, the area in which the oxide semiconductor 230 contacts the conductor 120 can be expanded.

[0268] <Variation Example 2 of Storage Device> Fig.13A and Fig. 13B 2 shows a structure in which the insulator 250 is arranged on the insulator 252, but the present invention is not limited thereto. FIG. 17A to FIG. 17D As shown, a structure without the insulator 250 may be adopted. In this case, the insulator 252 is used as a gate insulator of the transistor 200.

[0269] In the above structure, the conductor 260 is preferably provided in a manner embedded in the insulator 287. At this time, the height of the top surface of the conductor 260 is preferably consistent with the height of the top surface of the insulator 287. In addition, the conductor 265 is preferably provided on the conductor 260. By adopting such a structure, the conductor 260 and the conductor 240 can be prevented from being short-circuited.

[0270] The conductor 265 is used as a wiring WL electrically connected to the gate of the transistor 200. As the conductor 265, a single layer or a stacked layer of the conductors described in the above-mentioned [Conductor] can be used. For example, as the conductor 265, a highly conductive material such as tungsten can be used.

[0271] The conductor 265 is preferably provided in a manner embedded in the insulator 289. At this time, the height of the top surface of the conductor 265 and the height of the top surface of the insulator 289 are preferably the same.

[0272] Since insulator 287 and insulator 289 are used as interlayer films, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. As insulator 287 and insulator 289, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] above can be used.

[0273] exist Fig. 17B The side end of the conductor 265 is consistent with the side end of the conductor 260, but the present invention is not limited thereto. For example, the side end of the conductor 265 can be located outside the side end of the conductor 260, or inside the side end of the conductor 260.

[0274] <Example 1 of a method for manufacturing a storage device> Next, use FIG. 18A to FIG. 24C illustrate Figures 1A to 1D A method for manufacturing a storage device according to one embodiment of the present invention is shown.

[0275] A in each drawing is a plan view. In addition, B in each drawing is a cross-sectional view of a portion along the dashed line A1-A2 in A of each drawing. C in each drawing is a cross-sectional view of a portion along the dashed line A3-A4 in A of each drawing. Note that for the sake of clarity, some components are omitted in the plan view of A in each drawing.

[0276] Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be appropriately deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0277] In addition, as a sputtering method, there can be RF sputtering method using a high frequency power supply for a sputtering power supply, DC sputtering method using a direct current power supply, and pulse DC sputtering method changing the voltage applied to the electrode in a pulsed manner. RF sputtering method is mainly used when depositing insulating films, and DC sputtering method is mainly used when depositing metal conductive films. In addition, pulse DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0278] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0279] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object being processed can be reduced. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the storage device sometimes receive charges from plasma and generate charge accumulation (charge up). At this time, the wiring, electrodes, components, etc. included in the storage device are sometimes damaged by the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur when the thermal CVD method that does not use plasma is used, the yield of the storage device can be improved. In addition, when the thermal CVD method is used, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0280] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0281] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0282] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0283] In addition, when the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0284] First, a substrate (not shown) is prepared and an insulator 140 is formed on the substrate (see 18A to 18C ). The above-mentioned insulating materials can be appropriately used as the insulator 140. When depositing the insulator 140, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used.

[0285] Next, the conductor 110 is formed on the insulator 140. As the conductor 110, the above-mentioned conductive materials can be used appropriately. When depositing the conductor 110, sputtering, CVD, MBE, PLD, ALD, etc. can be used appropriately. For example, as the conductor 110, a stacked film in which tungsten and titanium nitride are deposited in sequence can be formed by CVD.

[0286] In addition, the conductor 110 may be processed into a shape extending in the X direction or the Y direction. The conductor 110 may be processed by photolithography. Dry etching or wet etching may be used as the above processing. Processing by dry etching is suitable for micro-processing. By performing this processing, the side end of the conductor 110 is covered by the insulator 130 to be formed later.

[0287] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (e.g., water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0288] In addition, as a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0289] Next, an insulator 130 is formed on the conductor 110. As the insulator 130, the above-mentioned High-k material or a material having ferroelectricity can be appropriately used. When depositing the insulator 130, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. For example, as the insulator 130, a stacked film in which zirconium oxide, aluminum oxide, and zirconium oxide are deposited in sequence can be formed by the ALD method.

[0290] In addition, when the conductor 110 is not processed, the conductor 110 and the insulator 130 may be processed into a shape extending in the X direction or the Y direction. The conductor 110 and the insulator 130 may be processed by photolithography. Dry etching or wet etching may be used as the above processing. Processing by dry etching is suitable for micro-processing. By performing this processing, the side end of the conductor 110 and the side end of the insulator 130 are consistent.

[0291] Next, a conductive film to be the conductor 120 is formed on the insulator 130. The conductive film can be made of the above-mentioned conductive materials as appropriate. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. For example, a stacked film in which titanium nitride and tantalum nitride are deposited in sequence can be formed by the CVD method as the conductive film. Alternatively, for example, a stacked film in which titanium nitride and tungsten are deposited in sequence can be formed by the CVD method as the conductive film.

[0292] Next, the conductive film to be the conductor 120 is processed to form the conductor 120 (see 18A to 18C ). The conductor 120 can be formed by photolithography. The conductive film can be processed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. Here, the conductor 120 can be formed in an island shape. The electrostatic capacitance of the capacitor 100 depends on the area of ​​the conductor 120, so the area of ​​the island-shaped conductor 120 can be appropriately set according to the design value of the capacitor 100.

[0293] Through the above steps, the capacitor 100 including the conductor 110 , the insulator 130 , and the conductor 120 can be formed.

[0294] Next, an insulator 280 is formed on the insulator 130 and the conductor 120 (see FIG. 19A to FIG. 19C ). The above-mentioned insulating materials can be appropriately used as the insulator 280. When depositing the insulator 280, the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be appropriately used. For example, as the insulator 280, a silicon oxide film can be deposited by sputtering. In addition, the insulator 280 is preferably subjected to CMP (Chemical Mechanical Polishing) treatment after deposition to flatten its top surface. By flattening the insulator 280, the conductor 240 used as wiring can be appropriately formed. In addition, sometimes the CMP treatment is not required. At this time, the top surface of the insulator 280 has a surface as shown in FIG. Fig. 12A and Fig. 12B By not performing a flattening process, the manufacturing cost can be reduced while the yield can be increased.

[0295] Here, the thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200 , and therefore the thickness of the insulator 280 may be appropriately set according to the design value of the channel length of the transistor 200 .

[0296] In addition, by depositing the insulator 280 by sputtering in an oxygen-containing atmosphere, the insulator 280 containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In this way, by depositing the insulator 280, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and VoH can be reduced.

[0297] Next, a conductive film 240A is deposited on the insulator 280. The above-mentioned conductive materials can be appropriately used as the conductive film 240A. When depositing the conductive film 240A, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used.

[0298] Next, a portion of the conductive film 240A and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120. The opening 290 can be formed by photolithography. Fig. 20A The shape of the middle opening 290 when viewed from above is circular, but is not limited thereto. For example, the shape of the opening 290 when viewed from above may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0299] As described above, the sidewalls of the opening 290 preferably have a tapered shape. By making the sidewalls of the opening 290 have a tapered shape, coverage with an oxide semiconductor film or the like to be the oxide semiconductor 230 described later is improved, thereby reducing defects such as voids.

[0300] The maximum width of the opening 290 (the maximum diameter when the opening 290 is circular when viewed from above) is preferably small. For example, the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and 1 nm or more or 5 nm or more. In this way, in order to perform microfabrication on the opening 290, it is preferable to use photolithography using short-wavelength light such as EUV light or electron beams.

[0301] Since the aspect ratio of the opening 290 is high, it is preferable to process a portion of the conductive film 240A and a portion of the insulator 280 by anisotropic etching. In particular, processing by dry etching is suitable for micro-processing and is therefore preferred. In addition, the processing may be performed under different conditions. Note that, for example, Figure 3A and Figure 3BAs shown, depending on the conditions for processing a portion of the conductive film 240A and a portion of the insulator 280 , the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may be different from each other.

[0302] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. In addition, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. In addition, the heat treatment may also be performed under reduced pressure. Alternatively, heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher to compensate for the oxygen that has been separated. By performing the above-mentioned heat treatment, impurities such as water contained in the insulator 280 or the like may be reduced before the deposition of the oxide semiconductor film that will become the oxide semiconductor 230, which will be described later.

[0303] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the insulator 280 and the like as much as possible.

[0304] Next, an oxide semiconductor film that will become the oxide semiconductor 230 is deposited in a manner that contacts the bottom and side walls of the opening 290 and at least a portion of the top surface of the conductive film 240A. As the oxide semiconductor film, the above-mentioned metal oxide that can be used for the oxide semiconductor 230 can be appropriately used. When depositing the oxide semiconductor film, sputtering, CVD, MBE, PLD, ALD, etc. can be appropriately used. Here, the oxide semiconductor film is preferably formed in a manner that contacts the bottom and side walls of the opening 290 with a high aspect ratio. Therefore, when depositing the oxide semiconductor film, it is preferred to use a deposition method with good coverage, and it is more preferred to use a CVD method or an ALD method. For example, as the oxide semiconductor film, In-Ga-Zn oxide can be deposited using the ALD method. In addition, the deposition method of the metal oxide using the ALD method will be described in detail in the following embodiments.

[0305] Note that when the side wall of the opening 290 has a tapered shape, the deposition method of the oxide semiconductor film to be the oxide semiconductor 230 is not limited to the CVD method or the ALD method, and for example, a sputtering method may be used.

[0306] In addition, if FIG. 7A to FIG. 7C As shown, in the case where the oxide semiconductor 230 has a stacked structure, the deposition methods of the layers included in the oxide semiconductor 230 may be the same or different. For example, in the case where the oxide semiconductor 230 has a two-layer stacked structure, the lower layer of the oxide semiconductor film may be deposited by sputtering and the upper layer of the oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering tends to have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Thus, even if a pinhole or a disconnection is formed in the lower layer of the oxide semiconductor film deposited by sputtering, the portion overlapping with the pinhole or disconnection can be blocked by the upper layer of the oxide semiconductor film deposited by the ALD method with good coverage.

[0307] Here, the oxide semiconductor film to be the oxide semiconductor 230 is preferably formed in contact with the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the top surface of the conductor 240. When the oxide semiconductor film is formed in contact with the conductor 120, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200. When the oxide semiconductor film is formed in contact with the conductor 240, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200.

[0308] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the oxide semiconductor film does not undergo polycrystallization, and can be performed at a temperature above 250°C and below 650°C, preferably above 400°C and below 600°C. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10%. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas can be set to about 20%. In addition, the heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere of an oxidizing gas of more than 10 ppm, more than 1%, or more than 10% to compensate for the detached oxygen.

[0309] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the above-mentioned oxide semiconductor film and the like as much as possible.

[0310] Here, the heat treatment is preferably performed while the insulator 280 containing excess oxygen is in contact with the oxide semiconductor film. By performing the heat treatment in this way, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VoH.

[0311] Note that in the above description, the heat treatment is performed after the oxide semiconductor film is deposited, but the present invention is not limited to this. Alternatively, the heat treatment may be performed in a subsequent step.

[0312] Next, the oxide semiconductor film to be the oxide semiconductor 230 is processed by photolithography to form the oxide semiconductor 230 (see FIG. 21A to FIG. 21C ). Thus, a portion of the oxide semiconductor 230 is formed in the opening 290. In addition, the oxide semiconductor 230 is in contact with a portion of the side surface and the top surface of the conductor 240. Therefore, the area of ​​the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.

[0313] Next, the conductive film 240A is processed to form the conductive body 240 (see FIG. 22A to FIG. 22C The conductor 240 can be formed by photolithography. The conductive film 240A can be processed by dry etching or wet etching. Dry etching is suitable for micro-processing.

[0314] Here, a method of forming the conductor 240 and the oxide semiconductor 230 which is different from the above-described method will be described.

[0315] To deposition FIG. 20A to FIG. 20C The method of forming the conductive film 240A is the same as described above.

[0316] Next, the conductive film 240A is processed to form the conductor 240. The method of forming the conductor 240 and the like can refer to the above description.

[0317] Next, a portion of the conductor 240 and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120. The method of forming the opening 290 and the like can refer to the above description.

[0318] Then, a heat treatment may be performed. The conditions of the heat treatment and the like can refer to the above description.

[0319] Next, an oxide semiconductor film to be the oxide semiconductor 230 is deposited in contact with the bottom and sidewall of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the top surface of the insulator 280. The deposition method of the oxide semiconductor film and the like can refer to the above description.

[0320] Next, heat treatment is preferably performed. The conditions of the heat treatment and the like can refer to the above description.

[0321] Next, the oxide semiconductor film to be the oxide semiconductor 230 is processed by photolithography to form the oxide semiconductor 230 (see FIG. 22A to FIG. 22C ).

[0322] The following methods for manufacturing storage devices can all be carried out using the same method.

[0323] Next, an insulator 250 is deposited on the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIG. 23A to FIG. 23C ). As the insulator 250, the above-mentioned insulating materials can be appropriately used. When depositing the insulator 250, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the insulator 250 is preferably formed in a manner of contacting the oxide semiconductor 230 provided in the opening 290 with a high aspect ratio. Therefore, when depositing the insulator 250, it is preferred to use a deposition method with good coverage, and it is more preferred to use a CVD method or an ALD method, etc. For example, as the insulator 250, silicon oxide can be deposited by the ALD method.

[0324] Note that, when the side wall of the opening 290 has a tapered shape, the deposition method of the insulator 250 is not limited to the CVD method or the ALD method, and for example, a sputtering method may be used.

[0325] By depositing the insulator 250 after forming the oxide semiconductor 230, the side end of the oxide semiconductor 230 is covered by the insulator 250. Therefore, it is possible to prevent the oxide semiconductor 230 from being short-circuited with the conductor 260. In addition, by adopting the above structure, the side end of the conductor 240 is covered by the insulator 250. Therefore, it is possible to prevent the conductor 240 from being short-circuited with the conductor 260.

[0326] In addition, when setting FIG. 13A to FIG. 13C When the insulator 252 is shown, for example, it is preferable to form the oxide semiconductor 230 and the insulator 252 at one time after depositing the oxide semiconductor film to be the oxide semiconductor 230 and the insulating film to be the insulator 252. In this way, by forming the oxide semiconductor 230 and the insulator 252 at one time, Fig. 17B and Fig. 17CAs shown, in a plan view, the side edge of the oxide semiconductor 230 is aligned with the side edge of the insulator 252. With such a structure, the oxide semiconductor 230 and the insulator 252 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0327] In addition, when an insulating film to be the insulator 252 is deposited before processing the oxide semiconductor film to be the oxide semiconductor 230, the deposition of the insulating film is preferably performed continuously from the deposition of the oxide semiconductor film without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, it is possible to suppress the mixing of impurities such as hydrogen into the oxide semiconductor film and the insulating film between the deposition steps.

[0328] Next, a conductive film to be the conductor 260 is deposited so as to be embedded in the recessed portion of the insulator 250 (see Fig.23A and Fig.23C ). In addition, FIG. 23A to FIG. 23C , the conductive film to be the conductor 260 is given a symbol 260A. As the conductive film, the above-mentioned conductive materials can be appropriately used. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used. Here, the conductive film is preferably formed in a manner of contacting the insulator 250 provided in the opening 290 with a high aspect ratio. Therefore, when depositing the conductive film, it is preferred to use a deposition method with good coverage or embedding properties, and more preferably to use a CVD method or an ALD method. For example, titanium nitride can be deposited as the conductive film using a CVD method or an ALD method.

[0329] Note that when a conductive film to be the conductor 260 is deposited by CVD, the average surface roughness of the top surface of the conductive film may become large. In this case, it is preferable to planarize the conductive film by CMP. In this case, a silicon oxide film or a silicon oxynitride film may be deposited on the conductive film before CMP treatment, and CMP treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0330] In the above description, the conductive film to be the conductor 260 is provided so as to be embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the central portion of the conductive film. Alternatively, the concave portion may be filled with an inorganic insulating material or the like.

[0331] Next, the conductive film to be the conductor 260 is processed to form the conductor 260 (see FIG. 24A to FIG. 24C ). The conductor 260 can be formed by photolithography. Dry etching or wet etching can be used as the above-mentioned processing. Processing by dry etching is suitable for micro-processing.

[0332] Here, if Figure 1A and Figure 1B As shown in FIG. 1 , the side end of the conductor 260 is preferably located inside the side end of the oxide semiconductor 230 in a plan view. This can prevent the conductor 260 and the oxide semiconductor 230 from being short-circuited.

[0333] Through the above steps, the transistor 200 including the conductor 120 , the conductor 240 , the oxide semiconductor 230 , the insulator 250 , and the conductor 260 can be formed.

[0334] Next, the insulator 283 is deposited to cover the conductor 260 and the insulator 250. The above-mentioned insulating materials can be appropriately used as the insulator 283. When depositing the insulator 283, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used.

[0335] Through the above process, it is possible to manufacture Figures 1A to 1D In addition, a storage device including the storage unit 150 can be manufactured. Figures 1A to 1D A storage device with transistor 200 and capacitor 100 is shown.

[0336] <Example 2 of the method for manufacturing a storage device> Next, explain FIG. 14A to FIG. 14D The method for manufacturing a memory device according to one embodiment of the present invention is shown. Note that the steps up to the step of forming the insulator 280 can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0337] An insulator 281 is formed on the insulator 280. The above-mentioned insulating materials can be used appropriately for the insulator 281. When depositing the insulator 281, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used appropriately. For example, a silicon oxide film can be deposited by a sputtering method as the insulator 281. In addition, the insulator 281 is preferably subjected to a CMP treatment after deposition to flatten its top surface.

[0338] Next, an opening reaching the insulator 280 is formed in the insulator 281. A conductor 240 serving as wiring is formed inside the opening so that the opening can extend in the X direction. When forming the opening, photolithography can be used. In addition, when etching the opening, dry etching or wet etching can be used. Processing using dry etching is suitable for micro-processing.

[0339] Alternatively, a structure may be adopted in which the insulator 280 has a stacked structure and an insulator serving as an etching stop film is provided on the topmost surface of the insulator 280. Fig. 10B and Fig. 10CInsulator 280c in the structure shown in the figure. For example, when silicon oxide or silicon oxynitride is used as the insulator 281 forming the above-mentioned opening, silicon nitride, aluminum oxide, hafnium oxide, or the like is preferably used as the etching stopper film.

[0340] Next, a conductive film to be the conductor 240 is deposited in such a manner as to be embedded in the opening formed in the insulator 281. As the conductive film, the above-mentioned conductive materials can be used as appropriate. When depositing the conductive film, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used as appropriate. For example, a stacked film in which tantalum nitride and tungsten are deposited in sequence can be formed by sputtering as the conductive film.

[0341] Next, a portion of the conductive film to be the conductor 240 on the insulator 281 is removed to form the conductor 240 inside the opening of the insulator 281. When forming the conductor 240, the conductive film may be subjected to CMP treatment until the top surface of the insulator 281 is exposed.

[0342] Note that the steps after forming the conductor 240 (after the step of forming the opening 290 ) can refer to the contents described in the above-mentioned <Example 1 of the method for manufacturing a memory device>.

[0343] Through the above process, it is possible to manufacture FIG. 14A to FIG. 14D In addition, a storage device including the storage unit 150 can be manufactured. FIG. 14A to FIG. 14D A storage device with transistor 200 and capacitor 100 is shown.

[0344] According to one embodiment of the present invention, a novel transistor, a novel semiconductor device, and a novel storage device can be provided. In addition, a storage device capable of miniaturization or high integration can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with a high operating speed can be provided. In addition, a storage device with high reliability can be provided. In addition, a storage device with low power consumption can be provided. In addition, a storage device including a transistor with a large on-state current can be provided. In addition, a storage device with small non-uniformity in transistor characteristics can be provided. In addition, a storage device with good electrical characteristics can be provided.

[0345] The memory cell 150 including the transistor 200 and the capacitor 100 shown in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the storage content can be maintained for a long time by using it in a memory device. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, since the frequency characteristics of the transistor 200 are high, high-speed reading and writing of the memory device can be performed.

[0346] In addition, use Fig.25A and Fig.25B An example of a memory device in which two memory cells 150 (hereinafter referred to as a memory cell 150 a and a memory cell 150 b ) are connected to the same wiring will be described. Fig.25A is a plan view of the storage device. Fig.25B It is along Fig.25A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.25A Some components are omitted in the plan view.

[0347] Here, Fig.25A and Fig.25B The memory cell 150a and the memory cell 150b shown in the figure have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. Fig.25A and Fig.25B In the storage device shown, the Figures 1A to 1D The components of the storage device shown in the figure have the same functions as the components thereof. In this section, the components of the storage device may also use the materials described in detail in the "Structural Example of Storage Device".

[0348] like Fig.25A and Fig.25B As shown, the conductor 260 used as the wiring WL is provided in the memory cell 150a and the memory cell 150b respectively. In addition, the conductor 240 used as a part of the wiring BL is provided in both the memory cell 150a and the memory cell 150b. In other words, the conductor 240 contacts the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.

[0349] Here, Fig.25A and Fig.25BThe illustrated memory device includes a conductor 245 and a conductor 246 which are electrically connected to the memory cells 150a and 150b and serve as plugs (which may also be referred to as connection electrodes). The conductor 245 is disposed in openings formed in the insulator 280 and the insulator 140 and is in contact with the bottom surface of the conductor 240. In addition, the conductor 246 is disposed in openings formed in the insulator 287, the insulator 283, and the insulator 250 and is in contact with the top surface of the conductor 240. In addition, as the conductor 245 and the conductor 246, the conductive material that can be used for the conductor 240 can be used.

[0350] Since the insulator 287 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 287, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above-mentioned [Insulator] can be used.

[0351] Note that the concentration of impurities such as water and hydrogen in the insulator 287 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0352] The conductors 245 and 246 are used as plugs or wirings for electrically connecting circuit elements, wirings, electrodes or terminals such as switches, transistors, capacitors, inductors, resistors and diodes with the memory cells 150a and 150b. For example, the following structure can be adopted: the conductor 245 and the circuit elements 246 are provided at the same time. Fig.25A and Fig.25B The sense amplifier (not shown) under the storage device shown is electrically connected, and the conductor 246 is connected to the Fig.25A and Fig.25B The same storage device (not shown) as shown in the storage device is electrically connected. In this case, the conductor 245 and the conductor 246 are used as part of the wiring BL. Fig.25A and Fig.25B By arranging a storage device above or below the storage device shown, the storage capacity per unit area can be increased.

[0353] In addition, the memory cell 150a and the memory cell 150b are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged linearly symmetrically with the conductor 245 and the conductor 246 sandwiched therebetween. Here, the conductor 240 serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. In addition, the transistor 200a and the transistor 200b share the conductor 245 and the conductor 246 used as the plug. In this way, by adopting the above structure as the connection relationship between the two transistors and the plug, a storage device that can achieve miniaturization or high integration can be provided.

[0354] In addition, the conductor 110 used as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in both of the memory cell 150a and the memory cell 150b. Fig.25B As shown, the conductor 110 is disposed in a manner separated from the conductor 245 to prevent the conductor 110 and the conductor 245 from being short-circuited.

[0355] In addition, by arranging the memory cells 150 in a matrix and three-dimensional manner, a memory cell array can be formed. As an example of a memory cell array, Fig.26A and Fig.26B An example of a storage device in which four×two×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction is shown. Fig.26A is a plan view of the storage device. Fig.26B It is along Fig.26A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.26A Some components are omitted in the plan view.

[0356] Here, Fig.26A and Fig.26B The memory cells 150a to 150d shown have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d. Fig.26A and Fig.26B In the storage device shown, the Figures 1A to 1D The components of the storage device shown in the figure have the same functions as the components thereof. In this section, the components of the storage device may also use the materials described in detail in the "Structural Example of Storage Device".

[0357] Hereinafter, a storage device composed of the storage cells 150a to 150d will be referred to as a memory cell. Fig.26A and Fig.26B The memory device shown includes memory cells 160 [1, 1] to 160 [2, 4]. In addition, memory cells 160 [1, 1] to 160 [2, 4] are sometimes collectively referred to as memory cells 160 below. Memory cell 160 [1, 2] is disposed on memory cell 160 [1, 1], memory cell 160 [1, 3] is disposed on memory cell 160 [1, 2], and memory cell 160 [1, 4] is disposed on memory cell 160 [1, 3]. Memory cell 160 [2, 1] is adjacent to memory cell 160 [1, 1] in the Y direction. Memory cell 160 [2, 2] is disposed on memory cell 160 [2, 1], memory cell 160 [2, 3] is disposed on memory cell 160 [2, 2], and memory cell 160 [2, 4] is disposed on memory cell 160 [2, 3].

[0358] like Fig.26B As shown in FIG. 1 , in the memory cell 160, the memory cell 150c is arranged outside the memory cell 150a and the memory cell 150d is arranged outside the memory cell 150b with the conductor 245 as the center. In other words, it can be said that the memory cell 160 is Fig.25A and Fig.25B The illustrated storage device has a storage unit 150c disposed adjacent to the storage unit 150a and a storage unit 150d disposed adjacent to the storage unit 150b.

[0359] like Fig.26A and Fig.26B As shown, the memory cells 150 adjacent to each other in the Y direction share the conductor 260 used as the wiring WL. In addition, the conductor 240 used as a part of the wiring BL is shared in the same memory cell. In other words, the conductor 240 is in contact with the oxide semiconductor 230 in each of the memory cells 150a to 150d.

[0360] The conductor 245 is disposed between the conductors 240 included in the memory cells adjacent to each other in the Z direction. Fig.26B As shown in FIG. 1 , the conductor 245 is provided in such a manner as to be in contact with the top surface of the conductor 240 in the memory cell 160 [1, 1] and the bottom surface of the conductor 240 in the memory cell 160 [1, 2]. In this way, the conductor 240 and the conductor 245 provided in each memory cell 160 form the wiring BL. The conductor 245 is electrically connected to the conductor provided in Fig.26A and Fig.26B Thus, by Fig.26A and Fig.26B In the memory device shown, a plurality of memory cells are stacked to increase the storage capacity per unit area.

[0361] In addition, the memory cell 150a and the memory cell 150c and the memory cell 150b and the memory cell 150d are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the symmetry axis. Therefore, the transistor 200a and the transistor 200c and the transistor 200b and the transistor 200d are also arranged linearly symmetrically with the conductor 245 sandwiched therebetween. Here, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200a to the transistor 200d. In addition, the transistor 200a to the transistor 200d share the conductor 245 used as a plug. In this way, by adopting the above structure as the connection relationship between the four transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0362] like Fig.26A and Fig.26B As shown, by stacking multiple memory cells, the cells can be integrated without increasing the occupied area of ​​the memory cell array. That is, a 3D memory cell array can be constructed. Note that Fig.26A and Fig.26B Although an example of a structure having four stacked layers including two memory cells is shown, the present invention is not limited thereto. The memory device may include one layer including at least one memory cell 150 or two or more of the above layers may be stacked.

[0363] Fig.26B 2 shows an example of a structure in which the conductor 245 serving as a plug is arranged between the memory cells 150. In other words, Fig.26B The structure shown is that the conductor 245 used as a plug is arranged inside the memory cell 160. Note that the present invention is not limited to this. The conductor 245 may be arranged outside the memory cell.

[0364] As an example of a memory cell array, Fig.27A and Fig.27B An example of a storage device is shown in which three×three×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction. Fig.27A is a plan view of the storage device. Fig.27B It is along Fig.27A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.27A Some components are omitted in the plan view.

[0365] Fig.27A and Fig.27BThe memory device shown has a structure in which m (m is an integer greater than or equal to 2) layers including memory cells 150 are stacked. Fig.27B In the above, the layer disposed at the first layer (the bottom layer) is referred to as layer 170[1], the layer disposed at the second layer is referred to as layer 170[2], the layer disposed at the (m-1)th layer is referred to as layer 170[m-1], and the layer disposed at the mth layer (the top layer) is referred to as layer 170[m]. That is, the storage device of one embodiment of the present invention may include a plurality of layers including the storage unit 150, and may have a structure in which a plurality of layers are stacked.

[0366] like Fig.27A and Fig.27B As shown, the conductor 245 may also be provided outside the memory cell. In addition, the conductor 245 may also be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2]. In addition, the wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. That is, the wiring may be formed in the same process as the conductor 110.

[0367] Here, Fig.28A is omitted Fig.27A A plan view of a portion of the components shown. Specifically, Fig.28A The plan view of FIG. 1 shows the conductor 260 serving as the wiring WL, the conductor 240 serving as the wiring BL, the conductor 245 , and the opening 290 .

[0368] Fig.27A and Fig.28A The structure in which the memory cells 150 are arranged in a matrix is ​​shown. In addition, the structure in which the openings 290 are arranged in a matrix is ​​also shown. Note that the present invention is not limited to this. Fig.28B Shown with Fig.28A The structures of the memory cell 150 and the opening 290 are configured in different ways.

[0369] Fig.28B is a plan view of the storage device. Fig.28A Likewise, in Fig.28B The conductor 260, the conductor 240, the conductor 245, and the opening 290 are shown in the plan view.

[0370] like Fig.28B As shown, the storage unit 150 may also be arranged in a sawtooth shape in the X direction. In addition, the opening 290 may also be arranged in a sawtooth shape in the X direction. Fig.28BIn the embodiment, the storage unit 150p is adjacent to the storage unit 150q in the Y direction, and the storage unit 150r is adjacent to the storage unit 150p and the storage unit 150q in the X direction. For example, the center of the storage unit 150r is located on a straight line passing through the middle of the storage unit 150p and the storage unit 150q and perpendicular to the Y direction. In this case, it can also be said that the storage unit 150r is located at a position halfway between the storage unit 150p and the storage unit 150q in the Y direction.

[0371] In addition, Fig.28B In the embodiment, the extending direction of the conductor 240 is arranged to be inclined with respect to the X direction. That is, depending on the arrangement of the memory cell 150 and the arrangement of the opening 290 , the extending direction of the conductor 240 may not be perpendicular to the extending direction of the conductor 260 .

[0372] By adopting the above structure, one or both of the distance between the conductors 260 and the distance between the conductors 240 can be reduced, and the miniaturization and high integration of the storage device can be achieved.

[0373] A memory device including a 3D memory cell array will be described in detail in the following embodiments.

[0374] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments described in this specification as appropriate.

[0375] (Implementation Method 2) In this embodiment, using FIG. 29A to FIG. 32C A metal oxide (hereinafter, sometimes referred to as an oxide semiconductor or an oxide) and a deposition method thereof which can be used for a semiconductor layer of a transistor in the memory device described in the above embodiment will be described.

[0376] In a semiconductor device of one embodiment of the present invention, a metal oxide with high crystallinity is preferably used as a metal oxide having a channel formation region. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (e.g., a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked.

[0377] In order to form the metal oxide having a layered crystal structure, it is preferable to deposit atoms layer by layer. For example, the ALD method can be used as a method for forming the metal oxide.

[0378] The ALD method can deposit atoms layer by layer, so it has the effects of being able to deposit extremely thin, being able to deposit structures with high aspect ratios, being able to deposit in a manner with fewer defects such as pinholes, being able to deposit with good coverage, and being able to deposit at low temperatures. In addition, the ALD method also includes a thermal ALD method that uses a thermal deposition method and a plasma ALD method that uses a plasma deposition method. By using plasma, deposition can be performed at a lower temperature, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, a film set by the ALD method sometimes contains more elements such as carbon or chlorine than a film set by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS.

[0379] Unlike a deposition method in which particles released from a target material are deposited, the ALD method is a deposition method in which a film is formed by a reaction on the surface of the object being processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object being processed and has good step coverage. In particular, the mold deposited by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for the case where the surface of an opening with a high aspect ratio is to be covered.

[0380] <Method of Depositing Metal Oxide by ALD Method> Here, a method for depositing a metal oxide using the ALD method which can be used in one embodiment of the present invention is described.

[0381] Here, use FIG. 29A to FIG. 29E An example of a method for depositing a three-layered crystal structure metal oxide using the ALD method is described. First, a precursor 611a is introduced into a chamber so that the precursor 611a is adsorbed onto the surface of a substrate 610 (see Fig.29A Hereinafter, this process is sometimes referred to as the first step. Fig.29A As shown, since the precursor 611a is adsorbed onto the surface of the substrate 610, the self-stop mechanism of the surface chemical reaction takes effect and the precursor 611a is no longer adsorbed on the layer of the precursor 611a on the substrate 610. Note that the appropriate range of substrate temperature for the self-stop mechanism of the surface chemical reaction to take effect is also referred to as the ALD window. The ALD window is determined based on the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and is sometimes set to be above 100°C and below 600°C, and preferably above 200°C and below 400°C.

[0382] Next, an inert gas (argon, helium, nitrogen, etc.) is introduced into the chamber to exhaust the remaining precursor 611a and the reaction products from the chamber (hereinafter, this process is sometimes referred to as the second step). Alternatively, the remaining precursor and the reaction products may be exhausted from the chamber by vacuum exhaust instead of introducing the inert gas into the chamber. The second step is also called purging.

[0383] Next, reactant 612a (e.g., oxidant (ozone (O 3 ), oxygen (O 2 ), water (H 2 O) and their plasma, free radicals, ions, etc.) are introduced into the chamber to react with the precursor 611a adsorbed on the surface of the substrate 610, so that a part of the components in the precursor 611a is separated while the constituent molecules of the precursor 611a are adsorbed on the substrate 610 (refer to Fig.29B (This process may be referred to as a third step hereinafter.) As a result, a layer of an oxide 613 a formed by oxidation of a portion of the precursor 611 a is formed on the surface of the substrate 610 .

[0384] Next, the remaining reactant 612a and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust (hereinafter, this process may be referred to as a fourth step).

[0385] Next, a precursor 611b containing a metal element different from the precursor 611a is introduced, and the same process as the first step is performed to make the precursor 611b adsorbed on the surface of the oxide 613a layer (see Fig.29C ). Here, if Fig.29C As shown, since the precursor 611 b is adsorbed onto the layer of the oxide 613 a , the self-stopping mechanism of the surface chemical reaction takes effect and the precursor 611 b is no longer adsorbed onto the layer of the precursor 611 b on the substrate 610 .

[0386] Next, similarly to the second step, the remaining precursor 611 b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0387] Next, as in the third step, a reactant 612b is introduced into the chamber. Here, the reactant 612b may be the same as or different from the reactant 612a (see Fig.29D ). As a result, a layer of oxide 613b formed by oxidation of a portion of the precursor 611b is formed on the layer of oxide 613a.

[0388] Next, similarly to the fourth step, the remaining reactant 612b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0389] Furthermore, by performing the first to fourth steps in the same manner, a layer of oxide 613c can be formed on the layer of oxide 613b. In this way, by repeatedly performing the steps of forming oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of oxides 613a to 613c is repeated can be formed (see Fig.29E ). That is, the first to fourth steps can be used as a set to form an oxide layer, and by repeatedly performing this set, a layered crystal structure in which a plurality of oxide layers are stacked can be formed.

[0390] The thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, and preferably 3 nm or more and less than 20 nm.

[0391] In addition, when forming a metal oxide having a layered crystal structure, it is preferable to heat the substrate while performing FIG. 29A to FIG. 29D The process shown. For example, the substrate temperature is set to be above 200°C and below 600°C, preferably above 300°C and below the decomposition temperature of the precursor. Note that when using multiple precursors of different types and depositing by the ALD method, it is preferred to set the substrate temperature to be below the decomposition temperature of the lowest precursor among the multiple precursors. Thus, in the deposition by the ALD method, the multiple precursors used can be adsorbed onto an object (e.g., a substrate, etc.) without being decomposed.

[0392] By performing the above deposition while heating the substrate within the above temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process from step 1 to step 4. For example, carbon in the metal oxide can be released as CO 2 and CO, which can release hydrogen from metal oxides to H 2 O. In addition, since the metal atoms and oxygen atoms are rearranged while removing the impurities, the layers of each oxide can be arranged in a highly orderly manner. Thus, a metal oxide having a layered crystal structure with high crystallinity can be formed.

[0393] In order to perform deposition while heating the substrate within the above-mentioned temperature range, the decomposition temperature of the precursor used for the above-mentioned deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, a precursor formed by an inorganic substance (hereinafter referred to as an inorganic precursor) is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed by organic substances (hereinafter referred to as organic precursors), and sometimes their ALD windows are located within the above-mentioned temperature range. In addition, because inorganic precursors do not contain impurities such as hydrogen or carbon, the concentration of impurities such as hydrogen or carbon in the deposited metal oxide can be prevented from increasing.

[0394] Furthermore, it is preferred to perform a heat treatment after the deposition of the above-mentioned metal oxide. In particular, it is preferred to perform a heat treatment continuously without exposing to the outside air after the deposition using the above-mentioned ALD method. The heat treatment is performed at a temperature of 100°C or more and 1200°C or less, preferably 200°C or more and 1000°C or less, more preferably 250°C or more and 650°C or less, further preferably 300°C or more and 600°C or less, further preferably 400°C or more and 550°C or less, and further preferably 420°C or more and 480°C or less. In addition, the heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. In addition, the heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more to compensate for the oxygen that has been separated.

[0395] By performing such a heat treatment, impurities such as hydrogen and carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO 2 and CO, which can release hydrogen from metal oxides to H 2 O. In addition, the metal atoms and oxygen atoms are rearranged while the impurities are removed, thereby improving crystallinity. Thus, a metal oxide having a layered crystal structure with high crystallinity can be formed.

[0396] In addition, it is preferred that microwave treatment is performed in an oxygen-containing atmosphere after the deposition of the metal oxide to reduce the concentration of impurities in the metal oxide. As impurities, hydrogen and carbon can be mentioned in particular. Here, microwave treatment refers to treatment using a device including a power supply that generates high-density plasma using microwaves, for example.

[0397] By performing microwave treatment in an oxygen-containing atmosphere, high frequencies such as microwaves or RF can be used to plasmatize the oxygen gas and allow the oxygen plasma to act. In addition, as oxygen acting on the metal oxide, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (atoms, molecules or ions with unpaired electrons also referred to as O free radicals). In addition, the oxygen acting on the metal oxide can be any one or more of the above forms, and is particularly preferably an oxygen free radical.

[0398] In addition, when the microwave treatment is performed in the oxygen-containing atmosphere, heating the substrate can further reduce the impurity concentration in the metal oxide, which is preferred. The heating of the substrate can be performed at 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.

[0399] When the substrate is heated during microwave treatment in the above oxygen-containing atmosphere, the carbon concentration in the metal oxide measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0400] Note that the above shows a structural example in which a metal oxide is subjected to microwave treatment in an oxygen-containing atmosphere, but the present invention is not limited thereto. For example, an insulating film located near the metal oxide, specifically a silicon oxide film, may also be subjected to microwave treatment in an oxygen-containing atmosphere. FIG. 23A to FIG. 23C In the process shown in the figure, microwave treatment may be performed after the insulator 250 is deposited. By performing microwave treatment on the silicon oxide film in an oxygen-containing atmosphere, hydrogen contained in the silicon oxide film can be converted into H 2 O is released to the outside. By releasing hydrogen from the silicon oxide film located near the metal oxide, a highly reliable semiconductor device can be provided.

[0401] Note that FIG. 29A to FIG. 29E In the above description, a structure in which the stacked structure of oxides 613a to 613c is repeated is described, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more layers of oxides are repeatedly formed may be used.

[0402] In addition, in the description of this specification, when ozone, oxygen, or water is used as a reactant or oxidant, unless otherwise specified, these include plasma states, radical states, and ion states and are not limited to gaseous states or molecular states. When deposition is performed using an oxidant in a plasma state, radical state, or ion state, a radical ALD apparatus or a plasma ALD apparatus described below may be used.

[0403] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferred to allow the precursor to fully react with the oxidant. For example, a longer pulse time for introducing the oxidant can be set. Alternatively, the oxidant can be introduced multiple times. When the oxidant is introduced multiple times, the same type of oxidant can be introduced, and different types of oxidants can be introduced. For example, water can be introduced into the chamber as the first oxidant and then vacuum evacuated, and ozone or oxygen that does not contain hydrogen can be introduced into the chamber as the second oxidant and vacuum evacuated.

[0404] In this way, by repeatedly introducing the oxidant and the inert gas (or vacuum exhaust) in the chamber for a short period of time, the remaining hydrogen atoms, carbon atoms, chlorine atoms, etc. can be removed from the precursor adsorbed on the substrate surface and discharged outside the chamber. In addition, by introducing two oxidants, more remaining hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being introduced into the film during deposition, water, hydrogen, etc. contained in the formed film can be reduced.

[0405] The ALD method is a deposition method that uses thermal energy to react precursors and reactants. The temperature required for the reaction of the precursors and reactants is determined according to their temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to be above 100°C and below 600°C, preferably above 200°C and below 600°C, and more preferably above 300°C and below 600°C.

[0406] Furthermore, an ALD method in which the above-mentioned precursor and reactant react and a reactant excited by plasma is introduced into a chamber as a third source gas for processing is sometimes referred to as a plasma ALD method. In this case, a plasma generating device is provided in the introduction portion of the third source gas. When generating plasma, inductively coupled plasma can be used. On the other hand, an ALD method in which a precursor and a reactant react using thermal energy is sometimes referred to as a thermal ALD method.

[0407] In the plasma ALD method, deposition is performed by introducing a reactant excited by plasma in the third step. Alternatively, deposition is performed by introducing a reactant excited by plasma (a second reactant) while repeating the first step to the fourth step. In this case, the reactant introduced in the third step is referred to as the first reactant. In the plasma ALD method, the second reactant used for the third source gas can use the same material as the above-mentioned oxidant. That is, ozone, oxygen and water excited by plasma can be used as the second reactant. In addition, a nitriding agent can also be used as the second reactant in addition to the oxidant. Nitrogen (N 2 ) or ammonia (NH 3 In addition, nitrogen (N 2 ) and hydrogen (H 2 ) can be used as a nitriding agent. For example, nitrogen (N 2 )5% and hydrogen (H 2 ) 95% of the mixed gas is used as a nitriding agent. By introducing nitrogen or ammonia excited by plasma and performing deposition, a nitride film such as a metal nitride film can be formed.

[0408] In addition, argon (Ar), helium (He), or nitrogen (N 2 ). By using a carrier gas such as argon, helium or nitrogen, it is easy to discharge plasma and generate a second reactant excited by the plasma, so it is preferred. Note that when an oxide film such as a metal oxide film is formed by a plasma ALD method and nitrogen is used as a carrier gas, nitrogen may be mixed into the film and the desired film quality may not be obtained. In this case, it is preferred to use argon or helium as a carrier gas.

[0409] By using the ALD method, a very thin film can be deposited with a uniform thickness, and a high coverage rate can be achieved on a surface having irregularities.

[0410] Here, refer to FIG. 30A to FIG. 30D This is an explanation of the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide. Fig. 30B and Fig.30D In the diagram, atoms are represented by spheres (circles), and the bonds between metal atoms and oxygen atoms are represented by lines. Fig. 30B and Fig.30D In the figure, the c-axis direction in the crystal structure of In-M-Zn oxide is indicated by the arrow in the figure. In addition, the ab plane direction in the crystal structure of In-M-Zn oxide is the same as that in Fig. 30B and Fig.30D The direction is perpendicular to the c-axis direction indicated by the arrow.

[0411] Fig. 30A6 is a diagram showing an oxide 660 including an In-M-Zn oxide formed on a structure 650. Here, a structure refers to a constituent element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate; a conductor such as a gate electrode, a source electrode, and a drain electrode; an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film; and a semiconductor such as a metal oxide and silicon. Fig. 30A The case where the deposition surface of the structure 650 is arranged in parallel with the substrate (or base, not shown) is shown.

[0412] Fig. 30B It is shown Fig. 30A This is an enlarged view of the atomic arrangement in the crystal of a portion of region 653 of oxide 660. Fig. 30A and Fig. 30B The composition of the oxide 660 shown is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is YbFe 2 O 4 In addition, the element M is a +3 valent metal element.

[0413] like Fig. 30B As shown, the crystals included in the oxide 660 are repeatedly stacked in sequence, including a layer 621 containing indium (In) and oxygen, a layer 631 containing element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen. The layers 621, 631, and 641 are arranged in a manner substantially parallel to the deposited surface of the structure 650. In other words, the ab plane of the oxide 660 is substantially parallel to the deposited surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposited surface of the structure 650.

[0414] like Fig. 30B As shown, the layer 621, the layer 631, and the layer 641 of the crystal are all composed of a metal element and oxygen, and can be arranged with high crystallinity to improve the mobility of the metal oxide.

[0415] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:1:1 [atomic ratio] is not limited to Fig. 30B The structure shown in FIG. 6 is a structure of ...

[0416] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] is shown, but its composition formula is In(1+α) M (1-α) O 3 (ZnO) m (α is a real number greater than 0 and less than 1, and m is a positive number) can also have a layered crystal structure. Fig. 30C and Fig.30D An In-M-Zn oxide having a composition of In:M:Zn=1:3:4 [atomic number ratio] is shown.

[0417] Fig. 30C is a diagram showing an oxide 662 including an In-M-Zn oxide formed on the structure 650. Fig.30D It is shown Fig. 30C An enlarged view of the atomic arrangement in the crystal of a region 654 of a portion of oxide 662 is shown.

[0418] like Fig.30D As shown, the crystal included in the oxide 662 has a layer 622 containing indium (In), element M and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing element M and oxygen. In the oxide 662, as a plurality of layers, a layer 622, a layer 641, a layer 631, and a layer 641 are repeatedly stacked in sequence. The layer 622, the layer 631, and the layer 641 are arranged in a manner substantially parallel to the deposited surface of the structure 650. In other words, the ab plane of the oxide 662 is substantially parallel to the deposited surface of the structure 650, and the c axis of the oxide 662 is substantially parallel to the normal direction of the deposited surface of the structure 650.

[0419] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:3:4 [atomic ratio] is not limited to Fig.30D The structure shown may be changed within the range of In:M:Zn=1:3:4 [atomic ratio]. For example, the stacking order of layer 622, layer 631, and layer 641 may be changed. In addition, a part of the element M in layer 631 may be replaced by zinc, and a part of the zinc in layer 641 may be replaced by element M. In addition, layer 621 or layer 631 may be formed instead of layer 622.

[0420] Next, refer to FIG. 31A to FIG. 32C Show Fig. 30A and Fig. 30B Detailed formation method of oxide 660 including In-M-Zn oxide is shown.

[0421] First, a source gas including a precursor containing indium is introduced into the chamber so that the precursor is adsorbed onto the surface of the structure 650 (see Fig.31AHere, the source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing indium, trimethylindium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0422] In addition, as a precursor containing indium, an inorganic precursor that does not contain hydrocarbons can also be used. As an inorganic precursor containing indium, a halogen indium compound such as indium trichloride, indium tribromide, or indium triiodide can be used. The decomposition temperature of indium trichloride is about 500°C or more and about 700°C or less. Therefore, by using indium trichloride, the substrate can be heated at about 400°C or more and about 600°C or less, for example, at 500°C, while deposition is performed using the ALD method.

[0423] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0424] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are desorbed while indium is adsorbed on the substrate, thereby forming a layer 621 formed by bonding indium and oxygen (see Fig.31B As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0425] Next, a source gas including a precursor containing element M is introduced into the chamber so that the precursor is adsorbed onto layer 621 (see Fig. 31C ). The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. When gallium is used as the element M, as a precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III)acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethyl gallium chloride, diethyl gallium chloride, dimethyl gallium isopropoxide, etc. can be used.

[0426] In addition, as a precursor containing gallium, an inorganic precursor that does not contain hydrocarbons may also be used. As an inorganic precursor containing gallium, a halogen gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide may be used. The decomposition temperature of gallium trichloride is about 550°C to about 700°C. Therefore, by using gallium trichloride, the substrate may be heated at about 450°C to about 650°C, for example, at 550°C, while deposition is performed using the ALD method.

[0427] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0428] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed on the substrate, thereby forming a layer 631 formed by bonding the element M and oxygen (see Fig.31D At this time, a part of the oxygen constituting the layer 641 may be adsorbed on the layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0429] Next, a source gas including a zinc precursor is introduced into the chamber so that the precursor is adsorbed onto the layer 631 (see Fig.32A ). At this time, a portion of the layer 641 formed by bonding zinc and oxygen is sometimes formed. The source gas includes a carrier gas such as argon, helium or nitrogen in addition to the precursor. As a precursor containing zinc, dimethyl zinc, diethyl zinc, bis (2,2,6,6-tetramethyl-3,5-heptanedione) zinc, zinc acetate, etc. can be used.

[0430] In addition, as a precursor containing zinc, an inorganic precursor that does not contain hydrocarbons may also be used. As an inorganic precursor containing zinc, a halogen-based zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide may be used. The decomposition temperature of zinc dichloride is about 450° C. to about 700° C. Therefore, by using zinc dichloride, the substrate may be heated at about 350° C. to about 550° C., for example, at 450° C., while deposition is performed using the ALD method.

[0431] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursors and reaction products from the chamber.

[0432] Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer 641 formed by bonding zinc and oxygen (see Fig.32B ). Next, the introduction of the oxidant is stopped, and the chamber is purged to discharge the remaining reactants and reaction products from the chamber.

[0433] Next, layer 621 is formed again on layer 641 by the above method (see Fig.32C ). By repeatedly performing the above method, an oxide 660 can be formed on the substrate or the structure.

[0434] Note that the above-mentioned precursor may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. In addition, a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.

[0435] As described above, by forming the oxide 660 using the ALD method, a metal oxide having a c-axis oriented substantially parallel to the normal direction of the deposited surface can be formed. Figure 1B and Figure 1C In the oxide semiconductor 230 shown, layered crystals can be formed that are substantially parallel to the side walls of the opening 290, and in particular, layered crystals that are substantially parallel to the side surfaces of the insulator 280. By adopting this structure, the layered crystals of the oxide semiconductor 230 are substantially parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.

[0436] Preferably, the substrate is heated while FIG. 31A to FIG. 32C For example, the substrate temperature may be set to be 200° C. or higher and 600° C. or lower, preferably 300° C. or higher and lower than the decomposition temperature of the precursor.

[0437] In order to perform deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably high. For example, the decomposition temperature of the precursor is preferably above 200°C and below 700°C, more preferably above 300°C and below 600°C. As such a precursor with a high decomposition temperature, an inorganic precursor is preferably used. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if deposition is performed while heating the substrate as described above, the precursor is not easily decomposed.

[0438] As inorganic precursors, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As mentioned above, the decomposition temperature of these precursors is above 350°C and below 700°C, which is much higher than the decomposition temperature of general organic precursors. However, as mentioned above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. When using multiple precursors of such different types and depositing using the ALD method, it is preferred to set the substrate temperature to be below the lowest decomposition temperature among the decomposition temperatures of the multiple precursors. In the above example, the substrate temperature can be set within a range where zinc dichloride, which has the lowest decomposition temperature of the precursor, will not decompose. As a result, in a state where other indium trichlorides and gallium trichlorides do not decompose, they can be adsorbed onto an object (for example, a substrate, etc.).

[0439] Notice, FIG. 31A to FIG. 32CAlthough an example is shown in which layer 621 is formed as a layer containing indium, layer 631 is formed as a layer containing element M thereon, and layer 641 is formed as a layer containing zinc thereon, this embodiment is not limited thereto. Alternatively, one of layer 631 and layer 641 may be formed, layer 621 may be formed thereon, and the other of layer 631 and layer 641 may be formed thereon. Alternatively, one of layer 631 and layer 641 may be formed, the other of layer 631 and layer 641 may be formed thereon, and layer 621 may be formed thereon.

[0440] When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above-mentioned layers 621, 631, and 641 may be formed appropriately according to the atomic ratio. Fig.32A The formation of the layer 641 may be repeated multiple times before and after the formation of the layer 631 shown, so that a stack of the layer 631 and the layer 641 having a desired number of atoms, number of layers, and thickness may be formed between the two layers 621 .

[0441] (Implementation 3) In this embodiment mode, a structural example of a memory device using the memory cell described in the above embodiment mode is described. In this embodiment mode, a structural example of a memory device is described in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0442] [Configuration Example of Storage Device] Fig.33 : is a block diagram showing a configuration example of a storage device 300 according to one embodiment of the present invention. Fig.33 The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0443] Fig.33 The example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. In addition, as an example, a functional circuit 51 is provided for each wiring BL used as a bit line. Fig.33 An example is shown in which a plurality of functional circuits 51 are provided corresponding to n wirings BL.

[0444] exist Fig.33, the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. Note that in the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0445] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0446] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0447] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor (making it non-conductive), the charge according to the data held in the capacitor can be maintained for a long time. Therefore, compared with a DRAM composed of a transistor containing silicon in the channel formation region (hereinafter also referred to as a "Si transistor"), the frequency of refresh operation of DOSRAM can be lower. As a result, low power consumption can be achieved.

[0448] In addition, the memory cell 10 can be stacked by stacking OS transistors as described in Embodiment Mode 1 and the like. Fig.33 In the memory array 20 shown, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the memory density of the memory cell 10 can be increased. In addition, the memory array 20 can be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 300 can reduce the manufacturing cost of the memory array 20.

[0449] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor used as a switch. Wiring PL has a function as a constant potential line connected to a capacitor.

[0450] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, the operation can be performed even if the capacitance of the capacitor included in the memory cell 10 is reduced.

[0451] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory array 20[1] to the memory cell 10 included in the memory array 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0452] In addition, the wiring BL is provided in a manner of contacting the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in a manner of contacting a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. Alternatively, the wiring BL is provided in a manner of contacting a conductor that functions as a source or a drain in a region of the semiconductor layer of the transistor included in the memory cell 10. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0453] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0454] By forming the functional circuit 51 with OS transistors similarly to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similarly to the memory arrays 20[1] to 20[m], thereby making it easy to integrate. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuit of the subsequent circuit such as the sense amplifier 46 can be miniaturized, thereby miniaturizing the memory device 300.

[0455] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (control circuit) and a voltage generation circuit 33.

[0456] In the storage device 300, each circuit, each signal and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0457] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 32.

[0458] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0459] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0460] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42 (RowDecoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (ColumnDriver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (SenseAmplifier).

[0461] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0462] The input circuit 47 has a function of holding a signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0463] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.33 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0464] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the memory density of the memory cell 10 may be increased. Fig.34A 1 is a perspective view of a memory device 300 showing a state in which five layers (m=5) of memory arrays 20 [ 1 ] to 20 [ 5 ] and a functional layer 50 are stacked on a drive circuit 21 .

[0465] exist Fig.34A In the embodiment, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the fifth layer is referred to as the memory array 20[5]. Fig.34A The wiring WL and the wiring PL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the memory arrays 20 is omitted. Note that Fig.34A Although the wiring PL is extended in the X direction, the present invention is not limited thereto. For example, the wiring PL may be extended in the Y direction, or in both the X and Y directions. For example, the wiring PL may be provided in a plane.

[0466] Fig.34B Yes Description Fig.34A FIG. 1 is a schematic diagram of a structural example of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to the memory array 20 [5] connected to the wiring BL. Fig.34B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0467] Fig.34B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. With respect to the transistor 11, the capacitor 12, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc.

[0468] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL.

[0469] For example, two memory cells 10 connected to the same wiring BL in the same layer may adopt the method according to Embodiment 1. Fig.25A and Fig.25B The structure shown.

[0470] in addition, Fig.34B , etc. show a structure in which two memory cells 10 are connected to the same wiring BL in the same layer, but the present invention is not limited thereto. For example, a structure in which four memory cells 10 are connected to the same wiring BL in the same layer may be adopted, or a structure in which eight memory cells 10 are connected to the same wiring BL in the same layer may be adopted. For example, when four memory cells 10 are provided in the same layer and connected to the same wiring BL, the structure according to Embodiment 1 may be adopted. Fig.26A and Fig.26B The structure shown.

[0471] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 12 .

[0472] Fig.34B The wiring GBL shown is provided so as to electrically connect the driving circuit 21 and the functional layer 50 . Fig.35ASchematic diagram of a memory device 300 is shown with a functional layer 50 and memory arrays 20[1] to 20[m] as a repeating unit 70. Fig.35A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0473] In addition, the wiring GBL is provided in a manner of contacting the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in a manner of contacting the region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as the source or drain. Alternatively, the wiring GBL is provided in a manner of contacting the conductor that contacts the region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as the source or drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0474] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig.35B The repeating unit 70 may include a repeating unit 70 [1] to a repeating unit 70 [p] (p is an integer greater than or equal to 2). The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of functional circuits 51.

[0475] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By arranging the wiring used as a bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0476] In addition, one embodiment of the present invention includes a functional layer 50 in a layer provided with the memory array 20, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the drive circuit 21. Since the circuit such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the operation can be performed even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0477] [Configuration Example of Memory Array 20 and Functional Circuit 51] Reference Fig.36 illustrate Figures 33 to 35B The described configuration examples of the functional circuit 51 and the memory array 20 and the sense amplifier 46 included in the driver circuit 21 are shown. Fig.36 The driving circuit 21 is shown, and the driving circuit 21 is connected to the wiring GBL (GBL_A, GBL_B), and the wiring GBL (GBL_A, GBL_B) is connected to the functional circuit 51 (51_A, 51_B), and the functional circuit 51 (51_A, 51_B) is connected to the memory cell 10 (10_A, 10_B) connected to the different wiring BL (BL_A, BL_B). Fig.36 The driving circuit 21 shown in the figure shows a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 in addition to the sense amplifier 46 .

[0478] As the functional circuit 51_A and the functional circuit 51_B, a transistor 52_a, a transistor 52_b, a transistor 53_a, a transistor 53_b, a transistor 54_a, a transistor 54_b, a transistor 55_a, and a transistor 55_b are shown. Fig.36 The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown are OS transistors like the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked like the memory arrays 20[1] to 20[m].

[0479] The wirings BL_A and BL_B are connected to the gates of the transistors 52_a and 52_b. The wirings GBL_A and GBL_B are connected to one of the source and the drain of the transistors 53_a, 53_b, 54_a, and 54_b. Similar to the wirings BL_A and BL_B, the wirings GBL_A and GBL_B are arranged in the vertical direction and connected to the transistors included in the driving circuit 21. Fig.36 As shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with control signals WE, RE, and MUX.

[0480] constitute Fig.36 The transistors 81_1 to 81_6 and 82_1 to 82_4 of the sense amplifier 46, precharge circuit 71_A and precharge circuit 71_B shown are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, 54_b is connected to the transistor or switch constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.

[0481] Precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. Precharge circuit 71_A is a circuit that precharges wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal supplied to precharge line PCL1.

[0482] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6 and precharges the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2.

[0483] The sense amplifier 46 includes a p-channel transistor 82_1, a p-channel transistor 82_2, and an n-channel transistor 82_3, and an n-channel transistor 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. By selecting the memory cells 10_A and 10_B, the potential of the precharged wiring BL_A and the wiring BL_B changes, and according to the change, the potential of the wiring GBL_A and the wiring GBL_B is set to the high power supply potential VDD or the low power supply potential VSS. The potential of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch 83_C and the switch 83_D and the write-read circuit 73. The wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B are equivalent to a bit line pair. The writing / reading circuit 73 is controlled to write a data signal based on the signal EN_data.

[0484] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B. The switch circuit 72_A can be switched on or off by controlling the switching signal CSEL1. In the case where the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and are turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched on or off by controlling the switching signal CSEL2. The switches 83_C and 83_D can be the same as the switches 83_A and 83_B.

[0485] like Fig.36As shown, the memory device 300 may have a structure in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected by the wiring BL and the wiring GBL arranged in the shortest vertical direction. Although the functional layer 50 including the transistor constituting the functional circuit 51 increases, the load of the wiring BL is reduced, so that the writing time can be shortened and the data can be easily read.

[0486] In addition, if Fig.36 As shown, each transistor included in the functional circuit 51_A, 51_B is controlled by the control signal WE, RE and the selection signal MUX. Each transistor can output the potential of the wiring BL to the driving circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A, 51_B can be used as a sense amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0487] As described above, by stacking a plurality of memory cell arrays and drive circuits, high integration of the memory device and increased storage capacity can be achieved.

[0488] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0489] (Implementation 4) In this embodiment, refer to Fig.37A and Fig.37B An example of a chip 1200 on which the memory device of the present invention is mounted will be described. A plurality of circuits (systems) are mounted on the chip 1200. In this way, the technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0490] like Fig.37A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0491] Bumps (not shown) are provided on the chip 1200. Fig.37B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0492] A storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOS RAM described in the above embodiment may be applied to the DRAM 1221. Thus, the DRAM 1221 can have low power consumption, high speed, and large capacity.

[0493] CPU1211 preferably has multiple CPU cores. In addition, GPU1212 preferably has multiple GPU cores. In addition, CPU1211 and GPU1212 may also each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned DOSRAM can be applied to the memory. In addition, GPU1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention in GPU1212, image processing and product-sum operations can be performed with low power consumption.

[0494] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0495] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0496] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0497] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0498] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0499] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0500] A motherboard 1203 including a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a DRAM 1221 , and a flash memory 1222 may be referred to as a GPU module 1204 .

[0501] The GPU module 1204 can be reduced in size because it has a chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles because of its high image processing capabilities. In addition, by using the product-sum operation circuit of the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby using the chip 1200 as an AI chip, or using the GPU module 1204 as an AI system module.

[0502] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments, etc. described in this specification as appropriate.

[0503] (Implementation method 5) This embodiment mode describes an example of an electronic component and an electronic device in which the storage device described in the above embodiment mode is incorporated. By using the storage device described in the above embodiment mode for the following electronic component and electronic device, low power consumption and high speed of the electronic component and electronic device can be achieved.

[0504] <Electronic components> First, refer to Fig.38A and Fig.38B An example of an electronic component in which the storage device 720 is incorporated will be described.

[0505] Fig.38A It is a perspective view of an electronic component 700 and a substrate (circuit board 704) on which the electronic component 700 is mounted. Fig.38A The electronic component 700 shown includes a storage device 720 within a mold 711. Fig.38A700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to a storage device 720 via a lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the above-mentioned electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0506] The storage device 720 includes a driving circuit layer 721 and a storage circuit layer 722 .

[0507] Fig.38B 7 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731. By using the storage device described in the above embodiment as the storage device 720, low power consumption and high speed can be achieved.

[0508] As the semiconductor device 735 , an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0509] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0510] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are arranged in a single layer or in multiple layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit arranged on the plug board 731 to the electrode arranged on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "redistribution substrate" or "intermediate substrate". In addition, sometimes a through electrode is arranged in the plug board 731 and the through electrode is used to electrically connect the integrated circuit to the package substrate 732. In addition, in the case of using a silicon plug board, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0511] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0512] In addition, in SiP, MCM, etc. using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. In particular, the silicon interposer is preferably used for 2.5D packaging (2.5D mounting), in which a plurality of integrated circuits are arranged on the interposer in a horizontal direction.

[0513] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the height of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the height of the storage device 720 and the semiconductor device 735 consistent.

[0514] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.38B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0515] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0516] As described above, the structure, method, and the like described in this embodiment mode can be used in combination with other structures, methods described in this embodiment mode, and structures, methods, and the like described in other embodiments mode as appropriate.

[0517] (Implementation 6) In this embodiment, an application example of a storage device using the storage device shown in the above embodiment is described. The storage device shown in the above embodiment can be applied to the storage device of various electronic devices (for example, information terminals, computers, smart phones, e-book readers, digital cameras (including video cameras), video playback devices, navigation systems, etc.). By using the storage device shown in the above embodiment for the storage device of the above electronic device, low power consumption and high speed of the electronic device can be achieved. Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the storage device shown in the above embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, SSDs (solid state drives), etc. FIG. 39A to FIG. 39E Several structural examples of the removable storage device are schematically shown. For example, the storage device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0518] Fig.39A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The storage device shown in the above embodiment can be assembled to the memory chip 1105 and the like.

[0519] Fig.39B This is a schematic diagram of the appearance of an SD card. Fig.39C 11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The storage device shown in the above embodiment can be assembled on the memory chip 1114, etc.

[0520] Fig.39D This is a schematic diagram of the appearance of SSD. Fig.39E1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The storage device shown in the above embodiment can be assembled to the memory chip 1154, etc.

[0521] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments, etc. described in this specification as appropriate.

[0522] (Implementation 7) The storage device according to one embodiment of the present invention can be used in a processor or chip such as a CPU or a GPU. By using such a processor or chip such as a CPU or a GPU in an electronic device, it is possible to realize low power consumption and high speed of the electronic device. FIG. 40A to FIG. 40H A specific example of an electronic device including a processor or chip such as a CPU or a GPU using the storage device is shown.

[0523] <Electronic equipment and systems> A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. Examples of electronic devices include television devices, displays for desktop or notebook information terminals, digital signage, large-scale game machines such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. In addition, by setting a GPU or chip according to one embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

[0524] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal using the antenna, an image, information, etc. can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0525] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of sensing, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0526] An electronic device of one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. FIG. 40A to FIG. 40H An example of an electronic device is shown.

[0527] [Information Terminal] Fig.40A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102 . The display portion 5102 is provided with a touch panel as an input interface, and buttons are provided on the housing 5101 .

[0528] The information terminal 5100 can realize low power consumption and high speed by adopting the chip of one embodiment of the present invention.

[0529] Fig.40B 1 and 2. The notebook information terminal 5200 is shown. The notebook information terminal 5200 includes an information terminal body 5201, a display portion 5202, and a keyboard 5203.

[0530] Similar to the above-mentioned information terminal 5100 , the notebook information terminal 5200 can realize low power consumption and high speed by adopting a chip according to one embodiment of the present invention.

[0531] Note that in the above, Fig.40A and Fig.40B Although a smartphone and a notebook information terminal are shown as examples of electronic devices, information terminals other than smartphones and notebook information terminals may also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0532] [Game console] Fig.40CA portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, and operation keys 5306. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, the housing 5302 and the housing 5303 can be used as an operation unit, respectively. Thus, multiple game players can play games at the same time. The chip shown in the above embodiment can be assembled to a chip provided on a substrate of the housing 5301, the housing 5302, and the housing 5303.

[0533] in addition, Fig.40D A stationary gaming machine 5400, which is one of the gaming machines, is shown. The stationary gaming machine 5400 is connected to a controller 5402 by wireless or wired connection.

[0534] By applying a GPU or chip of one embodiment of the present invention to a gaming machine such as the portable gaming machine 5300 and the fixed gaming machine 5400, a gaming machine with low power consumption can be realized. In addition, the heat generated by the circuit can be reduced by means of low power consumption, thereby reducing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0535] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, low power consumption and high speed can be achieved.

[0536] Although Fig.40C and Fig.40D Portable game consoles and stationary game consoles are shown as examples of game consoles, but game consoles to which a GPU or chip according to one embodiment of the present invention is applied are not limited thereto. Game consoles to which a GPU or chip according to one embodiment of the present invention is applied include, for example, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.

[0537] [Mainframe computer] The GPU or chip according to one embodiment of the present invention can be applied to large computers.

[0538] Fig.40E A supercomputer 5500 is shown as an example of a large-scale computer. Fig.40F A rack-mount computer 5502 included in the supercomputer 5500 is shown.

[0539] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are housed in the rack 5501. In addition, the computer 5502 is provided with a plurality of substrates 5504 on which the GPUs or chips described in the above embodiment can be mounted.

[0540] Supercomputer 5500 is a large computer mainly suitable for scientific computing. Scientific computing requires huge calculations at high speed, so the power consumption is large and the heat generation of the chip is high. For example, the amount of data used in a data center including multiple supercomputers 5500 is very large. Specifically, it is estimated that the amount of digital data in the world exceeds 10 24 (yota) bytes or 10 30 (quetta) bytes.

[0541] By applying a GPU or chip of one embodiment of the present invention to supercomputer 5500, a low-power supercomputer can be realized. In addition, low power consumption can reduce the heat generated by the circuit, thereby reducing the impact of heat on the circuit itself, peripheral circuits and modules. By applying a GPU or chip using a storage device of one embodiment of the present invention, a low-power supercomputer can be realized. Thus, by reducing the amount of digital data in the world, it is expected to contribute to global warming countermeasures.

[0542] exist Fig.40E and Fig.40F In the embodiment of the present invention, a supercomputer is shown as an example of a large-scale computer, but a large-scale computer to which a GPU or chip of one embodiment of the present invention is applied is not limited to this. As a large-scale computer to which a GPU or chip of one embodiment of the present invention is applied, for example, a computer (server) providing a service, a large-scale general-purpose computer (mainframe), etc. can be cited.

[0543] [Mobile body] The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0544] Figure 40G This is a diagram showing the periphery of a front windshield in an automobile as an example of a moving object. Figure 40G Display panels 5701, 5702, and 5703 installed on the instrument panel and display panel 5704 installed on the pillar are shown.

[0545] Display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a driving distance, a fuel gauge, a gear status, an air conditioning setting, etc. In addition, the user can appropriately change the display content and layout displayed on the display panel according to preference, which can improve the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0546] By displaying an image captured by a camera device (not shown) installed in the car on the display panel 5704, the field of view (blind spot) blocked by the pillar can be compensated. In other words, by displaying an image captured by a camera device installed outside the car, the blind spot can be compensated, thereby improving safety. In addition, by displaying an image that compensates for the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0547] Because the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of a car. In addition, the chip can be used in a system for navigation, danger prediction, etc. In addition, information such as navigation and danger prediction can also be displayed on display panels 5701 to 5704.

[0548] Note that although a car is described as an example of a mobile body in the above description, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (UAV), an airplane, a rocket), etc. can also be cited as a mobile body, and a chip of one embodiment of the present invention can be applied to these mobile bodies to provide a system using artificial intelligence.

[0549] [Electrical products] Figure 40H An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0550] By applying a chip of one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food, and the like.

[0551] An electric refrigerator-freezer is described as an example of an electrical appliance, but other electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0552] The electronic device, the functions of the electronic device, the application examples of artificial intelligence and the effects thereof, and the like described in this embodiment mode can be appropriately combined with the description of other electronic devices.

[0553] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments, etc. described in this specification as appropriate.

[0554] (Implementation 8) A storage device according to one embodiment of the present invention includes an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation and can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space. In this embodiment, an OS transistor is used. Fig.41 A specific example of a case where a storage device according to one embodiment of the present invention is applied to space equipment will be described.

[0555] exist Fig.41 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.41 An example is shown in which there is a planet 6804 in outer space. Note that outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0556] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. In addition, as radiation, for example, there can be cited: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0557] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0558] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0559] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, it is preferable to use a storage device including an OS transistor of one embodiment of the present invention. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0560] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0561] Note that in this embodiment, an artificial satellite is described as an example of a space device, but the present invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be appropriately applied to space devices such as a spacecraft, a space capsule, and a space probe. [Explanation of symbols]

[0562] BL: wiring, PL: wiring, Tr: transistor, WL: wiring, 10: memory cell, 11: transistor, 12: capacitor, 20: memory array, 21: drive circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 53_a: transistor, 53_b: transistor, 54_a: transistor, 54_b: transistor, 55_a: transistor, 55_b: transistor, 70: repeating unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write-read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 100a: capacitor, 100b: capacitor, 100c: capacitor, 100d: capacitor, 100: capacitor, 110: conductor, 120: conductor body, 130: insulator, 140: insulator, 150a: memory cell, 150b: memory cell, 150c: memory cell, 150d: memory cell, 150p: memory cell, 150q: memory cell, 150r: memory cell, 150: memory cell, 160[1,1]: memory cell, 160[1,2]: memory cell, 160[1,3]: memory cell, 160[1,4]: memory cell, 160[2,1]: memory cell, 160[2,2]: memory cell, 160[2,3]: memory cell, 160[2,4]: memory cell, 160: memory cell, 170[1]: layer, 170[2]: layer, 170[ m-1]: layer, 170[m]: layer, 200a: transistor, 200b: transistor, 200c: transistor, 200d: transistor, 200: transistor, 230a: oxide semiconductor, 230b: oxide semiconductor, 230i: region, 230na: region, 230nb: region, 230: oxide semiconductor, 240: conductor, 240A: conductive film, 245: conductor, 246: conductor, 250a: insulator, 250b: insulator, 250c: insulator, 250: insulator, 252: insulator, 260a: conductor, 260b: conductor, 260: conductor, 265: conductor, 280a: insulator, 280b: insulator,280c: insulator, 280: insulator, 281: insulator, 283: insulator, 287: insulator, 289: insulator, 290: opening, 300A: storage device, 300: storage device, 610: substrate, 611a: precursor, 611b: precursor, 612a: reactant, 612b: reactant, 613a: oxide, 613b: oxide, 613c: oxide, 621: layer, 622: layer, 631: layer, 641: layer, 650: structure, 653: region, 654: region, 660: oxide, 662: oxide, 700: electronic component, 702: printed circuit board, 704: circuit board, 711: mold, 712 : connection pad, 713: electrode pad, 714: lead, 720: storage device, 721: drive circuit layer, 722: storage circuit layer, 730: electronic component, 731: plug board, 732: package substrate, 733: electrode, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cover, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 11 53: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: simulation operation unit, 1214: storage controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5100: information terminal, 5101: casing, 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game console, 5301: casing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection unit, 5306: operation key, 5400: fixed game console, 5402: controller, 5500: supercomputer, 5501: rack, 5502: computer, 5504: substrate, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator door, 5803: freezer door, 6800: artificial satellite, 6801: main body, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device.

Claims

1. A storage device, comprising: Storage unit; as well as The first insulator, The storage unit includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductor, a second insulator on the first conductor, and a second conductor on the second insulator, The first insulator is arranged on the first conductor, the second insulator, and the second conductor. The transistor includes the second conductor, a third conductor on the first insulator, an oxide semiconductor, a third insulator, and a fourth conductor. An opening reaching the second conductor is provided in the first insulator and the third conductor, At least a portion of the oxide semiconductor is disposed in the opening, The oxide semiconductor has a region in contact with the top surface of the second conductor in the opening, a region in contact with the side surface of the third conductor in the opening, and a region in contact with at least a portion of the top surface of the third conductor, The third insulator is arranged on the oxide semiconductor in such a manner that at least a portion of the third insulator is located in the opening. The fourth conductor is arranged on the third insulator in such a manner that at least a portion of the fourth conductor is located in the opening. Furthermore, an angle formed by a side surface of the first insulator and a top surface of the first conductor in the opening is greater than or equal to 45 degrees and less than 90 degrees.

2. The storage device according to claim 1, The channel length of the transistor is at least smaller than the channel width of the transistor.

3. The storage device according to claim 1, The second insulator includes a material having ferroelectricity.

4. The storage device according to claim 1, The second insulator comprises a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

5. The storage device according to claim 1, The oxide semiconductor includes any one or more selected from In, Ga and Zn.

6. The storage device according to claim 5, wherein the first insulator comprises a laminated body, The laminate includes a first layer, a second layer on the first layer, and a third layer on the second layer, The first layer comprises silicon and nitrogen, The second layer comprises silicon and oxygen, And the third layer contains silicon and nitrogen.

7. A storage device, comprising: Storage unit; as well as The first insulator, The storage unit includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductor, a second insulator on the first conductor, and a second conductor on the second insulator, The first insulator is arranged on the first conductor, the second insulator, and the second conductor. The transistor includes the second conductor, a third conductor on the first insulator, an oxide semiconductor, a third insulator, and a fourth conductor. An opening reaching the second conductor is provided in the first insulator and the third conductor, At least a portion of the oxide semiconductor is disposed in the opening, The oxide semiconductor has a region in contact with the top surface of the second conductor in the opening, a region in contact with the side surface of the third conductor in the opening, and a region in contact with at least a portion of the top surface of the third conductor, The third insulator is arranged on the oxide semiconductor in such a manner that at least a portion of the third insulator is located in the opening. The fourth conductor is arranged on the third insulator in such a manner that at least a portion of the fourth conductor is located in the opening. Furthermore, the bottom of the fourth conductor located in the opening has a needle-like shape.

8. The storage device according to claim 7, The channel length of the transistor is at least smaller than the channel width of the transistor.

9. The storage device according to claim 7, The second insulator includes a material having ferroelectricity.

10. The storage device according to claim 7, The second insulator comprises a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

11. The storage device according to claim 7, The oxide semiconductor includes any one or more selected from In, Ga and Zn.

12. The storage device according to claim 11, wherein the first insulator comprises a laminated body, The laminate includes a first layer, a second layer on the first layer, and a third layer on the second layer, The first layer comprises silicon and nitrogen, The second layer comprises silicon and oxygen, And the third layer contains silicon and nitrogen.

13. The storage device according to any one of claims 1 to 12, wherein the fourth conductor extends in the first direction, And the third electrical conductor extends in a second direction orthogonal to the first direction.

14. The storage device according to claim 13, further comprising: a plurality of layers including said storage unit, A plurality of said layers are stacked.

Images