Memory device and method for manufacturing memory device

Abstract

Provided is a memory device capable of achieving miniaturization or high integration. The memory device includes a memory cell on a first transistor containing silicon in a semiconductor layer. The memory cell includes a capacitor and a second transistor on the capacitor. A first conductor, a first insulator, and a second conductor are laminated in this order in the capacitor. The second conductor also functions as one of a source and a drain of the second transistor. A third conductor serving as the other of the source and drain of the second transistor is on the second insulator. The second insulator and the third conductor are provided with openings to the second conductor. An oxide semiconductor, a third insulator, and a fourth conductor are laminated in this order so as to overlap the opening. The fourth conductor is electrically connected to the source or drain of the first transistor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a method for depositing a metal oxide. In addition, one embodiment of the present invention relates to a semiconductor device using the metal oxide and a method for manufacturing the semiconductor device. In addition, one embodiment of the present invention relates to a storage device using the metal oxide and a method for manufacturing the storage device. In addition, one embodiment of the present invention relates to a transistor including the metal oxide and a method for manufacturing the transistor.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, sometimes storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, or include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer into a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (eg, printed wiring boards) and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and display devices. As a semiconductor material that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In addition, in recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if a vertical transistor can be realized, integrated circuits can be made more dense. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered by a gate electrode via a gate insulator.

[0010] In addition, in oxide semiconductors, a CAAC (c-axis aligned crystal) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been found (see Non-Patent Documents 2 and 3).

[0011] Non-Patent Documents 2 and 3 disclose a technology for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior technical literature] [Patent Document]

[0012] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0013] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 [Non-patent document 2] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, pp. 183-186 [Non-patent document 3] S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, pp. 04ED18-1-04ED18-10 Summary of the invention Technical problem to be solved by the invention

[0014] One of the purposes of one embodiment of the present invention is to provide a novel metal oxide and a method for depositing the same. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, a semiconductor device or a storage device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, a semiconductor device or a storage device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or a storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with a fast operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing the above-mentioned transistor, semiconductor device or storage device.

[0015] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not necessarily achieve all of the above purposes. In addition, purposes other than the above can be extracted from the description of the specification, drawings, and claims. Solutions to technical problems

[0016] One embodiment of the present invention is a memory device, comprising a first transistor, a first conductor on the first transistor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator, wherein the first transistor includes silicon in a semiconductor layer, the first transistor and the first conductor are electrically insulated from each other, the memory cell comprises a capacitor and a second transistor on the capacitor, the capacitor comprises a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator, the first insulator is provided with a first opening portion reaching the first conductor, at least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening portion, and the second conductor, the third insulator, and the second insulator are arranged on the third conductor, The second transistor includes a third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator and a fifth conductor, the fourth conductor is electrically connected to the source or drain of the first transistor, the second insulator and the fourth conductor are provided with a second opening reaching the third conductor, at least a portion of the oxide semiconductor is arranged in the second opening, the oxide semiconductor has a region in contact with the top surface of the third conductor in the second opening, a region in contact with the side surface of the fourth conductor in the second opening, and a region in contact with at least a portion of the top surface of the fourth conductor, the fourth insulator is arranged on the oxide semiconductor in such a way that at least a portion of it is located in the second opening, and the fifth conductor is arranged on the fourth insulator in such a way that at least a portion of it is located in the second opening.

[0017] The second opening preferably has a region overlapping with the first opening.

[0018] The channel length of the second transistor is preferably smaller than the channel width of the second transistor.

[0019] The third insulator preferably includes a material that can have ferroelectricity.

[0020] The third insulator preferably includes a first zirconium oxide, aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

[0021] The oxide semiconductor preferably contains one or more selected from In, Ga, and Zn.

[0022] The oxide semiconductor preferably has a crystal part. In addition, the oxide semiconductor preferably has a layered crystal structure.

[0023] Preferably, the first insulator includes a first layer and a second layer on the first layer, the first layer includes silicon and nitrogen, and the second layer includes silicon and oxygen.

[0024] Preferably, a fifth insulator is provided between the side surface of the first insulator in the first opening and the second conductor, and the fifth insulator contains silicon and nitrogen.

[0025] Preferably, the fifth conductor is extended in the first direction, the fourth conductor is extended in the second direction, and the fifth conductor is orthogonal to the fourth conductor.

[0026] The above-mentioned storage device preferably further includes a plurality of stacked layers including storage cells.

[0027] One embodiment of the present invention is a method for manufacturing a storage device, comprising: forming a first conductor; forming a first insulator on the first conductor; processing the first insulator to form a first opening portion reaching the first conductor; forming a second conductor in contact with the side of the first insulator at the first opening portion; forming a second insulator on the second conductor; forming a third conductor on the second insulator; forming a third insulator on the third conductor; forming a fourth conductor on the third insulator; processing the fourth conductor and the third insulator respectively to form a second opening portion reaching the third conductor; forming an oxide semiconductor in contact with the top surface of the third conductor, the side surface of the third insulator, and the top surface and side surface of the fourth conductor at the second opening portion; forming a fourth insulator on the oxide semiconductor; and forming a fifth conductor on the fourth insulator, wherein in the formation process of the oxide semiconductor, a deposition process using an ALD method and an impurity removal process in an oxygen-containing atmosphere are repeatedly and alternately performed multiple times.

[0028] Microwave treatment is preferably performed as the impurity removal treatment. Preferably, a crystal portion is formed in the oxide semiconductor or the crystallinity of the oxide semiconductor is improved by the microwave treatment. Effects of the Invention

[0029] According to one embodiment of the present invention, a novel metal oxide and a method for depositing the same can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device or a storage device capable of miniaturization or high integration can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device or a storage device with high reliability can be provided. According to one embodiment of the present invention, a transistor with a large on-state current can be provided. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device or a storage device with low power consumption can be provided. According to one embodiment of the present invention, a storage device with a high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device or storage device can be provided.

[0030] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1A to 1Eis a cross-sectional view showing an example of a method for depositing a metal oxide. FIG. 2A to FIG. 2D is a cross-sectional view showing an example of a metal oxide. FIG. 3A to FIG. 3D is a cross-sectional view showing an example of a metal oxide. FIG. 4A to FIG. 4C This is a diagram showing an example of the range of the atomic number ratio of the metal oxide. FIG. 5A to FIG. 5D is a cross-sectional view showing an example of a method for depositing a metal oxide. FIG. 6A to FIG. 6C is a cross-sectional view showing an example of a method for depositing a metal oxide. Figure 7 is a top view showing an example of a deposition apparatus. Fig. 8A and Figure 8B is a cross-sectional view showing an example of a deposition apparatus. 9A to 9C is a cross-sectional view showing an example of a deposition apparatus. Fig. 10A and Fig. 10B This is a diagram showing an example of a method for depositing a metal oxide. Fig.11A and Fig. 11B This is a diagram showing an example of a method for depositing a metal oxide. Fig.12 This is a diagram showing an example of a method for depositing a metal oxide. Fig.13A is a plan view showing an example of a storage device. Fig. 13B and Fig. 13C is a cross-sectional view showing an example of a storage device. Fig.13D is a circuit diagram showing an example of a storage device. Fig.14A and Fig. 14B is a plan view showing an example of a storage device. FIG. 15A to FIG. 15D is a cross-sectional view showing an example of a storage device. FIG. 16A to FIG. 16D is a cross-sectional view showing an example of a storage device. Fig.17A and Fig. 17B is a cross-sectional view showing an example of a storage device. 18A to 18D is a cross-sectional view showing an example of a storage device. Fig.19A is a plan view showing an example of a storage device. Fig.19B and Fig.19Cis a cross-sectional view showing an example of a storage device. Fig. 20A and Fig. 20B is a cross-sectional view showing an example of a storage device. FIG. 21A to FIG. 21D is a cross-sectional view showing an example of a storage device. Fig.22A and Fig. 22B is a cross-sectional view showing an example of a storage device. Fig.23A is a plan view showing an example of a storage device. Fig. 23B and Fig.23C is a cross-sectional view showing an example of a storage device. Fig.24A is a plan view showing an example of a storage device. Fig. 24B is a cross-sectional view showing an example of a storage device. Fig.25A is a plan view showing an example of a storage device. Fig.25B is a cross-sectional view showing an example of a storage device. Fig.26A is a plan view showing an example of a storage device. Fig.26B is a cross-sectional view showing an example of a storage device. FIG. 27A to FIG. 27C FIG. 1 is a planar layout showing an example of a storage device. FIG. 28A to FIG. 28C FIG. 1 is a planar layout showing an example of a storage device. Fig.29 is a cross-sectional view showing an example of a storage device. Fig.30 is a block diagram showing an example of a storage device. Fig.31A and Fig.31B is a schematic diagram showing an example of a storage device. FIG. 32A to FIG. 32D is a circuit diagram showing an example of a storage device. Fig.33 is a circuit diagram showing an example of a storage device. Fig.34A and Fig.34B This is a diagram showing an example of an electronic component. Fig.35A and Fig.35B is a diagram showing an example of an electronic device, FIG. 35C to FIG. 35E This is a diagram showing an example of a large computer. Fig.36 is a diagram showing an example of space equipment. Fig.37is a diagram showing an example of a storage system that can be used in a data center. Fig.38 This is a cross-sectional TEM image of a metal oxide according to one embodiment of the present invention in an Example. Fig.39 This is a cross-sectional TEM image of a metal oxide of a comparative example in the example. FIG. 40A to FIG. 40D This is a graph showing the results of XRD analysis of metal oxides in Examples. Modes for Carrying Out the Invention

[0032] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0033] Note that in the invention structure described below, the same reference numerals are used in common in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0034] In addition, for ease of understanding, the positions, sizes, and ranges of the components shown in the drawings sometimes do not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to etching or other processes, but this is sometimes not reflected in the drawings for ease of understanding.

[0035] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0036] A transistor is a type of semiconductor element and can realize functions of amplifying current or voltage, controlling switching operations of conduction or non-conduction, etc. The transistor in this specification includes IGFET (Insulated Gate Field Effect Transistor) and thin film transistor (TFT: Thin Film Transistor).

[0037] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification, etc., a channel formation region refers to a region where current mainly flows.

[0038] In addition, when transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the source and the drain may be interchanged. Therefore, in this specification, the source and the drain may be interchanged.

[0039] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, the mixing of impurities sometimes leads to oxygen vacancies (also recorded as V O )’s formation.

[0040] Note that in this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen in its composition, and an oxynitride refers to a material containing more nitrogen than oxygen in its composition.

[0041] For example, the content of hydrogen, oxygen, carbon, nitrogen and other elements in the film can be analyzed by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (for example, 0.5 atomic% or more or 1 atomic%). On the other hand, SIMS is suitable when the content of the target element is low (for example, 0.5 atomic% or less or 1 atomic%). When comparing the content of elements, it is more preferable to use a composite analysis using both SIMS and XPS analysis techniques.

[0042] Note that in this specification, etc., “insulator” may be referred to as “insulating film” or “insulating layer”. Also, “conductor” may be referred to as “conductive film” or “conductive layer”. Also, “semiconductor” may be referred to as “semiconductor film” or “semiconductor layer”.

[0043] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0044] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions in addition to electrodes and wiring.

[0045] In addition, in this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also called the non-conducting state or the blocking state). In an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0046] In this specification, the top surface shape of a component refers to the outline shape of the component when viewed in a plan view. In addition, the plan view refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

[0047] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the formed surface. For example, it is preferred to have a region in which the angle (also referred to as a taper angle) formed by the inclined side surface and the substrate surface or the formed surface is less than 90 degrees. Here, the side surface, substrate surface, and formed surface of the constituent element do not necessarily have to be completely flat, and may also be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0048] In this specification and the like, when there is a description that "A is in contact with B", at least a portion of A is in contact with B. Therefore, for example, it can be alternatively stated that A includes a region in contact with B.

[0049] In this specification and the like, when there is a description that “A is located on B”, at least a portion of A is located on B. Therefore, for example, it can be alternatively stated that A includes a region located on B.

[0050] In this specification and the like, when there is a description that "A covers B", at least a portion of A covers B. Therefore, for example, it can be alternatively described that A includes a region covering B.

[0051] In this specification and the like, when there is a description that "A overlaps with B", at least a portion of A overlaps with B. Therefore, for example, it can be alternatively stated that A includes a region overlapping with B.

[0052] (Implementation Method 1) In this embodiment, using FIG. 1 to FIG. Fig.12 A metal oxide and a method for depositing the metal oxide according to one embodiment of the present invention will be described.

[0053] Depending on the type, combination, composition, etc. of the elements constituting the metal oxide, the metal oxide of one embodiment of the present invention can be used as any of a semiconductor material, an insulating material, and a conductive material. For example, the metal oxide of one embodiment of the present invention can be used for a semiconductor layer of a transistor. The metal oxide is sometimes referred to as an oxide semiconductor or an oxide.

[0054] Since the ALD (Atomic Layer Deposition) method is used in the deposition method of the metal oxide according to one embodiment of the present invention, a film having an extremely small thickness can be uniformly formed, and thus, the present invention is suitable for the deposition of metal oxide constituting a micro transistor.

[0055] In the metal oxide deposition method of one embodiment of the present invention, one or both of an inorganic precursor and an organic precursor may be used. Here, an organic precursor refers to a precursor containing carbon as a constituent element, and an inorganic precursor refers to a precursor not containing carbon as a constituent element.

[0056] The impurity concentration (eg, at least one of hydrogen concentration, carbon concentration, and nitrogen concentration) in the film of the metal oxide deposited using the inorganic precursor may be lower than that of the metal oxide deposited using the organic precursor.

[0057] Furthermore, by using an organic precursor, the metal oxide can be deposited at a lower concentration than when an inorganic precursor is used.

[0058] Even if the metal oxide formed by the ALD method is heat-treated after deposition, it is sometimes difficult to fully remove impurities in the film. On the other hand, when a high-temperature treatment (e.g., a treatment exceeding 700° C.) is performed to increase the maximum temperature in the manufacturing process of a transistor or semiconductor device in order to deposit a metal oxide with a low impurity content, productivity decreases.

[0059] In view of this, in a deposition method of a metal oxide in one embodiment of the present invention, an impurity removal treatment is intermittently performed in an oxygen-containing atmosphere during deposition. By performing an impurity removal treatment during deposition, impurities in the film can be more reliably removed compared to the case where the impurity removal treatment is performed after deposition. Thus, impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors can be suppressed from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. In addition, the crystallinity of the metal oxide can be improved.

[0060] Thus, by utilizing a metal oxide deposition method according to one embodiment of the present invention, a metal oxide having a low impurity content in a semiconductor layer for a micro transistor can be formed. In addition, by utilizing a metal oxide deposition method according to one embodiment of the present invention, a metal oxide having high crystallinity in a semiconductor layer for a micro transistor can be formed. Thus, a micro transistor having good electrical characteristics can be realized. In addition, a micro transistor having high reliability can be realized. In particular, a metal oxide having a CAAC structure is preferably formed.

[0061] Specifically, one embodiment of the present invention is a method for depositing a metal oxide, comprising the following steps: a first step of supplying a first compound into a chamber and then supplying an oxidant into the chamber; and a second step of supplying a second compound into the chamber and then supplying an oxidant into the chamber, and may also include a third step of supplying a third compound into the chamber and then supplying an oxidant into the chamber.

[0062] In the deposition method of a metal oxide according to one embodiment of the present invention, it is preferred that after the first step and the second step are performed more than once, an impurity removal treatment is performed in an oxygen-containing atmosphere. The impurity removal treatment is a treatment for removing impurities in the metal oxide from the film. In the impurity removal treatment, it is preferred that hydrogen, carbon, nitrogen, etc. in the metal oxide be removed from the film. In addition, in the impurity removal treatment, it is preferred that oxygen be supplied to the metal oxide. Thus, the oxygen vacancies (V O ) and impurities. By using oxygen vacancies (V O ) and metal oxides with reduced impurities can improve the electrical characteristics and reliability of transistors.

[0063] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0064] When plasma treatment or microwave treatment is performed, the substrate temperature is preferably set to be above room temperature (e.g., 25° C.), above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C. In addition, the temperature of the heat treatment is preferably above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C.

[0065] In particular, by setting the temperature in the impurity removal process to a temperature below the maximum temperature in the manufacturing process of the transistor or semiconductor device, the impurity content of the metal oxide can be reduced without reducing the productivity, so it is preferred. For example, by setting the maximum temperature in the manufacture of a transistor or semiconductor device using a metal oxide of one embodiment of the present invention to 500° C. or less, preferably 450° C. or less, the productivity of the transistor or semiconductor device can be improved.

[0066] In addition, the impurity removal treatment is preferably performed at a temperature lower than the decomposition temperature of the first compound and the second compound. And, when the third compound is used, it is preferably performed at a temperature lower than the decomposition temperature of the third compound. In addition, the impurity removal treatment may also be performed at a temperature higher than 500° C. (for example, higher than 500° C. and less than 700° C.).

[0067] The impurity removal treatment can also be performed while irradiating light (e.g., ultraviolet light). Thus, the impurity removal can be promoted. As the light source, a laser, a mercury lamp, etc. can be cited. For example, oxygen free radicals are generated by light excitation, and reacted with hydrogen, carbon, or nitrogen, etc., thereby reducing impurities in the film and promoting crystallization. Compared with the case where there is no irradiation of light, it is sometimes easier to remove impurities even if the heating temperature is lowered when irradiating light.

[0068] In addition, light may be irradiated during deposition. For example, in the first step, light may be irradiated to the surface where the metal oxide is to be formed when the first compound is supplied into the chamber or when the oxidant is supplied into the chamber, or both. The same applies to the second and third steps.

[0069] Preferably, as a first cycle, the first step and the second step are each performed one or more times, and then the impurity removal treatment is performed in an oxygen-containing atmosphere, and this first cycle is repeated multiple times.

[0070] Alternatively, preferably, the first cycle is to perform the first step and the second step respectively one or more times and then perform impurity removal treatment in an oxygen-containing atmosphere, and the second cycle is to perform the first step and the second step respectively one or more times in an order different from the first cycle and then perform impurity removal treatment in an oxygen-containing atmosphere, and the first cycle and the second cycle are alternately repeated multiple times.

[0071] For example, in each of the first cycle and the second cycle, it is preferred that the impurity removal treatment is performed every time one or both of the first step and the second step, whichever is smaller, is performed within a range of 5 times or more and 10 times or less.

[0072] If the impurity removal treatment is performed only after the metal oxide is deposited, the impurities may not be removed sufficiently. By intermittently (intermittently) performing the impurity removal treatment during the deposition, the impurities in the metal oxide can be removed sufficiently.

[0073] <Metal Oxides> Metal oxides sometimes have lattice defects. Lattice defects include point defects such as atomic vacancies and singular atoms, line defects such as dislocations, surface defects such as grain boundaries, and body defects such as voids. In addition, the causes of lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.

[0074] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with more lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the lattice defects in the metal oxide used for the semiconductor layer of the transistor are small.

[0075] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the metal oxide, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even if no voltage is applied to the gate electrode). Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0076] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0077] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure.

[0078] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in metal oxides having an a-like structure is higher than that of metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0079] Therefore, the semiconductor layer of the transistor preferably uses a metal oxide having a crystalline portion, and more preferably uses a metal oxide with high crystallinity. For example, it is preferred to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0080] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, the mobility of the metal oxide used for the transistor can be increased. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region through which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0081] Here, it is preferred to use a metal oxide with high crystallinity as the metal oxide having a channel formation region. Furthermore, the crystal preferably has a crystal structure stacked with multiple layers (for example, a first layer, a second layer, and a third layer). In other words, the crystal has a layered crystal structure (also referred to as layered crystal, layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors, CAAC-OS (c-axis aligned crystalline oxide semiconductor), and the like.

[0082] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0083] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. The second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. The third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0084] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and deformation structures thereof.

[0085] Furthermore, it is preferred that the first to third layers are all composed of a metal element or a plurality of metal elements having the same valence, and oxygen. It is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0086] By adopting the above structure, the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0087] The metal oxide of one embodiment of the present invention preferably contains at least indium or zinc. In particular, it is preferred to contain indium and zinc. In addition, it is preferred to contain at least one metal element having the same valence as indium or zinc in addition to the above. The metal element is, for example, gallium, aluminum, tin, etc. In addition, it may also contain one or more selected from yttrium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, cobalt, etc.

[0088] Here, the case where the metal oxide is an In-M-Zn oxide containing indium (In), element M, and zinc (Zn) is considered. Note that element M is aluminum, gallium, tin, or the like. Other elements that can be used as element M are yttrium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, cobalt, and the like. Note that as element M, multiple elements of the above elements may be combined in some cases.

[0089] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO or IAGZO), etc. can be mentioned.

[0090] When the ratio of the number of atoms of indium to the total number of atoms of all metal elements in the metal oxide is increased, the field effect mobility of the transistor can be increased.

[0091] Note that the metal oxide may also replace the metal element with a large period number in one or more periodic tables. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in the periodic table in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large period number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As the metal element with a large period number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0092] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0093] In addition, when the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity and the diffusion of impurities in the metal oxide can be suppressed. Therefore, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0094] In addition, when the ratio of the number of atoms of the element M in the metal oxide relative to the sum of the number of atoms of all metal elements is increased, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be formed. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0095] In addition, when the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide is increased, the transistor can obtain a large on-state current and high frequency characteristics.

[0096] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0097] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. In the method for depositing the metal oxide according to one embodiment of the present invention, the ALD method is used, so that the metal oxide having the layered crystal structure can be easily formed.

[0098] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0099] The ALD method can deposit atoms layer by layer, so it has the effects of being able to deposit extremely thin, being able to deposit structures with high aspect ratios, being able to deposit in a manner with few defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Because plasma is used, deposition can be performed at lower temperatures, so the PEALD method is sometimes preferred. The precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS. Note that in the deposition method of a metal oxide in one embodiment of the present invention, the ALD method is used. Because the conditions of high substrate temperature during deposition and one or both of impurity removal treatment are used, the amount of carbon and chlorine in the film is sometimes less than when the ALD method is used without these conditions.

[0100] Unlike a deposition method in which particles released from a target material or the like are deposited, the ALD method is a deposition method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has high step coverage. In particular, the ALD method has high step coverage and good thickness uniformity, so it is suitable for use in cases where the surface of an opening with a high aspect ratio is to be covered. Note that the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other deposition methods such as sputtering or CVD methods with fast deposition rates. For example, the following method can be cited: depositing a first metal oxide by sputtering; and depositing a second metal oxide on the first metal oxide by the ALD method. For example, when the first metal oxide has a crystalline portion, crystal growth of the second metal oxide sometimes occurs with the crystalline portion as the core.

[0101] The ALD method can control the composition of the resulting film according to the amount of source gas introduced. For example, in the ALD method, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying and adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0102] <Transistor including metal oxide> Next, a case where a metal oxide (oxide semiconductor) is used for a transistor is described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer is referred to as an OS transistor, and a transistor using silicon for an active layer is referred to as a Si transistor.

[0103] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0104] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×1013 cm -3 Below, preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case where the carrier concentration of the oxide semiconductor film is reduced, the impurity concentration of the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0105] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0106] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0107] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0108] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0109] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0110] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0111] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0112] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0113] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0114] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is working.

[0115] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0116] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0117] <Impurities in Metal Oxides> Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0118] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×1019 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0119] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, which increases the carrier concentration and is easily converted to n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, it is further preferred that 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0120] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, thereby sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, an electron as a carrier is sometimes generated. In addition, sometimes electrons as carriers are generated because a portion of hydrogen is bonded to oxygen bonded to a metal atom. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm3 , and more preferably less than 5×10 18 atoms / cm 3 , preferably less than 1×10 18 atoms / cm 3 .

[0121] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0122] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0123] <Deposition method> Next, a method for depositing a metal oxide according to one embodiment of the present invention will be described. Hereinafter, a method for depositing a metal oxide using a deposition apparatus using an ALD method (hereinafter, also referred to as an ALD apparatus) will be described.

[0124] In a deposition apparatus utilizing the ALD method, a first source gas (sometimes referred to as a precursor, a precursor, a metal precursor) and a second source gas (sometimes referred to as a reactant, a reactant, an oxidant, a non-metal precursor) used for the reaction are alternately introduced into a chamber, and the introduction of such source gases is repeated, thereby performing deposition. Note that, for example, the introduced source gas can be switched by switching each switching valve (sometimes referred to as a high-speed valve). In addition, when introducing the source gas, an inert gas such as nitrogen (N2), argon (Ar) or helium (He) is used as a carrier gas, and they are introduced into the chamber together with the source gas. By using a carrier gas, even if the volatility or vapor pressure of the source gas is low, the source gas can be suppressed from being adsorbed inside the pipe and the valve, thereby allowing the source gas to be introduced into the chamber. In addition, the uniformity of the formed film is also improved, so it is preferred.

[0125] use Figures 1A to 1E An example of a method of depositing a metal oxide having a three-layered crystal structure by the ALD method, which is one embodiment of the present invention, will be described.

[0126] First, if Figure 1A As shown, as a first step, a precursor 11 a is introduced into the chamber and the precursor 11 a is adsorbed on the surface of the substrate 10 .

[0127] Here, if Figure 1A As shown, since the precursor 11a is adsorbed on the surface of the substrate 10, the self-stop mechanism of the surface chemical reaction works, and the precursor 11a is no longer adsorbed on the layer of the precursor 11a on the substrate 10. Note that the appropriate range of substrate temperature for the self-stop mechanism of the surface chemical reaction to work is also called the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor.

[0128] Next, as a second step, an inert gas (for example, argon, helium, or nitrogen) is introduced into the chamber to exhaust the remaining precursor 11a and reaction products from the chamber. The second step is also called purging.

[0129] In the second step, the remaining precursor and reaction product may be exhausted from the chamber by vacuum exhaust instead of introducing the inert gas into the chamber. Note that in this specification, vacuum exhaust means exhaust at a pressure at least lower than atmospheric pressure (reduced pressure state).

[0130] Then, as a third step, Figure 1B As shown, a reactant 12a (e.g., an oxidant) is introduced into the chamber to react with the precursor 11a adsorbed on the surface of the substrate 10, so that a part of the components in the precursor 11a is desorbed in a state where the metal element constituting the precursor 11a is adsorbed on the substrate 10. As a result, a layer of oxide 13a formed by oxidation of a part of the precursor 11a is formed on the surface of the substrate 10.

[0131] Examples of the oxidizing agent include ozone (O 3 ), oxygen (O 2 ), water (H 2 O), and plasma, radicals, and ions thereof.

[0132] When the plasma ALD method is performed, oxygen may be continuously supplied as an oxidant to generate plasma in the third step. Thus, in the third step, oxygen plasma is generated and used as the reactant 12a. In this case, in the steps other than the third step, the precursor 11a that does not react with oxygen heated to the above temperature may be used.

[0133] Next, as a fourth step, the remaining reactant 12a and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0134] Then, if Figure 1C As shown, a precursor 11b containing a metal element different from the precursor 11a is introduced, and the same process as the first step is performed to allow the precursor 11b to be adsorbed on the surface of the oxide 13a layer.

[0135] Here, if Figure 1CAs shown, since the precursor 11 b is adsorbed on the layer of the oxide 13 a , the self-stopping mechanism of the surface chemical reaction takes effect, and the precursor 11 b is no longer adsorbed on the layer of the precursor 11 b on the substrate 10 .

[0136] Next, similarly to the second step, the remaining precursor 11 b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0137] Then, if Figure 1D As shown, the reactant 12b is introduced into the chamber, and the same process as the third step is performed. As a result, a layer of oxide 13b formed by oxidation of a part of the precursor 11b is formed on the layer of oxide 13a.

[0138] The reactant 12b may be the same material as the reactant 12a or a different material.

[0139] Next, similarly to the fourth step, the remaining reactant 12b and reaction products are exhausted from the chamber by introducing an inert gas or performing vacuum exhaust.

[0140] Then, by similarly performing the first step to the fourth step, a layer of oxide 13c is formed on the layer of oxide 13b. When forming the layer of oxide 13c, a compound containing a metal element different from the precursor 11a and the precursor 11b is used as a precursor. The reactant may be the same material as one or both of the reactant 12a and the reactant 12b, or may be a material different from both of the reactant 12a and the reactant 12b.

[0141] In this way, by repeatedly performing the steps of forming oxide 13a to oxide 13c, a metal oxide having a layered crystal structure in which the stacked structure 14 of oxide 13a to oxide 13c is repeated can be formed. Figure 1E That is, the first step to the fourth step can be used as a set (also referred to as one cycle) to form an oxide layer, and by repeatedly performing this set, a layered crystal structure in which a plurality of oxide layers are stacked can be formed.

[0142] The thickness of the metal oxide having a layered crystal structure is preferably 1 nm or more and less than 100 nm, and more preferably 3 nm or more and less than 20 nm.

[0143] When forming a metal oxide having a layered crystal structure, especially a metal oxide having a CAAC structure, it is preferred to perform the process shown in FIG. 1 while heating the substrate. The substrate temperature is preferably set to be above 200° C. and below 600° C., and more preferably to be above 300° C. and below 450° C. In addition, the substrate temperature is preferably a temperature lower than the decomposition temperature of any precursor used. Thus, in deposition using the ALD method, the various precursors used can be adsorbed onto an object (e.g., a substrate) without decomposing them.

[0144] By performing the above-mentioned deposition while heating the substrate within such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be removed from the metal oxide in each of the first step to the fourth step. For example, the carbon in the metal oxide can be released as CO2 and CO. In addition, for example, the hydrogen in the metal oxide can be released as H2O. Moreover, while the above-mentioned impurities are being removed, the metal atoms and oxygen atoms are rearranged, and the layers of each oxide can be arranged with high order. Therefore, a metal oxide with a layered crystal structure with high crystallinity, especially a metal oxide with a CAAC structure, can be formed.

[0145] Note that Figure 1A In the example, the structure in which the precursor 11a is adsorbed on the substrate 10 is illustrated, but the invention is not limited thereto. For example, an insulating film (an insulating film containing one or more of oxygen, nitrogen, silicon, aluminum, hafnium, etc.) or a conductive film (a conductive film containing one or more of tungsten, tantalum, molybdenum, zirconium, aluminum, titanium, etc.) may be provided on the substrate 10 to adsorb the precursor 11a. Alternatively, the precursor 11a may be adsorbed on a structure formed by the insulating film and the conductive film of the substrate 10.

[0146] In order to perform deposition while heating the substrate within the above temperature range, the decomposition temperature of the precursor used for the above deposition is preferably not too low. On the other hand, when the decomposition temperature is too high, it is difficult to handle the precursor and the substrate temperature during deposition needs to be very high, so it is not preferred. For example, the decomposition temperature of the precursor is preferably higher than 200°C and lower than 700°C, more preferably higher than 300°C and lower than 650°C, and further preferably higher than 400°C and lower than 600°C.

[0147] Since the inorganic precursor contains less impurities such as hydrogen and carbon, it is possible to suppress the increase in the impurity concentration in the deposited metal oxide. On the other hand, the decomposition temperature of the inorganic precursor tends to be higher than that of the organic precursor.

[0148] Therefore, in a method for depositing a metal oxide according to one embodiment of the present invention, an organic precursor having a decomposition temperature within the above range is used, deposition is performed while heating the substrate, and an impurity removal treatment is performed, thereby suppressing an increase in impurity concentration in the deposited metal oxide.

[0149] There is no particular restriction on the frequency of performing the impurity removal treatment. It is easier to remove impurities at a higher frequency, so it is preferred, but the productivity may decrease. At a lower frequency, the deposition process time of the metal oxide can be shortened, so it is preferred, but the impurities may not be fully removed. For example, it is preferred to repeat the process of forming oxides 13a to 13c, and perform the impurity removal treatment each time a plurality of oxide layers are formed. For example, it is also possible to perform the impurity removal treatment each time any layer of oxides 13a to 13c is formed, but it is preferred to perform the impurity removal treatment each time a plurality of oxide layers are formed or each time a plurality of stacked structures 14 are formed, because the process can be simplified.

[0150] For example, the impurity removal treatment may be performed each time n layers of oxide are formed (n is an integer of 1 to 100, preferably an integer of 2 to 50, and more preferably an integer of 5 to 30). For example, the metal oxide may be formed by repeating the following steps: forming oxides 13a, 13b, 13c, 13a, 13b in sequence and performing the impurity removal treatment; forming oxides 13c, 13a, 13b, 13c, 13a in sequence and performing the impurity removal treatment; forming oxides 13b, 13c, 13a, 13b, 13c, 13a in sequence and performing the impurity removal treatment; and forming oxides 13b, 13c, 13a, 13b, 13c in sequence and performing the impurity removal treatment.

[0151] Alternatively, for example, the impurity removal process may be performed each time m layers (m is an integer of 1 to 50, preferably an integer of 2 to 30, and more preferably an integer of 5 to 10) of the stacked structure 14 are formed.

[0152] As described above, examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment. In addition, the impurity removal treatment may be performed while irradiating light.

[0153] The chamber for performing the impurity removal process may be the same chamber as the chamber for performing the first to fourth steps, or may be a different chamber. That is, the chamber for deposition and the chamber for the impurity removal process may be the same or different.

[0154] When plasma treatment or microwave treatment is performed, the substrate temperature is preferably set to be above room temperature (e.g., 25° C.), above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C. In addition, the temperature of the heat treatment is preferably above 100° C., above 200° C., above 300° C., or above 400° C. and below 500° C. or below 450° C. In particular, by setting the temperature in the impurity removal treatment to a temperature below the highest temperature in the manufacturing process of the transistor or semiconductor device, it is possible to reduce the impurity content of the metal oxide without reducing productivity, which is preferred.

[0155] Note that when oxygen plasma is used in the third step, the plasma treatment can be used as an impurity removal treatment by extending the treatment time of the third step. For example, the treatment time of one of the multiple third steps can be made longer than the other steps to make it also serve as an impurity removal treatment.

[0156] Here, microwave treatment refers to, for example, treatment using a device including a power source for generating high-density plasma using microwaves. In addition, in this specification, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave treatment is also referred to as microwave-excited high-density plasma treatment.

[0157] Microwave treatment, for example, preferably uses a microwave processing device including a power supply that generates high-density plasma with microwaves. Here, the frequency of the microwave processing device is preferably set to more than 300MHz and less than 300GHz, more preferably more than 2.4GHz and less than 2.5GHz, for example, it can be 2.45GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably more than 1000W and less than 10000W, preferably more than 2000W and less than 5000W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0158] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. In addition, the treatment temperature is preferably room temperature (25° C.) or more and 750° C. or less, more preferably 300° C. or more and 500° C. or less, and may be 400° C. or more and 450° C. or less.

[0159] In addition, heat treatment may be continuously performed after microwave treatment or oxygen plasma treatment without exposure to the outside air. The heat treatment temperature is preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and further preferably 400° C. to 450° C.

[0160] For example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%.

[0161] Heat treatment is carried out in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen and oxygen, the ratio of oxygen gas is preferably set to about 20%. Heat treatment can also be carried out under reduced pressure. Alternatively, it can be carried out in a nitrogen or inert gas atmosphere, and then heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated. Heat treatment can be carried out in an atmosphere of ultra-dry air (air with a water content of less than 20ppm, preferably less than 1ppm, and more preferably less than 10ppb).

[0162] The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the metal oxide as much as possible.

[0163] By performing such heat treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Moreover, while removing the above impurities, metal atoms and oxygen atoms are rearranged, thereby improving crystallinity. Thus, a metal oxide with a layered crystal structure having high crystallinity can be formed, especially a metal oxide with the above CAAC structure.

[0164] Furthermore, it is preferred to perform heat treatment after the metal oxide is deposited (after forming all of the stacked structure 14 of the specified number of layers and before forming films of other materials or other compositions). In particular, it is preferred to perform heat treatment continuously without exposure to the outside air after deposition using the above-mentioned ALD method. The heat treatment is preferably performed at a temperature of 100°C or more and 500°C or less, more preferably 200°C or more and 500°C or less, further preferably 250°C or more and 500°C or less, further preferably 300°C or more and 500°C or less, further preferably 350°C or more and 450°C or less, further preferably 400°C or more and 450°C or less. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may also be performed under reduced pressure. Alternatively, it may be performed in a nitrogen gas or inert gas atmosphere, and then heat treated in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more to compensate for the oxygen that has been separated.

[0165] By performing such heat treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Moreover, while removing the above impurities, metal atoms and oxygen atoms are rearranged, thereby improving crystallinity. Thus, a metal oxide with a layered crystal structure having high crystallinity can be formed, especially a metal oxide with the above CAAC structure.

[0166] Alternatively, plasma treatment or microwave treatment may be performed after the metal oxide is deposited.

[0167] Note that in FIG. 1 , a structure in which the stacked structure 14 of oxides 13a to 13c is repeated is illustrated, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more layers of oxides are repeatedly formed may be used. In addition, in FIG. 1 , the order of oxide 13a, oxide 13b, and oxide 13c is repeatedly stacked without changing, but this is not limited to this. For example, the order of oxide 13a, oxide 13b, and oxide 13c may be changed each time the stacking is performed. In addition, the composition of oxide 13a, oxide 13b, and oxide 13c may be changed in the middle of the film. In addition, in FIG. 1 , layers of different oxides are arranged adjacent to each other, such as oxide 13a, oxide 13b, and oxide 13c, but this is not limited to this. For example, layers of the same oxide may be arranged continuously, such as oxide 13a, oxide 13a, oxide 13b, oxide 13b, oxide 13c, and oxide 13c.

[0168] In addition, in the following description of this specification, when ozone, oxygen, and water are used as reactants or oxidants, unless otherwise specified, the state includes plasma, radical, and ion states, and is not limited to gas and molecular states. When deposition is performed using an oxidant in a plasma, radical, or ion state, a radical ALD apparatus or a plasma ALD apparatus described below may be used.

[0169] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferred to allow the precursor to fully react with the oxidant. For example, a longer pulse time for introducing the oxidant can be set. Alternatively, the oxidant can be introduced multiple times. When the oxidant is introduced multiple times, the same type of oxidant can be introduced, and different types of oxidants can be introduced. For example, after water is introduced into the chamber as the first oxidant, vacuum exhaust can be performed, and ozone or oxygen that does not contain hydrogen can be introduced into the chamber as the second oxidant, and vacuum exhaust can be performed.

[0170] Note that in the above description, an example is shown in which the second source gas is introduced into the chamber after the first source gas is introduced into the chamber, but the present invention is not limited to this, and the first source gas may be introduced into the chamber after the second source gas is introduced into the chamber. In other words, deposition may be performed by first performing the third step and the fourth step, then performing the first step, the second step, the third step, and the fourth step, and then repeatedly performing the first step to the fourth step. Furthermore, deposition may be performed by repeatedly performing the third step and the fourth step a plurality of times, and then repeatedly performing the first step to the fourth step.

[0171] In this way, by performing the third step and the fourth step once or more before the first step, the deposition atmosphere in the chamber can be controlled, so it is preferred. For example, by introducing O3 and O2 as oxidants in the third step, the atmosphere in the chamber can be set to an oxygen atmosphere. When the atmosphere in the chamber is set to an oxygen atmosphere and deposition is performed, the oxygen concentration in the formed film can be increased, so it is preferred. In addition, oxygen can be supplied to the insulator and oxide of the substrate of the film. The semiconductor device formed by using this method can have good characteristics and obtain high reliability. In addition, for example, by introducing water as an oxidant in the third step, a hydrophilic group can be formed on the formed surface. Thereby, the adsorption of the precursor can be further improved.

[0172] In addition, the introduction of the second source gas in the third step and the vacuum exhaust or the introduction of the inert gas in the fourth step may be repeated multiple times after the first step and the second step. That is, the third step and the fourth step may be repeated in the order of the first step, the second step, the third step, the fourth step, the third step, and the fourth step, and then the first step and the second step may be performed.

[0173] For example, O3 and O2 may be introduced as oxidants in the third step and an inert gas may be introduced in the fourth step, and these steps may be repeated multiple times. In addition, when the third step and the fourth step are repeated, the introduction of the same type of source gas is not necessarily repeated. For example, H2O may be used as an oxidant in the first third step, and O3 may be used as an oxidant in the second and subsequent third steps.

[0174] In this way, by repeatedly introducing the oxidant and the inert gas (or vacuum exhaust) in a short period of time in the chamber, it is possible to further reliably remove the remaining hydrogen atoms, carbon atoms, etc. from the precursor adsorbed on the substrate surface and discharge them outside the chamber. In addition, by increasing the number of oxidants to two, more remaining hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being introduced into the film during deposition, water, hydrogen, etc. contained in the formed film can be reduced.

[0175] By adopting this method, it is possible to form a TDS analysis in which the amount of water molecules released is 1.0×10 13 molecule / cm 2 Above and 1.0×10 16 molecule / cm 2 Below, preferably 1.0×10 13 molecule / cm 2 Above and 3.0×10 15 molecule / cm 2 The following membrane.

[0176] The ALD method is a deposition method that uses thermal energy to react a precursor and a reactant. The temperature required for the reaction of the precursor and the reactant is determined according to their temperature characteristics, vapor pressure, decomposition temperature, etc., and is set to be 100°C or more and 600°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more and 600°C or less.

[0177] Furthermore, an ALD method in which the above-mentioned precursor and reactant react and the reactant excited by plasma is introduced into the chamber as a third source gas for processing is sometimes referred to as a plasma ALD method. In this case, the introduction portion of the third source gas is provided with a plasma generating device. When generating plasma, an inductively coupled plasma (ICP) can be used. On the other hand, an ALD method in which the precursor and reactant react using thermal energy is sometimes referred to as a thermal ALD method.

[0178] In the plasma ALD method, the reactant excited by the plasma in the third step is introduced for deposition. Alternatively, deposition is performed by repeatedly performing the first step to the fourth step while introducing the reactant excited by the plasma (the second reactant). In this case, the reactant introduced in the third step is referred to as the first reactant. In the plasma ALD method, the second reactant used for the third source gas can use the same material as the above-mentioned oxidant. That is, ozone, oxygen and water excited by the plasma can be used as the second reactant. In addition, as the second reactant, a nitriding agent can also be used in addition to the oxidant. Nitrogen (N2) or ammonia (NH3) can be used as the nitriding agent. In addition, a mixed gas of nitrogen (N2) and hydrogen (H2) can be used as a nitriding agent. For example, a mixed gas of 5% nitrogen (N2) and 95% hydrogen (H2) can be used as a nitriding agent. By depositing while introducing nitrogen or ammonia excited by plasma, a nitride film such as a metal nitride film can be formed.

[0179] In addition, argon (Ar), helium (He) or nitrogen (N2) may be used as a carrier gas for the second reactant. By using a carrier gas such as argon, helium or nitrogen, it is easy to discharge the plasma and easily generate the second reactant excited by the plasma, so it is preferred. Note that when an oxide film such as a metal oxide film is formed using a plasma ALD method and nitrogen is used as a carrier gas, nitrogen may be mixed into the film and the desired film quality may not be obtained. In this case, it is preferred to use argon or helium as a carrier gas.

[0180] By utilizing the ALD method, a very thin film can be deposited with a uniform thickness, and a high surface coverage is achieved even on a surface having irregularities.

[0181] By performing deposition using the plasma ALD method, deposition can be performed at a lower temperature than the thermal ALD method. For example, the plasma ALD method can sometimes perform deposition even at 100° C. or less without reducing the deposition rate.

[0182] In the case of performing the plasma ALD method, plasma damage can be suppressed by generating plasma in a state where a plasma source such as inductively coupled plasma (ICP) or electron cyclotron resonance plasma (ECR) is kept away from the substrate.

[0183] <Atomic Arrangement in Metal Oxide Crystals> Here, refer to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D This chapter describes the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide. Figure 2B , Figure 2D , Figure 3B and Figure 3DIn the diagram, atoms are represented by spheres (circles), and the bonds between metal atoms and oxygen atoms are represented by lines. Figure 2B , Figure 2D , Figure 3B and Figure 3D In the figure, the c-axis direction (c-axis) in the crystal structure of In-M-Zn oxide is indicated by the arrow in the figure. In addition, the ab plane direction in the crystal structure of In-M-Zn oxide is the same as that in Figure 2B , Figure 2D , Figure 3B and Figure 3D The direction is perpendicular to the c-axis direction indicated by the arrow.

[0184] Figure 2A is a diagram showing an oxide 60 including an In-M-Zn oxide formed on a structure 50. Here, a structure refers to a constituent element of a semiconductor device such as a transistor. The structure 50 includes a conductor such as a substrate, a gate electrode, a source electrode, and a drain electrode; an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film; and a semiconductor such as a metal oxide or silicon. Figure 2A The case where the deposition surface of the structure 50 is arranged in parallel with a substrate (not shown) is shown.

[0185] Figure 2B It is shown Figure 2A This is an enlarged view of the atomic arrangement in the crystal of a portion of region 53 of oxide 60. Figure 2A and Figure 2B The composition of the oxide 60 shown is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe2O4 type structure. In addition, the element M is a +3 valent metal element.

[0186] like Figure 2B As shown, the crystals included in the oxide 60 are repeatedly stacked in sequence, including a layer 21 containing indium (In) and oxygen, a layer 31 containing element M and oxygen, and a layer 41 containing zinc (Zn) and oxygen. The layers 21, 31, and 41 are arranged in a manner parallel or substantially parallel to the deposited surface of the structure 50. In other words, the ab plane of the oxide 60 is parallel or substantially parallel to the deposited surface of the structure 50, and the c-axis of the oxide 60 is parallel or substantially parallel to the normal direction of the deposited surface of the structure 50.

[0187] like Figure 2B As shown, the layers 21, 31 and 41 of the crystal are all composed of one metal element and oxygen, and can be arranged with high crystallinity to improve the mobility of the metal oxide.

[0188] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:1:1 [atomic ratio] is not limited to Figure 2BThe structure shown. The stacking order of layer 21, layer 31, and layer 41 may also be changed. For example, layer 21, layer 41, and layer 31 may be stacked repeatedly in sequence. Alternatively, layer 21, layer 31, layer 41, layer 21, layer 41, and layer 31 may be stacked repeatedly in sequence. In addition, a portion of the element M in layer 31 may be substituted with zinc, and a portion of the zinc in layer 41 may be substituted with element M.

[0189] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] is shown, but its composition formula is In (1+α) M (1-α) O3(ZnO) m (α is a real number greater than 0 and less than 1, and m is a positive number) can also have a layered crystal structure. Figure 2C and Figure 2D An In-M-Zn oxide having a composition of In:M:Zn=1:3:4 [atomic number ratio] is shown.

[0190] Figure 2C 1 is a diagram showing an oxide 62 including an In-M-Zn oxide formed on the structure 50 . Figure 2D It is shown Figure 2C An enlarged view of the atomic arrangement in the crystal of a portion of region 54 of oxide 62 .

[0191] like Figure 2D As shown, the crystal included in the oxide 62 has a layer 23 containing indium (In), element M and oxygen, a layer 41 containing zinc (Zn) and oxygen, and a layer 31 containing element M and oxygen. In the oxide 62, as a plurality of layers, the layer 23, the layer 41, the layer 31, and the layer 41 are repeatedly stacked in sequence. The layer 23, the layer 31, and the layer 41 are arranged in a manner parallel to or substantially parallel to the deposited surface of the structure 50. In other words, the ab plane of the oxide 62 is parallel to or substantially parallel to the deposited surface of the structure 50, and the c axis of the oxide 62 is parallel to or substantially parallel to the normal direction of the deposited surface of the structure 50.

[0192] Note that the structure of the In-M-Zn oxide with In:M:Zn=1:3:4 [atomic ratio] is not limited to Figure 2D The structure shown may be changed within the range of In:M:Zn=1:3:4 [atomic ratio]. The stacking order of layer 23, layer 31, and layer 41 may be changed. In addition, a part of the element M in layer 31 may be replaced by zinc, and a part of the zinc in layer 41 may be replaced by element M. In addition, layer 21 or layer 31 may be formed instead of layer 23.

[0193] In addition, if Figure 3AAs shown, a stacked structure in which an oxide 62 is formed on the structure 50 and an oxide 60 is formed thereon may also be adopted. Figure 3B It is shown Figure 3A An enlarged view of the atomic arrangement in the crystal of region 56 of oxide 62 and a portion of oxide 60 .

[0194] As described above, the oxide 62 is an In-M-Zn oxide with an atomic ratio of In:M:Zn=1:3:4, and the oxide 60 is an In-M-Zn oxide with an atomic ratio of In:M:Zn=1:1:1. That is, Figure 3A The oxide shown is an oxide film in which the atomic number ratio changes in the middle of the film. Figure 3B As shown, when the oxide 62 has a layered crystal structure, the crystallinity of the oxide 60 on the oxide 62 can be improved.

[0195] Note that the structures of oxide 62 and oxide 60 are not limited to Figure 3B As described above, the structure of oxide 62 and oxide 60 may be changed. Figure 3B In the embodiment, the layer 21 is arranged at the boundary between the oxide 62 and the oxide 60 , but the present invention is not limited to this. For example, the layer 23 may be formed at the boundary between the oxide 62 and the oxide 60 .

[0196] As described above, the ALD method can deposit structures with high aspect ratios and also deposit high coverage on the sides of the structure. By utilizing the ALD method, crystalline metal oxides having a CAAC structure or the like can be easily formed regardless of the direction of the deposited surface. For example, even if the structure has a convex shape or a concave shape, metal oxides can be formed with high coverage on the top, bottom, side, and inclined surfaces of the structure. That is, a metal oxide having a substantially constant thickness in the normal direction can be formed on each deposited surface. In each of the metal oxides formed on the top, bottom, side, and inclined surfaces of the structure, the ratio of the minimum thickness to the maximum thickness can be set to be greater than 0.5 and less than 1, preferably greater than 0.7 and less than 1, and more preferably greater than 0.9 and less than 1. At this time, when the metal oxide has a crystalline structure, its c-axis is oriented in a direction substantially parallel to the normal direction of each deposited surface. In other words, the c-axis is oriented in a direction perpendicular to each deposited surface.

[0197] Here, Figure 3C The case where the deposition surface of the structure 50 is arranged perpendicular to the substrate (not shown) and an oxide 64 is formed on the surface of the structure 50 is shown. Figure 3D yes Figure 3C An enlarged view of region 58 of a portion of oxide 64 in FIG. Figure 3DThe case where a layer 21 containing indium (In), a layer 31 containing element M, and a layer 41 containing zinc (Zn) are stacked on the side surface of the structure 50 relative to the deposited surface is shown. The layer 21 containing indium is arranged parallel or approximately parallel to the deposited surface of the structure 50, the layer 31 containing element M is arranged thereon in parallel or approximately parallel to the deposited surface of the structure 50, and the layer 41 containing zinc is arranged thereon in parallel or approximately parallel to the deposited surface of the structure 50. That is, the ab plane of the oxide 64 is parallel or approximately parallel to the deposited surface of the structure 50, and the c axis of the oxide 64 is parallel or approximately parallel to the normal direction of the deposited surface of the structure 50. Note that in Figure 3C and Figure 3D , an example of an In-M-Zn oxide with In:M:Zn=1:1:1 [atomic ratio] is shown, but oxides with different atomic ratios can also be formed in the same manner on the surface of the structure 50 whose deposited surface is configured in a manner perpendicular to the substrate.

[0198] In the above, examples of metal oxides of In:M:Zn=1:1:1 [atomic ratio] and In:M:Zn=1:3:4 [atomic ratio] are shown, but the present invention is not limited thereto.

[0199] Below, refer to Figure 4A , Figure 4B and Figure 4C The preferred range of the atomic ratio of indium, element M, and zinc contained in the metal oxide that can be used as the oxide shown in one embodiment of the present invention is described. Note that, Figure 4A , Figure 4B and Figure 4C The atomic ratio of oxygen is not shown. In addition, each of the atomic ratios of indium, element M, and zinc contained in the metal oxide is referred to as [In], [M], and [Zn], respectively.

[0200] exist Figure 4A , Figure 4B and Figure 4C In the figure, the dotted lines represent the atomic number ratio line (-1≤α≤1) of [In]:[M]:[Zn]=(1+α):(1-α):1, the atomic number ratio line of [In]:[M]:[Zn]=(1+α):(1-α):2, the atomic number ratio line of [In]:[M]:[Zn]=(1+α):(1-α):3, the atomic number ratio line of [In]:[M]:[Zn]=(1+α):(1-α):4 and the atomic number ratio line of [In]:[M]:[Zn]=(1+α):(1-α):5.

[0201] In addition, the dotted lines represent the atomic number ratio line of [In]:[M]:[Zn]=5:1:β (β≥0), the atomic number ratio line of [In]:[M]:[Zn]=2:1:β, the atomic number ratio line of [In]:[M]:[Zn]=1:1:β, the atomic number ratio line of [In]:[M]:[Zn]=1:2:β, the atomic number ratio line of [In]:[M]:[Zn]=1:3:β and the atomic number ratio line of [In]:[M]:[Zn]=1:4:β.

[0202] in addition, Figure 4A , Figure 4B and Figure 4C Metal oxides having an atomic ratio of [In]:[M]:[Zn]=0:2:1 or values ​​close thereto tend to have a spinel crystal structure.

[0203] In addition, sometimes multiple phases coexist in metal oxides (for example, two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is close to [In]: [M]: [Zn] = 0:2:1, two phases of spinel crystal structure and layered crystal structure are easy to coexist. When the atomic number ratio is close to [In]: [M]: [Zn] = 1:0:0, two phases of bixbyite crystal structure and layered crystal structure are easy to coexist. When multiple phases coexist in metal oxides, grain boundaries may be formed between different crystal structures.

[0204] Figure 4A The region A shown shows an example of a preferred range of the atomic number ratio of indium, element M, and zinc contained in the metal oxide.

[0205] By increasing the indium content, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, the carrier mobility of the metal oxide with a high indium content is higher than that of the metal oxide with a low indium content.

[0206] On the other hand, when the indium content and zinc content of the metal oxide decrease, the carrier mobility decreases. Therefore, when the atomic number ratio is [In]:[M]:[Zn]=0:1:0 or its approximate value (for example, Figure 4C Note that region C includes a region that is prone to the spinel crystal structure, so it is preferred to avoid the region that is prone to the spinel crystal structure.

[0207] For example, the metal oxide used for the channel formation region and the low resistance region preferably has a high carrier mobility. Figure 4AThe ratio of the number of atoms in the region A represented by the channel formation region. The metal oxide used in the channel formation region and the low resistance region can be set to, for example, In:Ga:Zn=4:2:3 to 4.1 or a value in the vicinity thereof. Alternatively, for example, it can be set to, for example, In:Ga:Zn=1:1:1 or a value in the vicinity thereof. On the other hand, when the metal oxide is provided in a manner surrounding the channel formation region and the low resistance region, it is preferred that the metal oxide has a high insulating property. Figure 4C The ratio of the number of atoms in the region C represented by the region C. The metal oxide provided in a manner surrounding the channel formation region and the low resistance region may be set to, for example, In:Ga:Zn=1:3:4 or its vicinity or In:Ga:Zn=1:3:2 or its vicinity. Alternatively, the metal oxide provided in a manner surrounding the channel formation region and the low resistance region may be the same metal oxide as that used for the channel formation region and the low resistance region.

[0208] Especially in Figure 4B In the region B shown, a metal oxide having higher carrier mobility and reliability than that in the region A is obtained.

[0209] Region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and values ​​near them. Nearby values ​​include, for example, [In]:[M]:[Zn]=5:3:4. In addition, region B includes [In]:[M]:[Zn]=5:1:6 and values ​​near it and [In]:[M]:[Zn]=5:1:7 and values ​​near it. Region B includes [In]:[M]:[Zn]=1:1:1 and values ​​near it.

[0210] As described above, the conductivity of the metal oxide greatly varies depending on the atomic number ratio. As described above, by depositing the metal oxide using the ALD method, a metal oxide having a layered crystal structure according to each atomic number ratio can be deposited. Therefore, by using the ALD method, a metal oxide corresponding to the required characteristics can be deposited.

[0211] Next, refer to FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6C Show Figure 2A and Figure 2B The detailed formation method of the oxide 60 including the In-M-Zn oxide is shown.

[0212] First, if Figure 5A As shown, a source gas including a precursor containing indium is introduced into the chamber so that the precursor is adsorbed on the surface of the structure 50 .

[0213] Here, the source gas containing the precursor includes a carrier gas such as argon, helium, or nitrogen in addition to the precursor.

[0214] As precursors containing indium, for example, trimethylindium, triethylindium, ethyldimethylindium, tri(1-methylethyl)indium, tri(2,2,6,6-tetramethyl-3,5-heptanedioate)indium, cyclopentadienylindium, iridium(III) acetylacetonate, (diethylphosphine)dimethylindium, dimethylindium chloride, dimethylindium bromide, dimethyl(2-propanolate)indium, indium trichloride, indium tribromide, and indium triiodide can be used.

[0215] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursor, reaction product, etc. from the chamber.

[0216] Then, if Figure 5B As shown, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are desorbed while indium is adsorbed on the substrate, thereby forming a layer 21 in which indium and oxygen are bonded.

[0217] As the oxidizing agent, ozone, oxygen, water or the like can be used.

[0218] Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants, reaction products, etc. from the chamber.

[0219] Then, if Figure 5C As shown, a source gas including a precursor containing an element M is introduced into the chamber so that the precursor is adsorbed on the layer 21. Here, as the element M, gallium, aluminum or tin is preferably used.

[0220] As a precursor containing gallium, for example, trimethylgallium, triethylgallium, triphenylgallium, diethyl(3-methyl-2,4-cyclopropadien-1-yl)gallium, [4-(1,1-dimethyl)phenyl]dimethylgallium, dimethyl(4-methylphenyl)gallium, dimethylphenylgallium, methyldiphenylgallium, ethyldimethylgallium, dimethylmethylenegallium, gallium(III) acetylacetonate, tri(2,2,6,6-tetramethyl-3,5-heptanedioate)gallium, dimethyl(2-methyl-2-propanol)gallium, methoxydimethylgallium, hydroxydimethylgallium, (methylthiolate)dimethylgallium, dimethylgallium chloride, diethylgallium chloride, dipropylgallium chloride, dimethylgallium bromide, diethylgallium bromide, dimethylgallium iodide, bis(2,2-dimethylpropyl)gallium chloride, gallium trichloride, gallium tribromide and gallium triiodide.

[0221] Examples of the precursor containing aluminum include trimethylaluminum, triethylaluminum, dimethylaluminum chloride, dimethylaluminum dichloro, dimethylaluminum bromide, dimethylaluminum iodide, aluminum acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedioate)aluminum, dimethylaluminum chloride, diethylaluminum chloride, aluminum trichloride, aluminum tribromide, and aluminum triiodide.

[0222] Examples of the precursor containing tin include tetramethyltin, tetraethyltin, tetravinyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tributylvinyltin, tributylphenyltin, trimethyltin chloride, triethyltin chloride, tin tetrachloride, tin tetrabromide, and tin tetraiodide.

[0223] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursor, reaction product, etc. from the chamber.

[0224] Then, if Figure 5D As shown, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed on the substrate, thereby forming a layer 31 formed by bonding the element M and oxygen. At this time, a part of the oxygen adsorbed on the layer 31 sometimes constitutes a layer 41 described later.

[0225] Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants, reaction products, etc. from the chamber.

[0226] Then, if Fig. 6A As shown, a source gas including a precursor containing zinc is introduced into the chamber, and the precursor is adsorbed on the layer 31. At this time, a part of the layer 41 in which zinc and oxygen are bonded may be formed.

[0227] Examples of the precursor containing zinc include dimethylzinc, diethylzinc, bis(1-methylethyl)zinc, bis(1,1-dimethylethyl)zinc, dibutylzinc, divinylzinc, dicyclohexylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioate)zinc, zinc dichloride, chloromethylzinc, zinc dibromide, bromomethylzinc and zinc diiodide.

[0228] Next, the introduction of the source gas is stopped, and the chamber is purged to exhaust the remaining precursor, reaction product, etc. from the chamber.

[0229] Then, if Figure 6B As shown, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer 41 in which zinc and oxygen are bonded.

[0230] Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge the remaining reactants, reaction products, etc. from the chamber.

[0231] Next, layer 21 ( Figure 6C ). By repeating the above steps, an oxide 60 can be formed on the substrate or the structure.

[0232] Note that some of the above precursors contain one or both of carbon and chlorine in addition to the metal element. Sometimes a film formed using a precursor containing carbon contains carbon. Also, sometimes a film formed using a precursor containing halogens such as chlorine contains halogens such as chlorine.

[0233] Preferably, the substrate is heated while FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6C For example, the substrate temperature is set to be 200°C or higher and 600°C or lower, preferably 300°C or higher and lower than the decomposition temperature of the precursor. By performing the above deposition while heating the substrate within such a temperature range, FIG. 5A to FIG. 6C In each process, impurities such as hydrogen or carbon contained in the precursor or reactant can be removed from the metal oxide. For example, the carbon in the metal oxide can be released as CO2 and CO, and the hydrogen in the metal oxide can be released as H2O. Moreover, while the above impurities are removed, the metal atoms and oxygen atoms are rearranged, and the layers of each oxide can be arranged with high order. Therefore, a metal oxide having a crystalline part can be formed. In addition, a metal oxide with a layered crystal structure with high crystallinity, such as a metal oxide with a CAAC structure, can be formed.

[0234] The impurity removal treatment is preferably performed intermittently during the deposition of the oxide 60. For example, the impurity removal treatment is performed every time a three-layer structure of the layer 21, the layer 31, and the layer 41 is formed n times (n is an integer of 1 to 50, preferably an integer of 2 to 30, and more preferably an integer of 5 to 10). In addition, the impurity removal treatment is preferably performed after the oxide 60 is deposited.

[0235] By performing an impurity removal treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, the carbon in the metal oxide can be released as CO2 and CO, and the hydrogen in the metal oxide can be released as H2O. Moreover, while removing the above impurities, the metal atoms and oxygen atoms are rearranged, so that the crystallinity can be improved. Therefore, a metal oxide having a crystalline portion can be formed. In addition, a metal oxide with a layered crystal structure with high crystallinity can be formed, especially a metal oxide with the above CAAC structure.

[0236] As described above, by forming the oxide 60 by the ALD method, a metal oxide having a CAAC structure in which the c-axis is oriented substantially parallel to the normal direction of the deposition surface can be formed.

[0237] Notice, FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6CAlthough an example is shown in which layer 21 is formed as a layer containing indium, layer 31 is formed as a layer containing element M thereon, and layer 41 is formed as a layer containing zinc thereon, the present embodiment is not limited thereto, and one of layer 31 and layer 41 may be formed, layer 21 may be formed thereon, and the other of layer 31 and layer 41 may be formed thereon. Alternatively, one of layer 31 and layer 41 may be formed, the other of layer 31 and layer 41 may be formed thereon, and layer 21 may be formed thereon.

[0238] When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above-mentioned layers 21, 31, and 41 may be formed appropriately according to the atomic ratio. Fig. 6A The formation of the layer 41 may be repeated multiple times before and after the formation of the layer 31 shown, so that a stack of the layer 31 and the layer 41 having a desired number of atoms, number of layers, and thickness may be formed between the two layers 21 .

[0239] <Deposition device> Here, as an example of an apparatus that can perform deposition using the ALD method, refer to Figure 7 , Fig. 8A and Figure 8B The structure of the deposition apparatus 4000 will be described. Figure 7 is a schematic diagram of a multi-chamber deposition apparatus 4000, Fig. 8A and Figure 8B is a cross-sectional view of an ALD device that can be used in the deposition apparatus 4000.

[0240] Figure 7 The deposition device 4000 shown includes a loading and unloading chamber 4002, a loading and unloading chamber 4004, a transfer chamber 4006, a deposition chamber 4008, a deposition chamber 4009, a processing chamber 4011, and a transfer arm 4014. Here, the loading and unloading chamber 4002, the loading and unloading chamber 4004, the deposition chamber 4008, the deposition chamber 4009, and the processing chamber 4011 are independently connected to the transfer chamber 4006 through gate valves. Thus, in the deposition chamber 4008, the deposition chamber 4009, and the processing chamber 4011, processing can be continuously performed without being exposed to the atmosphere, and impurities can be prevented from being mixed into the film. In addition, the contamination of the interface between the substrate and the film and the interface of each film is reduced, thereby obtaining a clean interface.

[0241] Note that in order to prevent the adhesion of moisture, etc., it is preferred to fill the loading and unloading chamber 4002, the loading and unloading chamber 4004, the transfer chamber 4006, the deposition chamber 4008, the deposition chamber 4009 and the processing chamber 4011 with an inert gas with a controlled dew point (nitrogen gas, etc.), and it is more preferred to maintain a reduced pressure state.

[0242] In deposition chambers 4008 and 4009, an ALD apparatus can be used. Additionally, deposition apparatuses other than the ALD apparatus can also be used for either deposition chamber 4008 or deposition chamber 4009. Examples of deposition apparatuses that can be used for deposition chambers 4008 and 4009 include, for example, a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like.

[0243] In addition, in processing chamber 4011, it is preferable to use apparatuses having functions other than deposition apparatuses, such as a heating apparatus (typically a vacuum heating apparatus) and a plasma generation apparatus (typically a microwave processing apparatus).

[0244] For example, when deposition chamber 4008 is an ALD apparatus, deposition chamber 4009 is a sputtering apparatus, and processing chamber 4011 is a heating apparatus, a base insulating film can be deposited in deposition chamber 4009, an oxide semiconductor film used as an active layer can be deposited in deposition chamber 4008, and a heat treatment can be performed in processing chamber 4011 after depositing the oxide semiconductor film. At this time, the deposition of the base insulating film, the deposition of the oxide semiconductor film, and the heat treatment can be continuously performed without being exposed to the atmosphere. Thus, after depositing a metal oxide, a heat treatment can be performed without an increase in impurities such as hydrogen or carbon in the film.

[0245] Although deposition apparatus 4000 includes load lock chambers 4002 and 4004, deposition chambers 4008 and 4009, and processing chamber 4011, the present invention is not limited thereto, and a structure in which the number of deposition chambers of deposition apparatus 4000 is one or three or more can also be adopted. In addition, a structure in which the number of processing chambers of deposition apparatus 4000 is two or more can also be adopted. Further, deposition apparatus 4000 can be either a single wafer type deposition apparatus or a batch type deposition apparatus that simultaneously deposits on a plurality of substrates.

[0246] <ALD apparatus> Next, use Fig. 8AThe structure of the thermal ALD apparatus that can be used for the deposition apparatus 4000 is described. The thermal ALD apparatus includes a deposition chamber (chamber 4520), a raw material supply part 4521 (raw material supply parts 4521a to 4521c), a raw material supply part 4531, high-speed valves 4522a to 4522d used as an introduction amount controller, a gas supply part 4532, a raw material introduction port 4523, a raw material discharge port 4524, and an exhaust device 4525. The raw material introduction port 4523 provided in the chamber 4520 is connected to the raw material supply part 4521a, the raw material supply part 4521b, the raw material supply part 4521c, the raw material supply part 4531, and the gas supply part 4532 through supply pipes and valves, respectively, and the raw material discharge port 4524 is connected to the exhaust device 4525 through, for example, an exhaust pipe, a valve, and a pressure regulator.

[0247] A substrate holder 4526 is provided inside the chamber 4520, and a substrate 4530 is arranged on the substrate holder 4526. The substrate holder 4526 may also include a rotating mechanism. In addition, a heater 4527 is provided on the outer wall of the chamber 4520, which can control the temperature of the inside of the chamber 4520, the substrate holder 4526, and the surface of the substrate 4530. The heater 4527 preferably controls the temperature of the surface of the substrate 4530 to be above 100°C and below 600°C, more preferably to be above 300°C and below 500°C, and further preferably to be above 400°C and below 450°C. For example, the temperature of the heater 4527 itself is preferably set to be above 100°C and below 600°C. By performing deposition while heating the substrate within such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be suppressed from remaining in the metal oxide. Moreover, while removing these impurities, the metal atoms and oxygen atoms are rearranged, and the layers of each oxide can be arranged with high order. Therefore, a metal oxide having a layered crystal structure with high crystallinity can be formed. In addition, the heater 4527 can also be used to perform a heat treatment after the metal oxide is deposited.

[0248] The source gas is formed from a solid raw material or a liquid raw material by a vaporizer or a heating unit in the raw material supply parts 4521a, 4521b, 4521c, and 4531. Alternatively, the raw material supply parts 4521a, 4521b, 4521c, and 4531 may have a structure for supplying a source gas of a gas.

[0249] exist Fig. 8A In the deposition apparatus shown in FIG. 4 , a metal oxide can be formed by appropriately selecting raw materials (volatile organic metal compounds, etc.) used in the raw material supply unit 4521 and the raw material supply unit 4531 and introducing them into the chamber 4520. As described above, when In-Ga-Zn oxide containing indium, gallium, and zinc is formed as the metal oxide, Fig. 8A As shown, it is preferable to use a deposition apparatus provided with at least three raw material supply parts 4521 a to 4521 c and at least one raw material supply part 4531 .

[0250] For example, the raw material supply unit 4521a supplies a precursor containing indium, the raw material supply unit 4521b supplies a precursor containing gallium, and the raw material supply unit 4521c supplies a precursor containing zinc. As the precursor containing indium, the precursor containing gallium, and the precursor containing zinc, the above precursors can be used respectively.

[0251] In addition, the raw material supply unit 4531 supplies a reactant. As the reactant, an oxidant containing at least one of ozone, oxygen, and water can be used.

[0252] In addition, the gas supply unit 4532 provides a carrier gas. As the carrier gas, an inert gas such as argon (Ar), helium (He), or nitrogen (N2) can be used. The precursor of the raw material supply unit 4521 and the reactant of the raw material supply unit 4531 are mixed with the carrier gas and introduced into the chamber 4520.

[0253] In addition, a pipe heater 4534a is provided in a manner that covers the pipes or valves between the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, the raw material supply unit 4531 and the gas supply unit 4532 and the chamber 4520. In addition, a pipe heater 4534b is provided in a manner that covers the pipes or valves between the exhaust device 4525 and the chamber 4520. The temperature of the pipe heater 4534a and the pipe heater 4534b can be appropriately set, for example, within a range above room temperature and below 300°C. By providing such a pipe heater, it is possible to prevent the precursor provided by the raw material supply unit 4521 from condensing on the inner wall of the pipe of the gas introduction system and the gas exhaust system. In addition, it is preferred to control the temperature of the pipe heater 4534a, the pipe heater 4534b and the heater 4527 independently. Alternatively, the temperature control of the pipe heater 4534a, the pipe heater 4534b and the heater 4527 can also be adjusted together.

[0254] The high-speed valves 4522 a to 4522 d may be controlled with time precision. Therefore, source gases provided by the raw material suppliers 4521 a , 4521 b , 4521 c , and 4531 may be controlled and introduced into the chamber 4520 .

[0255] For example, when the precursors included in the raw material supply part 4521a, the raw material supply part 4521b, and the raw material supply part 4521c are provided, the corresponding high-speed valves in the high-speed valves 4522a to 4522c are opened. In addition, when the reactants included in the raw material supply part 4531 are provided, the high-speed valve 4522d is opened. In addition, when the chamber 4520 is purged, the high-speed valves 4522a to 4522d are closed, and only the carrier gas in the gas supply part 4532 is introduced into the chamber 4520.

[0256] in addition, Fig. 8A Although an example is shown in which three raw material supply units 4521 and one raw material supply unit 4531 are provided, the present embodiment is not limited thereto, and one, two, or four or more raw material supply units 4521 may be provided. In addition, two or more raw material supply units 4531 may be provided.

[0257] In addition, Fig. 8A In the embodiment, the heater 4527, the raw material introduction port 4523 and the raw material discharge port 4524 are arranged below the chamber 4520, but the present invention is not limited thereto and their arrangement can be appropriately set. Fig. 8A In the figure, a common raw material inlet 4523 is provided as the inlet of the raw material supply part 4521a, the raw material supply part 4521b, the raw material supply part 4521c, the raw material supply part 4531 and the gas supply part 4532, but it is not limited to this, and different inlets may be provided respectively.

[0258] Next, use Figure 8B The structure of a plasma ALD device that can be used for the deposition device 4000 is described. The plasma ALD device includes a deposition chamber (chamber 4020), a raw material supply part 4021 (raw material supply parts 4021a to 4021c), a raw material supply part 4031, high-speed valves 4022a to 4022d used as an introduction amount controller, a gas supply part 4032, a raw material introduction port 4023, a raw material introduction port 4033, a raw material discharge port 4024, and an exhaust device 4025. The raw material introduction port 4023 and the raw material introduction port 4033 provided in the chamber 4020 are respectively connected to the raw material supply part 4021a, the raw material supply part 4021b, the raw material supply part 4021c, the raw material supply part 4031, and the gas supply part 4032 through supply pipes and valves, and the raw material discharge port 4024 is connected to the exhaust device 4025 through an exhaust pipe, a valve, and a pressure regulator. A substrate holder 4026 is provided inside the chamber 4020, and a substrate 4030 is placed on the substrate holder 4026. A heater 4027 is provided on the outer wall of the chamber, and a pipe heater 4034a and a pipe heater 4034b are provided to cover pipes connected to the chamber.

[0259] Here, chamber 4020 corresponds to chamber 4520, raw material supply section 4021 corresponds to raw material supply section 4521, raw material supply section 4031 corresponds to raw material supply section 4531, high-speed valves 4022a to 4022d correspond to high-speed valves 4522a to 4522d, gas supply section 4032 corresponds to gas supply section 4532, raw material inlet 4023 corresponds to raw material inlet 4523, raw material outlet 4024 corresponds to raw material outlet 4524, exhaust device 4025 corresponds to exhaust device 4525, substrate rack 4026 corresponds to substrate rack 4526, substrate 4030 corresponds to substrate 4530, heater 4027 corresponds to heater 4527, pipe heater 4034a corresponds to pipe heater 4534a, and pipe heater 4034b corresponds to pipe heater 4534b, so its detailed structure can refer to the above records.

[0260] like Figure 8B As shown, in the plasma ALD device, since the plasma generating device 4028 is connected to the chamber 4020, deposition can be performed not only by the thermal ALD method but also by the plasma ALD method. The plasma generating device 4028 is preferably an ICP type plasma generating device using a coil 4029 connected to a high-frequency power supply. The high-frequency power supply can output power with a frequency of 10 kHz or more and 100 MHz or less, preferably 1 MHz or more and 60 MHz or less, and more preferably 2 MHz or more and 60 MHz or less. For example, power with a frequency of 13.56 MHz can be output. By utilizing the plasma ALD method, deposition can be performed even at low temperatures without reducing the deposition rate, so it is preferred to use the plasma ALD method in a single-wafer deposition device with a low deposition efficiency.

[0261] The reactant discharged from the raw material supply part 4031 is in a plasma state through the plasma generating device 4028. The reactant in a plasma state is introduced into the chamber 4020 from the raw material introduction port 4033. Figure 8B Although not shown in the figure, the reactants discharged from the raw material supply unit 4031 can also be mixed with the carrier gas.

[0262] The substrate holder 4526 may also be provided with a mechanism to which a certain potential or high frequency is applied. Alternatively, the substrate holder 4526 may be in a floating state or grounded.

[0263] Note that Figure 8B In the embodiment, the raw material introduction port 4033 is arranged above the chamber 4520, the heater 4027 and the raw material introduction port 4023 are arranged on the side of the chamber 4520, and the raw material discharge port 4524 is arranged below the chamber 4520, but it is not limited to this and their arrangements can be appropriately set.

[0264] use 9A to 9C The following describes different structures of the ALD device that can be used in the deposition device 4000. Note that the following description is sometimes omitted. Figure 8B Details of the structure and function of the ALD device shown.

[0265] Fig.9A 4 is a schematic diagram showing one embodiment of a plasma ALD device. The plasma ALD device 4100 is provided with a reaction chamber 4120 and a plasma generating chamber 4111 at the upper portion of the reaction chamber 4120. The reaction chamber 4120 may be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generating chamber 4111 may be collectively referred to as a chamber. The reaction chamber 4120 includes a raw material introduction port 4123 and a raw material discharge port 4124, and the plasma generating chamber 4111 includes a raw material introduction port 4133. In addition, by means of a plasma generating device 4128, a high frequency such as RF or microwaves may be applied to the gas introduced into the plasma generating chamber 4111 to generate a plasma 4131 in the plasma generating chamber 4111. When microwaves are used to generate the plasma 4131, microwaves having a frequency of 2.45 GHz are typically used. Plasma generated by applying the above-mentioned microwaves and a magnetic field is sometimes referred to as ECR (Electron Cyclotron Resonance) plasma.

[0266] In addition, the reaction chamber 4120 includes a substrate holder 4126, and the substrate 4130 is arranged on the substrate holder 4126. The source gas introduced from the raw material introduction port 4123 is decomposed by the heat from the heater provided in the reaction chamber 4120 and deposited on the substrate 4130. In addition, the source gas introduced from the raw material introduction port 4133 is in a plasma state by the plasma generating device 4128. The source gas in the plasma state is recombined with electrons or other molecules before reaching the surface of the substrate 4130 and is in a radical state, and reaches the substrate 4130. In this way, an ALD device that uses radicals for deposition is sometimes referred to as a radical ALD (Radical-Enhanced ALD) device. In addition, in the plasma ALD device 4100, a structure in which the plasma generating chamber 4111 is provided on the upper part of the reaction chamber 4120 is shown, but the present embodiment is not limited thereto. The plasma generating chamber 4111 may also be provided in a manner adjacent to the side of the reaction chamber 4120.

[0267] Fig. 9B4 is a schematic diagram showing one mode of a plasma ALD device. The plasma ALD device 4200 includes a chamber 4220. The chamber 4220 includes an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, and a substrate 4230 is arranged on the substrate holder 4226. The electrode 4213 includes a raw material introduction port 4223 and a showerhead 4214 that provides the introduced source gas into the chamber 4220. In addition, the electrode 4213 is connected to a power supply 4215 that can apply a high frequency through a capacitor 4217. The substrate holder 4226 can also be provided with a mechanism to which a certain potential or high frequency is applied. Alternatively, the substrate holder 4226 can be in a floating state or can be grounded. The electrode 4213 and the substrate holder 4226 are respectively used as an upper electrode and a lower electrode for generating a plasma 4231. The source gas introduced from the raw material introduction port 4223 is decomposed by the heat from the heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the source gas introduced from the raw material introduction port 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The source gas in the plasma state is incident on the substrate 4230 due to the potential difference (also called ion sheath) generated between the plasma 4231 and the substrate 4230.

[0268] Fig. 9C is shown with Fig. 9BSchematic diagram of one embodiment of a different plasma ALD device. The plasma ALD device 4300 includes a chamber 4320. The chamber 4320 includes an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, and a substrate 4330 is arranged on the substrate holder 4326. The electrode 4313 includes a raw material inlet 4323 and a nozzle 4314 for providing the introduced source gas into the chamber 4320. In addition, the electrode 4313 is connected to a power supply 4315 to which a high frequency can be applied through a capacitor 4317. The substrate holder 4326 can also be provided with a mechanism to which a certain potential or high frequency is applied. Alternatively, the substrate holder 4326 can be in a floating state or can be grounded. The electrode 4313 and the substrate holder 4326 are used as an upper electrode and a lower electrode, respectively, for generating a plasma 4331. The plasma ALD device 4300 is different from the plasma ALD device 4200 in that a mesh 4319 connected to a power source 4321 to which a high frequency can be applied via a capacitor 4322 is provided between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The source gas introduced from the raw material introduction port 4323 is decomposed by the heat from the heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced from the raw material introduction port 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326. The source gas in the plasma state is decharged by the mesh 4319 and reaches the substrate 4130 in an electrically neutral state such as a free radical. Thus, deposition can be performed in which damage caused by ion injection and plasma is suppressed.

[0269] For example, you can also use Figure 8B , 9A to 9C The plasma ALD apparatus shown performs plasma treatment or microwave treatment as the impurity removal treatment. In this case, it is not necessary to move from the deposition chamber to another chamber for the impurity removal treatment, which is preferable.

[0270] In addition, you can also use Figure 8B , 9A to 9C The plasma ALD apparatus shown performs post-deposition plasma treatment or microwave treatment of the metal oxide.

[0271] <Deposition sequence> Next, use Figure 10 to Fig.12 Instructions for use Fig. 8A The metal oxide deposition sequence of the ALD device shown in FIG. Fig.12 In the figure, the introduction of the first source gas to the fourth source gas is recorded as "ON", and the period when the source gas is not introduced is recorded as "OFF".

[0272] Fig. 10A Show use Fig. 8A The deposition sequence of the ALD device shown in the figure. First, the substrate 4530 is arranged on the substrate rack 4526 in the chamber 4520 (step S101). Then, the temperature of the heater 4527 is adjusted (step S102). At this time, it is preferable to also adjust the temperature of the pipe heater 4534a and the pipe heater 4534b. Next, the substrate 4530 is maintained on the substrate rack 4526 in such a manner that the in-plane temperature of the substrate 4530 becomes constant (step S103). Next, the metal oxide is deposited through the above-mentioned first step to the fourth step (step S104). Note that if it is not necessary to adjust the temperature of the heater 4527 after the arrangement of the substrate 4530 (step S101), step S102 can also be omitted.

[0273] In step S104, the first source gas (the source gas containing the precursor) and the second source gas (the source gas containing the reactant) are alternately introduced into the chamber 4520, and deposition is performed on the substrate 4530. The first source gas and the second source gas are introduced in a pulsed state. The chamber 4520 is purged during the period when neither the first source gas nor the second source gas is introduced. In the deposition using the ALD method, the introduction of the first source gas (the first step described above), the purging of the first source gas (the second step described above), the introduction of the second source gas (the third step described above), and the purging of the second source gas (the fourth step described above) are referred to as a cycle, and a film having a desired thickness is formed by repeating the cycle. Note that intermittent impurity removal processing is not involved here, but it is preferred to perform impurity removal processing in the chamber 4520 or other chambers every time the cycle is repeated multiple times.

[0274] In addition, a second source gas containing a reactant may be introduced into the chamber 4020 between step S103 and step S104. As the second source gas, one or more selected from ozone (O3), oxygen (O2) and water (H2O) used as an oxidant is preferably introduced. By introducing water as the second source gas, a hydrophilic group can be formed on the substrate 4530, thereby further improving the adsorption of the precursor. By introducing ozone and oxygen as the second source gas, the interior of the chamber can be placed in an oxygen atmosphere and oxygen can be provided to a base insulating film formed on the substrate 4530. Thus, oxygen can be provided to the metal oxide film formed on the base insulating film to increase the oxygen concentration in the film. At this time, it is preferred to introduce the second source gas in a pulsed manner as in the method shown in step S104, but the present invention is not limited thereto, and the second source gas may also be introduced continuously. The exhaust in the chamber 4520 is performed during the period when the second source gas is not introduced.

[0275] By forming a first oxide layer using one cycle of the first source gas, forming a second oxide layer using one cycle of a third source gas different from the first source gas, and forming a third oxide layer using one cycle of a fourth source gas different from the first source gas, a layered crystalline oxide including a plurality of different oxide layers can be deposited. Fig. 10B A deposition sequence corresponding to the deposition process of the In—Ga—Zn oxide shown in FIGS. 5 and 6 will be described.

[0276] exist Fig. 10B In step S104 of the deposition sequence, an example of using the first source gas to the third source gas containing different precursors for deposition is shown. Steps S101 to S103 are as described above. Here, the first source gas includes a precursor containing indium, the third source gas includes a precursor containing gallium, and the fourth source gas includes a precursor containing zinc.

[0277] like Fig. 10B As shown, firstly, the first source gas is introduced to make the precursor containing indium adsorbed on the substrate 4530 (corresponding to Figure 5A ). Then, the introduction of the first source gas is stopped, and the remaining first source gas in the chamber is purged.

[0278] Next, a second source gas is introduced to react the adsorbed indium-containing precursor with an oxidant to form an indium oxide layer (corresponding to Figure 5B ). Then, the introduction of the second source gas is stopped, and the remaining second source gas in the chamber is purged.

[0279] Next, a third source gas is introduced to adsorb the precursor containing gallium onto the indium oxide layer (corresponding to Figure 5C ). Then, the introduction of the third source gas is stopped, and the remaining third source gas in the chamber is purged.

[0280] Next, a second source gas is introduced to react the adsorbed gallium-containing precursor with an oxidant to form a gallium oxide layer (corresponding to Figure 5D ). Then, the introduction of the second source gas is stopped, and the remaining second source gas in the chamber is purged.

[0281] Next, a fourth source gas is introduced to adsorb a precursor containing zinc onto the gallium oxide layer (corresponding to Fig. 6A ). Then, the introduction of the fourth source gas is stopped, and the remaining fourth source gas in the chamber is purged.

[0282] Next, a second source gas is introduced to react the adsorbed zinc-containing precursor with an oxidant to form a zinc oxide layer (corresponding to Figure 6BThen, the introduction of the second source gas is stopped, and the remaining second source gas in the chamber is purged. Furthermore, the precursor containing indium is adsorbed on the zinc oxide (corresponding to Figure 6C ).

[0283] The above-mentioned process of forming indium oxide, gallium oxide and zinc oxide is regarded as one cycle, and the cycle is repeated, thereby forming In-Ga-Zn oxide with In:Ga:Zn=1:1:1 [atomic ratio] having a desired thickness.

[0284] Note that the introduction of the first source gas to the fourth source gas is performed in a pulsed state. The pulse time for introducing the first source gas, the third source gas, and the fourth source gas into the chamber 4520 is preferably 0.05 seconds to 1 second, and more preferably 0.1 seconds to 0.5 seconds. In addition, the time for exhausting the first source gas, the third source gas, and the fourth source gas from the chamber 4520 is 0.1 seconds to 15 seconds, and preferably 0.5 seconds to 10 seconds. The pulse time for introducing the second source gas into the chamber 4520 is preferably 0.05 seconds to 30 seconds, and more preferably 0.1 seconds to 15 seconds. In addition, the time for exhausting the second source gas from the chamber 4520 is 0.1 seconds to 15 seconds, and preferably 0.1 seconds to 5 seconds.

[0285] Note that Fig. 10B In the sequence shown, the order of introducing the first source gas, the third source gas, and the fourth source gas is not limited thereto. For example, the fourth gas including a precursor containing zinc may be introduced first. Zinc oxide is easier to form a crystal structure than indium oxide and gallium oxide, so a stable zinc oxide crystal can be formed in the bottom layer. Thus, a layer of indium oxide and gallium oxide can be formed more easily on zinc oxide.

[0286] The above describes the deposition of In-Ga-Zn oxide with In:Ga:Zn=1:1:1 [atomic ratio], but the present invention is not limited to this. The same method can be used to form In-Ga-Zn oxides with different atomic ratios. Preferably, the number of pulses or pulse time of the source gas including the precursor in one cycle is set according to the atomic ratio of the required In-Ga-Zn oxide.

[0287] For example, in Fig. 10B In the sequence shown, in order to deposit In-Ga-Zn oxide with In:Ga:Zn=1:1:1 [atomic ratio], the number of pulses of the first source gas containing indium, the third source gas containing gallium, and the fourth source gas containing zinc in one cycle is set to one. At this time, the pulse time of each precursor is the same.

[0288] Fig.11AAn example of a deposition sequence of an In-Ga-Zn oxide with In:Ga:Zn=1:3:4 [atomic ratio] is shown. Fig.11A In one cycle, the pulse number of the first source gas containing indium is one, the pulse number of the third source gas containing gallium is three, and the pulse number of the fourth source gas containing zinc is four. That is, the pulse number of the source gas containing the precursor corresponds to In:Ga:Zn=1:3:4 [atomic number ratio]. By performing deposition in this way, a Figure 2D Metal oxides with a layered crystal structure.

[0289] In addition, as described above, by performing deposition by the ALD method while heating the substrate, the rearrangement of each oxide layer can be promoted. Fig.11A The sequence shown is deposited as Figure 2D As in the illustrated layer 23, a layer containing two metal elements (indium and gallium) may be formed in one oxide layer.

[0290] Note that in the above, different types of precursors are introduced, and the source gas including the reactant is introduced in the middle, but the present invention is not limited to this. For example, the source gas including the same type of precursor can also be continuously introduced, and the source gas including the reactant is introduced in the middle. In this case, the number of pulses of the source gas including the precursor in one cycle is preferably the same as the atomic number ratio of the desired In-Ga-Zn oxide.

[0291] In addition, the above shows a structure in which only one source gas including a precursor is introduced during the interval of oxidation using the second source gas, but the present invention is not limited thereto, and two or more source gases including a precursor may be introduced during the interval of oxidation using the second source gas. In this case, two or more source gases including a precursor may be introduced simultaneously. In addition, the same type of precursor may be continuously introduced twice during the interval of oxidation using the second source gas.

[0292] For example, when depositing an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:3:4, the Fig. 11B The deposition was performed in the sequence shown. Fig. 11B In, according to Figure 2D The crystal structure shown in FIG. 23, layer 41, layer 31, and layer 41 are sequentially stacked, and the first source gas and the third source gas, the fourth source gas, the third source gas, and the fourth source gas are sequentially introduced. Note that the second source gas is not introduced between the initial introduction of the first source gas and the third source gas. That is, the oxidant is introduced after the precursor containing indium included in the first source gas and the precursor containing gallium included in the third source gas are adsorbed. Thus, as Figure 2DAs shown in FIG. 23, an oxide layer containing two metal elements (indium and gallium) can be formed. At this time, the pulse time of the first source gas and the third source gas is preferably about half of the pulse time of the fourth source gas. Fig. 11B As shown, the ratio of the pulse time of the first source gas containing indium, the pulse time of the third source gas containing gallium, and the pulse time of the fourth source gas containing zinc in one cycle can be made the same as the atomic number ratio, that is, 1:3:4.

[0293] The above describes the deposition of oxides with a fixed atomic number ratio, but the present invention is not limited to this. Two or more oxides with different atomic number ratios can be continuously deposited using the same method. At this time, it is preferred that in stacked oxides with different atomic number ratios, the number of pulses or pulse time of the source gas including the precursor in one cycle is set according to the atomic number ratio of each oxide. By performing deposition in this way, stacked oxides with different atomic number ratios can be deposited in one chamber. Therefore, impurities such as hydrogen or carbon can be prevented from entering in the intervals between the deposition of each oxide.

[0294] Fig.12 An example of a deposition sequence is shown when an oxide of In:Ga:Zn=1:1:1 [atomic ratio] is stacked on an oxide of In:Ga:Zn=1:3:4 [atomic ratio]. Step 104a corresponds to an oxide of In:Ga:Zn=1:3:4 [atomic ratio], and Fig.11A In addition, step 104b corresponds to an oxide with In:Ga:Zn=1:1:1 [atomic ratio], which is the same as Fig. 10B Thus, when the pulse number of the first half cycle is the first source gas: the third source gas: the fourth source gas = 1:3:4, and the pulse number of the second half cycle is the first source gas: the third source gas: the fourth source gas = 1:1:1, a deposition having Figure 3B The metal oxide of the stacked structure of oxide 62 and oxide 60 is shown. That is, the first half is deposited with a pulse number corresponding to In:Ga:Zn=1:3:4 [atomic ratio], and the second half is deposited with a pulse number corresponding to In:Ga:Zn=1:1:1 [atomic ratio].

[0295] Note that, in the above, the deposition method is described by taking In-Ga-Zn oxide as an example, but the present invention is not limited to this. The precursor can be appropriately set according to the metal element in the required metal oxide. In addition, in the above, the number of precursors is one or three, but it is not limited to this, and it can also be two or more than four.

[0296] In addition, the above example shows the use of a precursor containing one metal element for deposition, but the present invention is not limited to this, and a precursor containing two or more metal elements may also be used. For example, a precursor containing indium and gallium or a precursor containing gallium and zinc may also be used. In this case, the Fig. 8A etc. as shown in the number of raw material supply units 4521.

[0297] <Metal oxide having CAAC structure> Hereinafter, the metal oxide having a CAAC structure will be described in detail.

[0298] The CAAC structure includes multiple crystals whose c-axes are oriented in a specific direction. The specific direction refers to the thickness direction of the metal oxide having the CAAC structure, the normal direction of the formed surface of the metal oxide having the CAAC structure, or the normal direction of the surface of the metal oxide having the CAAC structure. Note that when recorded as a "crystalline region", the crystalline region is the crystal itself included in the CAAC structure or the crystal included in the CAAC structure and the region near it. Therefore, the crystal included in the CAAC structure is sometimes recorded as the crystalline region included in the CAAC structure.

[0299] A crystalline region is a region with periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a consistent lattice arrangement. Furthermore, the CAAC structure has a region where multiple crystalline regions are connected in the ab plane direction, and sometimes the region has a distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region with a consistent lattice arrangement and other regions with a consistent lattice arrangement in a region where multiple crystalline regions are connected. In other words, a metal oxide having a CAAC structure is a metal oxide that is oriented along the c-axis and has no obvious orientation in the ab plane direction.

[0300] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystals with a maximum diameter less than 10nm). In the case where the crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10nm. In addition, in the case where the crystallization region is composed of multiple tiny crystals, the size of the crystallization region is sometimes about tens of nm.

[0301] In addition, in In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin and titanium, etc.), there is a tendency that the CAAC structure has a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen, a layer containing element M, zinc (Zn) and oxygen is stacked. Note that the layer containing indium and oxygen sometimes contains element M or zinc. In addition, the layer containing element M, zinc indium and oxygen sometimes contains indium. This layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0302] For example, when a metal oxide having a CAAC structure is subjected to structural analysis using an XRD device, a peak indicating c-axis orientation is detected at or near 2θ = 31° in an Out-of-plane XRD measurement using θ / 2θ scanning. Note that the position (2θ value) of the peak indicating c-axis orientation sometimes varies depending on the type and composition of the metal elements constituting the metal oxide.

[0303] In addition, for example, multiple bright spots (spots) are observed in the electron diffraction pattern of a metal oxide having a CAAC structure. In addition, when the spot of the incident electron beam passing through the sample (also called the direct spot) is the symmetry center, a certain spot and other spots are observed at point-symmetrical positions.

[0304] By performing FFT (Fast Fourier Transform) analysis on the TEM image, an FFT image having a pattern that reflects the reciprocal spatial information in the same way as the electron diffraction pattern can be obtained. That is, the crystal structure (for example, CAAC structure) can be confirmed and evaluated using FFT analysis. For example, when a cross-sectional TEM image of a metal oxide having a CAAC structure is taken in a direction perpendicular to its c-axis, it is possible to observe two spots of greater intensity in the FFT image. The intensities of the two spots represent the degree of crystallization of the metal oxide having a CAAC structure, and the angle of the line segment connecting the two spots represents the crystal orientation of the metal oxide having a CAAC structure.

[0305] When observing the crystalline region from the above-mentioned specific direction, although the lattice arrangement in the crystalline region is basically a hexagonal lattice, the unit lattice is not limited to a regular hexagon, and there are cases where it is a non-regular hexagon. In addition, in the above-mentioned distortion, sometimes there is a pentagonal, heptagonal and other lattice arrangements. In addition, no clear grain boundaries are observed near the distortion of the metal oxide with a CAAC structure. In other words, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because the metal oxide with a CAAC structure can tolerate distortion due to the low density of the arrangement of oxygen atoms in the ab plane direction or the change in the bonding distance between atoms due to the substitution of metal atoms.

[0306] The metal oxide having a CAAC structure is a metal oxide having high crystallinity and in which no clear grain boundaries are observed. In other words, it can be said that a decrease in electron mobility due to grain boundaries is not likely to occur in the metal oxide having a CAAC structure. Therefore, the physical properties of the metal oxide having a CAAC structure are stable. Therefore, the metal oxide having a CAAC structure is heat-resistant and has high reliability. Therefore, the metal oxide having a CAAC structure is one of the crystalline oxides having a crystal structure suitable as a semiconductor layer of a transistor.

[0307] In a deposition method of a metal oxide according to one embodiment of the present invention, an impurity removal process is intermittently performed in an oxygen-containing atmosphere during deposition. Thus, impurities contained in raw materials such as precursors can be suppressed from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. In addition, the crystallinity of the metal oxide can be improved.

[0308] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0309] (Implementation Method 2) In this embodiment, referring to FIGS. 13 to 14 Fig.29 A memory device according to one embodiment of the present invention is described. A memory device according to one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0310] <Configuration Example 1 of Storage Device> The structure of a memory device including a transistor and a capacitor will be described with reference to FIG. 13 . FIG. 13A to FIG. 13C 1 and 2 are a plan view and a cross-sectional view of a memory device including a transistor 200 and a capacitor 100 . Fig.13A is a plan view of the storage device. Fig. 13B and Fig. 13C is a cross-sectional view of the storage device. Fig. 13B It is along Fig.13A A cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Fig. 13C It is along Fig.13A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Fig.13A In the plan view, some components are omitted for clarity.

[0311] Note that arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings of this specification. Note that in this specification, "X direction" refers to the direction along the X axis, and sometimes the forward and reverse directions are not distinguished except for the cases clearly stated. The same is true for "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. Specifically, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, the X direction, Y direction, or Z direction is sometimes referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction".

[0312] FIG. 13A to FIG. 13CThe memory device shown includes: an insulator 140 on a substrate (not shown); a conductor 110 on the insulator 140; a memory cell 150 on the conductor 110; an insulator 180 on the conductor 110; an insulator 280; and an insulator 283 on the memory cell 150. The insulator 140, the insulator 180, the insulator 280, and the insulator 283 are used as interlayer films. The conductor 110 is used as wiring.

[0313] The memory cell 150 includes a capacitor 100 on a conductor 110 and a transistor 200 on the capacitor 100 .

[0314] The capacitor 100 includes a conductor 115 on a conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 115 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 130 is used as a dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0315] like Fig. 13B and Fig. 13C As shown, the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is arranged in the opening 190. Note that the conductor 115 has a region in contact with the top surface of the conductor 110 in the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulator 180. The insulator 130 is arranged so that at least a portion thereof is located in the opening 190. The conductor 120 is arranged so that at least a portion thereof is located in the opening 190. In addition, as Fig. 13B and Fig. 13C As shown, the conductor 120 is preferably provided in a manner embedded in the opening 190. In addition, the film provided inside the opening 190 is preferably formed by the ALD method. Thus, the film has good coverage. For example, the conductor 115, the insulator 130, and the conductor 120 are preferably formed by the ALD method.

[0316] Fig.14A 1 is a plan view schematically showing the conductor 110, the conductor 115, the conductor 120, and the opening 190. Note that the opening 190 provided in the insulator 180 is shown by a dotted line. Fig.14A As shown, the conductor 115 includes an opening 190 in a region overlapping with the conductor 110 .

[0317] The capacitor 100 has a structure in which the upper electrode and the lower electrode are opposed to each other through a dielectric body in the opening 190 not only on the bottom surface but also on the side surface, so that the electrostatic capacitance per unit area can be increased. Thus, the deeper the depth of the opening 190, the greater the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. In addition, the miniaturization or high integration of the storage device can be promoted.

[0318] The side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. In this case, the opening 190 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0319] Conductor 115 and insulator 130 are stacked along the sidewalls of opening 190 and the top surface of conductor 110. Conductor 120 is provided on insulator 130 so as to be embedded in opening 190. Capacitor 100 having such a structure may be referred to as a trench capacitor or trench capacitor.

[0320] The insulator 280 is disposed on the capacitor 100 . That is, the insulator 280 is disposed on the conductor 115 , the insulator 130 , and the conductor 120 . In other words, the conductor 120 is disposed under the insulator 280 .

[0321] The transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. The oxide semiconductor 230 is used as a semiconductor layer, the conductor 260 is used as a gate electrode, the insulator 250 is used as a gate insulator, the conductor 120 is used as one of a source electrode and a drain electrode, and the conductor 240 is used as the other of the source electrode and the drain electrode.

[0322] like Fig. 13B and Fig. 13C As shown, an opening 290 that reaches the conductor 120 is provided in the insulator 280 and the conductor 240. At least a portion of the oxide semiconductor 230 is disposed in the opening 290. In addition, the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 in the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a portion of the top surface of the conductor 240. The insulator 250 is disposed so that at least a portion thereof is located in the opening 290. The conductor 260 is disposed so that at least a portion thereof is located in the opening 290. In addition, as Fig. 13B and Fig. 13CAs shown, the conductor 260 is preferably provided in a manner embedded in the opening 290. In addition, the film provided inside the opening 290 is preferably formed by the ALD method. Thus, the film has good coverage. For example, the oxide semiconductor 230, the insulator 250 and the conductor 260 are preferably formed by the ALD method.

[0323] Fig. 14B 2 is a plan view schematically showing the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290. Note that the opening 290 provided in the insulator 280 is shown by a dotted line. Fig. 14B As shown, the conductor 240 includes an opening 290 in a region overlapping the conductor 120. In addition, the conductor 240 is preferably not disposed inside the opening 290. That is, the conductor 240 preferably does not have a region that contacts the side surface of the insulator 280 on the opening 290 side.

[0324] The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 and a region in contact with a portion of the top surface of the conductor 240 in the opening 290. In this way, since the oxide semiconductor 230 is in contact with the top surface of the conductor 240 in addition to the side surface, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased.

[0325] like FIG. 13A to FIG. 13C As shown, the transistor 200 overlaps with the capacitor 100. In addition, the opening 290 in which a part of the structure of the transistor 200 is provided has an area overlapping with the opening 190 in which a part of the structure of the capacitor 100 is provided. In particular, the conductor 120 is used as one of the source electrode and the drain electrode of the transistor 200 and is used as the upper electrode of the capacitor 100, so the transistor 200 and the capacitor 100 share part of the structure. By adopting this structure, the transistor 200 and the capacitor 100 can be arranged in a manner that does not significantly increase the occupied area when viewed from above. As a result, the occupied area of ​​the memory cell 150 can be reduced, so the memory cell 150 can be arranged at a high density to increase the storage capacity of the storage device. In other words, high integration of the storage device can be achieved.

[0326] Fig.13D 2 is a circuit diagram of a storage device shown in this embodiment. Fig.13D As shown, FIG. 13A to FIG. 13C The structure shown is used as a memory cell of a memory device. The memory cell includes a transistor Tr and a capacitor C. Here, the transistor Tr corresponds to the transistor 200, and the capacitor C corresponds to the capacitor 100.

[0327] One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitor C. The other of the source and drain of the transistor Tr is connected to the wiring BL. The gate of the transistor Tr is connected to the wiring WL. The other of the pair of electrodes of the capacitor C is connected to the wiring PL.

[0328] Here, the wiring BL corresponds to the conductor 240, the wiring WL corresponds to the conductor 260, and the wiring PL corresponds to the conductor 110. FIG. 13A to FIG. 13C As shown in FIG. 1 , it is preferred that the conductor 260 extends in the Y direction and the conductor 240 extends in the X direction. By adopting this structure, the wiring BL and the wiring WL intersect each other. Fig.13A The wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited thereto. For example, the wiring PL may be parallel to the wiring WL (conductor 260) or the wiring BL (conductor 240).

[0329] Note that the storage unit will be described in detail in a later embodiment.

[0330] [Capacitor 100] The capacitor 100 includes a conductor 115, an insulator 130, and a conductor 120. The conductor 110 is provided below the conductor 115. The conductor 115 has a region in contact with the conductor 110.

[0331] The conductor 110 is provided on the insulator 140. The conductor 110 is used as the wiring PL, and can be provided in a planar shape, for example. As the conductor 110, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 110, for example, a highly conductive conductive material such as tungsten can be used. By using a highly conductive conductive material in this way, the conductivity of the conductor 110 can be improved, so that the conductor 110 can fully function as the wiring PL.

[0332] In addition, as the conductor 115, it is preferred to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide with silicon added may be used. Alternatively, for example, a structure in which tantalum nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which a first titanium nitride, tungsten, and a second titanium nitride are stacked in sequence may be used. By adopting such a structure, when an oxide insulator is used as the insulator 130, oxidation of the conductor 110 due to the insulator 130 can be suppressed. In addition, when an oxide insulator is used as the insulator 180, oxidation of the conductor 110 due to the insulator 180 can be suppressed.

[0333] The insulator 130 is provided on the conductor 115. The insulator 130 is provided in contact with the top surface and the side surface of the conductor 115. That is, the insulator 130 preferably covers the side end portion of the conductor 110. Thus, the conductor 115 and the conductor 120 can be prevented from being short-circuited.

[0334] Alternatively, a structure may be adopted in which the side ends of the insulator 130 are aligned with the side ends of the conductor 115. With such a structure, the insulator 130 and the conductor 115 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0335] It is preferable to use a material having a high relative dielectric constant, i.e., a so-called high-k material, as described in [Insulator] described later as the insulator 130. By using the high-k material as the insulator 130, the thickness of the insulator 130 can be increased to a level that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0336] In addition, as the insulator 130, it is preferred to stack an insulator composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the high-k material. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic destruction of the capacitor 100 can be suppressed.

[0337] In addition, a material having ferroelectricity may be used as the insulator 130. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X(X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0338] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the atomic number ratio of the element M1, the element M2 and the element M3 can be appropriately set.

[0339] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0340] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0341] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulator 130 can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0342] Metal oxides containing one or both of hafnium and zirconium are preferred because they can have ferroelectricity even if they are processed into a thin film of a few nm. Here, the thickness of the insulator 130 can be less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and further preferably less than 10 nm (typically, more than 2 nm and less than 9 nm). For example, the thickness is preferably more than 8 nm and less than 12 nm. By using a ferroelectric layer that can be thin-filmed, the capacitor 100 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that in this specification, etc., a material that can have ferroelectricity and is formed in a layered state is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0343] In addition, a metal oxide containing one or both of hafnium and zirconium is preferred because it can have ferroelectricity even when its area is small. For example, even if the area (occupied area) of the ferroelectric layer in top view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following may also have ferroelectric properties. In addition, sometimes the ferroelectric layer has an area (occupied area) of 10000nm when viewed from above. 2 Below or 1000nm 2 The area occupied by the capacitor 100 can be reduced by reducing the area of ​​the ferroelectric layer.

[0344] Ferroelectrics are insulators that are polarized internally when exposed to an external electric field and that maintain polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses the material as a dielectric. Nonvolatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, and the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as the capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0345] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 130 is any one or more selected from the group consisting of cubic system, tetragonal system, orthorhombic system, monoclinic system and hexagonal system. In addition, the insulator 130 may also have an amorphous structure. At this time, the insulator 130 may also have a composite structure of an amorphous structure and a crystal structure.

[0346] The conductor 120 is provided in a manner of contacting a portion of the top surface of the insulator 130. Fig.14A As shown, the side end of the conductor 120 is preferably located inside the side end of the conductor 115 in both the X direction and the Y direction. Note that in the structure where the insulator 130 covers the side end of the conductor 115, the side end of the conductor 120 may also be located outside the side end of the conductor 115.

[0347] As the conductor 120, a single layer or a stack of conductors described in [Conductor] to be described later can be used. As the conductor 120, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. In addition, for example, there can also be a structure in which tantalum nitride is stacked on titanium nitride. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230. By adopting such a structure, excessive oxidation of the conductor 120 due to the oxide semiconductor 230 can be suppressed. In addition, when an oxide insulator is used for the insulator 130, excessive oxidation of the conductor 120 due to the insulator 130 can be suppressed. Alternatively, as the conductor 120, for example, there can be a structure in which tungsten is stacked on titanium nitride.

[0348] In addition, the conductor 120 has a region in contact with the oxide semiconductor 230, so it is preferable to use a conductive material containing oxygen in the [conductor] described later. By using a conductive material containing oxygen as the conductor 120, the conductor 120 can maintain conductivity even if it absorbs oxygen. In addition, even if an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 can maintain conductivity, so it is preferred. As the conductor 120, for example, indium tin oxide (also called ITO), indium tin oxide with silicon added (also called ITSO), indium zinc oxide (also called IZO (registered trademark)), etc. can be used in a single layer or a stacked layer.

[0349] Since the insulator 180 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 180, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 180b contains at least silicon and oxygen.

[0350] Note that Fig. 13B and Fig. 13C The insulator 180 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 180 may also have a stacked-layer structure.

[0351] For example, Fig.15A and Fig. 15B As shown, the insulator 180 may also have a stacked structure of an insulator 180a and an insulator 180b on the insulator 180a.

[0352] As the insulator 180 b , the insulating material described above that can be used as the insulator 180 can be used.

[0353] As insulator 180a, an insulator having oxygen barrier properties described below is preferably used. In addition, due to oxygen in insulator 180b, conductor 110 is oxidized, and the resistance sometimes increases. By providing insulator 180a between insulator 180b and conductor 110, it is possible to prevent conductor 110 from being oxidized and the resistance from increasing.

[0354] When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. In addition, when a material having ferroelectricity is used as the insulator 130, the crystallinity of the material having ferroelectricity may be reduced due to the mixing of impurities such as hydrogen into the material having ferroelectricity. In view of this, it is preferable to suppress the mixing of impurities such as hydrogen into the insulator 130.

[0355] Therefore, as the insulator 180a, it is preferable to use an insulator having hydrogen barrier properties in the [insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen to the insulator 130 through the insulator 180b and the conductor 115. Since silicon nitride and silicon oxynitride each have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 180a. In this case, the insulator 180a contains at least silicon and nitrogen.

[0356] In addition, as the insulator 180a, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, hydrogen of the insulator 130 can be captured or fixed to reduce the hydrogen concentration of the insulator 130. As the insulator 180a, magnesium oxide, aluminum oxide, or hafnium oxide can be used. For example, as the insulator 180a, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0357] Note that Fig.15A and Fig. 15B The middle insulator 180 has a two-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 180 may have a three-layer or more stacked structure.

[0358] For example, when the insulator 180 has a three-layer stacked structure, in addition to the insulators 180a and 180b, an insulator may be provided between the insulator 180b and the conductor 115 and the insulator 130. As the insulator, an insulator that can be used as the insulator 180a may be used. Thus, diffusion of hydrogen into the insulator 130 through the insulator 180b can be suppressed.

[0359] In addition, if Fig.15A and Fig. 15BAs shown in FIG. 1 , the insulator 185 is preferably provided between the conductor 115 and the insulator 180. In addition, the insulator 185 is preferably provided in a manner of contacting the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115. Since the insulator 185 is provided along the opening 190, it is preferably formed by the ALD method.

[0360] As insulator 185, an insulator having hydrogen barrier properties in [insulator] described later is preferably used. Thus, diffusion of hydrogen from the outside of capacitor 100 through insulator 180 to insulator 130 can be suppressed. For example, silicon nitride or silicon nitride oxide can be used as insulator 185. In this case, insulator 185 contains at least silicon and nitrogen.

[0361] In addition, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later as the insulator 185. By adopting such a structure, hydrogen in the insulator 130 can be captured or fixed to reduce the hydrogen concentration of the insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used as the insulator 185. For example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used as the insulator 185.

[0362] Note that Fig.15A and Fig. 15B In the embodiment, the insulator 185 is provided in a manner of contacting the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited thereto. Fig. 15C and Fig.15D As shown, the insulator 185 may be provided in a manner that contacts a portion of the top surface of the insulator 180 a and the side surface of the insulator 180 b in the opening 190 .

[0363] Note that Fig. 13B and Fig. 13C In the embodiment, the conductor 120 is located inside the conductor 115 via the insulator 130, but the present invention is not limited thereto. For example, the conductor 120 may also be located outside the conductor 115 via the insulator 130.

[0364] For example, Fig.16A and Fig. 16B As shown, the insulator 130 has a region on the side surface of the outer side of the conductor 115 in addition to a region in contact with the inner side of the recess of the conductor 115 and a region in contact with the top surface of the conductor 115 .

[0365] The conductor 120 is provided so as to be embedded in the recess of the conductor 115 via the insulator 130. The conductor 120 has a region facing a part of the outer side surface of the conductor 115 via the insulator 130.

[0366] By adopting the above structure, the electrostatic capacitance per unit area can be further increased.

[0367] Note that Fig.16A and Fig. 16B As shown, an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulator 130 and the insulator 180 .

[0368] Alternatively, an insulator 182 may be provided on the conductor 120 and the insulator 130. Preferably, the insulator 182 is planarized so that the top surface of the conductor 120 is exposed. By planarizing the insulator 182, the transistor 200 can be appropriately formed on the capacitor 100.

[0369] Since the insulator 182 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator that can be used as the insulator 180 can be used.

[0370] Note that in Fig.16A and Fig. 16B In the case where the conductor 120 is provided so as to face the inner side and the outer side of the conductor 115 as shown and a sufficient electrostatic capacitance as a memory cell can be ensured, the insulator 180 may not be provided.

[0371] Fig. 16C and Fig.16D The storage device shown is Fig.16A and Fig. 16B The memory device shown is different in that the former is not provided with the insulator 180. By not providing the insulator 180, the manufacturing process of the memory device can be simplified.

[0372] [Transistor 200] like FIG. 13A to FIG. 13C As shown, the transistor 200 may include a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 arranged in contact with a top surface of the conductor 120 exposed in an opening 290, a side surface of the insulator 280 in the opening 290, a side surface of the conductor 240 in the opening 290, and at least a portion of a top surface of the conductor 240, an insulator 250 arranged in contact with the top surface of the oxide semiconductor 230, and a conductor 260 arranged in contact with the top surface of the insulator 250.

[0373] At least a part of the components of the transistor 200 is disposed in the opening 290 . Here, the bottom of the opening 290 is the top surface of the conductor 120 , and the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240 .

[0374] The side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 110. In this case, the opening 290 has a cylindrical shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved.

[0375] Note that this embodiment shows an example in which the shape of the opening 290 when viewed from above is circular, but the present invention is not limited to this. For example, the shape of the opening 290 when viewed from above may also be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 290 may be appropriately calculated based on the shape of the uppermost portion of the opening 290. For example, when the shape of the opening when viewed from above is a quadrangle, the maximum width of the opening 290 is preferably the length of the diagonal line of the uppermost portion of the opening 290.

[0376] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 arranged in the opening 290 reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided so as to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fit into the recess of the insulator 250 reflecting the shape of the opening 290.

[0377] here, Fig.17A yes Fig. 13B An enlarged view of the oxide semiconductor 230 and its vicinity in FIG. Fig. 17B It is a cross-sectional view including the conductor 240 on the XY plane.

[0378] like Fig.17A As shown, the oxide semiconductor 230 includes a region 230i, and regions 230na and 230nb provided so as to sandwich the region 230i.

[0379] The region 230na is a region in the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na is used as one of the source region and the drain region of the transistor 200. The region 230nb is a region in the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb is used as the other of the source region and the drain region of the transistor 200. Fig. 17BAs shown, the conductor 240 is in contact with the entire periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 may be formed on the entire periphery of the portion of the oxide semiconductor 230 formed in the same layer as the conductor 240.

[0380] The region 230i is a region between the region 230na and the region 230nb in the oxide semiconductor 230. At least a portion of the region 230i is used as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region between the conductor 120 and the conductor 240 of the oxide semiconductor 230. In addition, it can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that contacts the insulator 280 or a region near the insulator 280.

[0381] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120. Fig.17A , the dotted double arrow indicates the channel length L of the transistor 200. When viewed from a cross section, the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact. That is, the channel length L is equivalent to the length of the side surface of the opening 290 side of the insulator 280 when viewed from a cross section.

[0382] In the existing transistor, the channel length is set according to the exposure limit of the photolithography method, but in the present invention, the channel length can be set according to the thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of the photolithography method (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 200 becomes larger, so that the frequency characteristics can be improved. As a result, the read speed and write speed of the memory cell 150 can be improved, so a memory device with a high operating speed can be provided.

[0383] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. Therefore, compared with a conventional transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane, the occupied area of ​​the transistor 200 can be reduced. Thus, the memory device can be highly integrated, so that the memory capacity per unit area can be increased.

[0384] In addition, Fig. 17BSimilarly, on the XY plane including the channel formation region of the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in concentric circles. Therefore, the side surface of the conductor 260 arranged in the center is opposite to the side surface of the oxide semiconductor 230 via the insulator 250. In other words, the entire circle of the oxide semiconductor 230 becomes the channel formation region when viewed from above. At this time, for example, the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (the maximum diameter when the shape of the opening 290 when viewed from above is circular). Fig.17A and Fig. 17B In FIG. 1 , the double-pointed arrow indicates the maximum width D of the opening 290. Fig. 17B In FIG. 1 , a double-pointed arrow indicates a channel width W of the transistor 200 . By increasing the maximum width D of the opening 290 , the channel width per unit area can be increased, thereby increasing the on-state current.

[0385] When the opening 290 is formed by photolithography, the maximum width D of the opening 290 is set according to the exposure limit of the photolithography. In addition, the maximum width D of the opening 290 is set according to the thickness of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width D of the opening 290 is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, for example. Note that in the case where the shape of the opening 290 when viewed from above is circular, the maximum width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0386] In addition, in a memory device according to one embodiment of the present invention, the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200. The channel length L of the transistor 200 according to one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, and preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, the channel width W of the transistor 200. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0387] In addition, by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. As a result, the distance between the conductor 260 and the oxide semiconductor 230 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor 230 substantially uniformly.

[0388] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, it is preferred that the number of oxygen vacancies is small or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source region and the drain region. In addition, hydrogen near an oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0389] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V O The resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0390] Note that Fig. 13B and Fig. 13C In the embodiment, the opening 290 is provided in such a manner that the side wall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited thereto. For example, the side wall of the opening 290 may also have a tapered shape.

[0391] exist Fig.18A and Fig.18B In the storage device shown, the side wall of the opening 290 has an inverse tapered shape. Fig.18A and Fig.18B The plan view of the storage device shown can be referred to Fig.13A .

[0392] By making the sidewall of the opening 290 have a tapered shape, the coverage of the oxide semiconductor 230 or the insulator 250 can be improved, thereby reducing defects such as voids. For example, the angle formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 110 ( Fig.18A The angle θ1) shown is preferably greater than or equal to 45 degrees and less than or equal to 90 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 75 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 65 degrees.

[0393] Fig.18A and Fig.18BThe shape of the opening 290 shown is a truncated cone shape. In this case, the shape of the opening 290 when viewed from above is circular, and the shape of the opening 290 when viewed from a cross section is a trapezoid. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the opening provided in the conductor 240) is smaller than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductor 120 exposed in the opening 290). In this case, the maximum diameter of the opening 290 can be calculated based on the upper bottom surface of the truncated cone shape.

[0394] When the side wall of the opening 290 has a tapered shape, the channel length can be set using the thickness of the insulator 280 and the angle θ1 formed by the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 110. In addition, the length of the periphery of the oxide semiconductor 230 can be calculated, for example, based on the region opposite to the conductor 240 or the position of half the thickness of the insulator 280. Note that the perimeter of any position of the opening 290 can be set as the channel width of the transistor 200 as needed. For example, the perimeter of the lowermost portion of the opening 290 can be set as the channel width, or the perimeter of the uppermost portion of the opening 290 can be set as the channel width.

[0395] Although in Fig.18A and Fig.18B , a structure in which the side surface of the conductor 240 in the opening 290 is aligned with the side surface of the insulator 280 in the opening 290 is shown, but the present invention is not limited to this. For example, the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 may also be discontinuous. In addition, the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may also be different from each other. In addition, for example, the angle formed by the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 110 is preferably smaller than the angle θ1. By adopting such a structure, the coverage of the side surface of the conductor 240 in the opening 290 by the oxide semiconductor 230 is improved, and defects such as voids can be reduced.

[0396] like Fig.18A and Fig.18B As shown in FIG. 1 , the bottom of the conductor 260 located in the opening 290 has a flat region. Note that depending on the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view), the thickness of the insulator 280 (equivalent to the depth of the opening 290), the thickness of the oxide semiconductor 230, and the thickness of the insulator 250, etc., the bottom of the conductor 260 located in the opening 290 may not have a flat region. For example, Fig. 18C and Fig.18D As shown, sometimes the bottom of the conductor 260 located in the opening 290 has a needle-like shape. Fig. 18C and Fig.18D The plan view of the storage device shown can be referred to Fig.13A .

[0397] Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top (closer to the bottom of the conductor 260 located in the opening 290). In addition, the top of the needle-like shape may be an acute angle or a curved shape that bulges downward. In addition, the shape of the needle-like shape with an acute angle at the top may also be called a V-shape.

[0398] The region of the conductor 260 located in the opening 290 facing the oxide semiconductor 230 through the insulator 250 is used as a gate electrode. Therefore, the conductor 260 that is embedded in the opening 290 and has a needle-like bottom shape can also be called a needle-shaped gate. Fig.18A and Fig.18B As shown, even if the bottom of the conductor 260 is in a shape having a flat region, the conductor 260 may sometimes be referred to as a needle-shaped gate.

[0399] Note that Fig. 13B and Fig. 13C In the embodiment, the opening 190 is provided so that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited thereto. For example, like the opening 290, the side wall of the opening 190 may also have a tapered shape.

[0400] By making the side wall of the opening 190 have a tapered shape, the coverage of the conductor 115 or the insulator 130 can be improved, thereby reducing defects such as voids. For example, the angle formed by the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 ( Fig.18A The angle θ2) shown is preferably greater than or equal to 45 degrees and less than or equal to 90 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 75 degrees. Alternatively, it is preferably greater than or equal to 45 degrees and less than or equal to 65 degrees.

[0401] like Fig.18A and Fig.18B As shown in FIG. 1 , the bottom of the conductor 120 located in the opening 190 has a flat region. Note that depending on the maximum width of the opening 190 (the maximum diameter when the opening 190 is circular in plan view), the thickness of the insulator 180 (equivalent to the depth of the opening 190), the thickness of the conductor 115, and the thickness of the insulator 130, etc., the bottom of the conductor 120 located in the opening 190 may not have a flat region. For example, Fig. 18C and Fig.18D As shown, sometimes the bottom of the conductor 120 located in the opening 190 has a needle-like shape. Fig. 18C and Fig.18D The plan view of the storage device shown can be referred to Fig.13A .

[0402] In addition, when the insulator 180 and the insulator 280 are made of the same material, the angle θ1 and the angle θ2 are consistent or approximately consistent. Note that the angle θ1 and the angle θ2 may be different depending on the material used for each of the insulators 180 and the insulators 280, the method for forming each of the openings 190 and the openings 290, etc. For example, the angle θ1 may be greater than or less than the angle θ2. In addition, one of the angles θ1 and θ2 may be 90 degrees or a value close thereto.

[0403] Alternatively, for example, the side wall of the opening 290 may have a reverse tapered shape.

[0404] Here, the inverse cone shape refers to a shape having a side or upper portion that protrudes more than the bottom in a direction parallel to the substrate. At this time, the shape of the opening 290 is a truncated cone shape. In this case, the opening 290 has a circular shape when viewed from above, and has a trapezoidal shape when viewed from a cross section. In addition, the area of ​​the upper bottom surface of the truncated cone shape (for example, the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone shape (the top surface of the conductor 120 exposed in the opening 290). By adopting this structure, the area in which the oxide semiconductor 230 contacts the conductor 120 can be expanded. Similarly, the side wall of the opening 190 may also have an inverse cone shape.

[0405] like Fig. 13B and Fig. 13C As shown, a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240. Fig. 13B 2 shows a structure in which the oxide semiconductor 230 is separated in the X direction, but the present invention is not limited thereto. Fig.19A and Fig.19B As shown in FIG. 1 , the oxide semiconductor 230 may also extend in the X direction. Fig.19A and Fig.19B The structure shown is also separated in the Y direction (refer to Fig.19C ).

[0406] also, Fig. 13C The structure in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240 is shown. Note that the present invention is not limited to this. For example, a structure in which the side end of the oxide semiconductor 230 is aligned with the side end of the conductor 240 in the Y direction may be adopted. Alternatively, a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be adopted.

[0407] The band gap of the metal oxide used as the oxide semiconductor 230 is preferably greater than 2 eV, and more preferably greater than 2.5 eV. By using a metal oxide with a large band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, the frequency of the refresh operation required for a general DRAM is about 1 time / 60 msec, and the frequency of the refresh operation of a memory device of one embodiment of the present invention can be about 1 time / 10 sec, that is, the frequency of the refresh line operation can be achieved more than 10 times or more than 100 times. In addition, by using a memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0408] Alternatively, as the oxide semiconductor 230 , a single layer or a stacked layer of the metal oxide described in Embodiment 1 can be used.

[0409] As the oxide semiconductor 230, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0410] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0411] As an analysis of the composition of the metal oxide used for the oxide semiconductor 230, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a plurality of the above methods can be combined for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content. In addition, it is sometimes difficult to quantify element M or element M cannot be detected.

[0412] The metal oxide can be formed appropriately by an atomic layer deposition (ALD: Atomic Layer Deposition) method.

[0413] Alternatively, the metal oxide may be formed by sputtering or CVD. Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content in the metal oxide after formation is sometimes reduced to about 50% of the zinc content in the sputtering target.

[0414] The oxide semiconductor 230 preferably has crystallinity (also referred to as "having a crystal portion"). Examples of the crystalline oxide semiconductor (also referred to as "crystalline oxide semiconductor") include CAAC-OS (c-axis alignedcrystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, and single crystal oxide semiconductor. CAAC-OS or nc-OS is preferably used as the oxide semiconductor 230, and CAAC-OS is particularly preferably used.

[0415] The CAAC-OS preferably has a plurality of layered crystal regions and the c-axis thereof is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 230 preferably has layered crystals that are roughly parallel to the side walls of the opening 290, and in particular, layered crystals that are roughly parallel to the side surfaces of the insulator 280. By adopting such a structure, the layered crystals of the oxide semiconductor 230 are roughly parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.

[0416] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0417] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0418] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 230, oxygen can be suppressed from being extracted from the oxide semiconductor 230 by the source electrode or the drain electrode. Therefore, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so that the transistor 200 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

[0419] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0420] Note that Fig. 13B and Fig. 13C The oxide semiconductor 230 is shown as a single-layer structure, but the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted.

[0421] For example, Fig. 20A and Fig. 20B As shown, the oxide semiconductor 230 may have a stacked-layer structure of an oxide semiconductor 230 a and an oxide semiconductor 230 b on the oxide semiconductor 230 a .

[0422] The conductivity of the material used for the oxide semiconductor 230 a is preferably different from the conductivity of the material used for the oxide semiconductor 230 b .

[0423] For example, the oxide semiconductor 230a may use a material having a higher conductivity than the oxide semiconductor 230b. By using a material having a higher conductivity for the conductor 120 used as a source electrode or a drain electrode and the oxide semiconductor 230a in contact with the conductor 240, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor having a large on-state current.

[0424] Here, when a material with high conductivity is used for an oxide semiconductor 230b disposed on one side of a conductor 260 used as a gate electrode, the threshold voltage of the transistor is sometimes caused to drift, so that the drain current (hereinafter also recorded as the cut-off current) flowing when the gate voltage is 0V becomes larger. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage is sometimes reduced. Therefore, the oxide semiconductor 230b preferably uses a material with a lower conductivity than the oxide semiconductor 230a. Thus, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cut-off current can be realized. Note that sometimes the cut-off current is recorded as normally closed.

[0425] As described above, by making the oxide semiconductor 230 have a stacked structure and using a material having higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally-off transistor with a large on-state current can be realized. Thus, a memory device having both low power consumption and high performance can be realized.

[0426] In addition, the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b. By increasing the carrier concentration of the oxide semiconductor 230a, the conductivity becomes higher, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. By reducing the carrier concentration of the oxide semiconductor 230b, the conductivity becomes lower, thereby realizing a normally-off transistor.

[0427] Here, although an example is shown in which a material having a higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a, one embodiment of the present invention is not limited thereto. The oxide semiconductor 230a may also use a material having a lower conductivity than the oxide semiconductor 230b. The carrier concentration of the oxide semiconductor 230a may be lower than the carrier concentration of the oxide semiconductor 230b.

[0428] The band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0429] The band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, thereby realizing a transistor with a large on-state current. In addition, in the case where the transistor 200 is an n-channel transistor, the threshold voltage can be increased, thereby realizing a normally closed transistor.

[0430] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0431] As described above, the band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from the composition of the second metal oxide, the band gap can be controlled. For example, the content of element M of the first metal oxide is preferably lower than the content of element M of the second metal oxide. Specifically, in the case where the first metal oxide and the second metal oxide use In-M-Zn oxide, the composition of the first metal oxide can be set to In:M:Zn=1:1:1 [atomic number ratio] or thereabouts, and the composition of the second metal oxide can be set to In:M:Zn=1:3:2 [atomic number ratio] or thereabouts. As element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0432] The first metal oxide may not contain the element M. For example, the first metal oxide used for the oxide semiconductor 230a may be an In-Zn oxide, and the second metal oxide used for the oxide semiconductor 230b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide may be set to In:Zn=1:1 [atomic ratio] or thereabouts or In:Zn=4:1 [atomic ratio] or thereabouts, and the composition of the second metal oxide may be set to In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts.

[0433] Here, although an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, one embodiment of the present invention is not limited thereto. The content of the element M of the first metal oxide may also be higher than the content of the element M of the second metal oxide. In addition, as long as the composition of the first metal oxide and the second metal oxide is different, the content of elements other than the element M of the first metal oxide and the second metal oxide may also be different.

[0434] The thickness of the oxide semiconductor 230 is preferably greater than or equal to 1 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm, and less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 12 nm, or less than or equal to 10 nm.

[0435] The thickness of each layer constituting the oxide semiconductor 230 (here, the oxide semiconductor 230a and the oxide semiconductor 230b) may be determined so that the thickness of the oxide semiconductor 230 is within the above range. The thickness of the oxide semiconductor 230a may be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within the required range. In addition, the thickness of the oxide semiconductor 230b may be determined so that the threshold voltage of the transistor is within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

[0436] Fig. 20A and Fig. 20B Although the oxide semiconductor 230 has an example of a stacked-layer structure of two layers, namely, the oxide semiconductor 230 a and the oxide semiconductor 230 b , the present invention is not limited thereto and may have a stacked-layer structure of three or more layers.

[0437] When the oxide semiconductor 230 has a three-layer stacked structure, for example, the following structure may be adopted: a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, and a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto may be provided in order from the conductor 120 side. By adopting such a structure, the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with less unevenness can be realized.

[0438] A single layer or a stack of insulators described in [Insulator] described later can be used as the insulator 250. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0439] In addition, a material having a high relative dielectric constant, that is, a so-called high-k material described in [Insulator] described later, may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0440] The thickness of the insulator 250 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulator 250 may be a region having the above thickness.

[0441] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0442] like Fig. 13B and Fig. 13C As shown, a portion of the insulator 250 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. At this time, the insulator 250 preferably covers the side end of the oxide semiconductor 230. Thus, the conductor 260 and the oxide semiconductor 230 can be prevented from being short-circuited. In addition, the insulator 250 preferably covers the side end of the conductor 240. Thus, the conductor 260 and the conductor 240 can be prevented from being short-circuited.

[0443] Note that Fig. 13B and Fig. 13C The insulator 250 is shown as a single layer, but the present invention is not limited thereto. The insulator 250 may also have a stacked structure.

[0444] For example, Fig. 20A and Fig. 20BAs shown, the insulator 250 may also have a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0445] The insulator 250b preferably uses a material with a low relative dielectric constant as described in [Insulator] to be described later. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 250b contains at least oxygen and silicon. By adopting this structure, the parasitic capacitance between the conductor 260 and the conductor 240 can be reduced. In addition, it is preferred that the impurity concentration of water, hydrogen, etc. in the insulator 250b is reduced.

[0446] The insulator 250a preferably uses an insulator having oxygen barrier properties as described in [Insulator] to be described later. The insulator 250a has a region in contact with the oxide semiconductor 230. When the insulator 250a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the oxide semiconductor 230 during heat treatment or the like. Therefore, the formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. As a result, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved. As the insulator 250a, for example, aluminum oxide is preferably used. In this case, the insulator 250a contains at least oxygen and aluminum.

[0447] The insulator 250c preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230. Silicon nitride has high hydrogen barrier properties and is therefore preferably used for the insulator 250c. In this case, the insulator 250c contains at least nitrogen and silicon.

[0448] The insulator 250c may also have oxygen barrier properties. The insulator 250c is provided between the insulator 250b and the conductor 260. Thus, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260 and oxidation of the conductor 260 can be suppressed. In addition, a reduction in the amount of oxygen supplied to the region 230i can be suppressed.

[0449] In addition, an insulator may be provided between the insulator 250b and the insulator 250c. The insulator preferably uses an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By providing the insulator, hydrogen contained in the oxide semiconductor 230 can be captured or fixed more efficiently. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced. As the insulator, for example, hafnium oxide is preferably used. In this case, the insulator contains at least oxygen and hafnium. In addition, the insulator may also have an amorphous structure.

[0450] In order to realize the miniaturization of transistor 200, the thickness of insulators 250a to 250c is preferably thin, and it is preferable to set their thicknesses within the above range. Typically, the thicknesses of insulator 250a, insulator 250b, insulator having the function of capturing or fixing hydrogen, and insulator 250c are set to 1nm, 2nm, 2nm, and 1nm, respectively. By adopting such a structure, even if transistor 200 is miniaturized or highly integrated, it can have good electrical characteristics.

[0451] exist Fig. 20A and Fig. 20B The insulator 250 has a three-layer laminated structure of insulators 250a to 250c, but the present invention is not limited thereto. The insulator 250 may also have a laminated structure of two or more layers. At this time, each layer included in the insulator 250 is preferably appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.

[0452] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 260. For example, a highly conductive material such as tungsten can be used as the conductor 260.

[0453] In addition, as the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thus, the decrease in the conductivity of the conductor 260 can be suppressed.

[0454] Note that Fig. 13B and Fig. 13C The conductor 260 is shown as a single layer, but the present invention is not limited thereto. The conductor 260 may also have a stacked structure. For example, Fig. 20A and Fig. 20B As shown in FIG. 1 , the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a. In this case, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By stacking tungsten in this way, the conductivity of the conductor 260 may be improved, and the conductor 260 may fully function as the wiring WL.

[0455] exist Fig. 20A and Fig. 20B The conductor 260 has a two-layer laminate structure of the conductor 260a and the conductor 260b, but the present invention is not limited thereto. The conductor 260 may also have a three-layer or more laminate structure.

[0456] exist Fig. 13B and Fig. 13C The conductor 260 is provided in a manner embedded in the opening 290, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the concave portion is located in the opening 290. In this case, the concave portion may be filled with an inorganic insulating material or the like.

[0457] In addition, if Fig. 13B and Fig. 13C As shown, a portion of the conductor 260 is preferably located outside the opening 290, that is, on the conductor 240 and the insulator 280. Fig. 13B As shown, the side end of the conductor 260 is preferably located inside the side end of the oxide semiconductor 230. This can prevent the conductor 260 from being short-circuited with the oxide semiconductor 230. In addition, the side end of the conductor 260 can be aligned with the side end of the oxide semiconductor 230 or can be located outside the side end of the oxide semiconductor 230.

[0458] The conductor 120 may be provided in the manner described in [Capacitor 100 ].

[0459] in addition, Fig. 13B and Fig. 13C Although the top surface of the conductor 120 is flat, the present invention is not limited thereto. For example, a structure may be adopted in which a concave portion overlapping the opening 290 is formed on the top surface of the conductor 120. By adopting a structure in which at least a part of the oxide semiconductor 230, the insulator 250, and the conductor 260 is formed so as to be embedded in the concave portion, the gate electric field of the conductor 260 can be easily applied to the conductor 120 near the oxide semiconductor 230.

[0460] A single layer or a stack of conductors described in [Conductor] described later can be used as the conductor 240. For example, a highly conductive material such as tungsten can be used as the conductor 240.

[0461] As with the conductor 260, the conductor 240 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting such a structure, excessive oxidation of the conductor 240 due to the oxide semiconductor 230 can be suppressed.

[0462] Alternatively, for example, tungsten may be stacked on titanium nitride. By stacking tungsten in this manner, the conductivity of the conductor 240 can be improved, and the conductor 240 can fully function as the wiring BL.

[0463] Furthermore, when the conductor 240 has a stacked structure of a first conductor and a second conductor, for example, the first conductor may be formed of a highly conductive conductive material and the second conductor may be formed of a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress diffusion of oxygen in the insulator 250 into the first conductor of the conductor 240. For example, tungsten may be used as the first conductor of the conductor 240 and indium tin oxide to which silicon is added may be used as the second conductor of the conductor 240.

[0464] When the oxide semiconductor 230 is in contact with the conductor 120, a metal compound or oxygen vacancy is formed, and the region 230na of the oxide semiconductor 230 is reduced in resistance. By reducing the resistance of the oxide semiconductor 230 in contact with the conductor 120, the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced. Similarly, when the oxide semiconductor 230 is in contact with the conductor 240, the region 230nb of the oxide semiconductor 230 is reduced in resistance. Thus, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0465] Insulator 140 and insulator 280 are used as interlayer films, so their relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulator 140 and insulator 280, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0466] In addition, the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0467] In addition, as the insulator 280 disposed near the channel formation region, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is preferably used. By heating the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and V O H. Thus, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

[0468] In addition, an insulator having a function of capturing or fixing hydrogen in the "insulator" described later may be used as the insulator 280. By adopting such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed to reduce the hydrogen concentration of the oxide semiconductor 230. Magnesium oxide, aluminum oxide, or the like can be used as the insulator 280.

[0469] Note that Fig. 13B and Fig. 13C The insulator 280 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 280 may also have a stacked-layer structure.

[0470] For example, Fig.21A and Fig.21B As shown, the insulator 280 may also have a stacked structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.

[0471] The insulator 280b preferably uses an insulator containing oxygen. The insulator 280b preferably has a region having a higher oxygen content than at least one of the insulator 280a and the insulator 280c. In particular, the insulator 280b preferably has a region having a higher oxygen content than the insulator 280a and the insulator 280c, respectively. When the oxygen content of the insulator 280b is high, an i-type region is easily formed in the region in contact with the insulator 280b in the oxide semiconductor 230 and in the vicinity thereof.

[0472] The insulator 280 b is preferably a film that releases oxygen by heating. Since the insulator 280 b releases oxygen due to heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, especially to the channel formation region of the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0473] For example, oxygen can be supplied to the insulator 280 b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulator 280 b by sputtering in an oxygen atmosphere. The oxide film can then be removed.

[0474] The insulator 280b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD). In particular, when sputtering is used, hydrogen gas does not need to be used as a deposition gas, thereby achieving a film with a very low hydrogen content. Therefore, the semiconductor 230 can be suppressed from being supplied with hydrogen to achieve stabilization of the electrical characteristics of the transistor 200.

[0475] When the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and V OThe influence of H on the power supply characteristics and reliability is particularly great. By supplying oxygen from the insulator 280 b to the oxide semiconductor 230, oxygen vacancies and V can be suppressed at least in the region of the oxide semiconductor 230 that is in contact with the insulator 280 b. O H increases. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0476] Insulator 280a and insulator 280c preferably use an insulator having oxygen barrier properties as described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of oxygen in insulator 280b to the substrate side through insulator 280a and to the insulator 250 side through insulator 280c due to heating. In other words, by clamping insulator 280b above and below using insulator 280a and insulator 280c, which are not easy to diffuse oxygen, oxygen in insulator 280b can be confined. Thus, oxygen can be effectively supplied to oxide semiconductor 230.

[0477] In addition, due to the oxygen in the insulator 280b, the conductor 120 and the conductor 240 are oxidized, and sometimes the resistance becomes higher. By providing the insulator 280a between the insulator 280b and the conductor 120, it is possible to suppress the conductor 120 from being oxidized and the resistance from becoming higher. In addition, by providing the insulator 280c between the insulator 280b and the conductor 240, it is possible to suppress the conductor 240 from being oxidized and the resistance from becoming higher. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and the oxygen vacancies in the oxide semiconductor 230 can be reduced.

[0478] In addition, in the oxide semiconductor 230, the amount of oxygen supplied to the region in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in contact with the insulator 280b. As a result, the region in contact with the insulator 280a and the region in contact with the insulator 280c of the oxide semiconductor 230 are sometimes reduced in resistance. That is, by adjusting the thickness of the insulator 280a, the range of the region 230na used as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb used as the other of the source region and the drain region can be controlled.

[0479] As described above, since the source region and the drain region can be controlled by the thickness of the insulator 280 a and the insulator 280 c , the thickness of the insulator 280 a and the insulator 280 c may be appropriately set according to the characteristics required for the transistor 200 .

[0480] For example, Fig.21A and Fig.21B As shown, the thickness of the insulator 280a and the thickness of the insulator 280c may also be substantially the same. Fig. 21C and Fig.21D As shown, the thickness of the insulator 280c may also be smaller than the thickness of the insulator 280a. Fig. 21C and Fig.21D The structure shown can make the region 230na close to the bottom of the conductor 260 in the opening 290. In this case, it can be said that the range of the region 230i is reduced. As a result, the on-state current of the transistor 200 can be increased.

[0481] In addition, Fig. 21C and Fig.21D , a structure in which an insulator 280c is provided on a flattened insulator 280b is shown, but the present invention is not limited thereto. For example, the insulator 280c may be deposited without performing a flattening treatment on the insulator 280b. By not performing a flattening treatment, the yield rate can be improved while reducing the manufacturing cost. In addition, the insulator 280a, the insulator 280b, and the insulator 280c may be continuously deposited without being exposed to the atmospheric environment. By depositing without being exposed to the atmospheric environment, impurities or moisture from the atmospheric environment may be prevented from adhering to the insulators 280a to 280c, thereby keeping the vicinity of the interface between the insulator 280a and the insulator 280b and the vicinity of the interface between the insulator 280b and the insulator 280c clean.

[0482] Insulator 280a and insulator 280c preferably use an insulator having hydrogen barrier properties described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through insulator 280a or insulator 280c to oxide semiconductor 230. Since silicon nitride film and silicon oxynitride film have the characteristics of less release of impurities (e.g., water and hydrogen) from themselves and less penetration of oxygen and hydrogen, respectively, they can be applied to insulator 280a and insulator 280c. Note that insulator 280a and insulator 280c can use the same material or different materials.

[0483] In addition, as the insulator 280a, it is preferable to use an insulator having the function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, it is possible to suppress the diffusion of hydrogen from the bottom of the insulator 280a to the oxide semiconductor 230, and to capture or fix the hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration of the oxide semiconductor 230. In addition, it is possible to suppress the diffusion of hydrogen from the top of the insulator 280a to the insulator 130, and to capture or fix the hydrogen in the insulator 130, thereby reducing the hydrogen concentration of the insulator 130. As the insulator 280a, magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used. In addition, for example, as the insulator 280a, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0484] The thickness of insulator 280a is preferably smaller than the thickness of insulator 280b. In addition, the thickness of insulator 280c is preferably smaller than the thickness of insulator 280b. The thickness of insulator 280a and insulator 280c is preferably greater than 1 nm and less than 15 nm, more preferably greater than 2 nm and less than 10 nm, further preferably greater than 3 nm and less than 7 nm, and further preferably greater than 3 nm and less than 5 nm. The thickness of insulator 280b is preferably greater than 3 nm and less than 30 nm, more preferably greater than 5 nm and less than 20 nm, and further preferably greater than 7 nm and less than 15 nm. By setting the thickness of insulators 280a to 280c within the above range, oxygen vacancies in the oxide semiconductor 230, especially oxygen vacancies in the channel formation region, can be reduced.

[0485] For example, it is preferable that the insulator 280a and the insulator 280c use silicon nitride, and the insulator 280b use silicon oxide. In this case, the insulator 280a and the insulator 280c contain at least silicon and nitrogen. In addition, the insulator 280b contains at least silicon and oxygen.

[0486] Notice, Fig.22A and Fig. 22B The insulator 280 is shown to have a three-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 280 may have a two-layer stacked structure or a four-layer stacked structure or more.

[0487] The insulator 283 preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 250 to the oxide semiconductor 230. Since the silicon nitride film and the silicon oxynitride film have the characteristics of less release of impurities (for example, water and hydrogen) from themselves and less penetration of oxygen and hydrogen, they can be applied to the insulator 283.

[0488] In addition, as the insulator 283, it is preferable to use an insulator having a function of capturing or fixing hydrogen in the [insulator] described later. By adopting such a structure, it is possible to suppress the diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230, and it is possible to capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration of the oxide semiconductor 230. As the insulator 283, magnesium oxide, aluminum oxide, or hafnium oxide can be used. For example, as the insulator 283, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0489] Although Fig. 13B and Fig. 13C Although the structure of the region where the top surface of the conductor 120 contacts the bottom surface of the oxide semiconductor 230 is shown, the present invention is not limited thereto. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230 .

[0490] For example, Fig.22A and Fig. 22B As shown, a conductor 125 may be provided between the conductor 120 and the oxide semiconductor 230. As the conductor 125, it is preferable to use a conductive material containing oxygen in the [Conductor] described later. By using a conductive material containing oxygen as the conductor 125, the conductor 125 can maintain conductivity even if it absorbs oxygen. In addition, diffusion of oxygen in the oxide semiconductor 230 to the conductor 120 can be suppressed. As the conductor 125, for example, indium tin oxide, indium tin oxide added with silicon, indium zinc oxide, etc. can be used in a single layer or a stacked layer.

[0491] Fig. 13B and Fig. 13C The structure in which the conductor 240 is provided on the insulator 280 is shown. In addition, the structure in which the insulator 250 has a region in contact with the top surface of the insulator 280 in a region not overlapping with the conductor 240 is also shown. Note that the present invention is not limited to this.

[0492] For example, Fig. 23B and Fig.23C As shown, the conductor 240 may be embedded in the insulator 281. In this case, the height of the top surface of the conductor 240 is preferably consistent with the height of the top surface of the insulator 281. By adopting this structure, the physical distance from the conductor 260 to the conductor 240 (especially the side end of the conductor 240) can be increased, and the conductor 260 and the conductor 240 can be prevented from short-circuiting. Note that Fig.23A yes Fig. 23B and Fig.23C A plan view of the storage device is shown.

[0493] Since the insulator 281 is used as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 281, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used.

[0494] Here, it is explained FIG. 13A to FIG. 13CAn example of a method for manufacturing a memory cell 150 is shown. First, an insulator 180 is formed on a conductor 110 and processed to form an opening 190 that reaches the conductor 110. Next, a conductor 115 is formed in contact with the side surface of the insulator 180 at the opening 190, an insulator 130 is formed on the conductor 115, a conductor 120 is formed on the insulator 130, an insulator 280 is formed on the conductor 120, and a conductor 240 is formed on the insulator 280. Then, the conductor 240 and the insulator 280 are processed to form an opening 290 that reaches the conductor 120. Next, an oxide semiconductor 230 is formed in contact with the top surface of the conductor 120, the side surface of the insulator 280, and the top surface and side surface of the conductor 240 at the opening 290, an insulator 250 is formed on the oxide semiconductor 230, and a conductor 260 is formed on the insulator 250. Thus, the memory cell 150 can be formed. Here, the oxide semiconductor 230 is preferably formed by the metal oxide deposition method described in Embodiment 1. Specifically, the oxide semiconductor 230 is formed by repeatedly performing a deposition step using an ALD method and an impurity removal process in an oxygen-containing atmosphere. Thus, the crystallinity of the oxide semiconductor 230 can be improved, and a transistor with good reliability can be manufactured.

[0495] <Constituent Materials of Storage Device> The following describes constituent materials that can be used for the memory device. Note that for metal oxides that can be used for the oxide semiconductor 230 , refer to Embodiment 1.

[0496] [Substrate] As a substrate for forming the transistor 200 and the capacitor 100, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0497] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0498] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin filmization of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferred to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0499] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0500] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0501] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0502] In addition, an insulator such as a gate insulator that contacts a semiconductor or an insulator that is disposed near a semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen contacts a semiconductor layer or when an insulator having a region containing excess oxygen is disposed near a semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0503] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0504] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0505] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0506] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0507] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise stated, the impurities recorded as corresponding substances refer to impurities in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0508] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0509] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. As conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0510] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0511] In addition, a plurality of conductors formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0512] In addition, when a metal oxide is used in the channel formation region of the transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0513] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0514] [Other semiconductor materials] The oxide semiconductor 230 may be referred to as a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As a semiconductor, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0515] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0516] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0517] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0518] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0519] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as a semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0520] <Storage Device Configuration Example 2> The memory cell 150 including the transistor 200 and the capacitor 100 can be used as a memory cell of a memory device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the storage content can be maintained for a long time by using it in a memory device. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, since the frequency characteristics of the transistor 200 are high, high-speed reading and writing of the memory device can be performed.

[0521] use Fig.24A and Fig. 24B An example of a memory device in which two memory cells 150 (hereinafter referred to as a memory cell 150 a and a memory cell 150 b ) are connected to the same wiring will be described. Fig.24A is a plan view of the storage device. Fig. 24B It is along Fig.24A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.24A Some components are omitted in the plan view.

[0522] Here, Fig.24A and Fig. 24B The memory cell 150a and the memory cell 150b shown in the figure have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. Fig.24A and Fig. 24B In the storage device shown, the same reference numerals are used for components having the same functions as those of the storage device shown in Fig. 13. In this section, the components of the storage device may also use the materials described in detail in <Configuration Example 1 of Storage Device>.

[0523] like Fig.24A and Fig. 24B As shown, the conductor 260 used as the wiring WL is provided in the memory cell 150a and the memory cell 150b respectively. In addition, the conductor 240 used as a part of the wiring BL is provided in both the memory cell 150a and the memory cell 150b. In other words, the conductor 240 contacts the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.

[0524] Here, Fig.24A and Fig. 24B The memory device shown includes a conductor 245 and a conductor 246 which are electrically connected to the memory cells 150a and 150b and serve as plugs (which may also be referred to as connection electrodes). The conductor 245 is disposed in openings formed in the insulators 180, 280, and 140 and is in contact with the bottom surface of the conductor 240. In addition, the conductor 246 is disposed in openings formed in the insulators 287, 283, and 250 and is in contact with the top surface of the conductor 240. In addition, as the conductor 245 and the conductor 246, the conductive material that can be used for the conductor 240 can be used.

[0525] Since the insulator 287 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 287, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in the above-mentioned [Insulator] can be used.

[0526] In addition, the concentration of impurities such as water and hydrogen in the insulator 287 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230 .

[0527] Conductors 245 and 246 are used as plugs or wirings for electrically connecting circuit elements, wirings, electrodes or terminals such as switches, transistors, capacitors, inductors, resistors and diodes to memory cells 150a and 150b. For example, the following structure can be adopted: conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 24, and conductor 246 is electrically connected to the same memory device (not shown) provided on the memory device shown in FIG. 24. In this case, conductors 245 and 246 are used as part of wiring BL. In this way, by providing a memory device above or below the memory device shown in FIG. 24, the storage capacity per unit area can be increased.

[0528] In addition, the memory cell 150a and the memory cell 150b are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged linearly symmetrically with the conductor 245 and the conductor 246 sandwiched therebetween. Here, the conductor 240 serves as the other of the source electrode and the drain electrode of the transistor 200a and the other of the source electrode and the drain electrode of the transistor 200b. In addition, the transistor 200a and the transistor 200b share the conductor 245 and the conductor 246 used as the plug. In this way, by adopting the above structure as the connection relationship between the two transistors and the plug, a storage device that can achieve miniaturization or high integration can be provided.

[0529] In addition, the conductor 110 used as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in both of the memory cell 150a and the memory cell 150b. Fig. 24B As shown, the conductor 110 is disposed in a manner separated from the conductor 245 to prevent the conductor 110 and the conductor 245 from being short-circuited.

[0530] In addition, by arranging the memory cells 150 in a matrix and three-dimensional manner, a memory cell array can be formed. As an example of a memory cell array, Fig.25A and Fig.25B An example of a storage device in which four×two×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction is shown. Fig.25A is a plan view of the storage device. Fig.25B It is along Fig.25A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.25A Some components are omitted in the plan view.

[0531] Here, Fig.25A and Fig.25B The memory cells 150a to 150d shown have the same structure as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, the memory cell 150b includes a capacitor 100b and a transistor 200b, the memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d. Fig.25A and Fig.25B In the storage device shown, the same reference numerals are used for components having the same functions as those of the storage device shown in Fig. 13. In this section, the components of the storage device may also use the materials described in detail in <Configuration Example 1 of Storage Device>.

[0532] Hereinafter, a storage device composed of the storage cells 150a to 150d will be referred to as a memory cell. Fig.25A and Fig.25B The memory device shown includes memory cells 160 [1, 1] to 160 [2, 4]. In addition, memory cells 160 [1, 1] to 160 [2, 4] are sometimes collectively referred to as memory cells 160 below. Memory cell 160 [1, 2] is disposed on memory cell 160 [1, 1], memory cell 160 [1, 3] is disposed on memory cell 160 [1, 2], and memory cell 160 [1, 4] is disposed on memory cell 160 [1, 3]. Memory cell 160 [2, 1] is adjacent to memory cell 160 [1, 1] in the Y direction. Memory cell 160 [2, 2] is disposed on memory cell 160 [2, 1], memory cell 160 [2, 3] is disposed on memory cell 160 [2, 2], and memory cell 160 [2, 4] is disposed on memory cell 160 [2, 3].

[0533] like Fig.25B As shown, in the memory cell 160, the memory cell 150c is arranged outside the memory cell 150a and the memory cell 150d is arranged outside the memory cell 150b with the conductor 245 as the center. In other words, it can be said that the memory cell 160 is a memory device in which the memory cell 150c is arranged adjacent to the memory cell 150a and the memory cell 150d is arranged adjacent to the memory cell 150b in the memory device shown in FIG. 24 .

[0534] like Fig.25A and Fig.25B As shown, the memory cells 150 adjacent to each other in the Y direction share the conductor 260 used as the wiring WL. In addition, the conductor 240 used as a part of the wiring BL is shared in the same memory cell. In other words, the conductor 240 is in contact with the oxide semiconductor 230 in each of the memory cells 150a to 150d.

[0535] The conductor 245 is disposed between the conductors 240 included in the memory cells adjacent to each other in the Z direction. Fig.25B As shown in FIG. 25 , the conductor 245 is provided in a manner in contact with the top surface of the conductor 240 in the memory cell 160 [1, 1] and the bottom surface of the conductor 240 in the memory cell 160 [1, 2]. In this way, the conductor 240 and the conductor 245 provided in each memory cell 160 form a wiring BL. The conductor 245 is electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 25 . In this way, by stacking a plurality of memory cells in the memory device shown in FIG. 25 , the storage capacity per unit area can be increased.

[0536] In addition, the memory cell 150a and the memory cell 150c and the memory cell 150b and the memory cell 150d are linearly symmetrical with the perpendicular bisector of the dot-dash line A1-A2 as the symmetry axis. Therefore, the transistor 200a and the transistor 200c and the transistor 200b and the transistor 200d are also arranged linearly symmetrically with the conductor 245 sandwiched therebetween. Here, the conductor 240 is used as the other of the source electrode and the drain electrode of the transistor 200a to the transistor 200d. In addition, the transistor 200a to the transistor 200d share the conductor 245 used as a plug. In this way, by adopting the above structure as the connection relationship between the four transistors and the plug, a storage device capable of miniaturization or high integration can be provided.

[0537] As shown in FIG. 25, by stacking a plurality of memory cells, the cells can be configured in an integrated manner without increasing the occupied area of ​​the memory cell array. That is, a 3D memory cell array can be constructed. Note that FIG. 25 shows an example of a structure having four stacked layers including two memory cells, but the present invention is not limited to this. In the memory device, one layer including at least one memory cell 150 can be included, and two or more of the above layers can be stacked.

[0538] 25 shows an example of a structure in which a conductor 245 serving as a plug is arranged between memory cells 150. In other words, FIG. 25 shows a structure in which a conductor 245 serving as a plug is arranged inside a memory cell 160. Note that the present invention is not limited thereto. The conductor 245 may be arranged outside a memory cell.

[0539] As an example of a memory cell array, Fig.26A and Fig.26B An example of a storage device is shown in which three×three×four storage cells 150 are arranged in the X direction, the Y direction, and the Z direction. Fig.26A is a plan view of the storage device. Fig.26B It is along Fig.26A The cross-sectional view of the portion of the dotted line A1-A2 in FIG. Fig.26A Some components are omitted in the plan view.

[0540] Fig.26A and Fig.26B The memory device shown has a structure in which m (m is an integer greater than or equal to 2) layers including memory cells 150 are stacked. Fig.26BIn the above, the layer disposed at the first layer (the bottom layer) is referred to as layer 170[1], the layer disposed at the second layer is referred to as layer 170[2], the layer disposed at the (m-1)th layer is referred to as layer 170[m-1], and the layer disposed at the mth layer (the top layer) is referred to as layer 170[m]. That is, the storage device of one embodiment of the present invention may include a plurality of layers including the storage unit 150, and may have a structure in which a plurality of layers are stacked.

[0541] like Fig.26A and Fig.26B As shown, the conductor 245 may also be provided outside the memory cell. In addition, the conductor 245 may also be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2]. In addition, the wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. That is, the wiring may be formed in the same process as the conductor 110.

[0542] Note that although Fig.26A and Fig.26B The structure in which the conductor 245 is electrically connected to the wiring provided in the upper layer of the layer including the conductor 245 is shown, but the present invention is not limited to this. For example, the conductor 245 may also be electrically connected to the wiring provided in the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may also be electrically connected to the wiring provided in the layer 170[1]. In addition, the wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[1]. That is, the wiring can be formed in the same process as the conductor 110.

[0543] Here, Fig.27A Show Fig.26A Specifically, in Fig.27A In the planar layout of FIG. 1 , a region including 4×4 memory cells 150 is shown. In addition, a conductor 260 used as a wiring WL, a conductor 240 used as a wiring BL, and an opening 290 are shown. In addition, the memory cell 150 is provided in the region where the conductor 260 and the conductor 240 overlap with the opening 290. In other words, the opening 290 is provided in the region where the conductor 240 and the conductor 260 intersect.

[0544] Fig.27AThe memory cells 150 are arranged in a matrix. The openings 290 are arranged in a matrix. The conductor 260 is extended in the Y direction (also referred to as the column direction) and the conductor 240 is extended in the X direction (also referred to as the row direction). In other words, the conductor 260 is orthogonal to the conductor 240. The width of the conductor 260 in the direction (X direction) perpendicular to the extension direction of the conductor 260 is constant and the width of the conductor 240 in the direction (Y direction) perpendicular to the extension direction of the conductor 240 is constant. Note that the present invention is not limited to this.

[0545] Fig.27B Another example of a planar layout of a storage device is shown. Fig.27A Likewise, in Fig.27B The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.27B The storage device shown is Fig.27A The main differences of the illustrated memory device are: the arrangement of the memory cell 150 ; the arrangement of the opening 290 ; the shape of the conductor 240 ; and the extending direction of the conductor 260 .

[0546] like Fig.27B As shown, the memory cells 150 may also be arranged in a zigzag pattern in the Y direction. The memory cells 150 are arranged in a manner that half of the repetition units of the memory cells 150 are staggered between the odd-numbered rows and the even-numbered rows. In addition, the memory cells 150 are arranged in a manner that half of the repetition units of the memory cells 150 are staggered between the odd-numbered columns and the even-numbered columns. Similarly, Fig.27B The openings 290 shown are arranged so that the repetition unit of the openings 290 is shifted by half between the odd-numbered rows and the even-numbered rows. In addition, the openings 290 are arranged so that the repetition unit is shifted by half between the odd-numbered columns and the even-numbered columns. Fig.27B In the embodiment, the storage cell adjacent to the first storage cell in the X direction is referred to as the second storage cell, and the storage cell closer to the second storage cell among the storage cells adjacent to the first storage cell in the extending direction of the conductor 260 is referred to as the third storage cell. At this time, it is preferred that the center of the third storage cell is located on a straight line passing through the middle of the first storage cell and the second storage cell and parallel to the Y direction. It can also be said that in the X direction, the third storage cell is located at a position offset by half of the repetition unit in the X direction relative to each of the first storage cell and the second storage cell.

[0547] In addition, if Fig.27BAs shown, the conductor 240 includes a first region and a second region. The first region is the opening 290 and the region in the vicinity thereof, and the width of the first region in the Y direction is referred to as the first width. When viewed from above, it can be said that the first region has a quadrilateral shape with arc-shaped corners. In addition, the second region is a region between adjacent openings 290 in a conductor 240 (it can also be said to be a region between two adjacent first regions), and the width of the second region in the Y direction is referred to as the second width. At this time, the second width is preferably smaller than the first width. By adopting this structure, the physical distance between the conductors 240 when the storage cells 150 (or the openings 290) are arranged in a manner that staggers half of the repetitive units in each row or column can be reduced. In this way, miniaturization and high integration of storage devices can be achieved.

[0548] In addition, Fig.27B In the embodiment, the extension direction of the conductor 260 is inclined to the Y direction. On the other hand, the conductor 240 is arranged to extend in the X direction. That is, the extension direction of the conductor 260 is sometimes not orthogonal to the extension direction of the conductor 240 depending on the configuration of the memory cell 150 (or the opening 290). In other words, the conductor 260 does not need to be orthogonal to the conductor 240, and the conductor 260 and the conductor 240 are arranged in a cross manner.

[0549] Fig.27C Another example of a planar layout of a storage device is shown. Fig.27B Likewise, in Fig.27C The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.27C The storage device shown is Fig.27B The memory device shown differs mainly in the shape of the first region of the electrical conductor 240 .

[0550] Fig.27B The first region of the conductor 240 shown in the figure has a quadrangular shape with curved corners when viewed from above, and one side of the quadrangular shape is parallel to the X direction or the Y direction. Fig.27C The first region of the conductor 240 shown has a quadrangular shape with curved corners when viewed from above, and the diagonal lines of the quadrangular shape are parallel to the X direction or the Y direction. By adopting this structure, the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged in a manner that the repetition units are staggered by half in each row or column. As a result, the memory device can be miniaturized and highly integrated.

[0551] Fig.27B and Fig.27C Although an example is shown in which the first region of the conductor 240 has a quadrangular shape with curved corners in a plan view, the present invention is not limited thereto.

[0552] Fig.28A Another example of a planar layout of a storage device is shown. Fig.27B Likewise, in Fig.28A The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.28A The storage device shown is Fig.27B and Fig.27C The memory device shown differs mainly in the shape of the first region of the electrical conductor 240 .

[0553] Fig.28B The first region of the conductor 240 shown has a circular shape in a plan view. By adopting this structure, the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged in a manner that the repetition unit is shifted by half in each row or column. As a result, the memory device can be miniaturized and highly integrated.

[0554] Note that the first region of the conductor 240 in plan view is not limited to the above shape. For example, the first region of the conductor 240 in plan view may have a substantially circular shape such as an ellipse, a polygon such as a quadrangle, or a polygon such as a quadrangle with curved corners.

[0555] in addition, Fig.28A The structure in which the width of the conductor 260 in the direction perpendicular to the extending direction of the conductor 260 is constant is shown, but the present invention is not limited thereto.

[0556] Fig.28B Another example of a planar layout of a storage device is shown. Fig.28A Likewise, in Fig.28B The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.28B The storage device shown is Fig.28A The memory devices shown differ primarily in the shape of the electrical conductor 260 .

[0557] Similar to the conductor 240, Fig.28B The conductor 260 shown includes a first region and a second region. The first region is the opening 290 and the region in the vicinity thereof, and has a circular shape when viewed from above. In addition, the second region is the region between adjacent openings 290 in one conductor 260 (it can also be said to be the region between two adjacent first regions). Note that the first region of the conductor 260 overlaps with the first region of the conductor 240. By adopting this structure, the physical distance between the conductors 260 can be reduced when the storage cells 150 (or the openings 290) are arranged in a manner that staggers the repetition unit by half in each row or column. In this way, miniaturization and high integration of the storage device can be achieved.

[0558] Fig.28C Another example of a planar layout of a storage device is shown. Fig.28A Likewise, in Fig.28C The plan layout of FIG. 1 shows the conductor 260 , the conductor 240 , the memory cell 150 , and the opening 290 . Fig.28C The storage device shown is Fig.28A The main difference between the illustrated memory devices is the shape and extension direction of the conductor 260 .

[0559] Fig.28C The conductor 260 shown has a triangular wave shape when viewed from above, and is extended in the Y direction. By adopting this structure, the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged in a manner that the repetition unit is staggered by half in each row or column. Thus, the memory device can be miniaturized and highly integrated. Note that the conductor 260 when viewed from above is not limited to the above shape, and can also have a serpentine shape, etc.

[0560] By adopting the above structure, one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the miniaturization and high integration of the storage device can be achieved.

[0561] Fig.29 An example of a cross-sectional structure of a memory device in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier is shown.

[0562] exist Fig.29 In the embodiment, the capacitor 100 is disposed above the transistor 300 , and the transistor 200 is disposed above the transistor 300 and the capacitor 100 .

[0563] The transistor 300 is one of the transistors included in the sense amplifier.

[0564] Fig.29 The structure of the illustrated memory cell 150 (transistor 200 and capacitor 100 ) is as described above.

[0565] like Fig.29 As shown, the bit line can be shortened by adopting a structure in which the sense amplifier is provided so as to overlap the memory cell 150. Thus, the bit line capacitance can be reduced, and high-speed driving of the memory device can be realized.

[0566] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the thermal history during the manufacture of the capacitor 100. Therefore, it is possible to suppress the degradation of the electrical characteristics of the transistor 200, such as the variation in threshold voltage and the increase in parasitic resistance, and the increase in the unevenness of the electrical characteristics caused by the degradation of the electrical characteristics.

[0567] Fig.29 The memory device shown may correspond to the memory device 80 described in Embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 46 in the memory device 80. In addition, the memory cell 150 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor 37, and the capacitor 100 corresponds to the capacitor 38.

[0568] The transistor 300 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 300 may be a p-channel type or an n-channel type.

[0569] Here, in Fig.29 In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, a material that adjusts the work function can also be used for the conductor 316. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion can also be provided. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex portion.

[0570] Notice, Fig.29 The structure of the transistor 300 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0571] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductor having the function of a plug or wiring, the same symbol is sometimes used to represent multiple structures. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0572] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the tra...

Claims

1. A storage device, comprising: a first transistor; a first conductor on the first transistor; a storage unit on the first electrical conductor; a first insulator on the first electrical conductor; as well as The second insulator, wherein the first transistor comprises silicon in a semiconductor layer, The first transistor and the first conductor are electrically insulated from each other, The storage unit includes a capacitor and a second transistor on the capacitor, The capacitor includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator, The first insulator is provided with a first opening portion reaching the first conductor, At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening. The second conductor, the third insulator, and the third conductor are provided with the second insulator. The second transistor includes the third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor. The fourth conductor is electrically connected to the source or drain of the first transistor, The second insulator and the fourth conductor are provided with a second opening reaching the third conductor, At least a portion of the oxide semiconductor is disposed in the second opening. The oxide semiconductor has a region in contact with the top surface of the third conductor in the second opening, a region in contact with the side surface of the fourth conductor in the second opening, and a region in contact with at least a portion of the top surface of the fourth conductor, The fourth insulator is arranged on the oxide semiconductor so that at least a part of the fourth insulator is located in the second opening. Furthermore, the fifth conductor is arranged on the fourth insulator such that at least a portion thereof is located in the second opening.

2. The storage device according to claim 1, The second opening has an area overlapping with the first opening.

3. The storage device according to claim 1, The channel length of the second transistor is smaller than the channel width of the second transistor.

4. The storage device according to claim 1, The third insulator includes a material having ferroelectricity.

5. The storage device according to claim 1, The third insulator includes a first zirconium oxide, an aluminum oxide on the first zirconium oxide, and a second zirconium oxide on the aluminum oxide.

6. The storage device according to claim 1, The oxide semiconductor includes one or more selected from In, Ga and Zn.

7. The storage device according to claim 1, The oxide semiconductor has a crystal portion.

8. The storage device according to claim 1, The first insulator includes a first layer and a second layer on the first layer, The first layer comprises silicon and nitrogen, And the second layer includes silicon and oxygen.

9. The storage device according to claim 1, A fifth insulator is provided between the side surface of the first insulator in the first opening and the second conductor, And the fifth insulator includes silicon and nitrogen.

10. The storage device according to any one of claims 1 to 9, wherein the fifth conductor is extended in the first direction, The fourth conductor is extended in the second direction. And the fifth electrical conductor is orthogonal to the fourth electrical conductor.

11. The storage device according to claim 10, further comprising: a plurality of layers including said storage unit, A plurality of said layers are stacked.

12. A method for manufacturing a storage device, comprising: forming a first electrical conductor; forming a first insulator on the first conductor; processing the first insulator to form a first opening reaching the first conductor; A second conductor formed in the first opening and in contact with a side surface of the first insulator; forming a second insulator on the second conductor; forming a third conductor on the second insulator; forming a third insulator on the third conductor; forming a fourth conductor on the third insulator; Processing the fourth conductor and the third insulator respectively to form a second opening reaching the third conductor; An oxide semiconductor is formed in the second opening and contacts the top surface of the third conductor, the side surface of the third insulator, and the top surface and side surface of the fourth conductor; forming a fourth insulator on the oxide semiconductor; as well as forming a fifth conductor on the fourth insulator, In the step of forming the oxide semiconductor, a deposition step using an ALD method and an impurity removal treatment in an oxygen-containing atmosphere are repeatedly and alternately performed multiple times.

13. The method for manufacturing a storage device according to claim 12, Here, microwave treatment is performed as the impurity removal treatment.

14. The method for manufacturing a storage device according to claim 13, wherein a crystal portion is formed in the oxide semiconductor by the microwave treatment.

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