Device and method for controlling connection voidage of large-area thermal interface of power electronic device

Abstract

According to the device and method for controlling the connection void rate of the large-area thermal interface of the power electronic device provided by the invention, the device part ensures that an organic solvent and water vapor in a soldering paste layer can be smoothly discharged by optimizing the grid structure shape design of a steel mesh printing module, so that the void rate in the welding process is effectively reduced; according to the method, through optimization of the reflow soldering technology, temperature control and vacuum degree optimization of all stages such as the heating process, the heat preservation process, the pre-reflow process and the reflow process are included, the gas escape time is properly prolonged, the voidage is controlled to be 1% or below, the interface thermal resistance is reduced, and the heat dissipation performance is improved. Through optimization design and process, the production process is simplified, the operation is more convenient, the cost is low, and the method is suitable for large-scale production; and meanwhile, the voidage is effectively controlled, so that the product quality consistency in the production process is guaranteed, the heat dissipation efficiency of the power electronic device is improved, and the service life of the power electronic device is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of high-power electronic device packaging, and in particular to a device and method for controlling the void rate of a large-area thermal interface connection of a power electronic device. Background Art

[0002] The third generation of semiconductor materials (such as gallium nitride and silicon carbide) have promoted the development of power electronic devices due to their superior properties such as high bandgap width, high breakdown electric field, high saturation electron velocity and high thermal conductivity. These materials enable power electronic devices to achieve higher operating frequencies and power densities. The power density of traditional silicon-based power devices is usually in the range of tens of watts to hundreds of watts per cubic centimeter (W / cm³), while the power density of third-generation semiconductor devices can exceed 1000W / cm³, even reaching 2000W / cm³ or higher. However, high power density causes power electronic devices to generate more heat during operation, so efficient and stable heat dissipation packaging technology is required to ensure the reliability and life of power electronic devices. The main function of thermal interface materials is to fill the gap between the power module and the heat sink, reduce the contact thermal resistance of the heat transfer interface, and enable the heat generated by the power electronic device to be transferred to the heat sink more quickly through the thermal interface material, thereby improving the heat dissipation performance of the power electronic device.

[0003] At present, widely used thermal interface materials include thermal grease, thermal gel, phase change materials, etc., but the thermal conductivity of these materials is generally lower than 10W / (m·K), which is difficult to meet the heat dissipation requirements of high-power electronic devices. Lead-free solder thermal interface materials have gradually attracted attention because of their high thermal conductivity, low thermal resistance and excellent reliability, becoming the key to solving the heat dissipation problem. At present, the common lead-free solders on the market include Sn-3.0Ag-0.5Cu (58W / (m·K)), Sn-5Sb (28W / (m·K)), In (80W / (m·K)), Sn-58Bi (20W / (m·K)), etc. In addition, Chinese patent CN115662966A discloses a solder-type thermal interface material that can be used for efficient heat dissipation of power electronic devices. It adjusts the thermal conductivity (60~250W / (m·K)) through a multi-layer composite structure, which can achieve "low temperature connection, high temperature service", and can achieve efficient and stable heat dissipation of power devices.

[0004] Although the application of lead-free solder thermal interface materials has received attention, the gas generated by the volatilization of organic solvents in the solder paste cannot escape effectively during the reflow process, resulting in voids in the thermal interface connection. The increase in void rate not only affects the mechanical strength and fatigue life of the thermal interface structure, but also increases the junction temperature and thermal resistance of the device, reducing its heat dissipation performance. As the thermal interface interconnection area of ​​power electronic devices continues to increase (for example, the ON Semiconductor VE-Trac double-sided cooling power module, whose thermal interface interconnection area exceeds 48mm×42mm), the control of void rate becomes increasingly difficult. The increase in junction temperature of power electronic devices will significantly increase their failure probability. For every 10°C temperature rise, the failure probability can be doubled. Therefore, controlling the void rate is crucial for lead-free solder thermal interface materials to play the advantage of efficient heat dissipation when interconnecting over a large area.

[0005] Regarding welding void rate control, there are some solutions in the existing technology:

[0006] For example, Chinese patent CN217336087U discloses a large pad solder void structure for a power device, and proposes to control the void rate through a spider web pad design. However, this design increases the complexity and manufacturing cost of the pad, and is not suitable for controlling large-area thermal interface interconnections.

[0007] For another example, Chinese patent CN118951211A discloses a device for reducing solder voids in power modules and its use method, which uses a solder paste printing net with a mesh structure composed of multiple triangular structures to solve problems such as uneven coating thickness of the solder paste layer and high voids. The amount of solder paste layer is reduced by a reserved microchannel, and the thickness of the solder paste layer is thinned at the thicker position by using the collapse effect after reflow to improve the uniformity of the thickness of the solder paste layer. However, this solution has high requirements on the processing accuracy of the steel mesh in actual application and may increase the manufacturing complexity.

[0008] For another example, Chinese patent CN114260530A discloses a welding process for large-area ceramic copper-clad laminates based on IGBT modules, which reduces the void rate by nitrogen filling and vacuum treatment. However, the process is relatively complicated, which limits its application in large-scale production.

[0009] In summary, although the existing technology has reduced the void rate to a certain extent, it still faces the problems of complex manufacturing process, high cost and limited scope of application. Especially in power electronic devices with large-area thermal interface interconnection, the existing solutions are often difficult to meet actual needs. Therefore, it is necessary to provide a device and method for controlling the void rate of large-area thermal interface connection of power electronic devices to solve the above problems. Summary of the invention

[0010] According to the technical problems raised above, a device and method for controlling the void rate of large-area thermal interface connection of power electronic devices is provided. The present invention mainly utilizes a large-area steel screen printing module designed for lead-free solder paste, and through the shape of the grid structure and the optimization of the reflow process, the void rate of large-area thermal interface connection is greatly reduced, and the void rate is controlled below 1%.

[0011] The technical means adopted by the present invention are as follows:

[0012] A device for controlling the void rate of a large-area thermal interface connection of a power electronic device, the device comprising:

[0013] The stencil printing module is used to print the solder paste onto the thermal interface area of ​​the substrate to be soldered during the printing process of the lead-free solder paste on the large-area thermal interface;

[0014] The steel screen printing module includes a grid structure arranged in a matrix with multiple preset sizes. The grid structure is used to divide the lead-free solder paste printing area into multiple units, and a gas exhaust channel for increasing the lead-free solder paste is formed between the units. The size of the grid structure is determined by the interconnection area of ​​the lead-free solder paste on the thermal interface.

[0015] Furthermore, the grid structure divides the lead-free solder paste printing area into a plurality of uniform units, and the grid structure is a square.

[0016] Furthermore, the interconnection area of ​​the thermal interface lead-free solder paste is greater than 20mm×20mm: when the interconnection area is between 20mm×20mm and 40mm×40mm, the length L1 of the grid structure is equal to the width W1 of 8~10mm, and the gap S1 between the units is 1~2mm; when the interconnection area is greater than 40mm×40mm, the length L1 of the grid structure is equal to the width W1 of 5~10mm, and the gap S1 between the units is 0.5~1mm.

[0017] The present invention also provides a method for controlling the void rate of a large-area thermal interface connection of a power electronic device, comprising the following steps:

[0018] Step 1: using the above-mentioned device, printing lead-free solder paste on the thermal interface interconnection area of ​​the upper substrate or the lower substrate to be soldered through the steel screen printing module;

[0019] Step 2: Place the upper substrate-lead-free solder paste layer-lower substrate interconnection structure obtained in step 1 into a reflow soldering device, perform reflow according to a set reflow process curve, and complete reflow soldering.

[0020] Furthermore, the upper substrate is one of the power electronic devices including metal-oxide semiconductor field effect transistor power module, insulated gate bipolar transistor power module and silicon carbide power module; the lower substrate is one of the heat sink materials for power electronic devices including aluminum, copper and copper alloy; the lead-free solder paste layer is a single-layer lead-free solder paste structure or a composite structure including multiple layers of lead-free solder paste.

[0021] Furthermore, the reflow soldering comprises the following steps:

[0022] S1, heating process: heating the temperature of the reflow oven from room temperature to the preheating temperature T1 at a certain heating rate;

[0023] S2, insulation process: heating the reflow oven temperature from T1 to the preheating temperature T2 and then keeping the temperature elevated;

[0024] S3, pre-reflow process: heat the reflow oven temperature from T2 to the low temperature solder paste melting point T m , keep the temperature and raise the temperature for pre-reflux;

[0025] S4, reflow process: the temperature of the reflow oven cavity is raised from the low temperature solder paste melting point T m Heating to a reflux peak temperature T3 for reflux;

[0026] S5, cooling process: cool the cavity temperature of the reflow oven to below the melting point of the solder paste until cooling is completed.

[0027] Furthermore, in the step S1, the heating rate is 30-90°C / min, and the heating zone time is 50-200s; in the step S2, the insulation heating rate is 0.1-5°C / min, and the insulation zone time is 200-400s; in the step S3, the insulation heating rate is 50-90°C / min, and the pre-reflow zone time is 5-50s; in the step S4, the reflow zone time is 100-300s; in the step S5, the cavity temperature in the reflow furnace is cooled to 30-50°C lower than the melting point of the solder paste, and the cooling zone time is 100-500s.

[0028] Furthermore, the target thickness of the lead-free solder paste layer after reflow is 0.01 to 0.2 mm.

[0029] Furthermore, in step S4, a vacuuming process is also provided, and the vacuuming method is to vacuum the reflow zone for 100 to 200 seconds, and the vacuum degree is 5 to 20 mbar; or a step-by-step vacuuming is adopted: first, the cavity in the reflow furnace is vacuumed to a vacuum degree of 50 mbar, maintained for 50 to 100 seconds, and then the vacuum degree of the cavity is vacuumed to 5 to 20 mbar, and maintained for 10 to 50 seconds.

[0030] Furthermore, the stencil printing module controls the uniform distribution and effective exhaust of lead-free solder paste during the reflow process by adjusting the size of the grid structure and the gap between units, thereby controlling the void rate of large-area thermal interface connections of power electronic devices to less than 1%.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] The present invention increases the exhaust channel for the volatilization of organic solvents in lead-free solder paste during the reflow process by changing the shape design of the grid structure and optimizing the reflow curve, appropriately prolongs the gas escape time, and uses a vacuum atmosphere to assist the discharge of volatile gases, thereby significantly improving the gas emission effect during the reflow process of lead-free solder paste with a large area thermal interface, and successfully controlling the void rate to below 1%.

[0033] Due to the reduction of void ratio and the reduction of thermal resistance of thermal interface structure, the heat dissipation performance of power electronic devices has been significantly improved, which directly enhances the working stability of the device and prolongs the service life. With the improvement of welding quality, heat can be more efficiently transferred from the power device to the heat sink, improving the overall heat dissipation efficiency and ensuring the stable operation of the device at high power density.

[0034] In addition, the technical solution adopted by the present invention is easy to operate, low in cost, and suitable for large-scale production. The shape design of the steel screen printing module and the optimization of the reflow process can be improved on the basis of existing equipment, avoiding the need for high-precision equipment and complex processes, making the entire production process more simplified without increasing additional production costs.

[0035] In summary, the present invention effectively controls the void rate in large-area thermal interface connections, reduces interface thermal resistance, improves the heat dissipation performance of power electronic devices, simplifies the production process, and reduces production costs. It has strong industrial application value, is suitable for large-scale production, and can significantly improve the performance and reliability of power electronic devices.

[0036] Based on the above reasons, the present invention can be widely promoted in the technical field of high-power electronic device packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0038] Figure 1 It is a schematic diagram of the shape of the steel screen printing module in the present invention.

[0039] Figure 2 Schematic diagram of the reflow curve used in the present invention.

[0040] Figure 3 This is the reflow curve measured in real time in Example 1 of the present invention.

[0041] Figure 4 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Example 1 of the present invention.

[0042] Figure 5 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Example 2 of the present invention.

[0043] Figure 6 This is the reflow curve measured in real time in Example 3 of the present invention.

[0044] Figure 7 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Example 3 of the present invention.

[0045] Figure 8 Schematic diagram of the shape of the steel screen printing module in Comparative Example 1 of the present invention.

[0046] Fig. 9 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Comparative Example 1 of the present invention.

[0047] Fig.10 Schematic diagram of the shape of the steel screen printing module in Comparative Example 2 of the present invention.

[0048] Fig.11 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Comparative Example 2 of the present invention.

[0049] Fig.12 It is a schematic diagram of the shape of the steel screen printing module in comparative example 3 of the present invention.

[0050] Fig.13 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Comparative Example 3 of the present invention.

[0051] Fig.14 This is the reflow curve measured in real time in Comparative Example 4 of the present invention.

[0052] Fig.15 This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Comparative Example 4 of the present invention.

[0053] Fig.16This is an X-ray void ratio detection diagram of a large-area, efficient heat dissipation interface connection structure obtained in Comparative Example 5 of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The present invention provides a method for controlling the void rate of a large-area thermal interface connection of a power electronic device, which specifically includes the following steps:

[0056] Step 1: Shape design of the steel screen printing module for large area thermal interface lead-free solder paste:

[0057] Printing lead-free solder paste at the soldering position where the thermal interface interconnection needs to be performed on the upper substrate or the lower substrate, and dividing the lead-free solder paste printing area into a plurality of uniform units (the grid structure is preferably a square) using the grid structure of the steel screen printing module, adding a lead-free solder paste gas exhaust channel, and the size of the grid structure is determined by the interconnection area of ​​the lead-free solder paste on the thermal interface;

[0058] The area of ​​the large-area thermal interface lead-free solder paste is greater than 20 mm×20 mm.

[0059] The upper substrate is one of power electronic devices including metal-oxide semiconductor field effect transistor power module, insulated gate bipolar transistor power module and silicon carbide power module; the lower substrate is one of the heat sink materials for power electronic devices, including aluminum, copper and copper alloy.

[0060] Wherein, the individual size of the grid structure is determined by the interconnection area of ​​the lead-free solder of the thermal interface (such as Figure 1 shown), specifically:

[0061] When the interconnection area is between 20 mm×20 mm and 40 mm×40 mm, the length L1 of the grid structure is equal to the width W1 of 8-10 mm, and the gap S1 between the units is equal to 1-2 mm;

[0062] When the interconnection area is larger than 40 mm×40 mm, the length L1 of the grid structure is equal to the width W1 of 5-10 mm, and the gap S1 between the units is equal to 0.5-1 mm.

[0063] Step 2: Optimization of large area thermal interface lead-free solder paste reflow process:

[0064] The upper substrate-lead-free solder paste layer-lower substrate interconnection structure obtained in step 1 is loaded into a reflow soldering device, and reflow is performed according to a set reflow process curve to complete reflow soldering. The lead-free solder paste layer is a single-layer lead-free solder paste structure or a composite structure including multiple layers of lead-free solder paste.

[0065] The specific process includes the following (such as Figure 2 shown):

[0066] S1, heating process: the temperature of the cavity in the reflow furnace is heated from room temperature to the preheating temperature T1, the heating rate of the heating process to T1 is 30-90℃ / min, and the heating zone time is 50-200s;

[0067] S2, insulation process: the temperature of the cavity in the reflow furnace is heated from T1 to the preheating temperature T2. After this process, the heating rate of insulation is 0.1-5℃ / min, and the insulation time is 200-400s.

[0068] S3, pre-reflow process: heat the cavity temperature of the reflow oven from T2 to the melting point of the selected low-temperature solder paste T m After this process, the heating rate of the insulation is 50-90℃ / min, and the pre-reflow zone time is 5-50s;

[0069] S4, reflow process: the temperature of the reflow oven cavity is raised from the low temperature solder paste melting point T m Heat to the reflux peak temperature T3, and the reflux zone time is 100~300s;

[0070] Vacuuming process: The vacuuming method is to vacuum the reflow zone for 100-200 seconds, with a vacuum degree of 5-20 mbar; or adopt a step-by-step vacuuming method: first vacuum the cavity to a vacuum degree of 50 mbar, maintain for 50-100 seconds, and then vacuum the cavity to 5-20 mbar, and maintain for 10-50 seconds.

[0071] S5, cooling process: cool the cavity temperature of the reflow oven to 30-50°C lower than the melting point of the low-temperature solder paste, and the cooling zone time is 100-500s;

[0072] According to the above steps, the void rate of large-area thermal interface connection of power electronic devices can be controlled below 1%.

[0073] Embodiment 1:

[0074] A method for controlling the void rate of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved by the following steps:

[0075] Step 1: Select pure Cu as the upper substrate, pure Cu (heat sink) as the lower substrate, and select Sn-58Bi single-layer lead-free solder paste structure as the thermal interface material. The upper substrate and the lower substrate to be soldered have an area of ​​55mm×55mm, the length L1 and width W1 of the grid structure are 5mm, the gap S1 between units is 1mm, and the target thickness of the Sn-58Bi single-layer lead-free solder paste structure after reflow is 0.15mm. Print the lead-free solder paste on the lower substrate according to the selected grid structure;

[0076] Step 2: Place the upper substrate-Sn-58Bi single-layer lead-free solder paste structure-lower substrate interconnection structure obtained in step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: heating zone time is 110s, insulation zone time is 300s, pre-reflow zone time is 20s, reflow zone time is 200s, cooling zone time is 300s, reflow zone is vacuumed for 100s, and the vacuum degree is 20mbar. The measured reflow curve is as follows: Figure 3 shown.

[0077] X-ray technology uses its penetrating ability to generate a two-dimensional image of the internal structure of the material by detecting the absorption and scattering characteristics of X-rays inside the material. Due to the density difference inside the material, the absorption rate of X-rays will be different. High-density areas (such as metals) appear darker or black in the image, while low-density areas (such as voids) appear brighter or white. The X-ray image is processed by Image J open source image processing software to identify and calculate the area of ​​the void area and the total area of ​​the entire thermal interface interconnection area. The ratio is the void ratio. Based on the above principle, X-ray was used to detect the void ratio of large-area thermal interface connection structures. The results are as follows: Figure 4 As shown, only a small amount of white voids appear in the thermal interface interconnection area within the blue dotted box, and the void rate calculated in this embodiment is less than 1%.

[0078] Embodiment 2:

[0079] A method for controlling the void rate of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved by the following steps:

[0080] Step 1: Select pure Cu as the upper substrate, pure Cu (heat sink) as the lower substrate, and select Sn-58Bi single-layer lead-free solder paste structure as the thermal interface material. The upper substrate and the lower substrate to be soldered have an area of ​​45mm×50mm, the length L1 and width W1 of the grid structure are 5mm, the gap S1 between units is 1mm, and the target thickness of the Sn-58Bi single-layer lead-free solder paste structure after reflow is 0.15mm. Print the lead-free solder paste on the lower substrate according to the selected grid structure;

[0081] Step 2: Load the upper substrate-Sn-58Bi single-layer lead-free solder paste structure-lower substrate interconnection structure obtained in step 1 into the reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: heating zone time 110s, insulation zone time 300s, pre-reflow zone time 20s, reflow zone time 200s, cooling zone time 300s, reflow zone vacuum 150s, and vacuum degree 20mbar.

[0082] X-ray was used to detect the void ratio of the large-area thermal interface connection structure obtained in the above steps. The results are as follows: Figure 5 As shown, only a small amount of white voids appear in the thermal interface interconnection area within the blue dotted box, and the void rate calculated in this embodiment is less than 1%.

[0083] Embodiment 3:

[0084] A method for controlling the void rate of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved by the following steps:

[0085] Step 1: Select a silicon carbide power module with a pure Cu surface to be welded as the upper substrate, and a pure Al (heat sink) with Sn plated surface to be welded as the lower substrate, and select the interface structure with efficient heat dissipation proposed by Chinese patent CN115662966A as the thermal interface material, that is, the lead-free solder paste layer is selected in the form of a composite structure including two layers of lead-free solder paste, wherein Sn-58Bi solder paste is selected as the low-temperature solder paste layer, that is, the composite structure of the two layers of lead-free solder paste is Sn-58Bi low-temperature solder paste layer-metal foam composite material-Sn-58Bi low-temperature solder paste layer. The areas to be soldered of the upper substrate and the lower substrate are both 30 mm × 45 mm, the length L1 and width W1 of the grid structure are 6 mm, the gap S1 between the units is 1 mm, and the target thickness of the Sn-58Bi low-temperature solder paste layer selected in the composite structure of the two layers of lead-free solder paste after reflow is 0.01 mm. The lead-free solder paste is printed on the upper substrate and the lower substrate according to the selected grid structure;

[0086] Step 2: Place the composite structure of the upper substrate-two layers of lead-free solder paste-lower substrate interconnection structure obtained in step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: heating zone time is 90s, holding zone time is 230s, pre-reflow zone time is 20s, reflow zone time is 160s, cooling zone time is 300s, reflow zone is vacuumed for 60s, and the vacuum degree is 20mbar. The measured reflow curve is as follows: Figure 6 shown.

[0087] X-ray was used to detect the void ratio of the large-area thermal interface connection structure obtained in the above steps. The results are as follows: Figure 7As shown, no white voids are found in the thermal interface interconnection area within the blue dotted box, and the void ratio in this embodiment is less than 1%.

[0088] Embodiment 4:

[0089] A method for controlling the void rate of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved by the following steps:

[0090] Step 1: Select a silicon carbide power module with a pure Cu surface to be welded as the upper substrate, pure Cu (heat sink) as the lower substrate, and select the interface structure with efficient heat dissipation proposed by Chinese patent CN115662966A as the thermal interface material, that is, the lead-free solder paste layer is selected in the form of a composite structure including two layers of lead-free solder paste, wherein Sn-57Bi-1Ag solder paste is selected as the low-temperature solder paste layer, that is, the composite structure of the two layers of lead-free solder paste is Sn-57Bi-1Ag low-temperature solder paste layer-metal foam composite material-Sn-57Bi-1Ag low-temperature solder paste layer. The soldering area of ​​the upper substrate and the lower substrate is 30 mm × 45 mm, the length L1 and width W1 of the grid structure are 5 mm, the gap S1 between the units is 1 mm, and the target thickness of the Sn-57Bi-1Ag low-temperature solder paste layer after reflow selected in the composite structure of the two layers of lead-free solder paste is 0.01 mm. The low-temperature solder paste is printed on the upper substrate and the lower substrate according to the selected grid structure;

[0091] Step 2: Load the composite structure of the upper substrate-two layers of lead-free solder paste-lower substrate interconnection structure obtained in step 1 into the reflow soldering device, and reflow according to the set reflow process curve. The selected reflow parameters are: heating zone time 90s, insulation zone time 230s, pre-reflow zone time 20s, reflow zone time 160s, cooling zone time 300s, reflow zone vacuum 50s, and the vacuum degree is 5mbar.

[0092] The void ratio of the large-area thermal interface connection structure obtained in the above steps was detected and calculated using X-ray. The void ratio in this embodiment was less than 1%.

[0093] Embodiment 5:

[0094] A method for controlling the void rate of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved by the following steps:

[0095] Step 1: Select an IGBT power module with a pure Cu surface to be soldered as the upper substrate, pure Cu (heat sink) as the lower substrate, and select the interface structure with efficient heat dissipation proposed by Chinese patent CN115662966A as the thermal interface material, that is, the lead-free solder paste layer is selected in the form of a composite structure including two layers of lead-free solder paste, wherein Sn-58Bi solder paste is selected as the low-temperature solder paste layer, that is, the composite structure of the two layers of lead-free solder paste is Sn-58Bi low-temperature solder paste layer-metal foam composite material-Sn-58Bi low-temperature solder paste layer. The areas to be soldered of the upper substrate and the lower substrate are both 50 mm × 50 mm, the length L1 and width W1 of the grid structure are 4 mm, the gap S1 between the units is 0.5 mm, and the target thickness of the Sn-58Bi low-temperature solder paste layer selected in the composite structure of the two layers of lead-free solder paste after reflow is 0.01 mm. The low-temperature solder paste is printed on the upper substrate and the lower substrate according to the selected grid structure;

[0096] Step 2: Load the composite structure of the upper substrate-two layers of lead-free solder paste-lower substrate interconnection structure obtained in step 1 into the reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: heating zone time is 100s, insulation zone time is 300s, pre-reflow zone time is 20s, reflow zone time is 160s, cooling zone time is 200s, reflow zone is vacuumed for 120s, and the vacuum degree is 50mbar.

[0097] The void ratio of the large-area thermal interface connection structure obtained in the above steps was detected and calculated using X-ray. The void ratio in this embodiment was less than 1%.

[0098] Therefore, the above-mentioned specific embodiments 1 to 5 achieve the control of the void ratio during the reflow process of the lead-free solder paste of the large-area thermal interface, and the void ratio is less than 1%.

[0099] Comparative Example 1:

[0100] Same as Example 1, except that the shape of the steel screen printing module is square (such as Figure 8 As shown), there is no grid structure arranged in a matrix, the length L1 is 55 mm, the width W1 is 55 mm, and the area to be soldered is the same as that of the upper substrate and the lower substrate. The reflow process is the same as that of Example 1. The void rate of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dotted box. The void rate calculated in this embodiment is 13%. The results are as follows Fig. 9 shown.

[0101] Comparative Example 2:

[0102] Same as Example 1, except that the grid structure is rectangular (e.g. Fig.10 As shown in the figure), the length L1 is 60 mm, the width W1 is 5 mm, the gap S1 between the units is 1 mm, and the reflow process is the same as that in Example 1. The void rate of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dotted box. The void rate calculated in this embodiment is 11%. The result is as follows Fig.11 shown.

[0103] Comparative Example 3:

[0104] Same as Example 1, except that the grid structure is in the shape of a triangle (such as Fig.12 As shown in the figure, the length L1 and width W1 of the two right-angle sides are both 5 mm, the gap S1 between the units is 1 mm, and the reflow process is the same as that in Example 1. The void rate of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dotted box. The void rate calculated in this embodiment is 6%. The result is as follows Fig.13 shown.

[0105] Comparative Example 4:

[0106] The same as Example 2, except that the reflow process parameters are different: the heating zone time is 110s, the holding zone time is 150s, the pre-reflow zone time is 20s, the reflow zone time is 150s, the cooling zone time is 300s, the reflow zone is evacuated for 150s, the vacuum degree is 20mbar, and the measured reflow curve is shown in 14. The void rate of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dotted box. The void rate calculated in this embodiment is 15%. The results are shown in Fig.15 shown.

[0107] Comparative Example 5:

[0108] The same as Example 2, except that the reflux process parameters are different: the heating zone time is 110s, the holding zone time is 150s, the pre-reflux zone time is 20s, the reflux zone time is 150s, the cooling zone time is 300s, and the reflux zone is not vacuumed. The measured reflux curve is as follows: Fig.14 The void ratio of the large-area thermal interface connection structure obtained in the above steps was detected by X-ray. A large number of white voids appeared in the thermal interface interconnection area within the blue dotted box. The void ratio calculated in this embodiment is 32%. Fig.16 shown.

[0109] It can be seen that the shape optimization of the grid structure proposed in the present invention and the combined effect of the reflow process are the key to controlling the void rate below 1% during the reflow process of the lead-free solder paste of the large-area thermal interface.

[0110] The above embodiments are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A device for controlling the void ratio of large-area thermal interface connections of power electronic devices, characterized in that: The device comprises: The stencil printing module is used to print the solder paste onto the thermal interface area of ​​the substrate to be soldered during the printing process of the lead-free solder paste on the large-area thermal interface; The steel screen printing module includes a grid structure arranged in a matrix with multiple preset sizes. The grid structure is used to divide the lead-free solder paste printing area into multiple units, and a gas exhaust channel for increasing the lead-free solder paste is formed between the units. The size of the grid structure is determined by the interconnection area of ​​the lead-free solder paste on the thermal interface.

2. The device for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 1, characterized in that: The grid structure divides the lead-free solder paste printing area into a plurality of uniform units, and the grid structure is a square.

3. The device for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 2, characterized in that: The interconnection area of ​​the lead-free solder paste of the thermal interface is greater than 20 mm×20 mm: when the interconnection area is between 20 mm×20 mm and 40 mm×40 mm, the length L1 of the grid structure is equal to the width W1 of 8-10 mm, and the gap S1 between the units is 1-2 mm; When the interconnection area is larger than 40 mm×40 mm, the length L1 of the grid structure is equal to the width W1 of 5-10 mm, and the gap S1 between the units is equal to 0.5-1 mm.

4. A method for controlling the void ratio of a large-area thermal interface connection of a power electronic device, characterized in that: The steps include: Step 1: using the device as claimed in any one of claims 1 to 3, printing lead-free solder paste on the thermal interface interconnection area of ​​the upper substrate or the lower substrate to be soldered through the steel screen printing module; Step 2: Place the upper substrate-lead-free solder paste layer-lower substrate interconnection structure obtained in step 1 into a reflow soldering device, perform reflow according to a set reflow process curve, and complete reflow soldering.

5. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 4, characterized in that: The upper substrate is one of the power electronic devices including metal-oxide semiconductor field effect transistor power module, insulated gate bipolar transistor power module and silicon carbide power module; the lower substrate is one of the heat sink materials for power electronic devices including aluminum, copper and copper alloy; the lead-free solder paste layer is a single-layer lead-free solder paste structure or a composite structure including multiple layers of lead-free solder paste.

6. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 5, characterized in that: The reflow soldering comprises the following steps: S1, heating process: heating the temperature of the reflow oven from room temperature to the preheating temperature T1 at a certain heating rate; S2, insulation process: heating the reflow oven temperature from T1 to the preheating temperature T2 and then keeping the temperature elevated; S3, pre-reflow process: heat the reflow oven temperature from T2 to the low temperature solder paste melting point T m , keep the temperature and raise the temperature for pre-reflux; S4, reflow process: the temperature of the reflow oven cavity is raised from the low temperature solder paste melting point T m Heating to a reflux peak temperature T3 for reflux; S5, cooling process: cool the cavity temperature of the reflow oven to below the melting point of the solder paste until cooling is completed.

7. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 6, characterized in that: In the step S1, the heating rate is 30-90°C / min, and the heating zone time is 50-200s; in the step S2, the heat preservation heating rate is 0.1-5°C / min, and the heat preservation zone time is 200-400s; in the step S3, the heat preservation heating rate is 50-90°C / min, and the pre-reflow zone time is 5-50s; in the step S4, the reflow zone time is 100-300s; in the step S5, the cavity temperature in the reflow furnace is cooled to 30-50°C lower than the melting point of the solder paste, and the cooling zone time is 100-500s.

8. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 7, characterized in that: The target thickness of the lead-free solder paste layer after reflow is 0.01 to 0.2 mm.

9. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 8, characterized in that: In the step S4, a vacuuming process is also provided, and the vacuuming method is to vacuum the reflow zone for 100-200 seconds, and the vacuum degree is 5-20 mbar; or a step-by-step vacuuming is adopted: first, the cavity in the reflow furnace is vacuumed to a vacuum degree of 50 mbar, maintained for 50-100 seconds, and then the vacuum degree of the cavity is vacuumed to 5-20 mbar, and maintained for 10-50 seconds.

10. The method for controlling the void ratio of large-area thermal interface connection of power electronic devices according to claim 4, characterized in that: The stencil printing module controls the uniform distribution and effective exhaust of lead-free solder paste during the reflow process by adjusting the size of the grid structure and the gap between units, thereby controlling the void rate of large-area thermal interface connections of power electronic devices to less than 1%.

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