A method for preparing a gain-adjustable MEMS pressure chip

Abstract

The present invention discloses a method for preparing a gain-adjustable MEMS pressure chip, which relates to the technical field of MEMS chip preparation. The method includes: forming an N+ buried layer area on the surface of a top silicon layer; bonding the top silicon layer to a double-polished silicon wafer, removing the SOI silicon wafer substrate layer and the buried oxide layer; forming a gain circuit area, an isolation area and a piezoresistive area on the top silicon layer; processing the double-polished silicon wafer layer to form a back cavity to obtain a MEMS chip; the collector area of ​​the gain circuit area is connected to the N+ buried layer area to reduce the series resistance and reduce the influence of parasitic transistors. The gain circuit area of ​​the present invention is located between the inner layer and the outer layer of the isolation area, the piezoresistive area is located within the range of the inner layer, and the gain circuit is integrated in the MEMS chip, which not only shortens the signal transmission path, but also effectively reduces the parasitic capacitance and signal loss in the traditional discrete design. The obtained MEMS pressure chip has the advantages of high integration, high signal sensitivity, high structural strength, and easy sensor integration.

Description

Technical Field

[0001] The invention relates to the technical field of MEMS chip preparation, and in particular to a method for preparing a gain-adjustable MEMS pressure chip. Background Art

[0002] MEMS pressure chip is an important achievement in the development of micro-electromechanical system (MEMS) technology application. It is a new type of micro-pressure measurement system produced by the combination of microelectronics and micromechanics. MEMS pressure chip is an ultra-small pressure measurement system. The piezoresistors of the system can convert external pressure into resistance changes under the action of micromechanical structures, thereby achieving the purpose of measuring pressure.

[0003] With the expansion of application scenarios, the demand for MEMS pressure chips in micro-pressure measurement is getting higher and higher, especially in the fields of medical devices, consumer electronics, industrial control, etc., where the requirements for accuracy, sensitivity and small size are constantly increasing. However, due to the limitations of process capabilities, the stability and measurement accuracy of MEMS pressure chips in the micro-pressure range are often difficult to meet these requirements. Specifically, the miniaturization of pressure sensors is difficult to manufacture, the signal output is weak and susceptible to noise interference, resulting in inaccurate measurements.

[0004] The invention application with application number 202411110473.7 discloses a fully differential MEMS active drive circuit applied to a MEMS oscillator circuit. Its solution is through a transimpedance amplifier circuit, a variable phase amplifier circuit, a variable gain amplifier circuit and an output buffer circuit. A bandpass phase gain adjustable MEMS active drive circuit is designed, and the phase gain is adjusted in the active drive circuit part to ensure that the entire MEMS oscillator loop of the MEMS resonator can oscillate stably under certain process deviations. It can be understood from its solution that its gain circuit is not directly integrated on the MEMS chip, which is easily affected by external noise and is not conducive to improving the accuracy of the MEMS chip.

[0005] Therefore, in reality, a solution is needed to integrate the gain circuit on the MEMS chip, enhance the signal at the source of the MEMS chip, avoid the influence of external noise, and improve the accuracy and stability of MEMS chip measurement. Summary of the invention

[0006] In view of the above problems, the present invention aims to provide a method for preparing a MEMS pressure chip with adjustable gain, integrate a gain circuit on a MEMS chip, and achieve adjustable gain of the MEMS chip.

[0007] The object of the present invention can be achieved by the following technical solution: A method for preparing a gain-adjustable MEMS chip, comprising the steps of:

[0008] S1, forming an N+ buried layer region on the surface of the top silicon layer of the SOI silicon wafer;

[0009] S2, bonding the top silicon layer of the SOI silicon wafer to the double-polished silicon wafer;

[0010] S3, removing the SOI silicon wafer substrate layer and buried oxide layer;

[0011] S4, processing the top silicon layer to form a gain circuit region, an isolation region and a piezoresistive region;

[0012] S5, processing the double-polished silicon wafer layer to form a back cavity to obtain a MEMS chip;

[0013] The gain circuit region includes a collector region, which is connected to the N+ buried layer region to reduce the series resistance and the influence of the parasitic transistor.

[0014] As a further solution of the present invention, when forming the N+ buried layer region on the surface of the top silicon layer of the SOI silicon wafer in S1, photolithography, implantation and annealing processes are used.

[0015] As a further solution of the present invention, when bonding the top silicon layer of the SOI silicon wafer to the double-polished silicon wafer layer in S2, a wafer-level vacuum bonding process is adopted.

[0016] As a further solution of the present invention, the top silicon layer is processed in S4, including: forming an isolation region and a gain circuit region by oxidation, photolithography, implantation and annealing processes on the top silicon layer; forming a piezoresistive region by photolithography, implantation and annealing processes on the top silicon layer.

[0017] As a further solution of the present invention, the top silicon layer is processed in S4, including:

[0018] The top silicon layer is subjected to film formation, photolithography, etching and sputtering processes to form hole contacts and metal wire connections.

[0019] As a further solution of the present invention, when the double-polished silicon wafer layer is processed in S5, a photolithography and etching process is used to form a back cavity.

[0020] The chip structure obtained based on the above-mentioned gain-adjustable MEMS chip preparation method includes:

[0021] A top silicon layer, wherein the top silicon layer forms a gain circuit region, an isolation region, and a piezoresistive region;

[0022] A double-polished silicon wafer layer, wherein the double-polished silicon wafer layer forms a back cavity;

[0023] The top silicon layer is bonded to the double-polished silicon wafer layer to form a MEMS chip structure. The top silicon layer is formed with an N+ buried layer area, and the N+ buried layer area is connected to the collector area of ​​the gain circuit area to reduce the series resistance and reduce the influence of parasitic transistors.

[0024] As a further solution of the present invention, the gain circuit region includes an N+ buried layer region, a collector region, a base region, and an emitter region;

[0025] The isolation region is an inner and outer double-layer structure, the piezoresistive region is located in the inner layer of the isolation region; and the gain circuit region is located between the inner layer and the outer layer of the isolation region.

[0026] Beneficial effects of the present invention:

[0027] 1. The top silicon layer of the MEMS chip of the present invention is formed with an isolation area, a gain circuit area and a piezoresistive area. The gain circuit area is located between the inner layer and the outer layer of the isolation area, and the piezoresistive area is located within the range of the inner layer; the isolation area isolates the gain circuit area and the piezoresistive area, and isolates the mutual influence between the gain circuit area and the piezoresistive area. Integrating the gain circuit in the MEMS chip not only shortens the signal transmission path, but also effectively reduces the parasitic capacitance and signal loss in the traditional discrete design. The obtained MEMS pressure chip has the advantages of high integration, high signal sensitivity, high structural strength, and easy sensor integration.

[0028] 2. The MEMS chip of the present invention forms an N+ buried region in the top silicon layer, and the N+ buried region is connected to the collector region. The body resistance of the collector region can be adjusted through the N+ buried region, which can reduce the series resistance and the influence of parasitic transistors, thereby achieving the adjustment of the MEMS chip gain. The overall size of the MEMS chip can be reduced, the manufacturing cost of the MEMS chip can be reduced, and the demand for miniaturized application of MEMS chips can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of forming an N+ buried layer region on a SOI silicon wafer according to the present invention;

[0030] Figure 2 This is a schematic diagram of the structure after the SOI silicon wafer and the double-polished silicon wafer are bonded in the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of the MEMS pressure chip of the present invention;

[0032] Figure 4 For the present invention Figure 3 Enlarged schematic diagram of part A in the middle.

[0033] 100, SOI silicon wafer; 110, top silicon layer; 120, buried oxide layer; 130, substrate layer;

[0034] 200, double-throw silicon wafer;

[0035] 310, isolation region; 320, gain circuit region; 321, collector region; 322, base region; 323, emitter region; 330, piezoresistive region; 340, metal wire; 350, back cavity;

[0036] 400. N+ buried layer region. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0038] With the expansion of application scenarios, the requirements for MEMS pressure chip accuracy, sensitivity and small size are constantly increasing. However, the existing MEMS pressure chip signal output is weak and susceptible to noise interference, resulting in inaccurate measurement. The stability and measurement accuracy in the micro-pressure range are often difficult to meet the requirements.

[0039] In view of the above problems, the present application discloses a method for preparing a gain-adjustable MEMS chip structure, the steps comprising:

[0040] S1. Form an N+ buried layer region 400 on the surface of the top silicon layer 110 of the SOI silicon wafer 100.

[0041] like Figure 1 As shown, the SOI silicon wafer 100 includes a substrate layer 130, a buried oxide layer 120 and a top silicon layer 110. On the surface of the top silicon layer 110, an N+ buried layer region 400 is formed by photolithography, implantation and annealing processes. After the N+ buried layer region 400 is connected to the collector region 321, it can be used to adjust the body resistance of the collector region 321, thereby making the gain of the MEMS chip adjustable.

[0042] S2, bonding the top silicon layer 110 surface of the SOI silicon wafer 100 to the double-polished silicon wafer 200.

[0043] like Figure 2 As shown, a double-polished silicon wafer 200 is used to bond the top silicon layer 110 of the SOI silicon wafer 100 to the double-polished silicon wafer 200 using a wafer-level vacuum bonding process.

[0044] S3 , removing the substrate layer 130 and the buried oxide layer 120 of the SOI silicon wafer 100 .

[0045] S4, the top silicon layer 110 is processed to form a gain circuit region 320, an isolation region 310 and a piezoresistive region 330. Figure 3 As shown, where:

[0046] The top silicon layer 110 is subjected to oxidation, photolithography, implantation and annealing processes to form an isolation region 310;

[0047] The top silicon layer 110 is subjected to oxidation, photolithography, implantation and annealing processes to form a gain circuit region 320;

[0048] The top silicon layer 110 is subjected to photolithography, implantation and annealing processes to form a piezoresistive region 330 .

[0049] The gain circuit region 320 and the piezoresistive region 330 of the top silicon layer 110 are connected by forming hole contacts and metal wires 340 by using film formation, photolithography, etching and sputtering processes.

[0050] S5. Process the double-polished silicon wafer 200 layers to form a back cavity 350 to obtain a MEMS chip.

[0051] When the double-polished silicon wafer 200 is processed, a back cavity 350 is formed by using photolithography and etching processes.

[0052] Through the above-mentioned method for preparing the MEMS chip structure, the top silicon layer 110 is formed with an isolation region 310, a gain circuit region 320 and a piezoresistive region 330. The gain circuit region 320 is located between the inner layer and the outer layer of the isolation region 310, and the piezoresistive region 330 is located within the range of the inner layer; the isolation region 310 isolates the gain circuit region 320 and the piezoresistive region 330, and isolates the mutual influence between the gain circuit region 320 and the piezoresistive region 330.

[0053] Through the above-mentioned method for preparing the MEMS chip structure, the N+ buried layer region 400 is connected to the collector region 321 , and the body resistance of the collector region 321 can be adjusted through the N+ buried layer region 400 , thereby achieving the adjustment of the MEMS chip gain.

[0054] The gain-adjustable MEMS chip of the present invention is compatible with integrated circuit and MEMS preparation processes, can be mass-produced, and the obtained MEMS pressure chip has the advantages of high integration, high signal sensitivity, high structural strength, and easy sensor integration.

[0055] Based on the above method, the present invention discloses a gain-adjustable MEMS chip structure, the structure is as follows Figure 2 As shown, it includes a top silicon layer 110 and a double-polished silicon wafer 200 layer.

[0056] like Figure 3 As shown, the top silicon layer 110 forms a gain circuit area 320, an isolation area 310 and a piezoresistive area 330; the double-polished silicon wafer 200 layer forms a back cavity 350; the top silicon layer 110 is bonded to the double-polished silicon wafer 200 layer, and the top silicon layer 110 and the double-polished silicon wafer 200 layer together form a MEMS pressure chip.

[0057] An N+ buried layer region 400 is formed on one side of the top silicon layer 110 close to the double-polished silicon wafer 200 layer, a collector region 321 is formed in the gain circuit region 320, and the N+ buried layer region 400 is connected to the collector region 321. The body resistance of the collector region 321 can be adjusted through the N+ buried layer region 400, thereby achieving adjustment of the gain of the MEMS chip.

[0058] like Figure 4 As shown, the isolation region 310, the gain circuit region 320 and the piezoresistive region 330 together constitute the device region, wherein the isolation region 310 is an inner and outer double-layer structure, the gain circuit region 320 includes a collector region 321, a base region 322 and an emitter region 323; the gain circuit region 320 is located between the inner layer and the outer layer of the isolation region 310, and the piezoresistive region 330 is located within the range of the inner layer; the isolation region 310 isolates the gain circuit region 320 and the piezoresistive region 330 to isolate each other from each other.

[0059] Through the above structure, the gain circuit is integrated on the MEMS chip, which can enhance the signal at the source, avoid the influence of external noise, and improve the measurement accuracy and stability. At the same time, the N+ buried layer area 400 is connected to the collector area 321, and the body resistance of the collector area 321 can be adjusted through the N+ buried layer area 400, thereby reducing the series resistance and reducing the influence of parasitic transistors.

[0060] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

[0061] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

Claims

1. A method for preparing a gain-adjustable MEMS pressure chip, characterized in that: Includes steps: S1, forming an N+ buried layer region (400) on the surface of the top silicon layer (110) of the SOI silicon wafer (100); S2, bonding the top silicon layer (110) surface of the SOI silicon wafer (100) to the double-polished silicon wafer (200); S3, removing the substrate layer (130) and the buried oxide layer (120) of the SOI silicon wafer (100); S4, performing a process on the top silicon layer (110) to form a gain circuit region (320), an isolation region (310) and a piezoresistive region (330); S5, performing a process on the double-polished silicon wafer (200) layer to form a back cavity (350), thereby obtaining a MEMS chip; The gain circuit region (320) includes a collector region (321), and the collector region (321) is connected to the N+ buried layer region (400) to reduce the series resistance and the influence of the parasitic transistor.

2. The preparation method according to claim 1, characterized in that: In the above S1, when forming the N+ buried layer region (400) on the surface of the top silicon layer (110) of the SOI silicon wafer (100), photolithography, implantation and annealing processes are used.

3. The preparation method according to claim 1, characterized in that: When bonding the top silicon layer (110) surface of the SOI silicon wafer (100) to the double-polished silicon wafer (200) layer in S2, a wafer-level vacuum bonding process is adopted.

4. The preparation method according to claim 1, characterized in that: The step S4 includes processing the top silicon layer (110), including: The top silicon layer (110) is subjected to oxidation, photolithography, implantation and annealing processes to form an isolation region (310) and a gain circuit region (320); The top silicon layer (110) is subjected to photolithography, implantation and annealing processes to form a piezoresistive region (330).

5. The preparation method according to claim 1, characterized in that: The processing of the top silicon layer (110) in S4 also includes: forming hole contacts and metal wire (340) connections on the top silicon layer (110) by film formation, photolithography, etching and sputtering processes.

6. The preparation method according to claim 1, characterized in that: When the double-polished silicon wafer (200) layer is processed in S5, a photolithography and etching process is used to form a back cavity (350).

7. A chip structure obtained based on the method according to any one of claims 1 to 6, characterized in that: include: A top silicon layer (110), wherein the top silicon layer (110) forms a gain circuit region (320), an isolation region (310) and a piezoresistive region (330); A double-polished silicon wafer (200) layer, wherein the double-polished silicon wafer (200) layer forms a back cavity (350); The top silicon layer (110) is bonded to a double-polished silicon wafer (200) layer to form a MEMS chip structure. The top silicon layer (110) is formed with an N+ buried layer region (400). The N+ buried layer region (400) is connected to a collector region (321) of a gain circuit region (320) to reduce series resistance and reduce the influence of parasitic transistors.

8. The chip structure according to claim 7, characterized in that: The gain circuit region (320) includes an N+ buried layer region (400), a collector region (321), a base region (322) and an emitter region (323); The isolation region (310) is an inner and outer double-layer structure; the piezoresistive region (330) is located in the inner layer of the isolation region (310); and the gain circuit region (320) is located between the inner layer and the outer layer of the isolation region (310).

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