Preparation method of Cavity-SOI (Silicon On Insulator) with thermal oxide layer on inner wall of cavity

Abstract

The invention discloses a preparation method of a Cavity-SOI (Silicon-On-Insulator) with a thermal oxide layer bestrewed on the inner wall of a cavity, and relates to the technical field of Cavity-SOI manufacturing, and the method comprises the steps of obtaining a cavity wafer, carrying out a primary thermal oxidation process on the cavity wafer, forming a primary thermal oxide layer, etching and removing the primary thermal oxide layer by adopting a wet process, and carrying out a secondary thermal oxidation process on the cavity wafer. And forming a secondary thermal oxide layer, and bonding the cavity wafer with another wafer to obtain the Cavity-SOI structure. According to the preparation method of the Cavity-SOI, the smooth and sinking effects of the thermal oxidation process on the corner of the non-planar silicon structure are utilized, the thermal oxidation process is applied twice, the micro-bulge effect of the thermal oxidation layer at the corner of the silicon is weakened, the micro-bulge effect is controlled below the top bonding surface, and the subsequent silicon-silicon direct bonding process is facilitated.

Description

Technical Field

[0001] The invention relates to the technical field of Cavity-SOI manufacturing, and in particular to a method for preparing a Cavity-SOI in which the inner wall of a cavity is covered with a thermal oxidation layer. Background Art

[0002] In the MEMS silicon wafer process technology, the silicon dioxide layer grown by the thermal oxidation process has the advantages of dense film, good uniformity, and strong insulation. It is a common process in silicon-silicon direct bonding, SOI preparation and other technologies. In the MEMS device processing technology, the preparation of Cavity-SOI structure is often involved. Taking MEMS inertial devices as a typical application, its bulk silicon processing technology requires the production of Cavity-SOI structure. A common process scheme is to first thermally oxidize the initial silicon substrate wafer to form a silicon dioxide insulation layer, and then perform oxide layer etching and deep cavity silicon etching after photolithography of the anchor point pattern, and then perform silicon-silicon direct bonding with another silicon double-polished wafer or SOI wafer, thin the bonded wafer to the required thickness, and then perform deep silicon etching to form the sensitive structure of the device. In this process scheme, since there is no thermal oxide layer at the bottom and sidewalls of the cavity, the silicon substrate wafer will be severely etched during the deep silicon etching of the sensitive structure, causing device reliability problems.

[0003] In order to prevent the etching damage to the substrate silicon during the deep silicon etching of the sensitive structure, it is necessary to first perform deep cavity silicon etching, and then perform a thermal oxidation process, so that the inner wall of the cavity is covered with a thermal oxide layer, and then perform silicon-silicon direct bonding and sensitive structure etching processes. In addition to the above, MEMS devices often involve the use of a thermal oxidation process to grow a silicon dioxide layer on a non-planar surface with a cavity three-dimensional structure, and then perform a silicon-silicon direct bonding process with another wafer to form a Cavity-SOI structure with a cavity inner wall covered with a thermal oxide layer.

[0004] However, experimental results show that when the thermal oxidation process is performed on a non-planar surface with a three-dimensional cavity structure, micro-bumps will form on the thermal oxidation layer at the corners of the silicon step due to the large contact surface, that is, the surface of the oxide layer on the top bonding surface of the wafer is uneven, and these micro-bumps are nanometer-sized. However, direct silicon-silicon bonding requires extremely high flatness of the wafer bonding surface, and these nanometer-sized micro-bumps will cause bonding failure.

[0005] In order to avoid failure of the silicon-silicon direct bonding process, the usual preparation method is: (1) after thermal oxidation, photolithography exposes the oxide layer at the corner, and then removes the micro-bumps of the thermal oxide layer by dry etching or wet etching; or (2) on the bonding surface of another bonded wafer, photolithography exposes the corresponding position of the micro-bump of the thermal oxide layer, and then etches a shallow cavity to remove the silicon at the corresponding position of the micro-bump. Method (1) involves deep cavity lithography, which is difficult and inefficient, does not meet the needs of mass production, and may not be realized when the cavity depth is large; method (2) adds more process steps and involves alignment bonding, which also increases the complexity of the process and does not meet the needs of mass production.

[0006] The invention application with application number 202410541275.X discloses a preparation process for the vacuum cavity structure of a high-temperature Cavity-SOI absolute pressure sensor chip. The application scheme solves the problems of long outsourcing processing cycle, high cost, and uncontrollable process of the vacuum cavity silicon-silicon bonding Cavity-SOI process of the high-temperature MEMS absolute pressure sensor chip. However, it also has the problem that the thermal oxide layer will form micro-bumps, affecting the silicon-silicon bonding. Summary of the invention

[0007] In view of the above-mentioned problems, the purpose of the present invention is to provide a Cavity-SOI preparation method in which the inner wall of the cavity is covered with a thermal oxide layer, and two thermal oxidation processes are used to weaken the micro-protrusions of the thermal oxide layer at the silicon corners, which is beneficial to the silicon-silicon bonding process.

[0008] The object of the present invention can be achieved by the following technical solution: A method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer, comprising:

[0009] S1. Making a cavity on a wafer to obtain a cavity wafer;

[0010] S2. Perform a thermal oxidation process on the cavity wafer to form a thermal oxidation layer

[0011] S3, using a wet etching process to remove the primary thermal oxide layer;

[0012] S4, performing a secondary thermal oxidation process on the cavity wafer to form a secondary thermal oxidation layer;

[0013] S5. Bond the cavity wafer to another wafer to obtain a Cavity-SOI structure.

[0014] As a further solution of the present invention, the steps of making a cavity on a silicon substrate wafer in S1 include:

[0015] S11, obtaining an anchor point pattern by using a photolithography process;

[0016] S12. Based on the anchor point pattern, a deep silicon etching process is used to etch a deep cavity.

[0017] As a further solution of the present invention, the wafer in S1 adopts a silicon substrate.

[0018] As a further solution of the present invention, when a thermal oxidation process is carried out in S2, the reaction gases are O2 and H2O.

[0019] As a further solution of the present invention, when a thermal oxidation process is performed in S2, the oxidation temperature ranges from 1000°C to 1200°C, wherein the silicon corners wrapped by the primary thermal oxidation layer sink slightly below the top surface of the cavity wafer.

[0020] As a further solution of the present invention, when a thermal oxidation process is performed in S2, the oxidation temperature is 1100°C.

[0021] As a further solution of the present invention, the wet process in S3 adopts a BOE wet process.

[0022] As a further solution of the present invention, the thickness of the primary thermal oxidation layer is adjusted according to the required thickness of the secondary thermal oxidation layer.

[0023] As a further solution of the present invention, the thickness of the primary thermal oxidation layer ranges from 1 μm to 3 μm.

[0024] As a further solution of the present invention, in S5, after the cavity wafer is bonded with another wafer, a thinning process is performed to obtain Cavity-SOI.

[0025] Beneficial effects of the present invention:

[0026] 1. The Cavity-SOI preparation method of the present invention utilizes the rounding and sinking effect of the thermal oxidation process on the corners of the non-planar silicon structure, and uses two thermal oxidation processes to weaken the micro-protrusion effect of the thermal oxide layer at the silicon corners and control it below the top bonding surface, which is beneficial to the subsequent silicon-silicon direct bonding process.

[0027] 2. The Cavity-SOI preparation method of the present invention has a simple and easy-to-control process flow, the inner wall of the cavity and the bonding surface have a uniform thermal oxide layer, does not involve deep cavity lithography and alignment bonding, is suitable for batch manufacturing, and has strong flexibility. It can realize structures that are difficult to achieve with traditional methods and meet the complex and changeable application requirements of MEMS device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of the cavity wafer of the present invention;

[0029] Figure 2This is a schematic diagram of the structure of the cavity wafer after one thermal oxidation of the present invention;

[0030] Figure 3 It is a schematic diagram of the structure of the cavity wafer after the wet process of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure of the cavity wafer after one thermal oxidation of the present invention;

[0032] Figure 5 It is a schematic diagram of the structure after the silicon-silicon bonding process of the present invention;

[0033] Figure 6 It is a schematic diagram of the structure after the thinning process of the present invention.

[0034] 110, cavity wafer; 120, silicon substrate; 130, primary thermal oxide layer; 140, secondary thermal oxide layer; 150, silicon corner; 160, micro-bump; 170, bonded wafer. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0036] When obtaining a Cavity-SOI structure in which the inner wall of the cavity is covered with a thermal oxide layer, micro-bumps 160 are formed on the thermal oxide layer at the corners of the silicon steps due to the large contact surface, that is, the surface of the oxide layer on the bonding surface of the top of the wafer is uneven. These micro-bumps 160 are nanometer-scale, and direct silicon-silicon bonding has extremely high requirements on the flatness of the wafer bonding surface. These nanometer-scale micro-bumps 160 may cause bonding failure.

[0037] In view of the above problems, the present invention discloses a method for preparing Cavity-SOI in which the inner wall of the cavity is covered with a thermal oxide layer, such as Figures 1 to 6 As shown, the steps include:

[0038] S1, making a cavity on a wafer to obtain a cavity wafer 110;

[0039] S2, performing a thermal oxidation process on the cavity wafer 110 to form a thermal oxidation layer 130;

[0040] S3, removing the primary thermal oxide layer 130 by wet etching;

[0041] S4, performing a secondary thermal oxidation process on the cavity wafer 110 to form a secondary thermal oxidation layer 140;

[0042] S5. Bond the cavity wafer 110 to another bonding wafer 170 to obtain a Cavity-SOI structure.

[0043] Example: Figure 1 As shown, the wafer adopts a silicon substrate 120, and a wafer cavity structure is manufactured through photolithography and deep silicon etching processes to obtain a cavity wafer 110. Specifically, the anchor point pattern is first obtained by photolithography, and then a deep silicon etching process is used to etch a deep cavity based on the anchor point pattern, for example, the etching depth is 50μm.

[0044] First, a thermal oxidation process is performed on the cavity wafer 110 , with O 2 and H 2 O being used as reaction gases, and the oxidation temperature being controlled at 1100° C., and the thickness of the formed primary thermal oxidation layer 130 being 2 μm.

[0045] After a thermal oxidation process, Figure 2 As shown, the primary thermal oxide layer 130 forms a micro-bump 160 at the silicon corner 150, causing the surface of the top bonding surface oxide layer to be uneven, affecting the subsequent silicon-silicon direct bonding process. At the same time, the silicon corner 150 wrapped by the thermal oxide layer will have a rounded morphology and sink below the top surface.

[0046] Then, the primary thermal oxide layer 130 is etched cleanly by a BOE wet process to expose the surface of the silicon substrate 120. Figure 3 As shown, at this time, the silicon corner 150 presents a rounded shape and sinks slightly below the top surface.

[0047] The smoothness and sinking degree of the silicon corner 150 can be controlled by controlling the thickness of the primary thermal oxidation layer 130, as well as the gas and oxidation temperature used in the thermal oxidation process; the thickness range of the primary thermal oxidation layer 130 can be controlled to be 1μm to 3μm; the oxidation temperature range can be adjusted between 1000°C and 1200°C. By adjusting and controlling the smoothness of the silicon corner 150, the silicon corner 150 wrapped by the primary thermal oxidation layer 130 sinks slightly lower than the top surface of the cavity wafer 110.

[0048] Then, the cavity wafer 110 is subjected to a secondary thermal oxidation process, and the thickness of the secondary oxidation layer and the oxidation conditions are adopted as required, for example: the reaction gas also uses O2 and H2O, the oxidation temperature is 1100°C, and the thickness of the formed secondary thermal oxidation layer 140 is 2μm, etc. The secondary thermal oxidation process and the primary thermal oxidation process environment are similar, making the entire process simple and easy to control, and having high practical value.

[0049] During the secondary thermal oxidation process, since the silicon corner 150 has a rounded shape and sinks slightly below the top highest surface, the micro-protrusion 160 formed by the secondary thermal oxidation is effectively offset. Figure 4As shown, after the secondary thermal oxidation, the oxide layer at the silicon corner 150 is no longer slightly raised 160, and the oxide layer surface used for bonding is flat, which can meet the subsequent silicon-silicon direct bonding process and meet the requirements of bonding surface flatness, which is conducive to obtaining a high-quality Cavity-SOI structure.

[0050] After the secondary thermal oxidation, the cavity inner wall and bonding surface of the cavity wafer 110 have a uniform thermal oxidation layer, such as Figure 5 As shown, the cavity wafer 110 is directly bonded to another bonding wafer 170 by silicon-silicon direct bonding, and then thinned to a desired thickness, as shown in FIG. Figure 6 As shown, the production of Cavity-SOI with the inner wall of the cavity covered with a thermal oxide layer is completed.

[0051] The preparation method of Cavity-SOI of the present invention has a simple and easy-to-control process flow, the inner wall of the cavity and the bonding surface have a uniform thermal oxide layer, deep cavity lithography and alignment bonding are not involved, it is suitable for batch manufacturing, and it has strong flexibility and can realize structures that are difficult to achieve with traditional methods, thus meeting the complex and changeable application requirements of MEMS device manufacturing.

[0052] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

[0053] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

Claims

1. A method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer, characterized in that: include: S1, making a cavity on a wafer to obtain a cavity wafer (110); S2, performing a thermal oxidation process on the cavity wafer (110) to form a primary thermal oxidation layer (130); S3, removing the primary thermal oxide layer (130) by etching using a wet process; S4, performing a secondary thermal oxidation process on the cavity wafer (110) to form a secondary thermal oxidation layer (140); S5. Bond the cavity wafer (110) to another bonding wafer (170) to obtain a Cavity-SOI structure.

2. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: The wafer in S1 uses a silicon substrate (120).

3. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 2, characterized in that: In S1, a cavity is formed on a wafer, and the steps include: S11, obtaining an anchor point pattern by using a photolithography process; S12. Based on the anchor point pattern, a deep silicon etching process is used to etch a deep cavity.

4. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: When a thermal oxidation process is performed in S2, the reaction gases are O2 and H2O.

5. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 4, characterized in that: When a thermal oxidation process is performed in S2, the oxidation temperature ranges from 1000° C. to 1200° C., wherein the silicon corner (150) wrapped by the primary thermal oxidation layer (130) sinks slightly below the top surface of the cavity wafer (110).

6. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 5, characterized in that: When a thermal oxidation process is performed in S2, the oxidation temperature is 1100°C.

7. The method for preparing Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: The wet process in S3 adopts BOE wet process.

8. The method for preparing Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: The thickness of the primary thermal oxidation layer (130) is adjusted according to the required thickness of the secondary thermal oxidation layer (140).

9. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 8, characterized in that: The thickness of the primary thermal oxidation layer (130) ranges from 1 μm to 3 μm.

10. The method for preparing Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: In S5, after the cavity wafer (110) is bonded to another bonding wafer (170), a thinning process is performed to obtain Cavity-SOI.

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