Three-layer silicon-based accelerometer and manufacturing method thereof

Abstract

The invention provides a manufacturing method of a three-layer silicon-based accelerometer, which comprises a first step, a second step, a third step and a fourth step, the first step comprises forming a silicon dioxide bonding layer on the surface of a clamped layer of a first substrate and carrying out patterning and etching treatment to form a first bonding anchor point, and the second step comprises forming a silicon dioxide bonding layer on the surface of the clamped layer of the first substrate based on the first bonding anchor point. The method includes the first step of bonding a functional layer of a second substrate with a silicon dioxide bonding layer of a first substrate to form a double-layer structure, and conducting thinning, patterning and etching treatment to obtain a double-layer accelerometer comb tooth structure, and the third step of conducting etching on the surface of a third substrate to form second bonding anchor points to obtain the double-layer accelerometer comb tooth structure. The method includes the first step of bonding a comb tooth structure of the double-layer accelerometer with a functional layer, the second step of bonding the comb tooth structure of the double-layer accelerometer with the functional layer, the third step of carrying out patterning and metal deposition processing on the surface of a third substrate to obtain a surface-patterned electrode layer, and the fourth step of bonding the comb tooth structure of the double-layer accelerometer with the surface-patterned electrode layer based on second bonding anchor points to obtain a three-layer structure, the first substrate, the second substrate and the third substrate are silicon wafers, and the clamped layer and the functional layer are silicon layers.

Description

Technical Field

[0001] The present invention relates to the field of sensors, and more particularly to a three-layer silicon-based accelerometer and a manufacturing method thereof. Background Art

[0002] Silicon accelerometers are sensors that use MEMS processing technology to convert input acceleration into output (usually electrical parameters) in proportion. The basic structure of a capacitive MEMS accelerometer is a capacitor composed of a mass block and a fixed electrode. When the mass block is displaced by acceleration, the plate area or spacing of the capacitor changes, and the acceleration is measured by measuring the capacitance. Capacitive MEMS accelerometers have been widely used in instrument measurement, wireless communications, energy and environment, biomedicine, military defense, aerospace, automotive electronics, consumer electronics and other fields.

[0003] Based on different application scenarios and requirements, silicon accelerometers have different structures and process flows, but most of them have problems such as poor full-temperature performance and complex processing flows, which seriously affect the product performance and processing cycle of silicon accelerometers. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a three-layer silicon-based accelerometer and a manufacturing method thereof.

[0005] According to one aspect of the present invention, a method for manufacturing a three-layer silicon-based accelerometer is provided, comprising a first step, a second step, a third step and a fourth step, wherein the first step comprises: forming a silicon dioxide bonding layer on the surface of a fixed support layer of a first substrate; patterning the silicon dioxide bonding layer; etching the pattern formed by the silicon dioxide bonding layer to form a first bonding anchor point, the second step comprises: bonding a functional layer of a second substrate to the silicon dioxide bonding layer of a first substrate based on the first bonding anchor point to form a double-layer structure; thinning the functional layer; patterning and etching the thinned functional layer to obtain a double-layer accelerometer comb structure, the third step comprises: forming a second bonding anchor point by etching the surface of a third substrate; forming a first insulating layer on the surface, and patterning the first insulating layer; The invention relates to a method for manufacturing a surface-patterned accelerometer of a semiconductor device and a semiconductor material. The method comprises the steps of: forming a first metal layer on the surface of the first insulating layer subjected to patterning, and patterning the first metal layer; forming a second insulating layer on the surface of the first metal layer subjected to patterning, and patterning the second insulating layer; forming a second metal layer on the surface of the second insulating layer subjected to patterning, and patterning the second metal layer to obtain a surface-patterned electrode layer. The fourth step comprises: based on the second bonding anchor point, bonding the double-layer accelerometer comb structure obtained by the second step with the surface-patterned electrode layer obtained by the third step to obtain a three-layer structure; forming a third metal layer on the surface of the three-layer structure, and patterning the third metal layer to obtain a three-layer silicon-based accelerometer, wherein the first substrate, the second substrate and the third substrate are silicon wafers, and the fixed support layer and the functional layer are silicon layers.

[0006] Furthermore, the first step further includes: after thinning the functional layer, performing surface treatment on the functional layer to form a metal bonding layer.

[0007] Furthermore, in the first step, a silicon dioxide bonding layer is formed on the surface of the anchor layer by thermal oxidation or PECVD process.

[0008] Furthermore, in the first step, the pattern formed by the silicon dioxide bonding layer is etched by a dry etching or a wet etching process.

[0009] Further, in the first step, the thinning process includes CMP.

[0010] According to another aspect of the present invention, a method for manufacturing a three-layer silicon-based accelerometer is provided, comprising a first step, a second step, a third step, a fourth step and a fifth step, wherein the first step comprises: forming a silicon dioxide bonding layer on the surface of a fixed support layer of a first substrate; patterning the silicon dioxide bonding layer; etching the pattern formed by the silicon dioxide bonding layer to form a first bonding anchor point, the second step comprises: etching the functional layer of the second substrate to obtain an accelerometer comb tooth structure, the third step comprises: bonding the functional layer of the second substrate to the silicon dioxide bonding layer of the first substrate based on the first bonding anchor point to form a double-layer structure; removing the bottom silicon and silicon dioxide buried oxide layer of the second substrate to obtain a double-layer accelerometer comb tooth structure, the fourth step comprises: forming a second bonding anchor point by etching the surface of the third substrate; forming a first insulating layer on the surface, and patterning the first insulating layer; forming a first metal layer on the surface of the patterned first insulating layer and patterning the first metal layer; forming a second insulating layer on the surface of the patterned first metal layer and patterning the second insulating layer; forming a second metal layer on the surface of the patterned second insulating layer and patterning the second metal layer to obtain a surface patterned electrode layer. The fifth step includes: based on the second bonding anchor point, bonding the double-layer accelerometer comb structure obtained by the third step with the surface patterned electrode layer obtained by the fourth step to obtain a three-layer structure; forming a third metal layer on the surface of the three-layer structure and patterning the third metal layer to obtain a three-layer silicon-based accelerometer, wherein the first substrate and the third substrate are silicon wafers, the second substrate is an SOI wafer, and the fixed support layer and the functional layer are silicon layers.

[0011] Furthermore, in the first step, a silicon dioxide bonding layer is formed on the surface of the anchor layer by thermal oxidation or PECVD process.

[0012] Furthermore, in the first step, the pattern formed by the silicon dioxide bonding layer is etched by a dry etching or a wet etching process.

[0013] Further, in the first step, the thinning process includes CMP.

[0014] According to another aspect of the present invention, there is provided a three-layer silicon-based accelerometer manufactured according to the above method for manufacturing the three-layer silicon-based accelerometer.

[0015] The present invention adopts a three-layer all-silicon-based solution and improves the full-temperature performance, sealing and impact resistance of the accelerometer through key processes such as silicon-silicon bonding, grinding and polishing, and cavity deep silicon etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1is a schematic diagram showing the structure of a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0017] Figure 2 is a flow chart showing a method for manufacturing a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0018] Figure 3 is a flow chart showing a method for manufacturing a three-layer silicon-based accelerometer according to another embodiment of the present invention.

[0019] Figure 4 FIG. 4 is a schematic diagram showing the structure of a three-layer silicon-based accelerometer according to another embodiment of the present invention.

[0020] Figure 5 is a flow chart showing a method for manufacturing a three-layer silicon-based accelerometer according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] Figure 1 is a schematic diagram showing the structure of a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0023] Reference Figure 1 The structure of the three-layer silicon-based accelerometer includes a fixed support layer 1 with a cavity anchor point, a silicon dioxide bonding layer 3, a functional layer 5, an accelerometer comb structure 6, an electrode layer 7 with a cavity anchor point, an anchor point 9, a first metal layer 11 for grounding and electrical connection, a first insulating layer 10 for isolating the first metal layer 11 from the electrode layer 7, a second metal layer 13 for gold-silicon bonding, grounding and electrical connection, a second insulating layer 12 for isolating the first metal layer 11 from the second metal layer 13, and a third metal layer 14 for grounding.

[0024] Although Figure 1 The scribe line and the alignment marks 2 and 8 are shown in FIG. 8 , but the scribe line and the alignment marks 2 and 8 are only used for alignment purposes and can be omitted.

[0025] Figure 2 is a flow chart showing a method for manufacturing a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0026] Reference Figure 2 Combined with Figure 1 , the manufacturing method of the three-layer silicon-based accelerometer comprises steps (a)-(p).

[0027] Although Figure 2 Step (a) is shown in FIG. 1 and represents making scribe lines and alignment marks 2 on the back side of the anchor layer 1 of the first substrate, but step (a) is only for alignment purposes and can therefore be omitted in the manufacturing method.

[0028] In the embodiment, the first substrate may be a silicon wafer, preferably, a double-patterned low-resistance silicon wafer, which is not limited in the present invention. The support layer 1 may be a silicon layer.

[0029] In an embodiment, step (b) may include preparing a silicon dioxide bonding layer 3 on the surface of the anchor layer 1, wherein the silicon dioxide bonding layer 3 may be prepared by using a process such as thermal oxidation or PECVD, and the present invention is not particularly limited thereto.

[0030] Thermal oxidation is a process that forms a thin film of silicon oxide on the surface of a silicon substrate. When the silicon wafer is heated, silicon reacts with oxygen or water vapor to form a silicon dioxide film.

[0031] PECVD is a process for forming a silicon oxide film on the surface of a silicon substrate. By using precursors such as silane and silicon dioxide gas, under the action of plasma, the silicon and oxygen in the precursor gas react chemically on the surface of the substrate to form a silicon dioxide film.

[0032] In an embodiment, step (c) may include patterning the silicon dioxide bonding layer 3 , wherein the patterning may include processes such as exposure and development.

[0033] Exposure is a process of exposing a photoresist (photosensitive material) to a light source. At this stage, the photoresist is coated on the surface of the silicon wafer, and then a specific pattern is transferred to the photoresist through a mask. The main steps of exposure include: coating: evenly coating the photoresist on the surface of the silicon wafer; alignment: using a mask to align the surface of the photoresist to ensure that the pattern can be transferred correctly; irradiation: irradiating the photoresist with ultraviolet light or other suitable light sources.

[0034] Development is the chemical treatment of the exposed photoresist to remove the unexposed or exposed parts to form the final pattern. The development process includes: immersion or spraying: immersing the silicon wafer in the developer, or spraying the developer on the surface of the silicon wafer; removing the photoresist: the developer will selectively remove the photoresist, usually removing the unexposed area (for positive photoresist) or the exposed area (for negative photoresist); cleaning and drying: after development, the residual developer and photoresist need to be removed through cleaning and drying steps.

[0035] In an embodiment, step (d) may include preparing bonding anchor points 4 according to the pattern of the silicon dioxide bonding layer 3 , wherein the bonding anchor points 4 may be prepared by dry etching or wet etching.

[0036] Dry etching is a process that uses gas phase reactions to remove materials, which usually includes the following steps: gas introduction: introducing specific gases (such as hydrogen fluoride, chloride, etc.) into the etching chamber; plasma generation: exciting the gas through radio frequency (RF) or microwaves to generate plasma. The active particles in the plasma can react with the material to be etched; reaction and removal: the particles in the plasma react with the surface of the material to form volatile by-products, which are then extracted to achieve material removal.

[0037] Wet etching is a process that uses liquid chemical solutions to remove materials, which usually includes the following steps: Solution selection: Select a suitable etching solution (such as hydrofluoric acid, sulfuric acid, sodium hydroxide, etc.) according to the type of material that needs to be removed; Soak or spray: Immerse the silicon wafer in the etching solution, or spray the etching solution on the surface of the material in a spray manner; Reaction: The etching solution reacts chemically with the surface of the material to form soluble by-products, and the material is removed; Rinse and dry: After etching is completed, use deionized water to rinse the silicon wafer to remove residual etching solution, and finally dry it.

[0038] Since the silicon dioxide bonding layer 3 is patterned and then etched, the formed bonding anchor point 4 can be a cavity anchor point.

[0039] In an embodiment, step (e) may include performing silicon-silicon bonding between the functional layer 5 of the second substrate and the anchor layer 1 based on the bonding anchor point 4, thereby forming a double-layer structure.

[0040] In the embodiment, the second substrate may be a silicon wafer, preferably, a double-patterned low-resistance silicon wafer, which is not limited in the present invention. The functional layer 5 may be a silicon layer.

[0041] In an embodiment, step (f) may include thinning and grinding the functional layer 5 included in the double-layer structure to obtain a predetermined thickness, wherein the thinning and grinding may be achieved by a CMP process.

[0042] CMP is a process used to flatten the surface of a wafer. It mainly includes: applying a polishing slurry containing chemicals and abrasives to the surface of the wafer; applying pressure to the wafer through a polishing disk, and rotating the wafer at the same time to make the polishing slurry fully contact with the wafer surface. The abrasive will physically grind the wafer surface, while the chemical components help remove the material; after polishing, the wafer needs to be cleaned to remove the residual polishing slurry and the waste generated.

[0043] In an embodiment, step (g) may include patterning and etching the thinned functional layer 5 , so as to obtain the accelerometer comb-tooth structure 6 .

[0044] The patterning and etching processes are described above with reference to steps (c) and (d), and step (g) will not be described in detail herein.

[0045] In particular, in step (g), a deep silicon etching process may be used.

[0046] Deep silicon etching usually uses dry etching technology, among which reactive ion etching or deep reactive ion etching is the most commonly used.

[0047] Although Figure 2 Step (h) is shown in FIG. 1 and represents making scribe lines and alignment marks 8 on the back side of the third substrate, but step (h) is only for alignment purposes and can therefore be omitted in the manufacturing method.

[0048] In an embodiment, the third substrate may be a silicon wafer, preferably, a double-throw low-resistance silicon wafer, which is not limited in the present invention.

[0049] In an embodiment, step (i) may include forming the anchor point 9 on the front side of the third substrate using dry etching or wet etching.

[0050] In an embodiment, step (j) may include preparing and patterning a first insulating layer 10 on the surface of the third substrate by thermal oxidation or PECVD, wherein the first insulating layer 10 may be silicon dioxide or silicon nitride.

[0051] In an embodiment, step (k) may include preparing and patterning the first metal layer 11 by sputtering or evaporation, wherein the first metal layer 11 may be any one or more of gold, titanium, tungsten, and the like.

[0052] In an embodiment, step (1) may include preparing and patterning a second insulating layer 12 , wherein the second insulating layer 12 may be silicon dioxide (or silicon nitride).

[0053] In an embodiment, step (m) may include preparing the second metal layer 13 by sputtering or evaporation and patterning the second metal layer 13 , and the second metal layer 13 may be gold, thereby obtaining the electrode layer 7 .

[0054] In an embodiment, step (n) may include bonding the functional layer 5 with the accelerometer comb structure 6 obtained in step (g) to the surface patterned electrode layer 7 obtained in step (m), for example, gold-silicon bonding.

[0055] In an embodiment, step (o) may include preparing the third metal layer 14 by sputtering or evaporation and patterning it, thereby obtaining a three-layer accelerometer.

[0056] Optionally, the method may further include step (p): obtaining a single three-layer accelerometer by slicing.

[0057] As above Figure 2The present invention provides a method for manufacturing a three-layer silicon-based accelerometer. In order to improve the problem of the difficulty of cavity deep silicon etching in the above method, the present invention provides a new method, which will be referred to below. Figure 3 Give a description.

[0058] Reference Figure 3 Combined with Figure 1 , the manufacturing method of the three-layer silicon-based accelerometer comprises steps (a)-(q).

[0059] Although Figure 3 Step (a) is shown in FIG. 1 and represents making scribe lines and alignment marks on the back side of the anchor layer 1 of the first substrate, but step (a) is only for alignment purposes and can therefore be omitted in the manufacturing method.

[0060] In the embodiment, the first substrate may be a silicon wafer, preferably, a double-patterned low-resistance silicon wafer, which is not limited in the present invention. The support layer 1 may be a silicon layer.

[0061] In an embodiment, step (b) may include preparing a silicon dioxide bonding layer 3 on the surface of the anchor layer 1, wherein the silicon dioxide bonding layer 3 may be prepared by using a process such as thermal oxidation or PECVD, and the present invention is not particularly limited thereto.

[0062] In an embodiment, step (c) may include patterning the silicon dioxide bonding layer 3 , wherein the patterning may include processes such as exposure and development.

[0063] In an embodiment, step (d) may include preparing bonding anchor points 4 according to the pattern of the silicon dioxide bonding layer 3 , wherein the bonding anchor points 4 may be prepared by dry etching or wet etching.

[0064] Since the silicon dioxide bonding layer 3 is patterned and then etched, the formed bonding anchor point 4 can be a cavity anchor point.

[0065] Although Figure 3 Step (e) is shown in FIG. 1 and represents making scribe lines and alignment marks on the back side of the SOI wafer 15 , but step (e) is only for alignment purposes and can therefore be omitted in the manufacturing method.

[0066] In an embodiment, step (f) may include preparing the accelerometer comb structure 6 on the second substrate 15 .

[0067] According to the present invention, the second substrate 15 may be an SOI wafer, but the present invention is not limited thereto. The method will be described below only with the second substrate 15 being an SOI wafer.

[0068] The SOI wafer 15 comprises a three-layer structure, which comprises a base layer of silicon at the bottom, a silicon dioxide buried oxide layer in the middle, and a silicon layer (ie, a functional layer) 5 at the surface.

[0069] In the embodiment, the accelerometer comb-tooth structure 6 can be obtained by etching the functional layer 5 of the SOI wafer 15 .

[0070] In an embodiment, step (g) may include performing silicon-silicon bonding between the accelerometer comb structure 6 obtained in step (f) and the fixed support layer 1 on which the bonding anchor point 4 is formed in step (d).

[0071] In an embodiment, step (h) may include removing the SOI substrate silicon and the silicon dioxide buried oxide layer of the SOI wafer 15 . The removal of the SOI substrate silicon may be accomplished by polishing or deep silicon etching, and the removal of the silicon dioxide buried oxide layer may be accomplished by wet etching or VHF.

[0072] In particular, polishing may include a CMP process.

[0073] Although Figure 3 Step (i) is shown in FIG. 1 and represents making scribe lines and alignment marks 8 on the back side of the third substrate, but step (i) is only for alignment purposes and can therefore be omitted in the manufacturing method.

[0074] In an embodiment, the third substrate may be a silicon wafer, preferably, a double-throw low-resistance silicon wafer, which is not limited in the present invention.

[0075] In an embodiment, step (j) may include forming anchor points 9 on the front side of the third substrate using dry etching or wet etching.

[0076] In an embodiment, step (k) may include preparing and patterning a first insulating layer 10 on the surface of the third substrate by thermal oxidation or PECVD, wherein the first insulating layer 10 may be silicon dioxide or silicon nitride.

[0077] In an embodiment, step (1) may include preparing the first metal layer 11 by sputtering or evaporation and patterning the first metal layer 11 , wherein the first metal layer 11 may be any one or more of gold, titanium, tungsten, and the like.

[0078] In an embodiment, step (m) may include preparing and patterning a second insulating layer 12 , wherein the second insulating layer 12 may be silicon dioxide (or silicon nitride).

[0079] In an embodiment, step (n) may include preparing the second metal layer 13 by sputtering or evaporation and patterning the second metal layer 13 , and the second metal layer 13 may be gold, thereby obtaining the electrode layer 7 .

[0080] In an embodiment, step (o) may include bonding the functional layer 5 with the accelerometer comb structure 6 obtained in step (f) to the surface patterned electrode layer 7 obtained in step (m), for example, by gold-silicon bonding.

[0081] In an embodiment, step (p) may include preparing the third metal layer 14 by sputtering or evaporation and patterning it, thereby obtaining a three-layer accelerometer.

[0082] Optionally, the method may further include step (q): obtaining a single three-layer accelerometer by slicing.

[0083] Reference above Figure 2 and Figure 3 Describes Figure 1 The preparation method of the three-layer accelerometer of the structure shown in the figure is to prevent Figure 1 The gold-silicon bonding in the structure shown in the figure is prone to overflow. The present invention proposes a new structure (as shown below) Figure 4 As shown), this structure is compared to Figure 1 The structure adds a metal bonding layer ( Figure 4 The metal bonding layer 18 is represented by the reference numeral 18 in the figure), and the metal bonding layer 18 is used for signal extraction or subsequent bonding (for example, bonding with the electrode layer 7).

[0084] Reference Figure 4 The structure of the three-layer silicon-based accelerometer includes Figure 1 In addition to the fixed support layer 1 with cavity anchor points, the silicon dioxide bonding layer 3, the functional layer 5, the accelerometer comb structure 6, the electrode layer 7 with cavity anchor points, the anchor point 9, the first metal layer 11 for grounding and electrical connection, the first insulating layer 10 for isolating the first metal layer 11 from the electrode layer 7, the second metal layer 13 for gold-silicon bonding, grounding and electrical connection, the second insulating layer 12 for isolating the first metal layer 11 from the second metal layer 13, and the third metal layer 14 for grounding, there is also a metal bonding layer 18.

[0085] Figure 5 Shows Figure 4 The manufacturing method of the structure shown in FIG. Figure 4 The structure shown is Figure 1 The difference between the structures shown is only in the metal bonding layer 18, so compared to the reference Figure 2 Description of the manufacturing Figure 1 The method of the structure shown, Figure 5 The method may further include the following steps: after the thinning process and before the deep silicon etching, a step of preparing a metal bonding layer 18 on the surface of the functional layer 5 by evaporation or sputtering (eg Figure 5 As shown in step (g) in Figure 5 Except for step (g), the other steps are the same as Figure 2 The steps described are identical, so to avoid repetition, Figure 5 The process will not be described in detail.

[0086] The present invention obtains a three-layer accelerometer by silicon-silicon bonding, gold-silicon bonding, etc. This method has good airtightness, does not require subsequent tube and shell packaging, and has good full-temperature performance due to the use of an all-silicon solution. The cavity depth can be flexibly designed according to the application environment to improve impact resistance.

[0087] This specification includes many details of specific embodiments, but it should be understood that these details do not limit any inventive concepts or what is claimed in the specification, but rather describe features of some exemplary embodiments.

[0088] Features described in the specification in the context of each exemplary embodiment may be implemented as a combination in one or more single exemplary embodiments. Conversely, various features described in the specification in the context of a single exemplary embodiment may be implemented as multiple exemplary embodiments individually or in appropriate sub-combinations.

[0089] Furthermore, features may be operated in a particular combination and may initially be described as claimed in the combination, but in certain cases one or more features may be excluded from the claimed combination and the claimed combination may be changed into a sub-combination or a modification of the sub-combination.

[0090] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that the operations be performed in a particular order or sequentially to achieve desirable results, nor should it be understood as requiring that all operations be performed.

[0091] While the inventive concept has been described in conjunction with what are presently considered to be practical exemplary embodiments, it should be understood that the inventive concept is not limited to such exemplary embodiments. Rather, the inventive concept is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a three-layer silicon-based accelerometer, characterized in that: The method comprises a first step, a second step, a third step and a fourth step, The first step includes: forming a silicon dioxide bonding layer on the surface of the fixed support layer of the first substrate; Patterning the silicon dioxide bonding layer; The pattern formed by the silicon dioxide bonding layer is etched to form a first bonding anchor point, The second step comprises: Based on the first bonding anchor point, bonding the functional layer of the second substrate to the silicon dioxide bonding layer of the first substrate to form a double-layer structure; Thinning the functional layer; The functional layer that has undergone the thinning process is patterned and etched to obtain a double-layer accelerometer comb structure. The third step comprises: forming a second bonding anchor point by etching the surface of the third substrate; forming a first insulating layer on the surface, and performing patterning on the first insulating layer; forming a first metal layer on the surface of the first insulating layer subjected to patterning, and performing patterning on the first metal layer; forming a second insulating layer on the surface of the patterned first metal layer, and performing patterning on the second insulating layer; forming a second metal layer on the surface of the second insulating layer subjected to patterning, and patterning the second metal layer to obtain an electrode layer with a surface patterning, The fourth step comprises: Based on the second bonding anchor point, the double-layer accelerometer comb structure obtained by the second step is bonded to the surface patterned electrode layer obtained by the third step to obtain a three-layer structure; A third metal layer is formed on the surface of the three-layer structure, and the third metal layer is patterned to obtain the three-layer silicon-based accelerometer. Wherein, the first substrate, the second substrate and the third substrate are silicon wafers, and the fixed support layer and the functional layer are silicon layers.

2. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that: The first step further includes: after thinning the functional layer, performing surface treatment on the functional layer to form a metal bonding layer.

3. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that: In the first step, the silicon dioxide bonding layer is formed on the surface of the anchor layer by thermal oxidation or PECVD process.

4. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that: In the first step, the pattern formed by the silicon dioxide bonding layer is etched by dry etching or wet etching process.

5. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that: In the first step, the thinning process includes CMP.

6. A method for manufacturing a three-layer silicon-based accelerometer, characterized in that: comprising a first step, a second step, a third step, a fourth step and a fifth step, The first step includes: forming a silicon dioxide bonding layer on the surface of the fixed support layer of the first substrate; Patterning the silicon dioxide bonding layer; The pattern formed by the silicon dioxide bonding layer is etched to form a first bonding anchor point, The second step comprises: The functional layer of the second substrate is etched to obtain an accelerometer comb structure. The third step comprises: Based on the first bonding anchor point, bonding the functional layer of the second substrate to the silicon dioxide bonding layer of the first substrate to form a double-layer structure; The bottom silicon and silicon dioxide buried oxide layer of the second substrate are removed to obtain a double-layer accelerometer comb structure. The fourth step comprises: forming a second bonding anchor point by etching the surface of the third substrate; forming a first insulating layer on the surface, and performing patterning on the first insulating layer; forming a first metal layer on the surface of the first insulating layer subjected to patterning, and performing patterning on the first metal layer; forming a second insulating layer on the surface of the patterned first metal layer, and performing patterning on the second insulating layer; forming a second metal layer on the surface of the second insulating layer subjected to patterning, and patterning the second metal layer to obtain an electrode layer with a surface patterning, The fifth step comprises: Based on the second bonding anchor point, the double-layer accelerometer comb structure obtained by the third step is bonded to the surface patterned electrode layer obtained by the fourth step to obtain a three-layer structure; A third metal layer is formed on the surface of the three-layer structure, and the third metal layer is patterned to obtain the three-layer silicon-based accelerometer. The first substrate and the third substrate are silicon wafers, the second substrate is an SOI wafer, and the fixed support layer and the functional layer are silicon layers.

7. The method for manufacturing a three-layer silicon-based accelerometer according to claim 6, characterized in that: In the first step, the silicon dioxide bonding layer is formed on the surface of the anchor layer by thermal oxidation or PECVD process.

8. The method for manufacturing a three-layer silicon-based accelerometer according to claim 6, characterized in that: In the first step, the pattern formed by the silicon dioxide bonding layer is etched by dry etching or wet etching process.

9. The method for manufacturing a three-layer silicon-based accelerometer according to claim 6, characterized in that: In the first step, the thinning process includes CMP.

10. A three-layer silicon-based accelerometer, characterized in that: The three-layer silicon-based accelerometer is manufactured according to the method for manufacturing a three-layer silicon-based accelerometer according to any one of claims 1 to 9.

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