Test circuit board structure and chip test system

Abstract

The invention provides a test circuit board structure and a chip test system, the test circuit board structure is formed by splicing a first daughter board and a second daughter board, and the first daughter board and the second daughter board are respectively provided with a first hollow part and a second hollow part corresponding to a first part and a second part of a packaging chip. The first hollow part and the second hollow part are respectively provided with a plurality of first pin holes and a plurality of second pin holes, and the first pin holes and the second pin holes are respectively provided with first conductive columns and second conductive columns. The plurality of first pin holes and the plurality of second pin holes are respectively used for insertion of a plurality of horizontally extending pins on two opposite side surfaces of the packaging chip. In this way, the test circuit board structure is free of a socket, the to-be-verified chip can be replaced, a space is reserved on the back face of the chip, and a fault analysis machine can carry out fault positioning analysis from the back face.

Description

Technical Field

[0001] The present invention relates to a chip verification technology, and more particularly to a socket-less test circuit board structure and a chip test system in which a chip to be verified is replaceable and a space is left on the back of the chip (under the chip) so that a fault analysis machine can perform fault location analysis from the back of the chip to be verified. Background Art

[0002] The existing chip verification technology requires the production of a circuit board with corresponding wiring and components to solder the chip to be verified on the circuit board for chip verification. If an abnormality is found in the chip verification, further fault analysis is required or a focused ion beam (FIB) is used to produce a partial cross-section of the chip and perform circuit repair.

[0003] Existing chip verification technology faces the following technical problems. The chip to be tested that is soldered on the circuit board needs to be desoldered, and the reflow of the chip can easily cause damage to the chip, so it is more difficult to replace the chip. In addition, the chip cover can only be opened from the front, but not from the back. Furthermore, when performing chip fault analysis, the electrical hotspot positioning (for example, InGaAs, OBIRCH or EMMI technology) used cannot locate the fault from the back of the chip. In addition, the focused ion beam machine has a height limit (usually 1 cm). After the circuit board is set on the chip (for example, a dual in-line package chip), the overall height of the circuit board and the chip often exceeds the height limit, so the circuit board and the chip cannot be sent into the focused ion beam machine together to produce a local cross-section of the chip and perform circuit repairs. Summary of the invention

[0004] It can be understood from the above description that the present invention aims to solve the technical problems in the prior art that the chip to be verified must be desoldered and reflowed before it can be replaced, the fault analysis machine cannot perform fault location analysis from the back, and the overall height of the circuit board and the chip often exceeds the height limit.

[0005] In order to solve the above-mentioned conventional problems, an embodiment of the present invention provides a test circuit board structure, which is used to verify at least one chip and includes a first sub-board and a second sub-board. The first sub-board has a first hollow portion corresponding to the first part of the first packaged chip, and the first prepreg material between two adjacent layers of substrates at the first end surface of the first hollow portion of the first sub-board is provided with a plurality of first pin holes, and the plurality of first pin holes are provided with a plurality of first conductive pillars. The second sub-board has a second hollow portion corresponding to the second part of the first packaged chip, and the second prepreg material between two adjacent layers of substrates at the second end surface of the second hollow portion of the second sub-board is provided with a plurality of second pin holes, and the plurality of second conductive pillars are provided with a plurality of second conductive pillars. The first packaged chip has a plurality of horizontally extending pins located on two opposite sides of the first packaged chip, and the plurality of first pin holes and the plurality of second pin holes are respectively used for inserting the plurality of horizontally extending pins on the two opposite sides of the first packaged chip, so that the plurality of horizontally extending pins on the two opposite sides of the first packaged chip contact the plurality of first conductive pillars and the plurality of second conductive pillars respectively.

[0006] In order to solve the above conventional problems, an embodiment of the present invention provides a chip testing system, and the chip testing system includes the above-mentioned testing circuit board structure and at least one chip.

[0007] In summary, the test circuit board structure provided by the present invention is a socket-less circuit board, and the chip to be verified can be replaced without desoldering and reflowing. Moreover, a space can be left on the back side of the chip (under the chip), so that the fault analysis machine can perform fault location analysis from the back side of the chip to be verified. Furthermore, after the chip to be verified is set on the test circuit board structure, the overall height will hardly exceed the height limit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0009] Figure 1 is a schematic top view of a chip testing system according to an embodiment of the present invention;

[0010] Figure 2 is an exploded schematic diagram of a chip testing system according to an embodiment of the present invention;

[0011] Figure 3 is a cross-sectional schematic diagram of a chip testing system according to an embodiment of the present invention;

[0012] Figure 4 is a schematic top view of one of the sub-boards of the test circuit board structure of the chip test system according to an embodiment of the present invention;

[0013] Figure 5is a top view schematic diagram of a chip testing system according to another embodiment of the present invention;

[0014] Figure 6 is a top view schematic diagram of a chip testing system according to another embodiment of the present invention; and

[0015] Figure 7 FIG. 4 is a top view schematic diagram of a chip testing system according to another embodiment of the present invention. DETAILED DESCRIPTION

[0016] Please refer to, Figure 1 1 is a top view of a chip test system according to an embodiment of the present invention. The chip test system 1 comprises a test circuit board structure 10 and at least one packaged chip 11 to be verified. The test circuit board structure 10 is composed of two sub-boards 10a and 10b. The two sub-boards 10a and 10b can be spliced ​​with the packaged chip 11 to form a Figure 1 The chip testing system 1 is provided. The packaged chip 11 has a plurality of horizontally extending pins 112 located on two opposite sides of a package body 111 of the packaged chip 11. The package body 111 has a die inside, and the plurality of horizontally extending pins 112 are electrically connected to the die.

[0017] In the embodiment of the present invention, the packaged chip 11 is a small outline package (SOP) chip, a thin small outline package (TSOP) chip, a very small outline package (VSOP) chip, a reduced SOP (SSOP) chip, a thin reduced SOP (TSSOP) chip, a small outline transistor (SOT) chip or a small outline integrated circuit (SOIC) chip, and the present invention is not limited thereto. As long as the pins on the two opposite sides of the packaged chip 11 extend horizontally, it can be spliced ​​with the daughter boards 10a and 10b of the present invention.

[0018] Please refer to Figure 1 and Figure 2 , Figure 2 It is an exploded schematic diagram of the chip testing system of an embodiment of the present invention. The sub-board 10a on the left has a hollow portion 104 corresponding to the left half of the packaged chip 11, and a plurality of pin holes 102 are opened at the end face of the hollow portion 104 of the sub-board 10a. The sub-board 10a has two connecting end faces 101 located at the upper and lower sides of its hollow portion 104. The sub-board 10b on the right has a hollow portion 104 corresponding to the right half of the packaged chip 11, and a plurality of pin holes 102 are opened at the end face of the hollow portion 104 of the sub-board 10b. The sub-board 10b has two connecting end faces 101 located at the upper and lower sides of its hollow portion 104. In addition, the front sides of the sub-boards 10a and 10b have a plurality of traces 103.

[0019] The plurality of pin holes 102 of the daughter boards 10a and 10b are respectively used for inserting the plurality of horizontally extending pins 112 on the opposite sides of the packaged chip 11, and the two connecting end surfaces 101 of the daughter board 10a can be connected to the two connecting end surfaces 101 of the daughter board 10b (electrically and physically connected). Figure 4 , Figure 4 FIG. 1 is a schematic top view of one of the sub-boards of the test circuit board structure of the chip test system of an embodiment of the present invention. Figure 4 In the embodiment, two connecting end surfaces 101 of the daughter board 10b are provided with a pin arrangement structure, correspondingly, Figure 2 The two connecting end surfaces 101 of the daughter board 10a are also provided with pin header structures. The pin header structure of the daughter board 10a will correspond to the pin header structure of the daughter board 10b. For example, one of them is a pin header structure of a male connector and the other is a pin header structure of a female connector.

[0020] Please refer to Figures 1 to 3 , Figure 3 It is a cross-sectional schematic diagram of a chip testing system according to an embodiment of the present invention. Both sub-boards 10a and 10b are structures of multi-layer substrates, for example, four-layer substrates (first layer substrate L1 to fourth layer substrate L4). The prepreg material PRG between two adjacent layers of substrates (first layer substrate L1, second layer substrate L2) of sub-board 10a is provided with a plurality of pin holes 102, and the prepreg material PRG between two adjacent layers of substrates (first layer substrate L1, second layer substrate L2) of sub-board 10b is provided with a plurality of pin holes 102. In the two sub-boards 10a and 10b, a plurality of conductive columns CV are provided at the plurality of pin holes 102. When the multiple horizontally extending pins 112 on the two opposite sides of the packaged chip 11 are inserted into the multiple pin holes 102 of the daughter boards 10a and 10b, the multiple horizontally extending pins 112 on the two opposite sides of the packaged chip 11 will respectively contact the multiple conductive columns CV of the daughter boards 10a and 10b, and the front and back surfaces of the packaged chip 11 are exposed to the hollow portions 104 of the daughter boards 10a and 10b.

[0021] In addition, please note that the number of layers of the substrate can be more than two layers, and the present invention is not limited to this. Furthermore, the two adjacent layers of the substrate where the pin hole 102 is set is not limited to the present invention, as long as the adjacent two layers of the substrate where the pin hole 102 is set on the sub-board 10a correspond to the adjacent two layers of the substrate where the pin hole 102 is set on the sub-board 10b, for example, both are the first layer of the substrate L1 and the second layer of the substrate L2. Furthermore, the thickness of each of the plurality of horizontally extending pins 112 on the two opposite sides of the package chip 11 can be 0.15 mm, and the thickness of the prepreg PRG between the first layer of the substrate L1 and the second layer of the substrate L2 is 0.2 mm. However, the above thickness is not used to limit the present invention, but the thickness of the horizontally extending pins 112 is less than the thickness of the prepreg between the two adjacent substrates.

[0022] Please refer to Figure 5 , Figure 5 FIG. 1 is a top view schematic diagram of a chip testing system according to another embodiment of the present invention. Figure 1 In the embodiment, the daughter board 10a has a plurality of hollow portions 104, and the daughter board 10b has a plurality of hollow portions 104, so the test circuit board structure 10 can test a plurality of packaged chips 11 at the same time, for example, three packaged chips 11. Similarly, the prepreg between two adjacent layers of the base material at the end surfaces of the plurality of hollow portions 104 of the daughter boards 10a and 10b is provided with a plurality of pin holes 102, and the plurality of pin holes 102 are provided with a plurality of conductive posts.

[0023] Please refer to Figure 6 , Figure 6 is a top view schematic diagram of a chip testing system according to another embodiment of the present invention, which is different from Figure 1 , Figure 5 An embodiment of Figure 6 The daughter boards 10a and 10b are not cut in half at the center point of the test circuit board structure 10. In short, the shapes of the daughter boards 10a and 10b are not intended to limit the present invention, as long as they correspond to each other and can be spliced.

[0024] Please refer to Figure 7 , Figure 7 FIG. 1 is a top view schematic diagram of a chip testing system according to another embodiment of the present invention. Figure 1 , Figure 5 and Figure 6 An embodiment of Figure 7 In the embodiment, the test circuit board structure 10 has three sub-boards 10a, 10b, and 10c. Similarly, the prepreg between two adjacent layers of the base material at the end surfaces of the multiple hollow parts 104 of the sub-boards 10a, 10b, and 10c is provided with multiple pin holes 102, and multiple pin holes 102 have multiple conductive columns. In this way, the three sub-boards 10a, 10b, and 10c can be spliced ​​with multiple packaged chips 11 to form the test circuit board structure 10. In short, there is no limit to the number of sub-boards 10a, 10b, and 10c, as long as there are multiple sub-boards.

[0025] Accordingly, the test circuit board structure and the chip test system provided by the present invention mainly use multiple sub-boards to splice with the chip to be verified. After the multiple sub-boards are spliced ​​with the chip to be verified, the hollowed-out parts thereof will expose the front and back sides (i.e., the front and back sides) of the chip to be verified to the hollowed-out parts, so the fault analysis machine can perform fault location analysis from the back side of the chip to be verified. On the other hand, since the hollowed-out parts of the sub-boards are provided with pin holes so that the sub-boards can be spliced ​​with the chip to be verified, the chip to be verified can be replaced without desoldering and reflowing, and a socket-less test circuit board structure is realized. Furthermore, the chip to be verified is arranged in the hollowed-out part and the test circuit board structure is socket-less, so after the chip to be verified is arranged in the test circuit board structure, there is almost no situation that the overall height often exceeds the height limit. If the overall height really exceeds the height limit, the chip to be verified can also be easily removed, and the chip to be verified can be sent to the focused ion beam machine to manufacture a local cross section of the chip and perform circuit repair.

[0026] The present invention is disclosed herein only in terms of preferred embodiments. However, anyone familiar with the technical field should understand that the above embodiments are only used to describe the present invention and are not used to limit the scope of the patent rights claimed by the present invention. Any changes or substitutions that are equal or equivalent to the above embodiments should be interpreted as being included in the spirit or scope of the present invention. Therefore, the scope of protection of the present invention should be based on what is defined in the claims.

Claims

1. A test circuit board structure for verifying at least one chip, characterized in that: include: The first sub-board has a first hollow portion corresponding to the first part of the first packaged chip, and a first prepreg material between two adjacent layers of the base material at the first end surface of the first hollow portion is provided with a plurality of first pin holes, and the plurality of first pin holes are provided with a plurality of first conductive columns; as well as A second sub-board has a second hollow portion corresponding to the second part of the first packaged chip, a second prepreg material between two adjacent layers of substrate at a second end surface of the second hollow portion is provided with a plurality of second pin holes, and the plurality of second pin holes are provided with a plurality of second conductive columns; The first packaged chip has a plurality of horizontally extending pins located on two opposite side surfaces of the first packaged chip, and the plurality of first pin holes and the plurality of second pin holes are respectively used for inserting the plurality of horizontally extending pins on the two opposite side surfaces of the first packaged chip, so that the plurality of horizontally extending pins on the two opposite side surfaces of the first packaged chip respectively contact the plurality of first conductive pillars and the plurality of second conductive pillars.

2. The test circuit board structure according to claim 1, characterized in that: The first sub-board has at least one first connection end surface located on one side of the first hollow portion, and the second sub-board has at least one second connection end surface located on one side of the second hollow portion, the first connection end surface is provided with a first needle row structure, and the second connection end surface is provided with a second needle row structure corresponding to the first needle row structure, wherein the first connection end surface is used to connect with the second connection end surface.

3. The test circuit board structure according to claim 1, characterized in that: The first packaged chip is a small outline packaged chip, a thin small outline packaged chip, a very small outline packaged chip, a reduced SOP chip, a thin reduced SOP chip, a small outline transistor chip or a small outline integrated circuit chip.

4. The test circuit board structure according to claim 1, characterized in that: The two adjacent layers of base material at the first end surface of the first hollow portion of the first sub-plate correspond to the two adjacent layers of base material at the second end surface of the second hollow portion of the second sub-plate.

5. The test circuit board structure according to claim 1, characterized in that: Also includes: A third sub-board has a third hollow portion of the third part of the second packaged chip, a third prepreg material between two adjacent layers of the base material at the third end surface of the third hollow portion is provided with a plurality of third pin holes, and the plurality of third pin holes are provided with a plurality of third conductive columns; The second sub-board further has a fourth hollow portion corresponding to the fourth part of the second packaged chip, and a fourth prepreg material between two adjacent layers of substrate at a fourth end surface of the fourth hollow portion is provided with a plurality of fourth pin holes, and the plurality of fourth pin holes are provided with a plurality of fourth conductive columns; The second packaged chip has a plurality of horizontally extending pins located on two opposite side surfaces of the second packaged chip, and the plurality of first pin holes and the plurality of second pin holes are respectively used for inserting the plurality of horizontally extending pins on the two opposite side surfaces of the second packaged chip, so that the plurality of horizontally extending pins on the two opposite side surfaces of the second packaged chip respectively contact the plurality of third conductive pillars and the plurality of fourth conductive pillars.

6. The test circuit board structure according to claim 1, characterized in that: The first sub-board further has a third hollow portion corresponding to the third part of the second packaged chip, and a third prepreg material between two adjacent layers of substrate at a third end face of the third hollow portion is provided with a plurality of third pin holes, and a plurality of third conductive columns are provided at the plurality of third pin holes; the second sub-board further has a fourth hollow portion corresponding to the fourth part of another second packaged chip, and a fourth prepreg material between two adjacent layers of substrate at a fourth end face of the fourth hollow portion is provided with a plurality of fourth pin holes, and a plurality of fourth conductive columns are provided at the plurality of fourth pin holes; and the second packaged chip has a plurality of horizontally extending pins located on two opposite side faces of the second packaged chip, and the plurality of first pin holes and the plurality of second pin holes are respectively used for the plurality of horizontally extending pins on the two opposite side faces of the second packaged chip to be inserted, so that the plurality of horizontally extending pins on the two opposite side faces of the second packaged chip respectively contact the plurality of third conductive columns and the plurality of fourth conductive columns.

7. The test circuit board structure according to claim 1, characterized in that: The thickness of each of the plurality of horizontally extending pins on the two opposite sides of the first package chip is 0.15 mm, and the thickness of each of the first prepreg material and the second prepreg material is 0.2 mm.

8. The test circuit board structure according to claim 4, characterized in that: The two adjacent layers of substrate at the first end surface of the first hollow portion of the first sub-board are the first layer of substrate and the second layer of substrate of the first sub-board, and the two adjacent layers of substrate at the second end surface of the second hollow portion of the second sub-board are the first layer of substrate and the second layer of substrate of the second sub-board.

9. The test circuit board structure according to claim 1, characterized in that: After the first sub-board, the second sub-board and the first packaged chip are connected, the front and back surfaces of the first packaged chip are exposed to the first hollow portion of the first sub-board and the second hollow portion of the second sub-board.

10. A chip testing system, characterized in that: include: The test circuit board structure according to any one of claims 1 to 9; as well as At least one chip.

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