A portable micro signal generator based on FPGA

Abstract

The invention discloses a portable micro signal generator based on FPGA, belonging to the technical field of signal generators; it includes a hardware part and a program, the hardware part adopts an LMX2595 chip; the program adopts a lookup table to develop a frequency conversion function; the program adopts a ROM lookup table to store register configurations in the ROM; the registers that need to be modified during frequency conversion are extracted, and the configurations of the registers that affect the output frequency are stored in the ROM; the configurations of these registers are obtained through address access, and are sent to the chip in conjunction with the state machine control in the program; the program uses an IP core to store the configuration data in a file. In the present invention, the SPI protocol is combined with a lookup table to perform frequency conversion control, and the frequency conversion functions are all concentrated on the FPGA chip; when the external required frequency parameters are changed, there is no need to modify the program, or the host computer sends a large string of configuration instructions, and the host computer only needs to send instructions containing frequency information and enable instructions to perform frequency conversion.

Description

Technical Field

[0001] The invention relates to the technical field of signal generators, and in particular to a portable micro signal generator based on FPGA. Background Art

[0002] A signal generator (i.e., a signal source or oscillator) is a device that can provide electrical signals of various frequencies, waveforms, and output levels. It is widely used in production practice and the field of science and technology, and is often used for the maintenance and debugging of electronic equipment. As a maintenance and debugging device, the signal source needs to generate a variety of waveforms, such as sine waves, rectangular waves, triangle waves, and sawtooth waves; and it needs to be able to adjust the parameters of these waveforms, such as frequency, continuous signal or pulse signal, power, period, pulse width, etc. The stronger the corresponding function and the wider the output signal frequency range, the larger the size of the signal generator.

[0003] In production practice, some equipment needs to be equipped with one or more signal generators, but the signal generator is required to be small and easy to load, and the function does not need to be complicated, and it only needs to generate a signal that meets the indicators. In addition, if a driver chip is used to generate the frequency, a driver program needs to be written; in terms of program design, it is necessary to facilitate transplantation, save resources, and be simple to control. However, the signal range generated by the micro signal generator modules on the market is relatively narrow, which cannot meet more needs of actual use.

[0004] FPGA is a field programmable array, which is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. It is the main hardware platform for digital system design today. Its main feature is that it can be completely configured and programmed by the user through software to complete a certain function, and it can be repeatedly erased and written. When modifying and upgrading, there is no need to change the PCB circuit board additionally, but only to modify and update the program on the computer, making the hardware design work become software development work, shortening the system design cycle, improving the flexibility of implementation and reducing costs.

[0005] The existing small signal generators have a narrow output frequency range, and the signal generators with a large output range are relatively large in size. In addition, there are few drivers based on FPGA programming, and most frequency conversion methods open up a large number of register groups to store configurations or hand over configuration to the host computer. Summary of the invention

[0006] The purpose of the invention is to provide a portable micro signal generator based on FPGA.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: A portable micro signal generator based on FPGA includes a hardware part and a program. The hardware part adopts an LMX2595 chip; the program adopts a lookup table to develop a frequency conversion function.

[0008] Preferably, the program uses a ROM lookup table to store the register configuration in the ROM; the registers that need to be modified during frequency conversion are extracted, and the configuration of the registers that affect the output frequency is stored in the ROM; the configuration of these registers is obtained through address access, and is sent to the chip under the control of the state machine in the program; the program uses the IP core to store the configuration data file.

[0009] Preferably, the program uses a state machine, a ROM lookup table and an SPI protocol; and includes the following steps: after the power-on system reset is released, the written initialization configuration is sent to the LMX2595 chip; after the initialization is completed, wait for the host computer instruction; when the host computer sends the instruction, the parsed frequency code is sent to the address of the ROM lookup table, the enable is pulled high, and the data of the corresponding address is sent to the state machine; the state machine controls the corresponding configuration data to be sent and transmitted to the LMX2595 chip through the SPI protocol.

[0010] Preferably, the program adopts: SPI protocol combined with lookup table to perform frequency conversion control, and the frequency conversion function is concentrated on the FPGA chip; when the external required frequency parameters change, there is no need to modify the program, or the host computer sends a large string of configuration instructions, the host computer only needs to send instructions containing frequency information and enable instructions to perform frequency conversion.

[0011] Preferably, the output signal includes the following steps: the host computer sends instruction information containing frequency code, enable, AB port switch, and amplitude adjustment; the FPGA module parses the host computer instruction to complete the logic development; the parsed instruction is sent to the drive module; according to the information in the instruction, the ROM lookup table outputs the configuration data of the corresponding frequency point; the state machine sends these frequency configuration data, AB switch instruction data and amplitude adjustment instruction data to the shift register one by one; according to the SPI communication protocol, it is sent to the hardware module; the hardware module outputs the signal.

[0012] Preferably, the control flow of the state machine is as follows: a1. When the system reset is released, set the counter as the first initialization judgment condition; a2. Wait for the frequency conversion enable command or external initialization command; a3. Register configuration is issued; a4. Register configuration preparation; set the counter. When the previous register configuration is sent, the counter is +1 and the next register configuration is sent. a5. Based on the counter, determine which state the state machine should enter, including: entering delay? entering the delivery segment? configuration completed? a61. If the delay is entered, it is implemented according to the chip manual. Some chips need time calibration after the configuration is sent down; go to step a7; a62. If the configuration is finished, return to a1; a7. When the time is up, return to a3.

[0013] Preferably, the state machine further includes the following preamble steps: After the system is powered on, it is in reset state. After a period of time when the system is stable, the reset is released and the program starts working. In the driver program, a counter is built in. When the time is up, the state machine starts working and sends the preset initialization configuration. This is an internal initialization setting and is only performed once. When the initialization is completed, the program enters the IDLE stage and waits for new instructions.

[0014] Preferably, the instruction for modifying the frequency requires a bit width of 15 bits, the enabling instruction requires a bit width of 1 bit, the switching AB channel instruction requires a bit width of 2 bits, the AB channel output amplitude adjustment instruction requires a bit width of 12 bits, the chip initialization instruction requires a bit width of 1 bit, the instruction does not contain special fields such as frame headers and frame tails, and only uses a bit width of 31 bits, which is applicable to most host computers.

[0015] An application of a portable micro signal generator based on FPGA includes: 1) application as an antenna calibration source; 2) application as a passive direction finding system calibration source; 3) application as a frequency conversion module local oscillator source.

[0016] Compared with the prior art, the present invention provides a portable micro signal generator based on FPGA, which has the following beneficial effects.

[0017] 1. The present invention uses the SPI protocol combined with a lookup table to perform frequency conversion control, and concentrates the frequency conversion functions on the FPGA chip; when the external frequency parameters are changed, there is no need to modify the program or send a large string of configuration instructions from the host computer. The frequency conversion can be performed only by sending instructions containing frequency information and enable instructions from the host computer.

[0018] 2. The hardware design of the present invention is small in size and can be connected to most chassis or directly soldered into a PCB board. It has a wider output range than similar designs and can generate signals with a frequency of 10MHz-20GHz.

[0019] Other advantages, objectives and features of the present invention will be described in part in the following description; and in part, will be apparent to those skilled in the art based on an examination of the following; or, may be taught from the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Lookup table program for rom.

[0021] Figure 2 Instantiate the IP core in the program.

[0022] Figure 3 Configure the snippet for program frequency conversion.

[0023] Figure 4 Write a method for the driver.

[0024] Figure 5 Write the second method for the driver.

[0025] Figure 6 Select the storage type single-port ROM.

[0026] Figure 7 To set the lookup table data width and depth map.

[0027] Figure 8 Associate the configuration table with the IP core.

[0028] Fig. 9 For the program structure.

[0029] Fig.10 Configure for data.

[0030] Fig.11 is the step of output signal.

[0031] Fig.12 Control flow for the state machine.

[0032] Fig.13 For state machine and spi simulation.

[0033] Fig.14 For the shift register.

[0034] Fig.15 This is the simulation diagram of ROM IP core.

[0035] Fig.16 The meaning of register is 1.

[0036] Fig.17 This is the second meaning of the register.

[0037] Fig.18 The following are photos of the bare board and the packaged board, as well as the structural block diagram.

[0038] Fig.19 For output effect.

[0039] Fig. 20 Match frequency and configuration data for if statements.

[0040] Fig.21 It is the ROM lookup table mode.

[0041] Fig. 22 Resource usage.

[0042] Fig.23 This is a waveform diagram with a starting frequency of 10MHz and a stepping frequency of 1MHz.

[0043] Fig.24 This is a waveform diagram of 100MHz stepping by 10MHz.

[0044] Fig.25 This is the waveform diagram of amplitude adjustment (only register configuration is modified).

[0045] Fig.26 This is the waveform diagram near 20GHz (stop). DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0047] A portable micro signal generator based on FPGA includes a hardware part and a program. The hardware part includes: an LMX2595 chip; the program uses a lookup table to develop a frequency conversion function.

[0048] LMX2595 is a high-performance broadband synthesizer chip that can generate frequencies from 10MHz to 20GHz. Due to the register distribution problem of LMX2595 controlling the frequency multiplier and divider, the frequency limit of Fvco and the limit of the number of divider stages, it is very troublesome to calculate the output frequency through the algorithm, and the program design is relatively complicated; there is currently no suitable solution in the industry; therefore, the applicant specially designed the development of the frequency conversion function by means of a lookup table.

[0049] Look-Up Table is a combinational logic unit with storage and calculation functions in FPGA; it can output predefined results according to different combinations of input signals. The program uses ROM lookup table to store register configuration in ROM. A large amount of BRAM resources are required at this time; LMX2595 has 113 registers, of which 6 are read-only registers and the other 107 registers need to be programmed; after optimized design, this program only needs to complete the first initialization of 79 registers, and frequency conversion only needs to repeatedly configure 9 registers; the operation configuration time is shorter, which is conducive to frequency sweep operation (sweep interval 100ms). The registers that need to be modified during frequency conversion are extracted, and the configuration of the registers that affect the output frequency is stored in ROM; the configuration of these registers is obtained through address access, and sent to the chip under the control of the state machine in the program.

[0050] The ROM lookup table is written in pure Verilog; define a register with a width of 64 and a depth of 20000: reg [63:0] rom [19999:0]; According to the depth, start assigning values ​​from 0: rom[0]<= 64-bit data; rom[1]<= 64 bits of data; … rom

[19999] <= 64-bit data; The depth here is used as the address addra, and the preset data can be searched and output according to the address: assign data = ron[addra].

[0051] In addition, due to the handwritten ROM lookup table, the program will be longer; therefore, the program uses IP cores and stores the configuration data in .coe files (the file format of Xilinx is .coe, and that of Altera is .mif).

[0052] like Figure 1 As shown, this is the ROM lookup table program.

[0053] like Figure 2 As shown, the IP core is instantiated in the program.

[0054] like Figure 3 As shown in the figure, the program frequency conversion configuration fragment; each time an instruction is issued, the state machine will re-issue the content of the above figure, and then output the data to the SDI pin of the 2595 chip through the shift register; SCK can be freely configured and the cycle is specified; MUXout is connected to the LED light as a status flag, and the red light is on to indicate that the chip configuration is successful.

[0055] It should be noted that the driver writing methods include: Method 1: (such as Figure 4 As shown in the figure, the host computer sends the frequency code, and the corresponding frequency configuration is selected through the case or if statement; this operation is suitable for outputting only a few fixed frequencies, but for outputting a wide range of frequencies, the program will be very long, and it is estimated that there will be more than 60,000 lines of code in the LMX2595 driver program; Method 2: (such as Figure 5 As shown in the figure, the register configuration is issued by parsing the instructions of the host computer to drive the chip; this method controls the length of the program, but both the host computer and the FPGA need to set multiple addresses for communication and parsing data packets, which has poor portability and poor integration.

[0056] In this application, unlike the above method, a ROM lookup table is used to pre-store data, and the pre-stored data is sent down to drive the chip according to the frequency code sent by the host computer; it is better to use this method to write the driving code.

[0057] like Figures 6 to 9 As shown, IP core customization; selecting storage type single-port ROM; setting lookup table data width and depth; IP core associated configuration table; program structure.

[0058] The data format of the association table is as follows: 1 memory_initialization_radix-16; 2 memory_initialization_vector = 3 0B80019003040026, 4 0B80019003040026, 5 0B80019003040026, 6 0B80019003040026, 7 0B80019003040026, 8 0B80019003040026, 9 0B80019003040026, 10 0B80019003040026, 11 0B80019003040026, 12 0B80019003040026, 13; 10M 4B / 2B / 25 / 24 14 0C40019003040026, 15 0C4000F00304002A, 16 0C4000500304002E, 17 0c40039803040031, 18 0C4002F804040035, 19 0c00019003040026, 20 0c0003c003040028, 21 0c0002080304002B, 22 0c0000500304002E, 23 0C00028003040030, Line 1: memory initialization base, =16 means hexadecimal; Line 2: Memory initialization vector, followed by the pre-stored configuration data; Line 3: Pre-stored data, corresponding to the address 0X0000 outside the program.

[0059] The file format is .coe.

[0060] Interface definition: addra: Input address, which corresponds to frequency code. Decimal 10 is 10MHz, and decimal 20000 is 20GHz. clka: clock; douta: output, output the corresponding pre-stored data according to the address; ena: Enable, set to 1 for output.

[0061] When ena is enabled and pulled high, douta will output the value of the corresponding position of addra; the configuration value stored in the associated file, the address starts from 0 and is separated by commas. The value after the comma indicates the value of the next address.

[0062] The program mainly uses state machine, ROM lookup table and SPI protocol. The communication mode is SPI protocol, and the SPI clock cycle can be changed freely; in addition, the program also includes an instruction parsing module.

[0063] The program includes the following steps: after the power-on system reset is released, the written initialization configuration is sent to the LMX2595 chip; after the initialization is completed, wait for the host computer instruction; when the host computer sends the instruction, the parsed frequency code is sent to the address of the ROM lookup table, the enable is pulled high, and the data of the corresponding address is sent to the state machine; the state machine controls the corresponding configuration data to be sent and transmitted to the LMX2595 chip through the SPI protocol.

[0064] accomplish: 1. 10MHz~20GHz arbitrary frequency output (unit: 1MHz); 2. A and B channels can be switched arbitrarily; (the output range of channel A is 10MHz~20GHz, and the output range of channel B is 10MHz~15GHz; and when the output of channel A is greater than 15GHz, the output of channel B is 1 / 2 of channel A); 3. The output signal amplitude can be fine-tuned.

[0065] The SPI protocol is combined with a lookup table to perform frequency control, concentrating the frequency conversion function on the FPGA chip; when the external frequency parameters change, there is no need to modify the program or have the host computer send a long string of configuration instructions. The host computer only needs to send instructions containing frequency information and enable instructions to perform frequency conversion.

[0066] The instruction to modify the frequency requires a 15-bit width, the enable instruction requires a 1-bit width, the switch AB channel instruction requires a 2-bit width, the AB channel output amplitude adjustment instruction requires a 12-bit width, and the chip initialization instruction requires a 1-bit width. The instruction does not contain special fields such as the header and the footer, and only uses a 31-bit width, which is applicable to most host computers. The lookup table method can also be used in similar AD chip drivers.

[0067] like Fig.11 As shown; the output signal includes the following steps: the host computer sends the instruction information containing frequency code, enable, AB port switch, and amplitude adjustment; the FPGA module parses the host computer instruction and completes the logic development; the parsed instruction is sent to the driver module; according to the information in the instruction, the ROM lookup table outputs the configuration data of the corresponding frequency point; the state machine sends these frequency configuration data, AB switch instruction data and amplitude adjustment instruction data to the shift register one by one; according to the SPI communication protocol, it is sent to the hardware module; wherein, it is sent to the hardware module through the lvttl interface; the hardware module outputs the signal.

[0068] The control flow of the state machine is as follows: a1. When the system reset is released, set the counter as the first initialization judgment condition; a2. Wait for the frequency conversion enable command or external initialization command; a3. Register configuration is issued; a4. Register configuration preparation; set the counter. When the previous register configuration is sent, the counter is +1 and the next register configuration is sent. a5. According to the counter, determine which state the state machine should enter; Including: Entering delay? Entering the delivery segment? Configuration completed? a61. If the delay is entered, it is implemented according to the chip manual. Some chips need time calibration after the configuration is sent down; go to step a7; a62. If the configuration is finished, return to a1; a7. When the time is up, return to the a3 register to send the configuration.

[0069] State machine program flowchart and working logic, such as Fig.12 As shown; set the working status IDLE, CFG_RDY, CFG_RGT, CFG_WAIT, CFG_DLY, OVER.

[0070] Before the control flow of the state machine, the following steps are also included: After the system is powered on, it is in reset state. After a period of time when the system is stable, the reset is released and the program starts working. In the driver program, a counter is built in. When the time is up, the state machine starts working and sends the preset initialization configuration. This is an internal initialization setting and is only performed once. When the initialization is completed, the program enters the IDLE stage and waits for new instructions.

[0071] State machine and spi emulation, such as Fig.13 As shown. Status definition: IDLE = 9'h001; CFG_RDY = 9'h002; CFG_RGT = 9'h004; CFG_WAIT = 9'h008; CFG_DLY = 9'h010; OVER = 9'h020.

[0072] After recognizing the enable signal, the state machine starts to start and enters CFG_RGT from IDLE; this state will send the corresponding configuration of the current counter para_cnt count to the shift register; it can be seen that the para_data_en enable signal is pulled high; the shift register shift_data value becomes the value of the corresponding configuration data para_data; at this time, there will be another counter to calculate the time for parallel data to be converted into serial data; at the moment when para_data_en is pulled high, the state machine enters the next state CFG_WAIT, this state will determine the next configuration data to be sent and complete the transmission of the previous configuration; this operation is repeated to complete the sending of the chip configuration data; in addition, the logical output of the chip select CSB and the SPI clock SCK will be completed in the process; after the last configuration data is sent, the state machine enters the OVER state, and then returns to the IDLE state to wait for the next instruction.

[0073] The CFG_DLY state is a delay. When configuring some chips, after a certain register is configured, a certain delay is required before the chip can be started. The delay time is processed according to the chip manual requirements.

[0074] Shift registers, such as Fig.14 shown.

[0075] When para_data_en is pulled high, the configured data is sent to shift_data, and is shifted left or right according to the designed time interval, and the highest or lowest bit is sent to sdi, for example: data=4'b1110, data<<1=5'b11100 ("<<" left shift operator and ">>" right shift operator), here data is shifted left by one bit, and the empty bit is filled with 0, but in fact the data bit width is fixed, so data<<1=4'1100, at this time, the high bit of data is sent to another signal signal<=data[3] (the data bit in the program starts from zero, so the highest bit of 4-bit wide data is 3), thus realizing the conversion of multi-bit data to single-bit data (parallel data to serial data).

[0076] Finally, the single bit data is output to the SDI pin of the lmx2595 chip. SCK is configured with a suitable cycle according to the chip manual, and the chip select CSB is pulled low when the parallel data is converted to serial data. MUXout is connected to the LED light as a status flag. The red light is on for a long time, indicating that the chip configuration is successful.

[0077] ROM IP core simulation, such as Fig.15 As shown; it can be seen that when ena is enabled and pulled high, douta will output the value corresponding to the addra address.

[0078] like Fig.10 As shown, they are the data configurations for 4000MHz-4010MHz, 12000MHz-12010MHz, and 19990MHz-20000MHz respectively.

[0079] These register configurations are filled in according to the official software or chip manual. For example, the registers that need to be repeatedly configured for LMX2595 are 75, 43, 37, and 36, and their meanings are as follows Fig.16 As shown; the meaning of the register selected for configuration is determined according to the frequency range, such as Fig.17 shown.

[0080] For program applicability; to drive other chips, you need to re-fill the data in the table according to the data sheet or official simulation software. For example: ADF41513 chip is an ultra-short wave noise frequency synthesizer; here ADF41513 module is used as the local oscillator source, and 39 frequency points are required, so the original program uses if statements to match the frequency and configuration data. After changing to the ROM lookup table method, add the chip configuration data back into the data table file, and then send the configuration data according to the LMX2595 operation.

[0081] like Fig. 20 As shown, the if statement matches the frequency and configuration data; Fig.21 As shown, the ROM lookup table method. The program drives the chip in the same way as the 2595 program. The register configuration is written into the chip through the state machine and SPI protocol (the interface protocol is applied according to the chip data manual), the enable signal is pulled high, the configuration data of the corresponding frequency code is read out and sent to the state machine, and then sent to the chip through the SPI protocol.

[0082] The ROM lookup table actually acts as a read-only memory, storing preset data and reading it out according to user needs. This method is more convenient for writing drivers with complex functions and cumbersome operations, and the functions cannot be well implemented through logic and algorithms. It can store the configuration data of some address segments and the configuration of the entire chip. It is mainly used in the driver program developed for frequency synthesizer chips as multi-output local oscillator sources and large broadband signal sources. Of course, this method will have resource limitations and needs to be adjusted according to the BRAM resources of the FPGA chip.

[0083] like Fig.18 Shown are photos of the bare board and the packaged board, as well as the structural block diagram; Fig.19 For output effect.

[0084] The method based on the phase-locked loop (PLL) frequency source used in this application: driving the phase-locked loop integrated circuit chip; for the sake of high integration, the phase-locked loop integrated circuit chip is directly used, and there is no need to design the core components of the PLL such as the frequency discriminator, divider, phase-locked loop, voltage-controlled oscillator, lock detection circuit and reset circuit; it does not involve digital signal processing issues, and the driver program drives the chip to realize signal output and adjustment, which is used in the calibration source, local oscillator source and reference clock source, so the requirement for the output signal is to generate a signal with a large frequency range, stable output signal and amplitude within the index range.

[0085] The hardware implementation and driver function implementation results of the LMX2595 module achieve the expected main function of 10MHz~20GHz stepping 1MHz; the initial idea is whether there is a pattern in the output frequency and configuration data changes, and find this pattern or calculation formula to implement in the program. After configuring a large number of frequency export configuration tables on the simulation software for comparison, it is found that there will be a pattern in a certain range of frequencies-other configurations remain unchanged and only the register of the frequency division coefficient needs to be modified to change the output frequency. If the output frequency is not within this range, other registers need to be adjusted because the frequency division multiplier coefficient inside the chip has a maximum value. Once the maximum value is reached, other frequency division multipliers need to be replaced (this operation modifies the register configuration to achieve). In the frequency range of 10MHz~20GHz required to output, the rules of register configuration are very messy, and it is very troublesome to process by the calculation formula logic method, so the lookup table method is used to pre-store these configurations and then output them according to the frequency code. In subsequent use, it was found that this method is very convenient in the driver of frequency synthesis chips, and it is also more convenient in program transplantation, maintenance and function modification.

[0086] like Figure 22-26 As shown; Fig. 22 The chip 10MHz-20GHz resource usage; Figure 23-26 As shown, they are the waveforms of 10MHz (start) stepping 1MHz, 100MHz stepping 10MHz, amplitude adjustment (only modifying the register configuration), and near 20GHz (end).

[0087] The output frequency is 10MHz-20GHz, and the stepping frequency is 1MHz. The decimal 10 is 10MHz, and the decimal 20000 is 20GHz. The output frequency amplitude can be adjusted (the amplitude within 100MHz is low and the external gain is recommended). There is no external gain attenuation module. The amplitude adjustment is completely dependent on the program to modify the register configuration, and the output amplitude cannot reach the specified size. Two outputs RFOUTA and RFOUTB, RFOUTA can output 10MHz-20GHz, RFOUTB outputs 10MHz-15GHz, and the channel is controllable. If output at the same time, when the output range is 10MHz-15GHz (equal to 15GHz), A and B output the same, when the output range is 15GHz (greater than 15GHz)-20GHz, B=A / 2. The overall size of the module is small, suitable for many devices that require an external signal generator, and can also be directly soldered on the PCB board. The program takes up less resources, has stable timing, the host computer sends simple instructions, the program is portable and maintainable, and can be used to drive other similar chips. In addition, the design of the lookup table does not require the opening of multiple register groups to store chip configurations or to hand over the configurations to the host computer for distribution. When changing the frequency, there is no need to repeatedly send all configuration values, which reduces configuration time and greatly improves efficiency.

[0088] An application of a portable micro signal generator based on FPGA at least includes the following.

[0089] 1) Used as antenna calibration source; Usage: Solder on PCB board; Function: As a standard signal generator, it is required to generate stable and accurate signals with a frequency range of 10MHz~18GHz to calibrate the collected signals.

[0090] 2) It is used as a calibration source for passive direction finding systems; Usage: single module connection; Function: As a standard signal generator, it is required to generate stable and accurate signals with a frequency range of 1GHz~12GHz to calibrate the collected signals.

[0091] The calibration source is a controllable signal source whose direction, frequency and amplitude are known in the direction finding system. By receiving, processing and analyzing the signal from the calibration source, the direction finding system can calibrate the phase and gain of the antenna array according to the signal from the calibration source, thereby reducing the error of the direction finding system and ensuring the accuracy and reliability of the direction finding system.

[0092] ① Phase calibration: The signal from the calibration source can be used to measure the phase difference between the antennas in the antenna array. By measuring the arrival time difference of the calibration source signal on different antennas, the phase difference between the antennas can be calculated and phase calibration can be performed to eliminate the influence of the phase difference on the direction finding result.

[0093] ②Gain calibration: The signal from the calibration source can be used to measure the gain differences of each antenna in the antenna array. By measuring the received signal strength of the calibration source signal on different antennas, the gain difference of each antenna can be calculated and gain calibration can be performed to eliminate the influence of the gain difference on the direction finding result.

[0094] ③ System direction error calibration: The signal of the calibration source can be used to measure the system error of the direction finding system. By measuring the output of the calibration source signal in the direction finding system and comparing it with the known calibration source direction, the system error of the direction finding system can be calculated and the system error calibration can be performed to improve the accuracy and reliability of the direction finding system.

[0095] 3) It is used as the local oscillator source of the frequency conversion module; Usage: soldered on PCB board; Function: Generate stable and accurate RF signals and provide a stable frequency reference signal to the equipment to ensure the normal operation of the communication system. The required frequency range is 4GHz~20GHz.

[0096] The role of the local oscillator in the frequency conversion module is to provide a stable local oscillator signal for converting the input RF signal into an intermediate frequency signal; there is a fixed difference between the frequency of the local oscillator signal and the frequency of the input RF signal, which is called the intermediate frequency. This intermediate frequency signal can be more easily processed and analyzed.

[0097] ① Generate local oscillator signal: Generate a stable local oscillator signal.

[0098] ② Adjust the local oscillator frequency: According to needs, FPGA can achieve different frequency conversion effects by changing the signal frequency output by the local oscillator source.

[0099] ③ Mixing operation: Mix the input RF signal with the local oscillator signal to obtain an intermediate frequency signal.

[0100] The hardware design of the present invention is small in size and can be connected to most chassis or directly welded into a PCB board. The output range is wider than that of the same type of design and can generate signals with a frequency of 10 MHz to 20 GHz.

[0101] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A portable micro signal generator based on FPGA, including hardware parts and programs, characterized in that: The hardware part uses the LMX2595 chip; the program uses a lookup table to develop the frequency conversion function.

2. The portable micro signal generator based on FPGA according to claim 1, characterized in that: The program uses a ROM lookup table to store the register configuration in ROM; Extract the registers that need to be modified during frequency conversion, and store the configuration of the registers that affect the output frequency in ROM; The configuration of these registers is obtained through address access and sent to the chip under the control of the state machine in the program; The program uses the IP core and stores the configuration data in the file.

3. The portable micro signal generator based on FPGA according to claim 1, characterized in that: The program uses a state machine, a ROM lookup table, and the SPI protocol; it includes the following steps: After the power-on system reset is released, the written initialization configuration is sent to the LMX2595 chip; after the initialization is completed, wait for the host computer instruction; when the host computer sends the instruction, the parsed frequency code is sent to the address of the ROM lookup table, the enable is pulled high, and the data of the corresponding address is sent to the state machine; the state machine controls the corresponding configuration data to be sent and transmitted to the LMX2595 chip through the SPI protocol.

4. The portable micro signal generator based on FPGA according to claim 3, characterized in that: The program uses: SPI protocol combined with a lookup table to perform frequency control, concentrating the frequency conversion function on the FPGA chip; when the external frequency parameters change, there is no need to modify the program or have the host computer send a long string of configuration instructions. The host computer only needs to send instructions containing frequency information and enable instructions to perform frequency conversion.

5. The portable micro signal generator based on FPGA according to claim 3, characterized in that: The output signal includes the following steps: The host computer sends command information including frequency code, enable, AB port switch, and amplitude adjustment; The FPGA module parses the host computer instructions and completes the logic development; the parsed instructions are sent to the driver module; according to the information in the instructions, the ROM lookup table outputs the configuration data of the corresponding frequency point; the state machine sends these frequency configuration data, AB switch instruction data and amplitude adjustment instruction data to the shift register one by one; and according to the SPI communication protocol, they are sent to the hardware module; Hardware module output signal.

6. The portable micro signal generator based on FPGA according to claim 5, characterized in that: The control flow of the state machine is as follows: a1. When the system reset is released, set the counter as the first initialization judgment condition; a2. Wait for the frequency conversion enable command or external initialization command; a3. Register configuration is issued; a4. Register configuration preparation; Set the counter. When the previous register configuration is sent, the counter is increased by 1 and the next register configuration is sent. a5. Based on the counter, determine which state the state machine should enter, including: entering delay? entering the delivery segment? configuration completed? a61. If the delay is entered, it is implemented according to the chip manual. Some chips need time calibration after the configuration is sent down; go to step a7; a62. If the configuration is finished, return to a1; a7. When the time is up, return to a3.

7. The portable micro signal generator based on FPGA according to claim 6, characterized in that: The state machine also includes the following steps: After the system is powered on, it is in reset state. After a period of time when the system is stable, the reset is released and the program starts working. In the driver program, a counter is built in. When the time is up, the state machine starts working and sends the preset initialization configuration. This is an internal initialization setting and is only performed once. When the initialization is completed, the program enters the IDLE stage and waits for new instructions.

8. The portable micro signal generator based on FPGA according to claim 5, characterized in that: The instruction for modifying the frequency requires a 15-bit width, the enabling instruction requires a 1-bit width, the switching AB channel instruction requires a 2-bit width, the AB channel output amplitude adjustment instruction requires a 12-bit width, and the chip initialization instruction requires a 1-bit width. The instruction does not contain special fields such as the frame header and frame footer, and only uses a 31-bit width, which is applicable to most host computers.

9. The application of the portable micro signal generator based on FPGA according to claims 1-8, characterized in that: include: 1) Used as antenna calibration source; 2) It is used as a calibration source for passive direction finding systems; 3) It is used as the local oscillator source of the frequency conversion module.

Images