Data transmission method and device for SPI device, and SPI device

Abstract

The present application relates to the technical field of integrated circuit digital design, and discloses a data transmission method and device for SPI devices, and SPI devices, the method comprising: generating a synchronous transmission clock according to the baud rate configuration; generating a delayed synchronous clock according to the baud rate configuration; wherein the delayed synchronous clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock; selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock; and sampling the serial data output by the SPI slave device using the receiving synchronous clock to obtain the received data. The method significantly improves the synchronous transmission clock frequency of the SPI communication, solves the problem of unstable data acquisition caused by transmission delay during high-frequency communication, and thus improves the data transmission rate.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit digital design, for example, to a data transmission method and apparatus for SPI devices, and SPI devices. Background Art

[0002] At present, in the master-slave device communication of SPI (Serial Peripheral Interface) in MCU (Micro Controller Unit), the master device outputs the synchronous transmission clock and serial transmission data MOSI (Master Out Slave In) to the slave device. The slave device outputs the slave device serial transmission data MISO (Master In Slave Out) only after receiving the synchronous transmission clock of the master device. The master device uses the output synchronous transmission clock to sample the serial data MISO to complete the data receiving function of the master device.

[0003] In order to realize mutual communication between master and slave devices, the related technology discloses a communication method, including: the master device outputs serial output data MOSI and synchronous transmission clock to the slave device. At the same time, the synchronous transmission clock is also used to collect the serial data MISO output by the slave device to complete the data receiving function of the master device.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] There is a transmission delay on the master-slave communication path. When the master-slave device transmission clock frequency is high, the transmission delay causes the master device to be unable to stably collect the data sent by the slave device.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a data transmission method and apparatus for an SPI device, and an SPI device, so as to improve the data transmission rate of the SPI device.

[0009] In some embodiments, the data transmission method for SPI devices includes: generating a synchronous transmission clock according to the baud rate configuration; generating a delayed synchronous clock according to the baud rate configuration; wherein the delayed synchronous clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock; according to the frequency of the synchronous transmission clock, selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device; and using the receiving synchronous clock to sample the serial data output by the SPI slave device to obtain the received data.

[0010] Optionally, according to the frequency of the synchronous transmission clock, selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device includes: obtaining the frequency of the synchronous transmission clock; comparing the frequency of the synchronous transmission clock with a preset frequency threshold; and selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the comparison result.

[0011] Optionally, a synchronous transmission clock or a delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device according to the comparison result, including: when the frequency of the synchronous transmission clock is less than or equal to a preset frequency threshold, the synchronous transmission clock is used as the receiving synchronous clock of the SPI master device; when the frequency of the synchronous transmission clock is greater than the preset frequency threshold, the delayed synchronous clock is used as the receiving synchronous clock of the SPI master device.

[0012] Optionally, generating a synchronous transmission clock according to the baud rate configuration includes: parsing the baud rate configuration according to the system high-speed clock to output a transmission clock generation control indication; generating a synchronous transmission clock according to the transmission clock generation control indication.

[0013] Optionally, a delayed synchronous clock is generated according to the baud rate of the synchronous transmission clock, including: parsing the baud rate configuration according to the system high-speed clock to output a transmission clock generation control indication; controlling the transmission clock generation control indication to delay output according to the acquired delay time parameter; and generating a delayed synchronous clock according to the delayed output transmission clock generation control indication.

[0014] Optionally, the delay time parameter is obtained in the following manner: a multiple relationship between a threshold period of the baud rate configuration and a system high-speed clock period is obtained, and the delay time parameter is output.

[0015] Optionally, the serial data outputted from the SPI slave device is sampled using a receiving synchronous clock to obtain received data, and further includes: converting the sampled serial data into parallel data and outputting the parallel data as received data.

[0016] In some embodiments, the data transmission device for SPI devices includes: a general synchronous clock generation circuit, configured to generate a synchronous transmission clock according to a baud rate configuration; a delayed synchronous clock generation circuit, configured to generate a delayed synchronous clock according to the baud rate configuration; wherein the delayed synchronous clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock; a receiving synchronous clock selection circuit, configured to select the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock; and a data receiving circuit, configured to use the receiving synchronous clock to sample the serial data output by the SPI slave device to obtain received data.

[0017] In some embodiments, the data transmission apparatus for SPI devices includes: a processor and a memory storing program instructions, and the processor is configured to execute the above-mentioned data transmission method for SPI devices when running the program instructions.

[0018] In some embodiments, the SPI device includes: a SPI master device; a SPI slave device configured to communicate with the SPI master device; and the data transmission device for the SPI device as described above, installed in the SPI master device.

[0019] The data transmission method and apparatus for SPI devices and the SPI devices provided in the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, by accurately controlling the use of the synchronous transmission clock and the delayed synchronous clock, the optimization of high-speed communication between SPI master and slave devices under different baud rate configurations is achieved. First, according to the set baud rate configuration, the universal synchronous clock generation circuit generates the synchronous transmission clock for the master-slave device communication. Secondly, the delayed synchronous clock generation circuit generates a delayed synchronous clock with respect to the synchronous transmission clock delay configuration period. Then, the receiving synchronous clock selection circuit selects to use the synchronous transmission clock or the delayed synchronous clock as the synchronous clock for data reception according to the frequency of the synchronous transmission clock. Finally, the data receiving circuit samples the serial data output from the device according to the selected synchronous clock and converts it into parallel data output. The disclosed embodiment significantly improves the synchronous transmission clock frequency of the SPI communication, solves the problem of unstable data acquisition caused by transmission delay during high-frequency communication, thereby improving the data transmission rate and ensuring the stability and reliability of data transmission in high-frequency communication scenarios.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of an SPI device provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a data transmission method for an SPI device provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a schematic diagram of the SPI master device sampling MISO at a high frequency provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another data transmission method for an SPI device provided by an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of a data transmission device for an SPI device provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a schematic diagram of another data transmission device for SPI devices provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] Currently, in SPI master-slave device communication, the master device outputs the synchronous transmission clock and serial transmission data MOSI to the slave device. After receiving the synchronous transmission clock of the master device, the slave device outputs the slave device serial transmission data MISO. The master device uses the output synchronous transmission clock to sample the serial data MISO.

[0036] However, there is a transmission delay on the master-slave communication path, including PAD (Pad Delay, input / output pad delay), internal processing delay, etc. On the one hand, the synchronous transmission clock received by the slave device is delayed compared to the receiving synchronous clock MISO used to receive the serial data of the slave device inside the master device. On the other hand, there is also a certain delay from the slave device sending data MISO to the master device receiving end. Therefore, when the master device receives the sent data MISO of the slave device, the sampling clock and MISO are not synchronized in timing.

[0037] The SPI interface protocol timing requires that if the master device sends data on the rising edge of the synchronous transmission clock, it should sample the received data on the falling edge of the synchronous transmission clock. If the master device is to stably sample the transmitted data MISO of the slave device, it is necessary to ensure that the half-cycle time length of the synchronous transmission clock is greater than the transmission delay of the master-slave communication path. When the synchronous transmission clock frequency of SPI is increased, the half-cycle time length of the synchronous transmission clock will be less than the transmission delay of the master-slave communication path. Then, at the falling edge of the master device, the valid serial transmission data MISO of the slave device has not arrived, and the master device cannot correctly sample the transmission data MISO of the slave device.

[0038] Therefore, it is necessary to delay the synchronous transmission clock to achieve effective sampling of the master device. Figure 1 Schematic diagram of an SPI device provided by an embodiment of the present disclosure. Figure 1 As shown, the SPI device may include a SPI master device 100 and a SPI slave device 200 .

[0039] The SPI master device 100 generates a synchronous transmission clock and a delayed synchronous clock respectively, and can select a suitable receiving synchronous clock according to the frequency of the synchronous transmission clock. The receiving synchronous clock needs to adapt to high-frequency communication to ensure that the SPI master device 100 can perform effective sampling operations from the SPI slave device 200 and obtain MISO.

[0040] Combination Figure 2 As shown, the embodiment of the present disclosure provides a data transmission method for an SPI device, comprising:

[0041] S201, the SPI master device generates a synchronous transmission clock according to the baud rate configuration.

[0042] S202, the SPI master device generates a delayed synchronization clock according to the baud rate configuration; wherein the delayed synchronization clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock.

[0043] S203, the SPI master device selects the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock.

[0044] S204, the SPI master device samples the serial data output by the SPI slave device using the received synchronization clock to obtain received data.

[0045] By adopting the data transmission method for SPI devices provided by the embodiment of the present disclosure, the optimization of high-speed communication between SPI master and slave devices under different baud rate configurations is achieved by accurately controlling the use of synchronous transmission clocks and delayed synchronous clocks. Baud rate is a unit for measuring digital communication rate, which indicates the number of signal units (called bauds) transmitted per second. First, according to the set baud rate configuration, the universal synchronous clock generation circuit generates a synchronous transmission clock for master-slave device communication. Secondly, the delayed synchronous clock generation circuit generates a delayed synchronous clock with respect to the synchronous transmission clock delay configuration period. The system clock (usually a high-speed clock) is the basis for generating the synchronous transmission clock. The frequency of the system clock is usually much higher than the baud rate of SPI communication. In order to generate a synchronous transmission clock of the required baud rate from the system clock, it is necessary to calculate the frequency division value. The frequency division value is calculated by dividing the system clock frequency by the baud rate, and this value determines the target frequency to which the system clock needs to be divided. Using a clock generation circuit such as a frequency divider or a phase-locked loop in a digital circuit, a synchronous transmission clock can be generated from the system clock according to the calculated frequency division value. For the generation of the delayed synchronous clock, an additional delay needs to be introduced on the basis of the synchronous transmission clock. This delay is usually half the baud rate period, that is, half the system clock period. The delay can be achieved by introducing a delay unit, such as a buffer or a dedicated delay-locked loop, in the path of the synchronous transmission clock.

[0046] Then, the receiving synchronous clock selection circuit selects to use the synchronous transmission clock or the delayed synchronous clock as the synchronous clock for the SPI master device to receive data according to the frequency of the synchronous transmission clock. Finally, the data receiving circuit samples the serial data output from the device according to the selected synchronous clock and converts it into parallel data output. The disclosed embodiment significantly improves the synchronous transmission clock frequency of SPI communication, solves the problem of unstable data acquisition caused by transmission delay during high-frequency communication, thereby improving the data transmission rate and ensuring the stability and reliability of data transmission in high-frequency communication scenarios.

[0047] Optionally, according to the frequency of the synchronous transmission clock, selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device includes: obtaining the frequency of the synchronous transmission clock; comparing the frequency of the synchronous transmission clock with a preset frequency threshold; and selecting the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the comparison result.

[0048] The disclosed embodiment can adapt to communication requirements at different frequencies. First, the frequency of the current synchronous transmission clock is obtained. The frequency of the synchronous transmission clock is a key clock signal used for synchronous data transmission during the communication process. Then, the obtained frequency is compared with a preset frequency threshold. The threshold is determined according to the communication protocol and device performance when the SPI master device is designed to distinguish different operating frequency ranges. The current communication rate can be evaluated by the preset frequency threshold, so that it can be distinguished into low-speed communication and high-speed communication, and then different clocks are selected as the receiving synchronization clock of the SPI master device.

[0049] This significantly improves the adaptability and stability of SPI devices at different operating frequencies, especially in high-frequency communications, which can effectively reduce communication errors caused by delays and improve the reliability and efficiency of data transmission.

[0050] Optionally, a synchronous transmission clock or a delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device according to the comparison result, including: when the frequency of the synchronous transmission clock is less than or equal to a preset frequency threshold, the synchronous transmission clock is used as the receiving synchronous clock of the SPI master device; when the frequency of the synchronous transmission clock is greater than the preset frequency threshold, the delayed synchronous clock is used as the receiving synchronous clock of the SPI master device.

[0051] In the disclosed embodiment, if the frequency of the synchronous transmission clock is lower than the frequency threshold, it is judged that the current communication rate is low, and the transmission delay has little effect on data synchronization. The original synchronous transmission clock is selected as the receiving synchronous clock. At this frequency, the delay of data transmission will not affect the stability of communication. However, if the frequency of the synchronous transmission clock is higher than the frequency threshold, it is judged that the current communication rate is high, and the transmission delay may affect data synchronization. The delayed synchronous clock of the delay configuration period is selected as the receiving synchronous clock to compensate for the transmission delay caused by high-frequency communication, ensuring that the master device can sample the data sent by the slave device at the right time. This enables the SPI master device to support a wider range of communication rates and adapt to more application scenarios.

[0052] Specifically, the master device samples the MISO of the receiving end at the falling edge of the synchronous transmission clock. Only when the overall transmission delay is less than half the time length of the synchronous transmission clock can MISO be correctly received by the master device. When the frequency of the synchronous transmission clock is low, it is easy to meet the condition that the T2 delay is less than half the period of the synchronous transmission clock SCK.

[0053] Specifically, Figure 3 As shown in FIG. 1 , the SPI master device samples MISO at a high frequency. As long as the overall transmission delay satisfies the condition of being less than the entire period of the synchronous transmission clock, the master device can correctly receive the MISO serial data.

[0054] Optionally, generating a synchronous transmission clock according to the baud rate configuration includes: parsing the baud rate configuration according to the system high-speed clock to output a transmission clock generation control indication; generating a synchronous transmission clock according to the transmission clock generation control indication.

[0055] In the disclosed embodiment, first, the baud rate configuration is parsed using a high-speed clock to determine the rate requirement for data transmission. During the parsing process, the system calculates the required clock frequency based on the relationship between the baud rate configuration and the system high-speed clock, and then outputs a transmission clock generation control instruction. The control instruction is the key to generating a synchronous transmission clock, and contains the parameters and settings required to generate a synchronous transmission clock. Subsequently, based on the transmission clock generation control instruction, the system generates a synchronous transmission clock, thereby converting the control instruction into an actual clock signal to ensure that SPI communication can be performed at the set baud rate. The synchronous transmission clock is a synchronization signal in SPI communication, which controls the sending and receiving timing of data, and ensures that data is accurately and synchronously transmitted between the master device and the slave device.

[0056] By precisely controlling the frequency of the synchronous transmission clock, it is possible to ensure that the communication between the master and slave devices remains synchronized at different data transmission rates, thereby improving the reliability of data transmission. In addition, the system can dynamically adjust the clock frequency according to actual communication needs, optimizing system performance, reducing energy consumption, and improving communication efficiency.

[0057] Optionally, a delayed synchronous clock is generated according to the baud rate of the synchronous transmission clock, including: parsing the baud rate configuration according to the system high-speed clock to output a transmission clock generation control indication; controlling the transmission clock generation control indication to delay output according to the acquired delay time parameter; and generating a delayed synchronous clock according to the delayed output transmission clock generation control indication.

[0058] In the disclosed embodiment, first, according to the relationship between the baud rate configuration and the system high-speed clock, the required clock frequency is calculated, and the transmission clock generation control instruction is output. Then, according to the acquired delay time parameter, the transmission clock generation control instruction is controlled to delay the output to ensure that the generated delayed synchronization clock can compensate for the delay problem caused by high-speed transmission. Finally, according to the delayed output transmission clock generation control instruction, the system generates a delayed synchronization clock, converts the delayed control instruction into an actual clock signal, and generates a delayed synchronization clock with a configuration period delayed compared to the synchronous transmission clock to meet the needs of high-speed communication.

[0059] The method of generating a delayed synchronous clock based on the baud rate significantly improves the stability and reliability of SPI communication at high speeds. By accurately controlling the clock delay, the synchronization of data transmission can be maintained at high baud rates, reducing communication errors caused by delays, especially when there is a transmission delay on the master-slave device communication path, which can effectively ensure that the master device samples the data sent by the slave device at the correct time.

[0060] Optionally, the delay time parameter is obtained in the following manner: a multiple relationship between a threshold period of the baud rate configuration and a system high-speed clock period is obtained, and the delay time parameter is output.

[0061] In the disclosed embodiment, it is necessary to determine the threshold period of the baud rate configuration, which refers to the minimum time unit required by the SPI communication protocol at a specific baud rate to ensure the accuracy and synchronization of data transmission. Then, the system obtains the period of the high-speed clock and calculates the multiple relationship between the two periods, that is, the ratio of the threshold period of the baud rate configuration to the system high-speed clock period. Finally, according to this multiple relationship, the delay time parameter is output, which will be used to subsequently generate a delayed synchronization clock to compensate for the phase difference between the high-speed transmission clock and the SPI communication clock.

[0062] Specifically, the sampling clock used by the data receiving circuit of the master device is a delayed synchronous clock generated by delaying the synchronous transmission clock by half a baud rate configuration period.

[0063] In high-speed SPI communication, due to the delay in the signal transmission path, the master device may not be able to sample the data sent by the slave device at the best moment, resulting in data errors or loss. By accurately calculating and applying the delay time parameters, the system can generate a delayed synchronous clock that is delayed by half the baud rate cycle relative to the original synchronous transmission clock, thereby ensuring that at high baud rates, the master device can sample the data of the slave device at the right moment, improving the accuracy and reliability of data transmission.

[0064] Optionally, the serial data outputted from the SPI slave device is sampled using a receiving synchronous clock to obtain received data, and further includes: converting the sampled serial data into parallel data and outputting the parallel data as received data.

[0065] Combination Figure 4 As shown, the embodiment of the present disclosure provides another data transmission method for an SPI device, including:

[0066] S401, the SPI master device generates a synchronous transmission clock according to the baud rate configuration.

[0067] S402, the SPI master device generates a delayed synchronization clock according to the baud rate configuration; wherein the delayed synchronization clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock.

[0068] S403, the SPI master device selects the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock.

[0069] S404, the SPI master device samples the serial data output by the SPI slave device using the received synchronous clock, converts the sampled serial data into parallel data, and outputs the parallel data as received data.

[0070] In the disclosed embodiment, first, the serial data output from the slave device is accurately sampled using the receive synchronization clock, ensuring that the data is read at the correct time, thereby ensuring the accuracy and integrity of the data. The receive synchronization clock is selected based on the synchronous transmission clock or the delayed synchronization clock, and can adapt to different communication rates and delays. Then, the sampled serial data is converted into parallel data, and the converted parallel data is output as the receive data for further processing or storage by the master device.

[0071] Combination Figure 5As shown, an embodiment of the present disclosure provides a data transmission device 50 for an SPI device, including a universal synchronous clock generating circuit 501 , a delayed synchronous clock generating circuit 502 , a receiving synchronous clock selecting circuit 503 and a data receiving circuit 504 .

[0072] The general synchronous clock generating circuit 501 is configured to generate a synchronous transmission clock according to the baud rate configuration. The delayed synchronous clock generating circuit 502 is configured to generate a delayed synchronous clock according to the baud rate configuration; wherein the delayed synchronous clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock. The receiving synchronous clock selecting circuit 503 is configured to select the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock. The data receiving circuit 504 is configured to sample the serial data output by the SPI slave device using the receiving synchronous clock to obtain the received data.

[0073] According to the set baud rate configuration, the universal synchronous clock generation circuit 501 generates a synchronous transmission clock for the communication between the master and slave devices. Secondly, the delayed synchronous clock generation circuit 502 generates a delayed synchronous clock with respect to the synchronous transmission clock delay configuration period. Then, the receiving synchronous clock selection circuit 503 selects to use the synchronous transmission clock or the delayed synchronous clock as the synchronous clock for data reception according to the frequency of the synchronous transmission clock. Finally, the data receiving circuit 504 samples the serial data output from the device according to the selected synchronous clock and converts it into parallel data output. The disclosed embodiment significantly improves the synchronous transmission clock frequency of SPI communication, solves the problem of unstable data acquisition caused by transmission delay during high-frequency communication, thereby improving the data transmission rate and ensuring the stability and reliability of data transmission in high-frequency communication scenarios.

[0074] The embodiment of the present disclosure provides a data transmission device 60 for an SPI device, including a processor 600 and a memory 601. Optionally, the device 60 may also include a communication interface 602 and a bus 603. The processor 600, the communication interface 602, and the memory 601 may communicate with each other through the bus 603. The communication interface 602 may be used for information transmission. The processor 600 may call the logic instructions in the memory 601 to execute the data transmission method for the SPI device of the above embodiment.

[0075] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0076] The memory 601 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 600 executes the functional application and data processing by running the program instructions / modules stored in the memory 601, that is, the data transmission method for the SPI device in the above embodiment is implemented.

[0077] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0078] The embodiment of the present disclosure provides an SPI device, including: an SPI master device; an SPI slave device, configured to communicate with the SPI master device, and the above-mentioned data transmission device for the SPI device. The data transmission device for the SPI device is installed in the SPI master device. The installation relationship described here is not limited to the internal placement of the SPI master device, but also includes the installation connection with other components of the SPI device, including but not limited to physical connection, electrical connection or signal transmission connection. It can be understood by those skilled in the art that the data transmission for the SPI device can be adapted to a feasible SPI device body, thereby realizing other feasible embodiments.

[0079] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0080] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0081] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0082] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0083] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A data transmission method for an SPI device, characterized in that: include: Generate synchronous transmission clock according to baud rate configuration; Generate a delayed synchronization clock according to the baud rate configuration; wherein the delayed synchronization clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock; According to the frequency of the synchronous transmission clock, the synchronous transmission clock or the delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device; The serial data output by the SPI slave device is sampled using the received synchronization clock to obtain the received data.

2. The data transmission method according to claim 1, characterized in that: According to the frequency of the synchronous transmission clock, the synchronous transmission clock or the delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device, including: Get the frequency of the synchronous transmission clock; comparing the frequency of the synchronous transmission clock with a preset frequency threshold; The synchronous transmission clock or the delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device according to the comparison result.

3. The data transmission method according to claim 1, characterized in that: The synchronous transmission clock or the delayed synchronous clock is selected as the receiving synchronous clock of the SPI master device according to the comparison result, including: When the frequency of the synchronous transmission clock is less than or equal to a preset frequency threshold, the synchronous transmission clock is used as a receiving synchronous clock of the SPI master device; When the frequency of the synchronous transmission clock is greater than a preset frequency threshold, the delayed synchronous clock is used as the receiving synchronous clock of the SPI master device.

4. The data transmission method according to claim 1, characterized in that: Generates synchronous transmission clock according to baud rate configuration, including: According to the system high-speed clock, the baud rate configuration is parsed to output the transmission clock generation control instruction; Generate a synchronous transmission clock according to the transmission clock generation control instruction.

5. The data transmission method according to claim 1, characterized in that: Generate a delayed synchronous clock according to the baud rate of the synchronous transmission clock, including: According to the system high-speed clock, the baud rate configuration is parsed to output the transmission clock generation control instruction; According to the acquired delay time parameter, controlling the transmission clock to generate a control indication delay output; A delayed synchronous clock is generated according to a transmission clock generation control instruction of the delayed output.

6. The data transmission method according to claim 5, characterized in that: Obtain the delay time parameters as follows: Get the multiple relationship between the threshold period of the baud rate configuration and the system high-speed clock period, and output the delay time parameter.

7. The data transmission method according to any one of claims 1 to 6, characterized in that: The serial data output by the SPI slave device is sampled using the receiving synchronous clock to obtain the received data, and also includes: The sampled serial data is converted into parallel data and output as received data.

8. A data transmission device for SPI equipment, characterized in that: include: a universal synchronous clock generation circuit configured to generate a synchronous transmission clock according to a baud rate configuration; The delayed synchronization clock generating circuit is configured to generate a delayed synchronization clock according to the baud rate configuration; wherein the delayed synchronization clock is delayed by half a baud rate cycle relative to the synchronous transmission clock to ensure that the overall transmission delay is within the cycle time length of the synchronous transmission clock; A receiving synchronous clock selection circuit is configured to select the synchronous transmission clock or the delayed synchronous clock as the receiving synchronous clock of the SPI master device according to the frequency of the synchronous transmission clock; The data receiving circuit is configured to sample the serial data outputted from the SPI slave device using the receiving synchronous clock to obtain the received data.

9. A data transmission device for an SPI device, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the data transmission method for an SPI device according to any one of claims 1 to 7 when running the program instructions.

10. An SPI device, characterized in that: include: SPI master device; SPI slave device, configured to communicate with the SPI master device; The data transmission device for an SPI device as claimed in claim 8 or 9, is installed in the SPI master device.

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