A CPU Synchronization System and Method Based on Dual-CPLD Bidirectional Control

Abstract

The present invention provides a CPU synchronization system and method based on dual-CPLD bidirectional control, which relates to the technical field of chip verification. The CPU includes multiple Dies; it includes a master CPLD and a slave CPLD; the pins of each Die are classified according to functional signals and connected to the CPLD with the closest physical distance; the master CPLD and the slave CPLD are connected through 4 bidirectional signal lines and 1 direction control signal line; the direction control signal line is used to control the data direction of the 4 bidirectional signal lines; the 4 bidirectional signal lines are used for data transmission between the dual CPLDs according to the data direction determined by the direction control signal line, and the 4 bidirectional signal lines can be switched to input or output at any time to complete the timing synchronization of the CPU; the present invention solves the resource limitation and signal transmission problems brought by the pins being concentrated on a single CPLD, and ensures that each Die can maintain consistency and reliability during startup, initialization and operation.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronic design automation (EDA) and chip verification. Specifically, it relates to a CPU synchronization system and method based on bidirectional control of dual CPLDs. Background Art

[0002] In the design of traditional verification platforms, a single CPLD is usually used to manage all the pins of the CPU. This solution is suitable for CPU designs with fewer pins and simpler functions.

[0003] Limitations of the single CPLD solution;

[0004] Insufficient resources: The single CPLD is limited in terms of logic units and the number of pins, making it difficult to meet the comprehensive verification requirements of the pins of multi-Die CPUs, resulting in many functions not being covered.

[0005] Inflexible PCB routing and difficult routing of stray signals: The single CPLD solution requires a large number of CPU pins to be connected in a limited space, which poses extremely high requirements for PCB routing. Due to the small area and dense routing of the CPLD, it is difficult to achieve flexible routing. Especially for multi-Die CPUs, the pins of each Die may be distributed in different regions of the chip. When the single CPLD centrally connects these pins, the difficulty of PCB routing increases significantly.

[0006] Difficult debugging and maintenance: The presence of stray signals increases the complexity of system debugging. After the PCB design is completed, it is difficult to adjust the signals, and the system maintenance cost rises.

[0007] For a high-complexity CPU verification platform, it is necessary to ensure that each IO and function can be comprehensively verified under limited resource conditions. If the CPU is composed of 4 Dies packaged together, the number of pins that need to be verified for functions through the CPLD is as high as more than 700. The function verification platform mainly verifies whether all the interface functions of the CPU are correct. For each Die, except for special interfaces such as DDR, PCIe, and high-speed interconnections, common low-speed communication interfaces, such as UART, SPI, JTAG, I2C, LPC, general GPIO, GPIO for special functions such as function configuration and function status, all need to perform signal switching, function testing, or monitoring inside the CPLD. Due to the Ballmap distribution of the CPU, two CPLDs have to be distributed on both sides of the CPU. With limited PCB signal layers, it is very difficult to distribute the pins of the same function of the CPU (4 Dies) on one CPLD for routing. Therefore, the pin allocation problem between the two CPLDs and the CPU will inevitably occur.

[0008] 4 The CPU starts up and initializes. There is a certain timing relationship in the interconnection between internal Dies, and the external enable is controlled by the Die initialization completion signal. Therefore, necessary communication signals must be retained between the two CPLDs to synchronize and ensure the timing control similar to the above.

[0009] With the wide application of multi-Die CPUs in the field of high-performance computing, the number of CPU pins and the types of functions show a sharp increasing trend. In a multi-Die packaged CPU, the startup, interconnection, and initialization of multiple Dies usually have strict timing requirements. At the same time, due to the large number of pins (such as more than 8000), the verification platform often requires multiple CPLDs to process these IO signals. However, the number of PCB signal layers and routing resources are limited. How to reasonably allocate pins and ensure the timing coordination and signal synchronization between multiple CPLDs has become an urgent problem to be solved.

[0010] Current limitations of the dual-CPLD communication scheme;

[0011] Limited bandwidth and speed of I2C communication: I2C is a low-speed serial communication protocol, suitable for low-speed data transmission, but it is insufficient in the timing control and high-speed signal synchronization of multi-Die CPUs. The I2C communication bandwidth is relatively low and cannot meet the timing synchronization requirements of the CPU during startup, initialization, and interconnection, making it difficult to achieve precise signal coordination.

[0012] Directional limitation of SPI communication: SPI is a high-speed communication protocol that supports full-duplex communication, but it is mainly used for data transmission between master and slave devices and does not support multiple master devices sharing the communication bus. The communication between dual CPLDs requires flexible bidirectional data transmission and timing control, while the fixed directionality of traditional SPI limits the free communication between dual CPLDs and is difficult to adapt to the complex signal interaction between CPU multi-Dies.

[0013] Large consumption of signal line resources for parallel buses: Parallel buses can provide relatively high data transmission speeds and wide communication bandwidths, but they require more signal lines. In PCB design, resources are limited, and the signal lines between dual CPLDs are usually also restricted, making it difficult to implement a relatively wide parallel bus. Especially in the case of limited pin numbers, the signal line requirements of parallel buses exceed the actual available resources, resulting in an increase in design complexity.

[0014] Complexity of synchronization control: The startup, initialization, and interconnection of multi-Die CPUs have strict timing control requirements, while the existing communication methods such as I2C and SPI have limited support for timing control. Existing communication schemes usually do not have dedicated direction control signals, which makes it difficult to achieve the strict timing requirements of the CPU for signal synchronization and direction switching, and the timing coordination of dual CPLDs becomes a major difficulty.

[0015] Therefore, the following technical problems exist in the current prior art:

[0016] 1. The traditional single CPLD architecture is difficult to cover a multi-Die CPU with nearly 800 pins. The resources of a single CPLD are limited, and it is unable to manage all pins and difficult to meet the requirements of complex IO function verification;

[0017] 2. The multi-Die CPU has very strict timing requirements for signals during startup, initialization, and interconnection. There are only 5 GPIOs for communication between two CPLDs, which is difficult to meet the timing control of multiple Dies inside the CPU;

[0018] 3. The multi-Die CPU and various system peripherals require various power supply signals for support (such as core power supply, IO power supply, etc.), and these signals need to be uniformly controlled during startup and operation. Summary of the Invention

[0019] In view of the above technical problems in the related art, the present invention proposes a CPU synchronization system and method based on dual-CPLD bidirectional control.

[0020] To achieve the above invention objectives, the present invention adopts the following technical solutions:

[0021] In a first aspect, the present invention provides a CPU synchronization system based on dual-CPLD bidirectional control, including power management signals; the CPU includes multiple Dies; the dual CPLDs include a master CPLD and a slave CPLD; the software working processes and state machine designs of the master CPLD and the slave CPLD are the same; the pins of each Die are classified according to functional signals and connected to the CPLD with the closest physical distance; the power management signals are generated by the CPU and the power supply module; the power supply module is connected to the slave CPLD, and the slave CPLD controls the startup and shutdown of the power management signals;

[0022] The power management signals include EN and PWROK; where EN is used for the slave CPLD to control the startup and shutdown of the power management signals, and is sent from the slave CPLD to the system peripherals. When EN = 1, it indicates starting the system peripherals, and when EN = 0, it indicates shutting down the system peripherals;

[0023] PWROK is used to feedback whether the peripherals are started or shut down, and is sent from the system peripherals to the slave CPLD. When PWROK = 1, it indicates that the system peripherals are started, and when PWROK = 0, it indicates that the system peripherals are shut down.

[0024] The master CPLD and the slave CPLD are connected through 4 bidirectional signal lines and 1 direction control signal line; the 4 bidirectional signal lines correspond to the bidirectional signals M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; among them, M2S[3:0] corresponds to the pins N1, N2, N3, N4 of the CPLD; M2S_CTRL corresponds to the pin R1 of the CPLD.

[0025] The direction control signal line is used to control the data direction of the 4 bidirectional signal lines; the 4 bidirectional signal lines are used for data transmission between the dual CPLDs according to the data direction determined by the direction control signal line, and the 4 bidirectional signal lines can be switched to input or output at any time to complete the timing synchronization of the CPU.

[0026] Specifically, the way that the direction control signal line controls the data direction of the 4 bidirectional signal lines is as follows:

[0027] When M2S_CTRL is at a high level, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the master CPLD is the receiver.

[0028] Specifically, after the data direction is determined, the sending CPLD loads the data onto the 4 bidirectional signal lines, and the receiving CPLD reads the data. During data transmission, the sending side keeps the signal line in the output mode, and the receiving side switches to the input mode.

[0029] Specifically, the direction control signal M2S_CTRL is controlled by the master CPLD.

[0030] Specifically, the function signals include UART, I2C, SPI, JTAG, SPI, GPIO, and FUNC.

[0031] Specifically, the data transmission between the dual CPLDs includes the key signals flash_done, good, and en:

[0032] The flash_done signal: It is used to indicate the signal that the Die has completed reading the flash information during the Die initialization stage, and is output from the Die to the CPLD; when flash_done is equal to 0, it means that the Flash of the Die has not been read completely; when flash_done is equal to 1, it means that the Flash of the Die has been read completely;

[0033] During the Die2Die stage of Die, flash_done is also used as a flag indicating whether the Die2Die training is completed, and it also needs to cooperate with the good signal of Die. Only when flash_done is 1 and good is 1 does it indicate that the Die2Die training of the corresponding Die is completed. When flash_done is 0, it indicates that the Die2Die training is not completed.

[0034] good: It is used to jointly indicate with the flash_done signal whether the Die2Die training of Die is completed, and is output from Die to CPLD. When good is equal to 0, it indicates that the Die2Die training of Die is not completed. When flash_done is equal to 1 and good is equal to 1, it indicates that the Die2Die training of Die is completed.

[0035] en: It is used to indicate the start and shutdown of Die2Die training enable, and is output from CPLD to Die. When en is equal to 0, it indicates that the Die2Die training enable is shut down. When en is equal to 1, it indicates that the Die2Die training enable starts.

[0036] Specifically, the CPU includes Die0, Die1, Die2, and Die3. Die0 and Die1 are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD. The direction control signal M2S_CTRL controls the data transfer direction in 4 bidirectional data lines. M2S[3:0] represents the flash_done and good of two Dies of the master CPLD or slave CPLD according to whether M2S_CTRL is equal to 1 or 0.

[0037] Specifically, when M2S_CTR of the slave CPLD is equal to 0, the 4 bidirectional signal lines are used as outputs, that is, M2S[3:0] represents Die0_flash_done, Die0_good, Die1_flash_done, and Die1_good of the slave CPLD in sequence. The master CPLD obtains the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0].

[0038] When M2S_CTRL of the slave CPLD is equal to 1, the 4 bidirectional signal lines are used as inputs, that is, M2S[3:0] represents Die2_flash_done, Die2_good, Die3_flash_done, and Die3_good of the master CPLD in sequence. The slave CPLD obtains the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

[0039] The present invention reasonably distributes the high number of pins of a multi-Die CPU on two CPLDs through a dual-CPLD architecture, avoiding the resource limitations and signal transmission problems caused by pin concentration on a single CPLD; divides signals according to pin functions and physical regions, optimizes PCB routing, and improves the integrity of signal transmission. The dual-CPLD structure reduces the pin density on the PCB, ensuring more abundant PCB routing space, especially in high-speed signal routing and power routing, avoiding problems such as excessive stray signals and crosstalk.

[0040] The dual-CPLD distributed architecture not only physically adapts better to the pin distribution of the CPU, but also through partition management, enables each CPLD to independently complete the function verification of the pins in its jurisdiction, ensuring full pin coverage, optimizing PCB routing, reducing routing interference, and improving the effective utilization of CPLD resources;

[0041] In addition, the two CPLDs are located on both sides of the CPU respectively, using PCB layers in different regions, reducing the stray interference of cross-region signal lines, and improving the flexibility and signal quality of PCB design.

[0042] Furthermore, the present invention manages multiple power signals in one CPLD, avoiding the timing control and signal coordination problems caused by the dispersion of power signals between the two CPLDs. Through centralized control, it ensures that the core power supply, IO power supply, etc. of each Die of the CPU can maintain consistency and reliability during startup, initialization, and operation, avoiding the power coordination requirements between the two CPLDs.

[0043] In a second aspect, the present invention provides a CPU synchronization method based on dual-CPLD bidirectional control. Based on the CPU synchronization system based on dual-CPLD bidirectional control described in any one of the first aspects, it includes the following steps:

[0044] S1. After the main board is powered on, both the main CPLD and the slave CPLD are in the Idle state, M2S_CTRL is set to 1, the main CPLD resets Die3, enters the Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1;

[0045] S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2, enters the Die2_flash_read state, M2S_CTRL is set to 1, Die2 starts to read the flash, and after the reading is completed, the CPU sets Die2_flash_done to 1;

[0046] S3. When the main CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and sets M2S_CTRL to 0. In steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. When both of them are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state;

[0047] S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 and enters the Die0_flash_read state. Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1;

[0048] S5. In steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. When both of them are equal to 1, it enters the Die2die_ready1 state;

[0049] S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset period, and the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, and enters the Die2die_ready2 state;

[0050] S7. When in the Die2die_ready2 state, the CPU first sets the flash_done of the 4 Dies to 0. When the main and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, start the Die2Die training for the first time;

[0051] S8. When the main and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good, and Die0_good are all 1, the Die2Die training ends and enters the Die2die_finish state.

[0052] Specifically, when the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0 in step S7, the first enabling of Die2Die training specifically includes:

[0053] S71. When the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, start Die2Die training, enter the Die2die_ctl_en_wait state, set M2S_CTRL to 1, wait for a preset cycle time, and the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively;

[0054] S72. After a preset cycle time, enter the Die2die_ctl_en state, set M2S_CTRL to 0, and the master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all Dies between the master and slave CPLDs is completed. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, disable Die2Die training and enter the Die2Die_pre1 state.

[0055] Specifically, step S8 specifically includes:

[0056] S81. When in the Die2Die_pre1 state, set M2S_CTRL to 1, and the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively. Wait for a preset cycle time, enter the Die2Die_pre2 state, and set M2S_CTRL to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively;

[0057] S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, the Die2Die training enable is turned on for the second time, and the Die2die_start1 state is entered. M2S_CTRL is set to 1. The slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and enters the Die2Die_start2 state. M2S_CTRL is set to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively;

[0058] S83. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, the Die2Die training enable is turned off for the second time, and the Die2die_done1 state is entered;

[0059] S84. When in the Die2die_done1 state, M2S_CTRL is set to 1. The slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, and synchronously obtains the values of Die2_good and Die3_good through the data lines M2S[2] and M2S[0] respectively. After waiting for one cycle, it enters the Die2die_done2 state;

[0060] S85. When in the Die2die_done2 state, M2S_CTRL is set to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively, and synchronously obtains the values of Die0_good and Die0_good through the data lines M2S[2] and M2S[0] respectively. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good, and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, the Die2die_finish state is entered, and the Die2die training ends. Otherwise, it waits continuously, indicating that the training is not completed.

[0061] In the dual-CPLD architecture of the present invention, efficient signal synchronization between CPLDs is achieved through 4 bidirectional signal lines and 1 direction control signal. The 4-wire bidirectional communication allows the two CPLDs to flexibly switch the signal direction, ensuring that each CPLD can read or send the signals of the other party when needed; the direction control signal is used for timing control to meet the strict timing requirements during the startup and initialization of the multi-Die CPU. This method ensures precise timing control and signal synchronization between the two CPLDs with limited signal resources;

[0062] Furthermore, during the startup and initialization of the multi-Die CPU, the switching of the direction signal is controlled by a state machine to precisely manage the signal timing synchronization between the CPLDs. This timing synchronization control strategy ensures signal consistency between the multi-Dies and avoids signal delay and loss problems in the dual-CPLD communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0064] Figure 1 is a schematic diagram of a CPU synchronization system based on dual-CPLD bidirectional control provided by an embodiment of the present invention;

[0065] Figure 2 is a schematic diagram of the connection between DIE, CPLD and Flash provided by an embodiment of the present invention;

[0066] Figure 3 is a schematic diagram of the hardware circuit and key signals of the master-slave CPLD based on the bidirectional control part provided by an embodiment of the present invention;

[0067] Figure 4 is a schematic diagram of a CPU synchronization method based on dual-CPLD bidirectional control provided by an embodiment of the present invention;

[0068] Figure 5 is a schematic diagram of a state machine based on dual-CPLD bidirectional control provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present invention.

[0070] In the description of the present invention, if the first, second, etc. are described only for the purpose of distinguishing technical features, they should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0071] In the description of the present invention, it should be noted that unless otherwise clearly defined, words such as setting, installation, and connection should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0072] Embodiment 1

[0073] Reference Figure 1 , this embodiment provides a CPU synchronization system based on dual-CPLD bidirectional control, including a power management signal; the CPU includes multiple Dies; the dual-CPLD includes a master CPLD and a slave CPLD; the pins of each Die are classified according to functional signals and connected to the CPLD with the closest physical distance; the power management signal is generated by the CPU and a power module; the power module is connected to the slave CPLD;

[0074] The power management signal includes EN and PWROK;

[0075] Among them, EN is used for the slave CPLD to control the start and stop of the power management signal, and is sent from the slave CPLD to the power module. When EN = 1, it means starting the power module, and when EN = 0, it means shutting down the power module;

[0076] PWROK is used to feedback whether the power module is normal after startup, and is sent from the power module to the slave CPLD. When PWROK = 1, it means the power module is working normally, and when PWROK = 0, it means the power module is not working properly.

[0077] Based on the background of the dual-CPLD design requirements, this embodiment centralizes all the power management signals of the CPU and the power module (all core power supplies and IO power supplies) in the slave CPLD for management to ensure the controllability of the timing of the power signals.

[0078] The functional signals include UART, I2C, SPI, JTAG, SPI, GPIO, and FUNC;

[0079] The dual-CPLD architecture design of this application distributes more than 700 pins to be verified on the multi-Die CPU to two CPLDs for management. According to the physical distribution and functional requirements of the CPU pins, the pins in different Die areas are reasonably allocated to the two CPLDs; through distributed management, the same type of functional signals (such as UART, I2C, SPI, JTAG, etc.) of each Die are concentrated on the same CPLD for verification as much as possible.

[0080] In this embodiment, the CPU includes Die0, Die1, Die2, and Die3.

[0081] This embodiment provides a connection method between a CPU with 4 Dies and dual CPLDs;

[0082] For example, if Die0 and Die1 of the CPU are close to the slave CPLD, then all UART (usually multiple paths) interfaces of Die0 and Die1 are connected to the slave CPLD. Similarly, all I2C interfaces are connected to the slave CPLD. On the contrary, all UART, I2C and other interfaces of Die2 and Die3 are connected to the master CPLD.

[0083] This design facilitates each CPLD to be physically close to the pin area it manages, reduces cross-area wiring, and improves the integrity of signal transmission. Distributed IO management effectively improves the utilization rate of CPLD resources, avoids resource bottlenecks in the number of pins and function management of a single CPLD, and ensures that the verification requirements of each pin are met.

[0084] The system further includes a Flash, in which BIOS information is stored, and the Die can read the BIOS information from the Flash.

[0085] Reference Figure 2 , the Flash is external. During Die initialization, it is independent. Because the configuration files are the same, therefore, on the circuit, a single Flash can be shared through a MUX (multiplexer) and read in different time periods. The CPLD is used to determine whether the Flash is completed and switch the channel for reading the Flash;

[0086] In this embodiment, the multiplexer is a 4-to-1 multiplexer; x0 of the multiplexer corresponds to the Die0 flash channel, x1 corresponds to the Die1 flash channel, x2 corresponds to the Die2 flash channel, x3 corresponds to the Die3 flash channel, x corresponds to the common flash channel, and the switch of the selector channel is controlled by SEL1 and SEL0.

[0087] The channel control relationship is as follows: when SEL[1:0] = 11, the switch channel between X3 and X is opened, that is, the hardware path is the channel for Die3 to read Flash; when SEL[1:0] = 10, the switch channel between X2 and X is opened, that is, the hardware path is the channel for Die2 to read Flash; when SEL[1:0] = 01, the switch channel between X1 and X is opened, that is, the hardware path is the channel for Die1 to read Flash; when SEL[1:0] = 00, the switch channel between X0 and X is opened, that is, the hardware path is the channel for Die0 to read Flash.

[0088] In this embodiment, the Flash configurations of the 4 Dies are the same. Circuit-wise, a single Flash is shared through a MUX, and there is a priority reading in terms of timing. After power-on, it defaults to entering the state where Die3 reads Flash first. The main CPLD sets SEL[1:0] = 11, then Die2 reads Flash, the main CPLD sets SEL[1:0] = 10, then Die1 reads Flash, the main CPLD sets SEL[1:0] = 01, and finally Die0 reads Flash, and the main CPLD sets SEL[1:0] = 00, thus completing the Flash reading of the 4 Dies in sequence.

[0089] In another possible implementation, each Die can also correspond to a Flash.

[0090] Reference Figure 3 As shown, the main CPLD and the slave CPLD are connected through 4 bidirectional signal lines and 1 direction control signal line; the 4 bidirectional signal lines correspond to the bidirectional signals M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; among them, M2S[3:0] corresponds to the pins N1, N2, N3, N4 of the CPLD; M2S_CTRL corresponds to the pin R1 of the CPLD.

[0091] The direction control signal line is used to control the direction of the 4 bidirectional signal lines.

[0092] Specifically, when M2S_CTRL is at a high level, the main CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the main CPLD is the receiver.

[0093] Specifically, when M2S_CTRL is at a high level, it can be 1; when M2S_CTRL is at a low level, it can be 0.

[0094] The M2S_CTRL signal is controlled by the main CPLD. The slave CPLD only serves as an output when M2S_CTRL = 0.

[0095] When the R1 pin of the main CPLD is at a high level, M2S_CTRL is at a high level; that is, when the R1 pin of the main CPLD is at a low level, M2S_CTRL is at a low level; the main CPLD controls the level of its R1 pin, thereby controlling the high and low levels of M2S_CTRL;

[0096] The 4 bidirectional signal lines are used to determine the data direction according to the value of M2S_CTRL for data transmission between the two CPLDs, and the 4 bidirectional signal lines can be switched to input or output at any time;

[0097] Specifically, after the direction control signal determines the data direction, the CPLD of the sender loads the data onto the 4 bidirectional signal lines, and the CPLD of the receiver reads the data. During data transmission, the sender keeps the signal lines in the output mode, and the receiver switches to the input mode.

[0098] Specifically, the communication operation process:

[0099] 1) Direction switching: According to the timing requirements, the M2S_CTRL signal is controlled by the state machine of the main CPLD. The slave CPLD acts as an output only when M2S_CTRL = 0.

[0100] For example, when a certain Die of the CPU completes startup and needs to notify the other CPLD, the state machine of the main CPLD switches the M2S_CTRL signal to the corresponding direction to ensure correct signal transmission.

[0101] 2) Data transmission: After the direction control signal determines the data direction, the CPLD of the sender loads the data onto the 4 bidirectional signal lines, and the CPLD of the receiver reads the data. During data transmission, the sender keeps the signal lines in the output mode, and the receiver switches to the input mode.

[0102] In the existing solution, the master and slave CPLDs complete the startup and interconnection communication between Die and Die, and normally 8 direct-through signals are required; in this embodiment, a communication mechanism of 4 bidirectional signal lines (corresponding to the signals M2S[3:0]) and 1 direction control signal line (corresponding to the signal M2S_CTRL) is designed. Through these 5 signal lines, the two CPLDs can flexibly perform bidirectional data transmission as needed to meet the timing synchronization requirements during the startup, initialization, and interconnection of the multi-Die CPU.

[0103] Direction control signal (M2S_CTRL): This signal is used to control the direction of the 4 bidirectional signal lines, and M2S_CTRL is controlled by the main CPLD. Specifically, when M2S_CTRL is at a high level, the main CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the main CPLD is the receiver.

[0104] In this embodiment, the key signals between the Die and the CPLD include flash_done, good, and en; among them:

[0105] The flash_done signal: It is used to indicate the signal that the Die has completed reading the flash information during the Die initialization stage and is output from the Die to the CPLD; when flash_done is equal to 0, it means that the Flash of the Die has not been read completely; when flash_done is equal to 1, it means that the Flash of the Die has been read completely;

[0106] During the Die2Die stage of the Die, flash_done is also used as a flag to indicate whether the Die2Die training is completed and needs to cooperate with the good signal of the Die; only when flash_done is 1 and good is 1 does it mean that the Die2Die training of the corresponding Die is completed; when flash_done is 0, it means that the Die2Die training is not completed;

[0107] good: It is used to jointly indicate with the flash_done signal whether the Die2Die training of the Die is completed and is output from the Die to the CPLD; when good is equal to 0, it means that the Die2Die training of the Die is not completed; when flash_done is equal to 1 and good is equal to 1, it means that the Die2Die training of the Die has been completed;

[0108] The values of flash_done and good are assigned by the Die according to its own situation, and the CPLD only reads them;

[0109] en: It is used to indicate the start and close of the Die2Die training enable, and is output from the CPLD to the Die; when en is equal to 0, it means that the Die2Die training enable is closed; when en is equal to 1, it means that the Die2Die training enable starts;

[0110] In addition, other key signals can be expanded between the Die and the CPLD according to requirements;

[0111] For the convenience of distinction, in this embodiment, the naming method of "Die name_key signal" is used to facilitate distinguishing which Die the key signal belongs to; for example:

[0112] The flash_done signal of Die3 is Die3_flash_done; the flash_done signal of Die2 is Die2_flash_done;

[0113] The good signal of Die3 is Die3_good; the good signal of Die2 is Die2_good;

[0114] The enable signal of Die3 is Die3_en; the enable signal of Die2 is Die2_en;

[0115] The naming of the key signals between Die1, Die0 and the CPLD follows the same pattern. If there are more Dies, the above naming rules can also be applied.

[0116] Signal line configuration: 4 bidirectional signal lines are used for data transmission. Each signal line can be switched to input or output at any time, and dynamic data exchange between the two CPLDs is achieved according to the indication of the direction control signal line M2S_CTRL.

[0117] In this embodiment, Die0 and Die1 of the CPU are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD. The software working processes and state machine designs of the master CPLD and the slave CPLD are basically the same. The data transmission direction in the 4 bidirectional data lines is controlled by the direction control signal M2S_CTRL;

[0118] Specifically, when the direction control signal M2S_CTRL is equal to 1 or 0, the bidirectional signal M2S[3:0] represents flash_done and good of the two Dies connected to the master CPLD or the slave CPLD.

[0119] Specifically, M2S_CTRL is controlled by the state machine of the master CPLD. When M2S_CTR of the slave CPLD is equal to 0, the 4 bidirectional signal lines are used as outputs, that is, M2S[3:0] respectively represent Die0_flash_done, Die0_good, Die1_flash_done, Die1_good of the slave CPLD. That is, when M2S_CTRL is equal to 0, M2S[3] represents Die0_flash_done, M2S[2] represents Die0_good, M2S[1] represents Die1_flash_done, and M2S[0] represents Die1_good; the master CPLD obtains the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0];

[0120] When M2S_CTRL in the CPLD equals 1, four bidirectional signal lines are used as inputs. That is, M2S[3:0] respectively represent Die2_flash_done, Die2_good, Die3_flash_done, and Die3_good of the master CPLD. When M2S_CTRL equals 1, M2S[3] represents Die2_flash_done, M2S[2] represents Die2_good, M2S[1] represents Die3_flash_done, and M2S[0] represents Die3_good. The slave CPLD obtains the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

[0121] In this embodiment of the dual-CPLD architecture, efficient signal synchronization between CPLDs is achieved through four bidirectional signal lines and one direction control signal. The four-wire bidirectional communication allows the two CPLDs to flexibly switch the signal direction, ensuring that each CPLD can read or send the signals of the other party when needed. The direction control signal is used for timing control to meet the strict timing requirements during the startup and initialization of the multi-Die CPU.

[0122] Based on the background of the dual-CPLD design requirements, in this embodiment, all the power management signals of the CPU and system peripherals are centralized in the slave CPLD for management to ensure the controllability of the power signal timing.

[0123] The slave CPLD is responsible for controlling the startup and shutdown of all core power supplies, IO power supplies, and other related signals. All power control signals and the power OK indication signal PWROK are implemented through the power signal control logic within a single CPLD, avoiding the need for power signal transmission between the dual CPLDs, effectively reducing the delay and inconsistency of the power timing, and ensuring the reliable startup and operation of the CPU.

[0124] The power control logic is designed according to the system power timing requirements. For example, a CPU includes multiple power supplies, such as the core voltage (VDD), IO voltage (VDDIO), PCIe voltage (VDDH), memory voltage (VDDQ), etc. There is a certain sequence, i.e., timing requirement, among these power supplies during power-on. The CPLD controls the enabling of these power supplies in sequence according to the timing relationship to achieve control.

[0125] The traditional I2C communication rate is relatively low and difficult to meet the transmission requirements of high-speed CPU signals. Although SPI has a relatively high speed, it lacks flexible direction control and cannot perform two-way timing synchronization switching between dual CPLDs. In addition, although the parallel bus scheme has a high bandwidth, it requires a large amount of PCB wiring resources, increasing the complexity and design cost.

[0126] In this embodiment, the high pins of the multi-Die CPU are reasonably distributed on two CPLDs through a dual-CPLD architecture, avoiding the resource limitations and signal transmission problems caused by the concentration of pins on a single CPLD; signals are divided according to pin functions and physical regions, optimizing the PCB wiring and improving the integrity of signal transmission. The dual-CPLD structure reduces the pin density on the PCB, ensuring more abundant PCB wiring space, especially in high-speed signal wiring and power wiring, avoiding excessive stray signals and crosstalk problems.

[0127] The dual-CPLD distributed architecture not only physically adapts better to the pin distribution of the CPU, but also through partition management, enables each CPLD to independently complete the function verification of the pins in its jurisdiction, ensuring full coverage of the pins, optimizing the PCB wiring, reducing wiring interference, and improving the effective utilization of CPLD resources;

[0128] In addition, the two CPLDs are located on both sides of the CPU respectively, using different regions of the PCB layers, reducing the stray interference of cross-region signal lines, and improving the flexibility and signal quality of the PCB design.

[0129] Furthermore, in this embodiment, multiple power signals are centralized in one CPLD for management, avoiding the timing control and signal coordination problems caused by the dispersion of power signals between the two CPLDs. Through centralized control, it is ensured that the core power supply, IO power supply, etc. of each Die of the CPU can maintain consistency and reliability during startup, initialization, and operation, avoiding the power coordination requirements between the two CPLDs.

[0130] Embodiment 2

[0131] Reference Figure 4 , this embodiment provides a CPU synchronization method based on dual-CPLD bidirectional control. Based on the CPU synchronization system based on dual-CPLD bidirectional control described in Embodiment 1, the CPU includes Die0, Die1, Die2, and Die3; the method includes the following steps:

[0132] S1. After the main board is powered on, both the main CPLD and the slave CPLD are in the Idle state, M2S_CTRL is set to 1, the main CPLD resets Die3, enters the Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1;

[0133] S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2, enters the Die2_flash_read state, sets M2S_CTRL to 1, and Die2 starts to read the flash. After the reading is completed, the CPU sets Die2_flash_done to 1;

[0134] S3. When the main CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and sets M2S_CTRL to 0; in steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. When both are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state;

[0135] S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 and enters the Die0_flash_read state, and Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1;

[0136] S5. In steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. When both are equal to 1, it enters the Die2die_ready1 state;

[0137] S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset period, and the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, and enters the Die2die_ready2 state; at this time, the synchronization of all Die's flash done signals between the main and slave CPLDs and the initialization of all Dies are completed;

[0138] In this embodiment, the flash_done of the Die is multiplexed, and its meaning is different in different steps. In steps S1 - S6, flash_done is used to represent the flash reading state of the corresponding Die; when the flash_done of the Die is 1, it means that the corresponding Die has completed reading the flash, and when the flash_done of the Die is 0, it means that the corresponding Die has not completed reading the flash;

[0139] In steps S7 - S8, flash_done is used to represent some parameters of the Die - to - Die training status corresponding to the Die. Only when flash_done of the Die is 1 and good is 1, it indicates that the Die - to - Die training corresponding to the corresponding Die is completed. The Die - to - Die training is the behavior of the CPU, and the CPLD only monitors these two signals.

[0140] If the Die - to - Die training is not successful, flash_done will not be 1, and the CPLD will always be in a waiting state. The CPU will try to train multiple times internally, and the CPLD only monitors these signals.

[0141] S7. After the initialization of all Dies is completed, the CPU first sets the flash_done of the 4 Dies to 0. When the master - slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, it starts the Die - to - Die training for the first time;

[0142] It can be understood that the master - slave CPLD is the abbreviation of the master CPLD and the slave CPLD;

[0143] Specifically, when the master - slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, starting the Die - to - Die training for the first time specifically includes:

[0144] S71. When the master - slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, it starts the Die - to - Die training, enters the Die2die_ctl_en_wait state, sets M2S_CTRL to 1, waits for a preset cycle time, and the slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively;

[0145] After a preset cycle time, it enters the Die2die_ctl_en state, sets M2S_CTRL to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all Dies between the master and slave CPLDs is completed. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, the Die2Die training enable is turned off and it enters the Die2Die_pre1 state.

[0146] The preset cycle time is determined according to specific needs; in this embodiment, the preset cycle time is 20 ns;

[0147] S8. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good, and Die0_good are all 1, the Die2Die training ends and it enters the Die2die_finish state.

[0148] Step S8 specifically includes:

[0149] S81. After the Die2Die training enable is turned off in step S72 and it enters Die2Die_pre1, set M2S_CTRL to 1. The slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and enters the Die2Die_pre2 state. Set M2S_CTRL to 0, and the master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively;

[0150] S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 0, the Die2Die training enable is turned on for the second time, and the Die2die_start1 state is entered. M2S_CTRL is set to 1. The slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and then enters the Die2Die_start2 state. M2S_CTRL is set to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively;

[0151] S83. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, the Die2Die training enable is turned off for the second time, and the Die2die_done1 state is entered;

[0152] Repeating the opening and closing of the Die2Die training enable twice is the behavior of the CPU, mainly used for two instruction synchronizations to ensure stability;

[0153] S84. When in the Die2die_done1 state, M2S_CTRL is set to 1. The slave CPLD synchronously obtains the values of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, and synchronously obtains the values of Die2_good and Die3_good through the data lines M2S[2] and M2S[0] respectively. After waiting for a cycle, it enters the Die2die_done2 state;

[0154] S85. When in the Die2die_done2 state, M2S_CTRL is set to 0. The master CPLD synchronously obtains the values of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively, and synchronously obtains the values of Die0_good and Die0_good through the data lines M2S[2] and M2S[0] respectively. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good, and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done, and Die3_flash_done are all 1, it enters the Die2die_finish state, and the Die2die training ends. Otherwise, it keeps waiting, indicating that the training is not completed.

[0155] The synchronization of the CPU in this embodiment can be regarded as two stages. The first stage: complete the initialization of 4 dies, that is, steps S1 - S6; the second stage: complete the training between Dies, that is, steps S7 - S8;

[0156] These two stages of Die initialization and Die2Die training are independent. After all 4 dies are initialized, the CPU will set its flash_done to 0 and start entering Die2Die training.

[0157] After the first stage of reading the flash is completed, it enters the second stage of Die2Die training. The condition for entry is that the flash_done of the four dies are all 0. After the Die2Die enable en is turned on, the CPLD will detect the flash_done signals of the 4 dies again. If they are all 1, it means that the CPU has received the Die2Die training command, and the Die2Die enable en can be turned off and enter the Die2die_done state. At this time, the CPLD only needs to detect whether the good signals of the 4 dies are 1. If it is 1, it means the training is completed and the whole process ends. If it is not 1, it continues to wait.

[0158] After the main board is powered on, in the default state, the main CPLD first resets Die3, enters the state of reading Die3 flash and M2S_CTRL equals 1, and Die3 starts to read flash. The main CPLD waits for whether Die3_flash_done is 1. If it is 1, then it resets Die2 to enter the state of reading Die2 flash and M2S_CTRL equals 1, and Die2 starts to read flash. The main CPLD waits for whether Die2_flash_done is 1. The first two states of the slave CPLD are to judge whether Die3 and Die2 have completed reading flash. Because M2S_CTRL equals 1 and M2S[3:0] is used as the input of the slave CPLD, the slave CPLD only needs to judge these values of M2S[3:0]. Returning to the main CPLD state machine, if it is 1, similarly, the main CPLD enters the state of judging whether Die1 and Die0 have completed reading flash and M2S_CTRL equals 0, and M2S[3:0] is used as the input judgment value of the main CPLD.

[0159] When the subsequent state machine needs to judge flash_done and good of 4 Dies simultaneously, only one level of direction control state of M2S_CTRL needs to be added to the main CPLD to synchronize the values of M2S[3:0] on both sides. The above is the coordination mechanism principle of 5 signal lines.

[0160] Reference Figure 5 , this embodiment provides a partial state machine for bidirectional control of the main CPLD;

[0161] Idle: Indicates idle;

[0162] flash_read: Indicates the state of Die reading flash;

[0163] flash_done: In the initialization stage of Die, it is used to indicate whether Die has completed reading flash; when preparing to start the Die2Die training stage, flash_done of 4 Dies is 0 simultaneously to start Die2Die training, and is 1 simultaneously to close Die2Die training. There are two identical operations in total for synchronous confirmation; during the Die2Die training process, in addition to good, this signal is also used as one of the conditions to indicate whether the Die2Die training of a certain Die is successful;

[0164] good: In the Die2Die training stage, this signal is used to indicate whether the Die2Die training of a certain Die is completed, and at the same time flash_done needs to be set to 1;

[0165] When flash_done equals 1, it indicates that Die has completed reading flash or is one of the conditions for the Die2Die training of Die to be completed;

[0166] When flash_done is equal to 0, it indicates that the flash reading of the Die is not completed or one of the Die2Die training flags of the Die is not completed;

[0167] The CPU can also be considered that the Die tells the CPLD whether the flash reading is completed through the flash_done signal;

[0168] For easy distinction, in this embodiment, the naming method of "Die name_fsm type" is used to facilitate distinguishing which Die the fsm type belongs to;

[0169] For example: Die3_flash_read: indicates the flash reading status of Die3; when Die3 finishes reading the flash, set Die3_flash_done to 1; when Die3 fails to finish reading the flash, set Die3_flash_done to 0;

[0170] Die2_flash_read: indicates the flash reading status of Die2; when Die2 finishes reading the flash, set Die2_flash_done to 1; when Die2 fails to finish reading the flash, set Die2_flash_done to 0;

[0171] Die1_flash_read: indicates the flash reading status of Die1; when Die1 finishes reading the flash, set Die1_flash_done to 1; when Die1 fails to finish reading the flash, set Die1_flash_done to 0;

[0172] Die0_flash_read: indicates the flash reading status of Die0; when Die0 finishes reading the flash, set Die0_flash_done to 1; when Die0 fails to finish reading the flash, set Die0_flash_done to 0;

[0173] Die2die_ready1: set M2S_CTRL = 1, wait for one cycle, and obtain the flash_done of Die3 and Die2 from the CPLD;

[0174] Die2die_ready2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 0. If they are 0, enable the Die2Die enable condition;

[0175] Die2die_ctl_en_wait: Set M2S_CTRL = 1, wait for one cycle, and obtain the flash_done of Die3 and Die2 from the slave CPLD;

[0176] Die2die_ctl_en: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 1. If they are 1, disable the Die2Die enable condition;

[0177] Die2die_pre1: Set M2S_CTRL = 1, indicating waiting for one cycle to obtain the flash_done of Die3 and Die2 from the slave CPLD; Repeat the Die2Die enable process once. This is the behavior of the CPU for two - handshake synchronization.

[0178] Die2die_pre2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 0. If they are 0, enable the Die2Die enable condition; Here, it has the same function as the Die2die_ready2 state, used for two - handshake synchronization to ensure stability;

[0179] Die2die_start1: Set M2S_CTRL = 1, wait for one cycle, and obtain the flash_done of Die3 and Die2 from the slave CPLD;

[0180] Die2die_start2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 1. If they are 1, disable the Die2Die enable condition;

[0181] Since it is the communication between two CPLDs, the slave CPLD judges the value of M2S_CTRL in this state. For example, in the previous cycle, it outputs signals to the master CPLD to transfer die1 and die0, and in the next cycle, it becomes an input to read the signals of die3 and die2 transferred from the master CPLD. Since M2S_CTRL is controlled by the master CPLD, therefore, when the slave CPLD judges that M2S_CTRL has changed, it enters the next state.

[0182] Die2die_done1: Set M2S_CTRL = 0, indicating to wait for one cycle for the master CPLD to obtain the flash_done and training good signals of Die1 and Die0;

[0183] Die2die_done2: Set M2S_CTRL = 1. If the master and slave CPLDs have synchronously obtained the flash_done and training good signals of Die3, Die2, Die1, and Die0 and the results are all 1, then the training is completed;

[0184] Die2die_finish: Indicates that the Die2Die training is completed.

[0185] In this embodiment, in the dual-CPLD architecture, through 4 bidirectional signal lines and 1 direction control signal, efficient signal synchronization between CPLDs is achieved. The 4-wire bidirectional communication allows the two CPLDs to flexibly switch the signal direction, ensuring that each CPLD can read or send the signals of the other party when needed; the direction control signal is used for timing control to meet the strict timing requirements during the startup and initialization of the multi-Die CPU. This method ensures precise timing control and signal synchronization between the two CPLDs with limited signal resources;

[0186] Furthermore, during the startup and initialization of the CPU multi-Die, the switching of the direction signal is controlled by the state machine to precisely manage the signal timing synchronization between the CPLDs. This timing synchronization control strategy ensures the signal consistency between the multi-Dies and avoids the problems of signal delay and loss in the dual-CPLD communication.

[0187] Those of ordinary skill in the art will understand that all or some of the steps and systems in the methods provided above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as a microprocessor, such as a central processing unit, a digital signal processor, or software executed by a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that a communication medium typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0188] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A CPU synchronization system based on dual CPLD bidirectional control, characterized in that: Including power management signal; the CPU includes multiple Dies; the dual CPLD includes a master CPLD and a slave CPLD; the software workflow and state machine design of the master CPLD and the slave CPLD are the same; the pins of each Die are classified according to the functional signal and connected to the CPLD with the closest physical distance; the power management signal is generated by the CPU and the power module; the power module is connected to the slave CPLD, and the slave CPLD controls the start and stop of the power management signal; The master CPLD and the slave CPLD are connected via four bidirectional signal lines and one direction control signal line; the four bidirectional signal lines correspond to the bidirectional signal M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; The direction control signal line is used to control the data direction of the four bidirectional signal lines; the four bidirectional signal lines are used to perform data transmission between the two CPLDs according to the data direction determined by the direction control signal line, and the four bidirectional signal lines can be switched to input or output at any time to complete the timing synchronization of the CPU.

2. The CPU synchronization system based on dual CPLD bidirectional control according to claim 1 is characterized in that: The direction control signal line is used to control the data direction of the four bidirectional signal lines: When M2S_CTRL is at a high level, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the master CPLD is the receiver.

3. The CPU synchronization system based on dual CPLD bidirectional control according to claim 2 is characterized in that: When the data direction is determined, the CPLD of the sender loads the data onto the four bidirectional signal lines, and the CPLD of the receiver reads the data. During data transmission, the sender keeps the signal line in output mode, and the receiver switches to input mode.

4. The CPU synchronization system based on dual CPLD bidirectional control according to claim 3 is characterized in that: The direction control signal M2S_CTRL is controlled by the main CPLD.

5. The CPU synchronization system based on dual CPLD bidirectional control according to claim 3 is characterized in that: The data transmission between the dual CPLDs includes key signals flash_done, good and en: flash_done signal: used to indicate the completion signal of Die reading flash information during Die initialization phase, and output by Die to CPLD; When flash_done is equal to 0, it means that the Die Flash has not been read; when flash_done is equal to 1, it means that the Die Flash has been read; In the Die2Die stage of Die, flash_done is also used to indicate whether the Die2Die training is completed, and it must be combined with the good signal of Die. Only when flash_done is 1 and good is 1, it indicates that the Die2Die training of the corresponding Die is completed; when flash_done is 0, it indicates that the Die2Die training is not completed. good: used in conjunction with the flash_done signal to indicate whether the Die2Die training of Die is completed, and is output by Die to CPLD; when good is equal to 0, it indicates that the Die2Die training of Die is not completed; when flash_done is equal to 1 and good is equal to 1, it indicates that the Die2Die training of Die is completed; en: used to indicate the start and stop of Die2Die training, output by CPLD to Die; when en is equal to 0, it indicates that Die2Die training is turned off; when en is equal to 1, it indicates that Die2Die training is started.

6. The CPU synchronization system based on dual CPLD bidirectional control according to claim 5 is characterized in that: The CPU includes Die0, Die1, Die2 and Die3; Die0 and Die1 are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD; the direction control signal M2S_CTRL controls the data transmission direction in the four bidirectional data lines; M2S[3:0] represents the flash_done and good of the two dies of the master CPLD or the slave CPLD according to whether M2S_CTRL is equal to 1 or 0.

7. The CPU synchronization system based on dual CPLD bidirectional control according to claim 6 is characterized in that: When M2S_CTR of the slave CPLD is equal to 0, the four bidirectional signal lines are used as outputs, that is, M2S[3:0] represents Die0_flash_done, Die0_good, Die1_flash_done, Die1_good of the slave CPLD in turn. The master CPLD obtains the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0]. When M2S_CTRL of the slave CPLD is equal to 1, the four bidirectional signal lines are used as inputs, that is, M2S[3:0] represents Die2_flash_done, Die2_good, Die3_flash_done, Die3_good of the master CPLD respectively. The slave CPLD obtains the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

8. A CPU synchronization method based on dual CPLD bidirectional control, based on the CPU synchronization system based on dual CPLD bidirectional control according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. After the mainboard is powered on, both the master CPLD and the slave CPLD are in Idle state, M2S_CTRL is set to 1, the master CPLD resets Die3 and enters Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1; S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2 and enters the Die2_flash_read state. M2S_CTRL is set to 1, and Die2 starts to read the flash. After the reading is completed, the CPU sets Die2_flash_done to 1. S3. When the master CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and M2S_CTRL is set to 0. In steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively. When both are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state. S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 to enter the Die0_flash_read state, and Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1. In S5, steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively, and when both are equal to 1, enters the Die2die_ready1 state; S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset cycle, and synchronously obtain the values ​​of Die2_flash_done and Die3_flash_done from the CPLD through the data lines M2S[3] and M2S[1] respectively, and enter the Die2die_ready2 state; S7, when in Die2die_ready2 state, the CPU first sets the flash_done of the four Dies to 0. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started for the first time. S8. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good and Die0_good are all 1, Die2Die training ends and enters the Die2die_finish state.

9. The CPU synchronization method based on dual CPLD bidirectional control according to claim 8, characterized in that: In step S7, when the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the first opening of Die2Die training enable specifically includes: S71. When the master-slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started, the Die2die_ctl_en_wait state is entered, M2S_CTRL is set to 1, and a preset cycle time is waited. The slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively; S72. After a preset cycle time, the system enters the Die2die_ctl_en state, sets M2S_CTRL to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all dies between the master and slave CPLDs is completed. When the master and slave CPLDs both detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, the Die2Die training enable is turned off and the system enters the Die2Die_pre1 state.

10. The CPU synchronization method based on dual CPLD bidirectional control according to claim 8, characterized in that: Step S8 specifically includes: S81. When in the Die2Die_pre1 state, M2S_CTRL is set to 1, and the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and enters the Die2Die_pre2 state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively; S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 0, the Die2Die training enable is turned on for the second time, and the state of Die2die_start1 is entered. M2S_CTRL is set to 1. The slave CPLD obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. After waiting for a preset cycle time, the state of Die2Die_start2 is entered. M2S_CTRL is set to 0. The master CPLD obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. S83, when both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 1, the Die2Die training enable is turned off for the second time and the state of Die2die_done1 is entered; S84, when in the Die2die_done1 state, M2S_CTRL is set to 1, and the values ​​of Die2_flash_done and Die3_flash_done are synchronously obtained from the CPLD through the data lines M2S[3] and M2S[1], and the values ​​of Die2_good and Die3_good are synchronously obtained through the data lines M2S[2] and M2S[0], respectively. After waiting for one cycle, it enters the Die2die_done2 ​​state; S85. When in the Die2die_done2 ​​state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1], and synchronously obtains the values ​​of Die0_good and Die0_good through the data lines M2S[2] and M2S[0]. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, they enter the Die2die_finish state and the Die2die training is completed. Otherwise, they keep waiting, indicating that the training is not completed.

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