Register indirect access circuit

Abstract

The invention relates to chip design, in particular to a register indirect access circuit which comprises a block enabling generation device and a plurality of register block read-write devices, and the block enabling generation device and the register block read-write devices share a register clock, write data, write enabling, read enabling and read-write addresses. Block enabling register read data output by the block enabling generation device and register block read data output by each register block read-write device are subjected to OR operation, then are beat by a group of D triggers and are sent to read data; according to the technical scheme provided by the invention, the defect that the addressing space of the register is difficult to effectively expand under the condition that the address bus width is not expanded in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to chip design, and in particular to a register indirect access circuit. Background Art

[0002] In the process of chip development, in order to meet the design requirements, a certain number of registers are generally used, such as readable and writable configuration registers, readable-only status registers, etc. These registers will occupy a certain size of addressing space, so a certain width of address bus is required for addressing. When the number of registers is large, a larger addressing space is required. The general solution to this problem is to ensure that all registers can be correctly addressed by widening the address bus.

[0003] Widening the address bus can solve the problem of insufficient addressing space, but it also brings the disadvantage of increasing chip area. When the number of registers is large, the required addressing space will be relatively large, and the required address bus width may be too large to be accepted. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above shortcomings of the prior art, the present invention provides a register indirect access circuit, which can effectively overcome the defect of the prior art that it is difficult to effectively expand the register addressing space without widening the address bus width.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A register indirect access circuit includes a block enable generating device and a plurality of register block read / write devices, wherein the block enable generating device and each register block read / write device share a register clock, write data, write enable, read enable, and read / write address, and the block enable register read data output by the block enable generating device and the register block read data output by each register block read / write device are ORed and then sent to the read data after being struck by a group of D flip-flops;

[0009] The block enable generating device comprises a block enable register, a first register clock gating ICG1, a first equal comparator Q1, a first AND gate A1, a second AND gate A2, a first two-selector M1 and a second equal comparator Q2, wherein the first equal comparator Q1 is connected to a read / write address and a preset block enable register address, the first AND gate A1 is connected to an output end and a write enable of the first equal comparator Q1, the second AND gate A2 is connected to an output end and a read enable of the first equal comparator Q1, the first register clock gating ICG1 is connected to a register clock and an output end of the first AND gate A1, the block enable register is connected to an output end and write data of the first register clock gating ICG1, the first two-selector M1 is connected to an output end of the second AND gate A2, a block enable register value output by the block enable register and 0, the first two-selector M1 outputs block enable register read data, the second equal comparator Q2 is connected to a block enable register value output by the block enable register and a preset register block base address, and the second equal comparator Q2 outputs a block enable corresponding to the register block;

[0010] The register block read-write device includes a register block, a third equal comparator Q3, a third AND gate A3, a second register clock gating ICG2, a first OR gate O1, and a plurality of groups of equal comparators, AND gates and two-to-one selectors matching the number of registers stored in the register block. The register block stores a plurality of registers. The third equal comparator Q3 is connected to the read-write address and the preset register address. The third AND gate A3 is connected to the output end of the third equal comparator Q3, the block enable output by the second equal comparator Q2, and the write enable. The second register clock gating ICG2 is connected to the register clock and the output end of the third AND gate A3. The register block is connected to the output end of the second register clock gating ICG2, write data, the read-write address and the preset register address. The register block outputs the register value.

[0011] The first equal comparator q1 is connected to the read-write address and the preset register 1 address, the first AND gate a1 is connected to the output end, read enable and block enable of the first equal comparator q1, the first two-to-one selector m1 is connected to the output end of the first AND gate a1, the register 1 value and 0 output by the register block, the first OR gate O1 is connected to the register 1 read data output by the first two-to-one selector m1, and the remaining groups of equal comparators, AND gates and two-to-one selectors have the same connection structure as the first equal comparator q1, the first AND gate a1 and the first two-to-one selector m1, and the first OR gate O1 outputs the register block read data.

[0012] Preferably, the register clock accessed by the first register clock gating ICG1 is the working clock of the block enable generating device. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gating ICG1 is turned on, otherwise the first register clock gating ICG1 is turned off, so as to realize the data update of the block enable register;

[0013] When the read / write address matches the preset block enable register address and the read enable is valid, the block enable register read data will be assigned the block enable register value, otherwise the block enable register read data will be assigned 0;

[0014] After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches a register block base address, the second equal comparator Q2 outputs the block enable corresponding to the register block to enable the corresponding register block.

[0015] Preferably, the register block stores N registers, a certain register is selected by a read / write address, each register block shares a read / write address bus with a block enable register, and the values ​​of the N registers are output to other circuits in the chip for use;

[0016] Each register block shares the write data bus and the read data bus with the block enable register.

[0017] Preferably, the register clock accessed by the second register clock gating ICG2 is the working clock of the register block reading and writing device. When the reading and writing address matches a certain register address, and the write enable and block enable are valid, the second register clock gating ICG2 is turned on, otherwise the second register clock gating ICG2 is turned off;

[0018] After the second register clock gating ICG2 is turned on, the register block receives the register clock and starts working, and the register block outputs the values ​​of registers 1, 2, ..., N, so as to update the data of multiple registers in the register block;

[0019] When the read / write address matches the preset register 1, 2, ..., N address, and the read enable and block enable are valid, the register 1, 2, ..., N read data will be assigned to the register 1, 2, ..., N value, otherwise the register 1, 2, ..., N read data will be assigned to 0, and finally the register 1, 2, ..., N read data will be ORed and assigned to the register block read data.

[0020] The register clock accessed by the second register clock gating ICG2 is the same as the register clock accessed by the first register clock gating ICG1.

[0021] (III) Beneficial effects

[0022] Compared with the prior art, the register indirect access circuit provided by the present invention can effectively expand the register addressing space without widening the address bus width, avoid the increase of chip area, and has a simple circuit, which is easy to implement and consumes less resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a schematic diagram of the hardware structure of the present invention;

[0025] Figure 2 For the present invention Figure 1 The circuit structure diagram of the middle block enabling generating device;

[0026] Figure 3 For the present invention Figure 1 Circuit diagram of a single register block read / write device. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] A register indirect access circuit, such as Figure 1 As shown, it includes a block enable generating device and multiple register block read-write devices. The block enable generating device and each register block read-write device share register clock, write data, write enable, read enable, read-write address, and the block enable register read data output by the block enable generating device and the register block read data output by each register block read-write device are ORed and then sent to the read data after being struck by a group of D flip-flops.

[0029] like Figure 2As shown, the block enable generating device includes a block enable register, a first register clock gating ICG1, a first equal comparator Q1, a first AND gate A1, a second AND gate A2, a first two-to-one selector M1 and a second equal comparator Q2, the first equal comparator Q1 is connected to the read-write address and the preset block enable register address, the first AND gate A1 is connected to the output end and write enable of the first equal comparator Q1, the second AND gate A2 is connected to the output end and read enable of the first equal comparator Q1, and the first register clock gating ICG1 is connected to the register The clock and the output end of the first AND gate A1, the block enable register is connected to the output end of the first register clock gate ICG1 and the write data, the first two-to-one selector M1 is connected to the output end of the second AND gate A2, the block enable register value output by the block enable register and 0, the first two-to-one selector M1 outputs the block enable register read data, the second equal comparator Q2 is connected to the block enable register value output by the block enable register and the preset register block base address (1, 2, ..., M), and the second equal comparator Q2 outputs the block enable corresponding to the register block.

[0030] The register clock accessed by the first register clock gating ICG1 is the working clock of the block enable generating device. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gating ICG1 is turned on, otherwise the first register clock gating ICG1 is turned off to realize the data update of the block enable register;

[0031] When the read / write address matches the preset block enable register address and the read enable is valid, the block enable register read data will be assigned the block enable register value, otherwise the block enable register read data will be assigned 0;

[0032] After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches a register block base address, the second equal comparator Q2 outputs the block enable corresponding to the register block to enable the corresponding register block.

[0033] Figure 2 In the block enable register, write data refers to the data written to the block enable register, and read data refers to the data read from the block enable register.

[0034] like Figure 3As shown, the register block read-write device includes a register block, a third equal comparator Q3, a third AND gate A3, a second register clock gating ICG2, a first OR gate O1, and a plurality of groups of equal comparators, AND gates and two-to-one selectors matching the number of registers stored in the register block. A plurality of registers are stored in the register block. The third equal comparator Q3 is connected to the read-write address and the preset register address (1, 2, ..., N). The third AND gate A3 is connected to the output end of the third equal comparator Q3, the block enable output by the second equal comparator Q2, and the write enable. The second register clock gating ICG2 is connected to the register clock and the output end of the third AND gate A3. The register block is connected to the output end of the second register clock gating ICG2, write data, the read-write address and the preset register address. The register block outputs the register value.

[0035] The first equal comparator q1 is connected to the read-write address and the preset register 1 address, the first AND gate a1 is connected to the output end, read enable and block enable of the first equal comparator q1, the first two-to-one selector m1 is connected to the output end of the first AND gate a1, the register 1 value and 0 output by the register block, the first OR gate O1 is connected to the register 1 read data output by the first two-to-one selector m1, and the remaining groups of equal comparators, AND gates and two-to-one selectors have the same connection structure as the first equal comparator q1, the first AND gate a1 and the first two-to-one selector m1, and the first OR gate O1 outputs the register block read data.

[0036] The register block stores N registers. A register is selected by reading and writing addresses. Each register block shares the read-write address bus with the block enable register (due to the shared read-write address bus, the position with the same address as the block enable register in each register block cannot be accessed, that is, the address of the block enable register is unique). The values ​​of the N registers are output to other circuits in the chip for use.

[0037] Each register block shares the write data bus and the read data bus with the block enable register.

[0038] The register clock accessed by the second register clock gating ICG2 is the working clock of the register block read / write device. When the read / write address matches a certain register address, and the write enable and block enable are valid, the second register clock gating ICG2 is turned on, otherwise the second register clock gating ICG2 is turned off;

[0039] After the second register clock gate ICG2 is turned on, the register block receives the register clock and starts working, and the register block outputs the values ​​of registers 1, 2, ..., N, thereby updating the data of multiple registers inside the register block;

[0040] When the read / write address matches the preset register 1, 2, ..., N address, and the read enable and block enable are valid, the register 1, 2, ..., N read data will be assigned to the register 1, 2, ..., N value, otherwise the register 1, 2, ..., N read data will be assigned to 0, and finally the register 1, 2, ..., N read data will be ORed and assigned to the register block read data.

[0041] The register clock accessed by the second register clock gating ICG2 is the same as the register clock accessed by the first register clock gating ICG1.

[0042] Figure 3 In the register block, write data refers to the data written to the register block, and register block read data refers to the data read from the register block.

[0043] In the technical solution of this application, register access through the register indirect access circuit needs to be implemented through the following two steps:

[0044] 1) Configure the block enable register in the block enable generating device to be the base address of the register block where the target register is located, and first enable the register block to be accessed;

[0045] 2) Perform data update or data read operations on the target register in the selected register block.

[0046] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A register indirect access circuit, characterized in that: It includes a block enable generating device and a plurality of register block read / write devices. The block enable generating device and each register block read / write device share register clock, write data, write enable, read enable, read / write address. The block enable register read data output by the block enable generating device and the register block read data output by each register block read / write device are ORed and then sent to the read data after being struck by a group of D flip-flops. The block enable generating device comprises a block enable register, a first register clock gating ICG1, a first equal comparator Q1, a first AND gate A1, a second AND gate A2, a first two-selector M1 and a second equal comparator Q2, wherein the first equal comparator Q1 is connected to a read / write address and a preset block enable register address, the first AND gate A1 is connected to an output end and a write enable of the first equal comparator Q1, the second AND gate A2 is connected to an output end and a read enable of the first equal comparator Q1, the first register clock gating ICG1 is connected to a register clock and an output end of the first AND gate A1, the block enable register is connected to an output end and write data of the first register clock gating ICG1, the first two-selector M1 is connected to an output end of the second AND gate A2, a block enable register value output by the block enable register and 0, the first two-selector M1 outputs block enable register read data, the second equal comparator Q2 is connected to a block enable register value output by the block enable register and a preset register block base address, and the second equal comparator Q2 outputs a block enable corresponding to the register block; The register block read-write device includes a register block, a third equal comparator Q3, a third AND gate A3, a second register clock gating ICG2, a first OR gate O1, and a plurality of groups of equal comparators, AND gates and two-to-one selectors matching the number of registers stored in the register block. The register block stores a plurality of registers. The third equal comparator Q3 is connected to the read-write address and the preset register address. The third AND gate A3 is connected to the output end of the third equal comparator Q3, the block enable output by the second equal comparator Q2, and the write enable. The second register clock gating ICG2 is connected to the register clock and the output end of the third AND gate A3. The register block is connected to the output end of the second register clock gating ICG2, write data, the read-write address and the preset register address. The register block outputs the register value. The first equal comparator q1 is connected to the read-write address and the preset register 1 address, the first AND gate a1 is connected to the output end, read enable and block enable of the first equal comparator q1, the first two-to-one selector m1 is connected to the output end of the first AND gate a1, the register 1 value and 0 output by the register block, the first OR gate O1 is connected to the register 1 read data output by the first two-to-one selector m1, and the remaining groups of equal comparators, AND gates and two-to-one selectors have the same connection structure as the first equal comparator q1, the first AND gate a1 and the first two-to-one selector m1, and the first OR gate O1 outputs the register block read data.

2. The register indirect access circuit according to claim 1, characterized in that: The register clock accessed by the first register clock gating ICG1 is the working clock of the block enable generating device. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gating ICG1 is turned on, otherwise the first register clock gating ICG1 is turned off, so as to realize the data update of the block enable register; When the read / write address matches the preset block enable register address and the read enable is valid, the block enable register read data will be assigned the block enable register value, otherwise the block enable register read data will be assigned 0; After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches a register block base address, the second equal comparator Q2 outputs the block enable corresponding to the register block to enable the corresponding register block.

3. The register indirect access circuit according to claim 1, characterized in that: The register block stores N registers inside, and a register is selected by reading and writing addresses. Each register block shares a read and write address bus with a block enable register, and the values ​​of the N registers are output to other circuits in the chip for use; Each register block shares the write data bus and the read data bus with the block enable register.

4. The register indirect access circuit according to claim 3, characterized in that: The register clock accessed by the second register clock gating ICG2 is the working clock of the register block read / write device. When the read / write address matches a certain register address and the write enable and block enable are valid, the second register clock gating ICG2 is turned on, otherwise the second register clock gating ICG2 is turned off; After the second register clock gating ICG2 is turned on, the register block receives the register clock and starts working, and the register block outputs the values ​​of registers 1, 2, ..., N, so as to update the data of multiple registers in the register block; When the read / write address matches the preset register 1, 2, ..., N address, and the read enable and block enable are valid, the register 1, 2, ..., N read data will be assigned to the register 1, 2, ..., N value, otherwise the register 1, 2, ..., N read data will be assigned to 0, and finally the register 1, 2, ..., N read data will be ORed and assigned to the register block read data. The register clock accessed by the second register clock gating ICG2 is the same as the register clock accessed by the first register clock gating ICG1.

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