Data transmission method, chip and electronic equipment

Abstract

The invention relates to the technical field of data processing, and discloses a data transmission method, a chip and electronic equipment, and the method comprises the steps that a second chip sends a state change notice to a first chip on the basis of detecting that at least one of a first buffer area and a second buffer area has a state change; the first chip responds to the state change notification to obtain a state value from the second chip; and if the state value indicates that the buffer area state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the abnormal buffer area. The corresponding bus transmission speed is adjusted according to the state of the amount of buffer area data of the first buffer area and the second buffer area, and dynamic adjustment is achieved so that the buffer area data can be kept within a reasonable range all the time. Therefore, the interruption of playing and recording caused by insufficient received or sent data is avoided, and the skip playing of playing and recording caused by data overflow and data loss of the buffer area is also avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a data transmission method, a chip and an electronic device. Background Art

[0002] Microcontroller units (MCU) and field-programmable gate arrays (FPGA) are commonly used in multi-channel audio processing circuits. MCU is used to communicate with personal computers (PC). MCU and FPGA communicate through multiple buses. FPGA is used for channel expansion to achieve multi-channel communication with power amplifiers (PA).

[0003] However, since MCU works serially and FPGA works in parallel, how to coordinate the multiple buses between FPGA and MCU directly affects the communication efficiency between FPGA and MCU. Summary of the invention

[0004] The embodiments of the present invention provide a data transmission method, a chip and an electronic device.

[0005] In a first aspect, the present invention provides a data transmission method, which is applied to an electronic device, wherein the electronic device includes a first chip and a second chip, the second chip includes a first buffer and a second buffer, the first chip writes data to the first buffer through a first bus, and reads data from the second buffer through a second bus, wherein the method includes: the second chip sends a state change notification to the first chip based on detecting that a state change occurs in at least one of the first buffer and the second buffer; in response to the state change notification, the first chip obtains a state value used to represent the buffer state of the second chip; if the state value indicates that the buffer state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the buffer where the abnormality occurs.

[0006] In the embodiment of the present invention, in the above data transmission method, the corresponding bus transmission speed is adjusted according to the state of the buffer data in the first buffer and the second buffer, so as to achieve dynamic adjustment to keep the buffer data always within a reasonable range. In this way, there will be no interruption of playback and recording due to insufficient received or sent data, and there will be no playback and recording skipping due to buffer data overflow and data loss.

[0007] In a possible implementation of the first aspect above, if the status value indicates that the buffer state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the buffer where the abnormality occurs, including: if the status value indicates that the current storage capacity of the first buffer is greater than or equal to the first threshold, reducing the write rate of the first bus; if the status value indicates that the current storage capacity of the first buffer is less than or equal to the second threshold, increasing the write rate of the first bus; if the status value indicates that the current storage capacity of the second buffer is greater than or equal to the third threshold, increasing the read rate of the second bus; if the status value indicates that the current storage capacity of the second buffer is less than or equal to the fourth threshold, reducing the read rate of the second bus.

[0008] In a possible implementation of the first aspect, the second chip sends a state change notification to the first chip, including: the second chip sends the state change notification to the first chip in a manner of sending an interrupt signal.

[0009] In a possible implementation of the first aspect, the first chip acquires a status value indicating a buffer status of the second chip, including: the first chip acquires the status value from the second chip through a third bus.

[0010] In a possible implementation of the first aspect above, the method further includes: the first chip detecting states of the first buffer and the second buffer at a preset first time interval.

[0011] In a possible implementation of the first aspect above, the method further includes: the first chip determines a state value based on a detection result of the detection, and sends a state change notification to the first chip when the state value is different from a previous state value.

[0012] In a possible implementation of the first aspect above, the method further includes: the first chip obtains the state value from the second chip through the third bus at a preset second time interval.

[0013] In a possible implementation of the first aspect above, the first chip communicates with the second chip in a serial manner.

[0014] In a possible implementation of the first aspect above, the method further includes: the second chip outputting the data in the first buffer to the power amplifier to drive the power amplifier; and the second chip writing the data collected by the power amplifier into the second buffer.

[0015] In a possible implementation of the first aspect above, the data in the first buffer includes audio playback data, and the data in the second buffer includes recorded audio data, wherein the recorded audio data is recorded data of the audio playback data.

[0016] In a possible implementation of the first aspect, the second chip communicates with the power amplifier in a parallel manner.

[0017] In a possible implementation of the first aspect above, the method further includes: if the status value indicates that the buffer status is a normal status, the first chip obtains the status of the power amplifier from the second chip through the third bus.

[0018] In a possible implementation of the first aspect above, the first chip includes at least a microcontroller unit; the second chip includes at least a field programmable gate array, the first bus includes at least an external bus interface bus, and the second bus includes at least a serial peripheral interface bus.

[0019] In a possible implementation of the first aspect above, the first chip includes a main state machine trigger module and a multi-bus execution module, and the second chip includes a slave state machine acquisition module and a state synchronization module; the second chip detects the status of the first buffer and the second buffer through the slave state machine acquisition module, and sends the detection result to the state synchronization module; the second chip determines the state value based on the detection result through the state synchronization module and sends a state change notification to the main state machine trigger module when the state value is different from the previous state value; the first chip obtains the occurring state value from the state synchronization module through the main state machine trigger module in response to the state change notification, and sends the state value to the multi-bus execution module; the first chip adjusts the transmission rate of the corresponding bus based on the state value through the multi-bus execution module.

[0020] In a second aspect, the present invention provides an electronic device comprising a first chip and a second chip, the second chip comprising a first buffer and a second buffer, the first chip writing data to the first buffer via a first bus, and reading data from the second buffer via a second bus, wherein: the second chip is used to send a state change notification to the first chip based on detecting a state change in at least one of the first buffer and the second buffer; the first chip is used to obtain a state value representing the buffer state of the second chip in response to the state change notification; the first chip is also used to adjust the transmission rate of the bus corresponding to the buffer where the abnormality occurs if the state value indicates that the buffer state is an abnormal state.

[0021] In a third aspect, the present invention provides a data transmission method, which is applied to a first chip, wherein the first chip writes data to a first buffer of a second chip through a first bus, and reads data from a second buffer of the second chip through a second bus, wherein the method comprises: in response to a status change notification sent by the second chip, obtaining a status value used to represent the buffer status of the second chip, wherein the status change notification is used to indicate that a status change occurs in at least one of the first buffer and the second buffer; if the status value indicates that the buffer status is an abnormal state, adjusting the transmission rate of the bus corresponding to the buffer where the abnormality occurs.

[0022] In a possible implementation of the third aspect above, if the status value indicates that the buffer state is an abnormal state, the transmission rate of the bus corresponding to the buffer where the abnormality occurs is adjusted, including: if the status value indicates that the current storage capacity of the first buffer is greater than or equal to the first threshold, the write rate of the first bus is reduced; if the status value indicates that the current storage capacity of the first buffer is less than or equal to the second threshold, the write rate of the first bus is increased; if the status value indicates that the current storage capacity of the second buffer is greater than or equal to the third threshold, the read rate of the second bus is increased; if the status value indicates that the current storage capacity of the second buffer is less than or equal to the fourth threshold, the read rate of the second bus is reduced.

[0023] In a possible implementation of the third aspect above, the method further includes: if the state value indicates that the buffer state is a normal state, acquiring a state of a power amplifier corresponding to the second chip from the second chip through a third bus.

[0024] In a possible implementation of the third aspect above, the method further includes: acquiring a status value from the second chip through the third bus at a preset second time interval.

[0025] In a fourth aspect, the present invention provides a chip, characterized in that the chip includes a processor and a data interface, and the processor reads instructions stored in a memory through the data interface to execute any of the above methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 According to some embodiments of the present invention, a schematic diagram of a chip of an electronic device is shown;

[0027] Figure 2 According to some embodiments of the present invention, a module schematic diagram of an electronic device is shown;

[0028] Figure 3 According to some embodiments of the present invention, a communication schematic diagram of an MCU and an FPGA is shown;

[0029] Figure 4 According to some embodiments of the present invention, a schematic diagram of a buffer zone is shown.

[0030] Figure 5 According to some embodiments of the present invention, a schematic diagram of an interrupt notification is shown;

[0031] Figure 6 According to some embodiments of the present invention, a schematic diagram of adjusting the rate is shown;

[0032] Figure 7 According to some embodiments of the present invention, another communication schematic diagram between an MCU and an FPGA is shown;

[0033] Figure 8 According to some embodiments of the present invention, a schematic diagram of steps of a data transmission method is shown;

[0034] Fig. 9 According to some embodiments of the present invention, a schematic diagram of steps of another data transmission method is shown. DETAILED DESCRIPTION

[0035] Illustrative embodiments of the present invention include, but are not limited to, a data transmission method, a chip, and an electronic device.

[0036] The following is combined with Figures 1 to 9 The technical solution of the present invention is introduced.

[0037] In some embodiments, a multi-channel audio processing circuit is generally implemented in an electronic device by configuring an MCU and an FPGA. For example, the electronic device can control the speaker of the electronic device to play audio and collect the recorded audio when the speaker plays audio through the multi-channel audio processing circuit. It can be understood that the electronic device of the present application can be any device with audio playback and recording functions, such as a mobile phone, a computer, etc., without specific limitation.

[0038] In order to more clearly explain the embodiments of the present application, the communication process between the MCU and the FPGA is illustrated below.

[0039] Exemplarily, the MCU is connected and communicated with the FPGA via multiple buses. For example, the MCU writes playback audio data to the FPGA via an external bus interface (EBI) bus, the MCU reads recording audio data from the FPGA via a serial peripheral interface (SPI) bus, and the MCU obtains PA status from the FPGA via an inter-integrated circuit (I2C) bus.

[0040] In some embodiments, since the MCU works in serial mode, that is, when the MCU is connected to the FPGA through multiple buses for communication, the MCU sequentially communicates with the FPGA through multiple buses in serial mode. For example, the MCU sequentially writes playback audio data to the FPGA, reads recording audio data from the FPGA, and obtains PA status from the FPGA through the EBI bus, SPI bus, and I2C bus in serial communication mode.

[0041] Exemplarily, the FPGA communicates with the PA through multiple channels. For example, the FPGA sends playback audio data to the PA through channel 1 to drive the speaker corresponding to the PA to play audio, and the FPGA receives the recording audio data collected by the PA when the speaker plays audio through channel 2.

[0042] In some embodiments, since the FPGA works in parallel, that is, when the FPGA is connected to the PA through multiple channels, the FPGA synchronously communicates with the PA through multiple channels in parallel. For example, the FPGA synchronously sends playback audio data to the PA and receives recording audio data collected by the PA through channel 1 and channel 2 in parallel communication.

[0043] In some embodiments, since the MCU works in serial mode and the FPGA works in parallel mode, how to coordinate the multiple buses between the FPGA and the MCU directly affects the communication efficiency between the FPGA and the MCU.

[0044] For example, the MCU writes the playback audio data to the buffer 01 of the FPGA through the EBI bus, and then the FPGA reads the playback audio data from the buffer 01 to drive the PA to control the speaker corresponding to the PA to play audio; further, the FPGA writes the recording audio data of the corresponding speaker playing audio collected by the PA into the buffer 02, and then the MCU reads the recording audio data from the buffer 02 of the FPGA through the SPI bus. It can be understood that in the aforementioned process, the FPGA is usually configured to have a fixed read rate to read the playback audio data from the buffer 01, and is configured to have a fixed write rate to write the recording audio data into the buffer 02; and, since the FPGA works in parallel, that is, the FPGA is configured to be able to synchronously execute the two steps of reading the playback audio data from the buffer 01 and writing the recording audio data into the buffer 02.

[0045] Furthermore, since the MCU works serially, that is, the MCU is configured to asynchronously execute the two steps of writing the playback audio data into the buffer 01 and reading the recording audio data from the buffer 02. However, if the writing rate of the MCU to write the playback audio data into the buffer 01 is too fast, the buffer 01 may be quickly filled up, causing data overflow, resulting in data loss, and then causing a playback error when the FPGA drives the speaker to play audio; or, if the writing rate of the MCU to write the playback audio data into the buffer 01 is too slow, the data in the buffer 02 may be quickly read out by the FPGA, resulting in data interruption, and then causing a playback error when the FPGA drives the speaker to play audio. Similarly, if the reading rate of the MCU to read the recording audio data from the buffer 02 is too fast, the data may be read out and cause data interruption; if the reading rate of the MCU to read the recording audio data from the buffer 02 is too slow, data overflow may occur, resulting in data loss, etc.

[0046] To this end, the present invention proposes a data transmission method, which increases the writing rate of the MCU into the buffer area 01 to write playback audio data when the buffer area 01 is in an empty state (such as a state that is about to be read empty), so as to avoid data interruption caused by reading empty data in the buffer area 01; when the buffer area 01 is in a full state (such as a state that is about to be written full), reduces the writing rate of the MCU into the buffer area 01 to write playback audio data, so as to avoid data loss caused by data overflow in the buffer area 01; when the buffer area 02 is in an empty state, reduces the reading rate of the MCU reading recording audio data from the buffer area 02, so as to avoid data interruption caused by reading empty data in the buffer area 02; when the buffer area 02 is in a full state, increases the reading rate of the MCU reading recording audio data from the buffer area 02, so as to avoid data loss caused by data overflow in the buffer area 02.

[0047] Figure 1 According to some embodiments of the present application, a schematic diagram of a chip of an electronic device is shown. Figure 1 As shown, the electronic device includes a first chip and a second chip, and the electronic device implements a multi-channel audio processing circuit by configuring the first chip and the second chip. For example, the first chip writes playback audio data to the second chip and reads recording audio data from the second chip, and the second chip drives the corresponding speaker to play audio based on the playback audio data and collects the recording audio data when the speaker plays audio. Exemplarily, the following uses MCU as an example of the first chip and FPGA as an example of the second chip to illustrate the embodiment of the present application.

[0048] In some embodiments, Figure 2 As shown, the MCU is correspondingly configured with a main state machine trigger module and a multi-bus execution module, and the FPGA is correspondingly configured with a slave state machine acquisition module and a state synchronization module. Exemplarily, the slave state machine acquisition module is used to acquire the buffer state in the FPGA and send the buffer state to the state synchronization module; the state synchronization module is used to send a state change notification to the main state machine trigger module when it detects that the buffer state has changed, for example, when it detects that the current state is different from the previous historical state; the main state machine trigger module is used to respond to the state change notification, acquire the buffer state from the state synchronization module and send the buffer state to the multi-bus execution module; the multi-bus execution module is used to adjust the write rate and / or read rate of the MCU based on the buffer state.

[0049] Combination Figure 1 and Figure 2 , Figure 3 According to some embodiments of the present application, a communication diagram of an MCU and an FPGA is shown. Figure 3As shown, at least three buses such as the first bus, the second bus and the third bus are deployed between the MCU and the FPGA, and a sending buffer and a receiving buffer are deployed in the MCU, and a first buffer and a second buffer are deployed in the FPGA. Among them, the MCU's sending buffer is pre-stored with playback audio data, and the MCU writes the playback audio data to the first buffer through the first bus; the MCU reads the recording audio data from the second buffer through the second bus, and stores the recording audio data in the receiving buffer; the MCU obtains FPGA information such as the first buffer state, the second buffer state, the PA state, etc. from the FPGA through the third bus. Exemplarily, the following uses the EBI bus as an example of the first bus, the SPI bus as an example of the second bus, and the I2C bus as an example of the third bus to illustrate the embodiments of the present application.

[0050] In some embodiments, three states are set for the first buffer according to the current storage capacity of the first buffer, which are marked as B1. For example, when the current storage capacity of the first buffer is greater than or equal to the first threshold, the first buffer is in a state of being almost full, that is, B1 is almost full; when the current storage capacity of the first buffer is less than or equal to the second threshold, the first buffer is in a state of being almost empty, that is, B1 is almost empty; when the current storage capacity of the first buffer is greater than the second threshold or less than the first threshold, the first buffer is in a normal state, that is, B1 is normal. Similarly, three states are set for the second buffer according to the current storage capacity of the second buffer, which are marked as B2. For example, when the current storage capacity of the second buffer is greater than or equal to the third threshold, the second buffer is in a state of being almost full, that is, B2 is almost full; when the current storage capacity of the second buffer is less than or equal to the fourth threshold, the second buffer is in a state of being almost empty, that is, B2 is almost empty; when the current storage capacity of the second buffer is greater than the fourth threshold or less than the third threshold, the second buffer is in a normal state, that is, B2 is normal.

[0051] Exemplarily, the first threshold value may be a capacity value of two-thirds of the total storage capacity corresponding to the first buffer, and the second threshold value may be a capacity value of one-third of the total storage capacity corresponding to the first buffer, that is, when the current storage capacity of the first buffer accounts for more than two-thirds of the total storage capacity, the state of the first buffer is B1 will be full; when the current storage capacity of the first buffer accounts for less than one-third of the total storage capacity, the state of the first buffer is B1 will be empty. Similarly, the third threshold value may be a capacity value of two-thirds of the total storage capacity corresponding to the second buffer, and the fourth threshold value may be a capacity value of one-third of the total storage capacity corresponding to the second buffer, that is, when the current storage capacity of the second buffer accounts for more than two-thirds of the total storage capacity, the state of the second buffer is B2 will be full; when the current storage capacity of the second buffer accounts for less than one-third of the total storage capacity, the state of the second buffer is B2 will be empty. It can be understood that the first threshold value is greater than the second threshold value, the third threshold value is greater than the fourth threshold value, and the first threshold value, the second threshold value, the third threshold value, and the fourth threshold value may also be other capacity values, without specific limitation.

[0052] In some embodiments, see Figure 3 As shown, the FPGA is configured as a slave state machine, and the state of the slave state machine is marked as Ss. Exemplarily, at least five states are configured for the slave state machine according to the states of the first buffer and the second buffer, for example: 0, 1, 2, 3, 4; wherein, among the five states of the slave state machine, state 0 corresponds to non-real-time information transmission, such as non-real-time information transmission used to indicate the state when B1 is normal and B2 is normal; state 1 corresponds to B1 being full; state 2 corresponds to B1 being empty; state 3 corresponds to B2 being full; and state 4 corresponds to B2 being empty. Further, the MCU is configured as a master state machine, and the state of the master state machine is marked as Sm. Exemplarily, the master state machine is configured with at least five states according to the state of the slave state machine, for example: 0, 1, 2, 3, and 4; wherein, among the five states of the master state machine, state 0 corresponds to state 0 of the slave state machine, i.e., non-real-time information transmission; state 1 corresponds to state 1 of the slave state machine, i.e., B1 will be full; state 2 corresponds to state 2 of the slave state machine, i.e., B1 will be empty; state 3 corresponds to state 3 of the slave state machine, i.e., B2 will be full; state 4 corresponds to state 4 of the slave state machine, i.e., B2 will be empty.

[0053] In some embodiments, the FPGA obtains the state of the slave state machine through the slave state machine acquisition module, such as state 0 (non-real-time information transmission), state 1 (B1 will be full), state 2 (B1 will be empty), state 3 (B2 will be full), and state 4 (B2 will be empty), and sends the obtained state of the slave state machine to the state synchronization module; when the FPGA detects a state change in the state of the slave state machine through the state synchronization module, for example, when it detects that the current state of the slave state machine is different from the previous historical state of the slave state machine, it sends a state change notification to the master state machine trigger module; the MCU responds to the state change notification through the master state machine trigger module, obtains the current state of the slave state machine from the state synchronization module through the I2C bus, updates the state of the master state machine based on the current state of the slave state machine, and sends the state of the master state machine to the multi-bus execution module; the MCU adjusts the write rate and / or read rate of the EBI bus and / or the SPI bus based on the state of the master state machine through the multi-bus execution module.

[0054] In some embodiments, the slave state machine acquisition module may be configured with a timer A, so that the FPGA can obtain the state of the slave state machine at a predetermined first time interval in the timer A without obtaining the state of the slave state machine in real time, thereby reducing the power consumption of the FPGA operation. Figure 4As shown, the slave state machine acquisition module periodically updates the state of the slave state machine according to the first time interval preset in the timer A, for example, the state of the slave state machine is updated periodically every 1ms, that is, Ss is updated periodically every 1ms, that is; when the state synchronization module detects that the current state Ss of the slave state machine is different from the previous historical state Sp of the slave state machine, that is, Ss!=Sp, at this time, the FPGA sends an interrupt notification to the MCU to notify the MCU to obtain the current state of the slave state machine.

[0055] Furthermore, if Figure 5 As shown, when the state of the slave state machine changes, the FPGA pulls up an I / O pin connected to the MCU to send a rising edge interrupt signal to the MCU. When the MCU receives the interrupt signal, the MCU obtains the current state of the slave state machine from the FPGA through the I2C bus. Subsequently, when the MCU obtains the current state of the slave state machine, the pulled-up I / O pin is restored. It can be understood that when the I / O pin is pulled high, the information sent by the FPGA to the MCU is the current state of the slave state machine, that is, Ss is sent. In some embodiments, when the I / O pin is restored, the information sent by the FPGA to the MCU is the state of PA, that is, the PA state is sent.

[0056] In some embodiments, the master state machine trigger module may be configured with a timer B, so that the MCU can actively and regularly obtain the state of the slave state machine according to the second time interval preset in the timer B, thereby improving the detection efficiency of the state of the slave state machine. For example, the master state machine trigger module can actively and regularly obtain the state of the slave state machine according to the second time interval preset in the timer B to update the state of the master state machine, for example, obtaining the state of the slave state machine through the I2C bus at a time of 10ms.

[0057] In some embodiments, when the state of the slave state machine obtained by the master state machine trigger module regularly or through an interrupt signal is 0, the state of the master state machine is updated to 0. At this time, the MCU obtains the state of the PA from the FPGA through the I2C bus.

[0058] In other embodiments, when the state of the slave state machine obtained by the master state machine trigger module periodically or through an interrupt signal is 1 / 2 / 3 / 4, the state of the master state machine is updated to 1 / 2 / 3 / 4, and the state of the master state machine is sent to the multi-bus execution module, and the multi-bus execution module adjusts the write rate and / or read rate of the EBI bus and / or SPI bus based on the state of the master state machine. It can be understood that when the state of the master state machine is 0, the multi-bus execution module is marked as Ex==0, and when the state of the master state machine is 1 / 2 / 3 / 4, the multi-bus execution module is marked as Ex==1 in response to the information sent by the master state machine trigger module.

[0059] In some embodiments, Figure 6 As shown, if the current state of the master state machine is state 0, that is, non-real-time information transmission, the multi-bus execution module is marked as Ex==0, and the MCU obtains the state of PA from the FPGA through the I2C bus; if the current state of the master state machine changes to state 1 / 2 / 3 / 4, the multi-bus execution module is marked as Ex==1, and the multi-bus execution module adjusts the write rate and / or read rate of the EBI bus and / or SPI bus based on the current state of the master state machine. For example, if the state of the master state machine is state 1, that is, B1 will be full, the write rate of the EBI bus is reduced; if the current state of the slave state machine is state 2, that is, B1 will be empty, the write rate of the EBI bus is increased; if the current state of the slave state machine is state 3, that is, B2 will be full, the read rate of the SPI bus is increased; if the current state of the slave state machine is state 4, B2 will be empty, and the read rate of the SPI bus is reduced.

[0060] In some embodiments, when a state of one of the first buffer and the second buffer changes and changes to a nearly empty or nearly full state, the multi-bus execution module may adjust the corresponding bus based on the current state of the buffer whose state changes. For example, if the first buffer changes to a nearly empty state, that is, the current state of the first buffer is a nearly empty state, the multi-bus execution module increases the write rate of the EBI bus.

[0061] In other embodiments, when both the first buffer and the second buffer undergo state changes and the changes become the nearly empty and / or nearly full states, the multi-bus execution module may adjust the corresponding buses in sequence based on the current states of the multiple buffers that undergo state changes. For example, if the first buffer and the second buffer simultaneously change into the nearly empty state, that is, the current states of the first buffer and the second buffer are both nearly empty states, the multi-bus execution module may first increase the write rate of the EBI bus and then reduce the read rate of the SPI bus; or first reduce the read rate of the SPI bus and then increase the write rate of the EBI bus, and the adjustment order is not specifically limited.

[0062] It can be understood that by using the slave state machine to periodically obtain the states of the first buffer and the second buffer from the FPGA and synchronize them to the master state machine, according to the state of the master state machine, the multi-bus execution module decides to continue reading the state of the PA, or adjusts the write rate and / or read rate of the EBI bus and / or the SPI bus, so that the cache data in the first buffer and the second buffer in the FPGA will not be read out quickly and affect the subsequent data reading and interruption, or the cache data will not be written full quickly and affect the subsequent data loss due to data overflow, so as to always keep the data volume in the first buffer and the second buffer in the FPGA at a suitable level. At the same time, the I2C bus can be fully utilized in the spare time to read other non-real-time information as much as possible, such as the state of the PA, so as to ensure that the device can fully utilize the spare time of the low-speed bus to obtain other non-important data information while giving priority to ensuring that important data meets the transmission requirements on the high-speed bus, so as to achieve the purpose of improving the communication and transmission capabilities of the device.

[0063] In some embodiments, in combination Figures 1 to 6 ,like Figure 7 As shown, the first bus can be a high-speed bus, the MCU uses the EBI bus to connect to the Advanced eXtensible Interface (AXI-Lite) of the FPGA, and the transmission rate of the first bus can be set to high (H), medium (M) and low (L) three speeds, such as 10MHz, 20Mhz and 40MHz, and the first bus is referred to as the EBI bus below; the second bus can be a high-speed bus, the MCU uses the SPI bus to connect to the SPI bus of the FPGA, and the transmission rate of the second bus can be set to high (H), medium (M) and low (L) three speeds, such as 15MHz, 25MHz and 50MHz, and the second bus is referred to as the SPI bus below; the third bus can be a low-speed bus, the MCU uses the I2C bus to connect to the I2C bus of the FPGA, and the third bus is referred to as the I2C bus below. The total storage capacity of the first buffer can be 30kBytes, and the total storage capacity of the second buffer can be 20kBytes. It is understandable that the first bus / the second bus may also have other faster or slower transmission rates, and the first buffer / the second buffer may also have other larger or smaller total storage capacities, without specific limitation.

[0064] In some embodiments, the write rate and / or read rate of the EBI bus and / or the SPI bus may be adjusted by, for example, adjusting from H to M in adjacent gears, or by adjusting from L to H in non-adjacent gears, without limitation. Further, after adjusting the write rate and / or read rate of the EBI bus and / or the SPI bus, a test may be performed.

[0065] For example, if the current state of the slave state machine is state 2, that is, B1 will be empty, and the current write rate of the EBI bus is 10MHz, then the current write rate of the EBI bus is adjusted to 20MHz. Subsequently, the MCU transmits a verification frame L1 data, such as 0x112233445566778899aabbccddeeff, to the FPGA through the EBI bus, and reads the L1 data from the first buffer through the I2C bus, verifies and compares, if the same, the bus speed setting is increased to take effect, otherwise the previous level speed is restored. Or for example, if the current state of the slave state machine is state 4, B2 will be empty, and the current read rate of the SPI bus is 25MHz, then the current write rate of the EBI bus is adjusted to 15MHz. Subsequently, the MCU transmits a verification frame L2 data, such as 0x112233445566778899aabbccddeeff, to the FPGA through the SPI bus, and reads the L2 data from the second buffer through the I2C bus, verifies and compares, if the same, the bus speed setting is reduced to take effect, otherwise the previous level speed is restored.

[0066] In some embodiments, when the write rate and / or read rate of the EBI bus and / or SPI bus needs to be reduced or increased, if the current speed of the write rate and / or read rate of the EBI bus and / or SPI bus is the lowest rate or the highest rate, the write rate and / or read rate of the EBI bus and / or SPI bus is not adjusted.

[0067] Figure 8 According to some embodiments of the present application, a flowchart of a data transmission method is shown. Figure 8 As shown, the process includes but is not limited to the following steps:

[0068] S11: The second chip sends a status change notification to the first chip based on detecting that a status change occurs in at least one of the first buffer and the second buffer.

[0069] In some embodiments, the first chip and the second chip are deployed in an electronic device. Figures 1 to 3As shown, MCU is an example of the first chip, and FPGA is an example of the second chip. Exemplarily, MCU writes the playback audio data to the first buffer of FPGA through the first bus such as EBI bus, and FPGA reads the playback audio data from the first buffer area to drive PA to control the speaker to play audio; at the same time, FPGA writes the recording audio data collected by PA when the corresponding speaker plays audio into the second buffer area, and MCU reads the recording audio data from the second buffer area of ​​FPGA through the second bus such as SPI bus. Among them, the recording audio data is the recording data of the audio playback data, EBI bus and SPI bus are high-speed buses, MCU communicates with FPGA in serial mode, and FPGA communicates with PA in parallel mode.

[0070] In some embodiments, for example Figure 4 and Figure 5 As shown, the FPGA detects the state of the first buffer and / or the second buffer at a first time interval of, for example, 1ms and determines a state value based on the detection result, for example: 0, 1, 2, 3, 4; if the FPGA detects that the state value is different from the previous state value, it determines that the state of the first buffer and / or the second buffer has changed, and sends a state change notification to the MCU by way of an interrupt signal. Figure 5 As shown, the FPGA sends a rising edge interrupt signal to the MCU by pulling up an I / O pin connected to the MCU.

[0071] S12: In response to the status change notification, the first chip obtains a status value indicating a buffer status of the second chip.

[0072] In some embodiments, for example Figure 5 As shown, in response to the state change notification, the MCU obtains the state value from the FPGA through a third bus such as the I2C bus; then, after the MCU obtains the state value, the pulled-up I / O pin is restored. The I2C bus is a low-speed bus.

[0073] In some other embodiments, the MCU may also actively obtain the status value from the FPGA via a third bus such as an I2C bus at a second time interval such as 10 ms.

[0074] S13: If the state value indicates that the buffer state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the buffer where the abnormality occurs.

[0075] In some embodiments, if the status value is any one of 1, 2, 3, and 4, the status value indicates that the buffer status is an abnormal status.

[0076] Exemplarily, if the state value is 1, the state value indicates that the current storage capacity of the first buffer is greater than or equal to the first threshold, and the write rate of the first bus is reduced. Figure 6 As shown, if the status value indicates that the current storage capacity of the first buffer is greater than or equal to the first threshold, that is, the current state of the first buffer is almost full, the write rate of the first bus is reduced, that is, the write rate of the MCU writing the playback audio data to the first buffer through the EBI bus is reduced to avoid data loss due to data overflow in the first buffer.

[0077] Exemplarily, if the state value is 2, the state value indicates that the current storage capacity of the first buffer is less than or equal to the second threshold value, and the write rate of the first bus is increased. Figure 6 As shown, if the status value indicates that the current storage capacity of the first buffer is less than or equal to the second threshold, that is, the current state of the first buffer is empty, the write rate of the first bus is increased, that is, the write rate of the MCU writing the playback audio data to the first buffer through the EBI bus is increased to avoid data interruption caused by reading empty playback audio data in the buffer.

[0078] For example, if the state value is 3, the state value indicates that the current storage capacity of the second buffer is greater than or equal to the third threshold value, and the read rate of the second bus is increased. Figure 6 As shown, if the status value indicates that the current storage capacity of the second buffer is greater than or equal to the third threshold, that is, the current state of the second buffer is almost full, the read rate of the second bus is increased, that is, the read rate of the recorded audio data read by the MCU from the second buffer through the SPI bus is increased to avoid data loss due to data overflow in the second buffer.

[0079] Exemplarily, if the state value is 4, the state value indicates that the current storage capacity of the second buffer is less than or equal to the fourth threshold value, and the read rate of the second bus is reduced. Figure 6 As shown, if the status value indicates that the current storage capacity of the second buffer is less than or equal to the fourth threshold value, that is, the current state of the second buffer is empty, the read rate of the second bus is reduced, that is, the read rate of the recorded audio data read by the MCU from the second buffer through the SPI bus is reduced to avoid data interruption caused by empty data in the second buffer.

[0080] In other embodiments, if the status value is 0, the status value indicates that the current storage capacity of the first buffer is greater than the second threshold or less than the first threshold, and indicates that the current storage capacity of the second buffer is greater than the fourth threshold or less than the third threshold, that is, the buffer status is normal, and the MCU obtains the status of the PA from the FPGA through the I2C bus.

[0081] It can be understood that in the above data transmission method, the appropriate speed range and the appropriate buffer size of two high-speed buses such as the EBI bus and the SPI bus are selected, and the transmission speed of the two buses is adjusted according to the state of the buffer data of the first buffer and the second buffer, so as to achieve dynamic adjustment to keep the buffer data always within a reasonable range. In this way, there will be no interruption of playback and recording due to insufficient received or sent data, and there will be no playback and recording skipping due to buffer data overflow and data loss. While ensuring normal playback and recording, the status of the PA can also be read regularly for real-time monitoring, which optimizes the mutual coordination of the buses and improves the performance of the equipment.

[0082] In some embodiments, the MCU can use M487 with a main frequency of 192MHz; the MCU cooperates with the FPGA to achieve real-time monitoring of the PA status at 100Hz while the MCU's 16-channel 48kHz audio is playing and recording in real time, optimizing the bus dynamic adjustment speed, and significantly improving the utilization rate of the equipment, which not only ensures smooth playback and recording, but also fully utilizes the equipment performance.

[0083] Fig. 9 According to some embodiments of the present application, a flowchart of another data transmission method is shown. It can be understood that Fig. 9 The execution subject of each step of the process shown is the first chip. Fig. 9 The execution entities of each step will not be described repeatedly in the steps of the process shown. Fig. 9 As shown, the process includes but is not limited to the following steps:

[0084] S21: In response to the state change notification sent by the second chip, obtain a state value used to represent the buffer state of the second chip.

[0085] The state change notification is used to indicate that a state change occurs in at least one of the first buffer and the second buffer.

[0086] In some embodiments, for example Figure 5 As shown, the MCU (as an example of the first chip) obtains the state value from the FPGA (as an example of the second chip) through a third bus such as an I2C bus in response to the state change notification.

[0087] In some other embodiments, the MCU may also actively obtain the status value from the FPGA via a third bus such as an I2C bus at a second time interval such as 10 ms.

[0088] The specific process of step S21 can refer to the process of controlling the first chip to execute the data transmission method in step S12 above, which will not be repeated here.

[0089] S22: If the state value indicates that the buffer state is an abnormal state, adjust the transmission rate of the bus corresponding to the buffer where the abnormality occurs.

[0090] The specific process of step S22 can refer to the process of controlling the first chip to execute the data transmission method in step S13 above, which will not be repeated here.

[0091] In some embodiments, the present invention further provides an electronic device. Figure 1 As shown, the electronic device includes a first chip and a second chip, and the electronic device implements a multi-channel audio processing circuit by configuring the first chip and the second chip. The second chip includes a first buffer and a second buffer, and the first chip writes data to the first buffer through a first bus and reads data from the second buffer through a second bus.

[0092] In some embodiments, the second chip is used to send a status change notification to the first chip based on detecting that at least one of the first buffer and the second buffer has a status change; the first chip is used to obtain a status value representing the buffer status of the second chip in response to the status change notification; the first chip is also used to adjust the transmission rate of the bus corresponding to the buffer where the abnormality occurs if the status value indicates that the buffer status is an abnormal state. For details, please refer to the description of the aforementioned steps S11 to S13, which will not be repeated here.

[0093] In some embodiments, the present invention further provides a chip, the chip includes a processor and a data interface, the processor reads instructions stored in the memory through the data interface to execute the following steps: Figure 8 The method steps shown, or the execution as Fig. 9 The method steps are shown.

[0094] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0095] It should be noted that the units / modules mentioned in the various device embodiments of the present invention are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present invention. In addition, in order to highlight the innovative part of the present invention, the above-mentioned device embodiments of the present invention do not introduce units / modules that are not closely related to solving the technical problems proposed by the present invention, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0096] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0097] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention.

Claims

1. A data transmission method, applied to electronic equipment, characterized in that: The electronic device includes a first chip and a second chip, the second chip includes a first buffer and a second buffer, the first chip writes data to the first buffer through a first bus, and reads data from the second buffer through a second bus, wherein the method includes: The second chip sends a status change notification to the first chip based on detecting that a status change occurs in at least one of the first buffer and the second buffer; In response to the state change notification, the first chip acquires a state value representing a buffer state of the second chip; If the state value indicates that the buffer state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the buffer where the abnormality occurs.

2. The method according to claim 1, characterized in that If the state value indicates that the buffer state is an abnormal state, the first chip adjusts the transmission rate of the bus corresponding to the buffer where the abnormality occurs, including: If the state value indicates that the current storage capacity of the first buffer is greater than or equal to a first threshold, reducing the write rate of the first bus; If the state value indicates that the current storage capacity of the first buffer is less than or equal to a second threshold, increasing the write rate of the first bus; If the state value indicates that the current storage capacity of the second buffer is greater than or equal to a third threshold, increasing the read rate of the second bus; If the status value indicates that the current storage capacity of the second buffer is less than or equal to a fourth threshold, the read rate of the second bus is reduced.

3. The method according to claim 1, characterized in that The second chip sending a state change notification to the first chip includes: The second chip sends a status change notification to the first chip in a manner of sending an interrupt signal.

4. The method according to claim 1, characterized in that: The first chip acquires a status value indicating a buffer status of the second chip, including: The first chip obtains the state value from the second chip through a third bus.

5. The method according to claim 1, characterized in that The method further comprises: The first chip detects the states of the first buffer and the second buffer at a preset first time interval.

6. The method according to claim 5, characterized in that The method further comprises: The first chip determines the state value based on a detection result of the detection, and sends the state change notification to the first chip when the state value is different from a previous state value.

7. The method according to claim 1, characterized in that The method further comprises: The first chip obtains the state value from the second chip through the third bus at a preset second time interval.

8. The method according to claim 1, characterized in that The first chip communicates with the second chip in a serial manner.

9. The method according to claim 1, characterized in that: The method further comprises: The second chip outputs the data in the first buffer to a power amplifier to drive the power amplifier; The second chip writes the data collected by the power amplifier into the second buffer.

10. The method according to claim 9, characterized in that The data in the first buffer includes audio playback data, and the data in the second buffer includes recorded audio data, wherein the recorded audio data is recorded data of the audio playback data.

11. The method according to claim 9, characterized in that The second chip communicates with the power amplifier in a parallel manner.

12. The method according to claim 9, characterized in that The method further comprises: If the status value indicates that the buffer state is a normal state, the first chip obtains the state of the power amplifier from the second chip through a third bus.

13. The method according to any one of claims 1 to 12, characterized in that: The first chip at least includes a micro control unit; the second chip at least includes a field programmable gate array, the first bus at least includes an external bus interface bus, and the second bus at least includes a serial peripheral interface bus.

14. The method according to claim 1, characterized in that The first chip includes a main state machine trigger module and a multi-bus execution module, and the second chip includes a slave state machine acquisition module and a state synchronization module; The second chip detects the states of the first buffer and the second buffer through the module for acquiring the state from the state machine, and sends the detection result of the detection to the state synchronization module; The second chip determines the state value based on the detection result through the state synchronization module and sends the state change notification to the main state machine trigger module when the state value is different from the previous state value; The first chip, through the main state machine trigger module, responds to the state change notification, obtains the state value from the state synchronization module, and sends the state value to the multi-bus execution module; The first chip adjusts the transmission rate of the corresponding bus based on the state value through the multi-bus execution module.

15. An electronic device, characterized in that: The invention comprises a first chip and a second chip, wherein the second chip comprises a first buffer and a second buffer, the first chip writes data to the first buffer through a first bus, and reads data from the second buffer through a second bus, wherein: The second chip is used for sending a state change notification to the first chip based on detecting that a state change occurs in at least one of the first buffer and the second buffer; The first chip is used for acquiring a state value representing a buffer state of the second chip in response to the state change notification; The first chip is further configured to adjust a transmission rate of a bus corresponding to the buffer where the abnormality occurs if the status value indicates that the buffer is in an abnormal state.

16. A data transmission method, applied to a first chip, characterized in that: The first chip writes data to a first buffer of the second chip through a first bus, and reads data from a second buffer of the second chip through a second bus, wherein the method includes: In response to a state change notification sent by the second chip, acquiring a state value used to represent a buffer state of the second chip, wherein the state change notification is used to represent that a state change occurs in at least one of the first buffer and the second buffer; If the state value indicates that the buffer state is an abnormal state, the transmission rate of the bus corresponding to the buffer where the abnormality occurs is adjusted.

17. The method according to claim 16, characterized in that If the state value indicates that the buffer state is an abnormal state, adjusting the transmission rate of the bus corresponding to the buffer where the abnormality occurs includes: If the state value indicates that the current storage capacity of the first buffer is greater than or equal to a first threshold, reducing the write rate of the first bus; If the state value indicates that the current storage capacity of the first buffer is less than or equal to a second threshold, increasing the write rate of the first bus; If the state value indicates that the current storage capacity of the second buffer is greater than or equal to a third threshold, increasing the read rate of the second bus; If the status value indicates that the current storage capacity of the second buffer is less than or equal to a fourth threshold, the read rate of the second bus is reduced.

18. The method according to claim 16, characterized in that The method further comprises: If the status value indicates that the buffer state is a normal state, the state of the power amplifier corresponding to the second chip is obtained from the second chip through the third bus.

19. The method according to claim 16, characterized in that The method further comprises: According to a preset second time interval, the state value is obtained from the second chip through the third bus.

20. A chip, characterized in that: The chip includes a processor and a data interface, and the processor reads instructions stored in a memory through the data interface to execute the method as claimed in any one of claims 1 to 13, or executes the method as claimed in any one of claims 15 to 19.

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