Monolithic 3D integrated circuit layout method, device, equipment and medium

Abstract

The invention discloses a monolithic 3D integrated circuit layout method, device and equipment and a medium, relates to the technical field of layout and wiring, and aims to solve the problem that the total length of layout connecting lines of an existing 3D integrated circuit is too long. The method comprises the steps of obtaining unit information of a to-be-arranged integrated circuit; determining a first root unit and a to-be-distributed unit; for any unit in the to-be-distributed units, determining the area of the current first circuit layer and the area of the current second circuit layer according to the unit width and the unit height, and determining the circuit layer with the small area as a target circuit layer of the to-be-distributed unit; based on the connection information and the port coordinates, determining the position of the to-be-allocated unit in the target circuit layer as a target position when the total length of the connection lines of the 3D integrated circuit is shortest; and determining the target circuit layers and the target positions of the remaining units in sequence to complete the 3D integrated circuit layout. The monolithic 3D integrated circuit layout method provided by the invention is used for shortening the total length of connecting lines of the 3D integrated circuit and improving the performance of the 3D integrated circuit.

Description

Technical Field

[0001] The present invention relates to the field of layout and wiring technology, and in particular to a monolithic 3D integrated circuit layout method, device, equipment and medium. Background Art

[0002] 3D integrated circuit, also known as stereoscopic integrated circuit or three-dimensional integrated circuit, is a technology that vertically stacks multiple layers of chips and interconnects them through tiny through-holes.

[0003] The existing 3D integrated circuit layout usually converts the 2D circuit netlist into a hypergraph, and then calculates the weight of the hypergraph. Each unit and line length takes a value, and then sorts the line lengths from long to short. If the line length is greater than the via between the upper and lower circuits in the monolithic 3D, it is split, and the split units are placed in a new circuit layer to obtain a new hypergraph, which is then converted into a 3D netlist. Since the division between units is based only on the line length of the unit, if a hyperedge connects multiple hyperedges, it is easy to increase the total length of the connection when cutting based on the above.

[0004] Therefore, there is an urgent need for a monolithic 3D integrated circuit layout method, device, equipment and medium. Summary of the invention

[0005] The object of the present invention is to provide a monolithic 3D integrated circuit layout method, device, equipment and medium for reducing the total area of ​​the 3D integrated circuit and the total connection length.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a monolithic 3D integrated circuit layout method, comprising:

[0008] Obtaining unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0009] Determine a first root unit and a unit to be allocated according to the connection information; the first root unit is a unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0010] For any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0011] Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position;

[0012] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0013] Compared with the prior art, the present invention provides a monolithic 3D integrated circuit layout method, comprising obtaining unit information of each unit of the integrated circuit to be laid out; determining a first root unit and a unit to be allocated according to connection information; for any unit in the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with a smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in the 3D integrated circuit; based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection of the 3D integrated circuit is the shortest as the target position; and determining the target circuit layers and target positions of the remaining units in turn to complete the 3D integrated circuit layout. The present invention can effectively reduce the total length of the connection of the 3D integrated circuit by first determining the root unit, allocating the units connected to the root unit, and then allocating other units. When allocating, each time it is allocated to the circuit layer with a small area, the area size of the two circuit layers of the 3D integrated circuit finally obtained is similar, and the preset conditions are met, which can effectively reduce the area of ​​the formed 3D integrated circuit. In addition, each time the position with the smallest total length of the connection is determined as the target position, which can also shorten the total length of the connection of the 3D integrated circuit. The present invention can directly generate a 3D integrated circuit layout based on the unit information, without converting it into a 2D circuit, and the method is simple.

[0014] Optionally, for any one of the units to be allocated, determining the area of ​​the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with a smaller area as the target circuit layer for placing the unit to be allocated, includes:

[0015] For a first target cell among the cells to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the cell width and the cell height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated;

[0016] For the second target unit in the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the units to be allocated are determined.

[0017] Optionally, determining, based on the connection information and the port coordinates, a position of the to-be-allocated unit in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position comprises:

[0018] The preset position of the unit to be allocated is determined according to the position of the laid out unit in the target circuit layer; the laid out unit is all the units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the laid out unit, and the preset position contacts one side of the laid out unit.

[0019] Calculate the total length of the connection corresponding to each preset position according to the port coordinates and connection information;

[0020] The preset position corresponding to the minimum total length of the connection line is determined as the target position.

[0021] Optionally, calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information includes:

[0022] Determine a first port and a second port connected to each other according to the connection information;

[0023] Based on the first and second ports, the formula is:

[0024] H=|X1-X2|+|Y1-Y2

[0025] Calculate the length of the connection between the first port and the second port;

[0026] Wherein, H is the length of the connection line between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port;

[0027] The total length of the wires is determined as the sum of the lengths of all wires.

[0028] Optionally, the first circuit layer is located below the second circuit layer; and before the method of determining the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the units to be allocated, and determining the circuit layer with a smaller area as the target circuit layer for placing the unit to be allocated further comprises:

[0029] The first root cell is placed in a first circuit layer.

[0030] Optionally, the integrated circuit to be laid out includes a plurality of root cells; and sequentially determining target circuit layers and target positions of remaining cells includes:

[0031] Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out except the first root unit;

[0032] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0033] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0034] Optionally, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0035] In a second aspect, the present invention provides a monolithic 3D integrated circuit layout device, comprising:

[0036] A unit information acquisition module, used to acquire unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0037] A first root unit and to-be-allocated unit determination module, configured to determine a first root unit and to-be-allocated units according to the connection information; the first root unit is a unit with the largest number of connected units; the to-be-allocated units are multiple units connected to the first root unit;

[0038] a target circuit layer determination module, for determining the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the cells to be allocated, and determining the circuit layer with a smaller area as the target circuit layer for placing the cell to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0039] a target position determination module, configured to determine, based on the connection information and the port coordinates, a position of the unit to be allocated in the target circuit layer when the total length of the connection of the 3D integrated circuit is the shortest as a target position;

[0040] The loop module is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

[0041] In a third aspect, the present invention provides a monolithic 3D integrated circuit layout device, comprising:

[0042] A communication unit / communication interface, used to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0043] A processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is a unit having the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0044] For any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0045] Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position;

[0046] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0047] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, the monolithic 3D integrated circuit layout method is implemented.

[0048] The technical effects achieved by the device type solution provided in the second aspect, the equipment type solution provided in the third aspect, and the computer-readable storage medium solution provided in the fourth aspect are the same as those of the method type solution provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1 It is a connection diagram before segmentation in the prior art;

[0051] Figure 2 It is a schematic diagram of the connection after segmentation in the prior art;

[0052] Figure 3 A flow chart of a monolithic 3D integrated circuit layout method provided by the present invention;

[0053] Figure 4 A flow chart of the minimum width arrangement algorithm provided by the present invention;

[0054] Figure 5 A schematic diagram of a 3D integrated circuit structure after placing the inv2 unit and the inv3_1 unit provided by the present invention;

[0055] Figure 6 A schematic diagram of a 3D integrated circuit structure after placing the inv3_2 unit provided by the present invention;

[0056] Figure 7 A schematic diagram of a 3D integrated circuit structure after placing the inv8_1 unit provided by the present invention;

[0057] Figure 8 A schematic diagram of a first preset position of the inv8_2 unit provided by the present invention;

[0058] Fig. 9 A schematic diagram of a second preset position of the inv8_2 unit provided by the present invention;

[0059] Fig.10 A schematic diagram of a first preset position of a PG unit provided by the present invention;

[0060] Fig.11 A schematic diagram of a second preset position of the PG unit provided by the present invention;

[0061] Fig.12 A schematic diagram of a third preset position of the PG unit provided by the present invention;

[0062] Fig.13 A schematic diagram of the structure of a monolithic 3D integrated circuit layout device provided by the present invention;

[0063] Fig.14 A schematic structural diagram of a monolithic 3D integrated circuit layout device provided by the present invention. DETAILED DESCRIPTION

[0064] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0065] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0066] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0067] See also Figure 1 and Figure 2 In the prior art, when dividing units, the cutting is only based on the line length of the unit. If a hyperedge connects multiple hyperedges, the following situation is likely to occur: there are four hyperedges A, B, C, and D, and B is connected to A, C, and D. The existing layout method is to cut off the connection between A and B and move B to the top of A. At this time, the length of the connection between B and A is shortened, but the length of the connection between B and C, and B and D will be increased.

[0068] To solve the above problems, the present invention provides a monolithic 3D integrated circuit layout method, device, equipment and medium, such as Figure 3 As shown, the minimum width arrangement algorithm is used, the root unit is first determined, and then the units connected to the root unit are arranged in order from small to large according to the value of the unit width, the upper and lower layer areas are compared, and the units are placed in the layer with a small area, and the units are placed at the position corresponding to the minimum value of the connection length, and then it is determined whether the units connected to the root unit are arranged. If not, the remaining units connected to the root unit are arranged. If they are arranged, it is determined whether all units are arranged. If they are arranged, it ends. If they are not arranged, the remaining units are allocated. The present invention can convert unit information into 3D integrated circuit layout, shorten the total length of the connection, and reduce the area. The following is a detailed description.

[0069] Figure 4 A flow chart of a monolithic 3D integrated circuit layout method provided by the present invention, such as Figure 3As shown, a monolithic 3D integrated circuit layout method includes the following steps:

[0070] Step S1: obtaining unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0071] The unit is a component in a 3D integrated circuit. The port coordinates are the coordinates of the port in this unit. The origin of the coordinate system of this unit is located at the vertex of the lower right corner of the unit. The unit width side is the horizontal axis, and the unit height side is the vertical axis. The connection information includes the unit connected to this unit, and the corresponding relationship between the ports connected to each other of the two connected units. The unit height of all units is the same. If there are multiple rows in the circuit layer, the height of each row is the unit height.

[0072] Step S2: determining the first root unit and the unit to be allocated according to the connection information;

[0073] The first root unit is a unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0074] Before step S3, the first root unit is placed in the first circuit layer. At this time, the area of ​​the first circuit layer is the area of ​​the root unit. Since the first circuit layer and the second circuit layer are empty at the beginning, there is no need to determine the target position of the root unit in the first circuit layer.

[0075] Step S3: for any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with a smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in the 3D integrated circuit;

[0076] As an optional method, step S3 can be implemented by the following steps:

[0077] Step S31: for the first target cell among the cells to be allocated, determine the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height, and determine the circuit layer with the smaller area as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated;

[0078] As an alternative, use the formula:

[0079] S=max(w1,w2,w3...w i )×(i×h)

[0080] Calculate the area of ​​the first circuit layer or the second circuit layer; where S is the area of ​​the first circuit layer or the area of ​​the second circuit layer, w i is the cell width of the i-th cell, i is the total number of cells in the first circuit layer or the total number of cells in the second circuit layer, h is the cell height, max(w1,w2,w3...w i ) is the cell width with the largest value among all cell widths.

[0081] For example, if the first circuit layer has three rows of cells, the cell height of each cell is 8 mm, the height of each row of cells is the cell height, the cell width of the first row of cells is 11 mm, the width of the second row of cells is 9 mm, and the width of the third row of cells is 13 mm, the total cell height of the first circuit layer is 3×8 mm=24 mm, and the area of ​​the first circuit layer is 13 mm×24 mm=312 mm. 2 .

[0082] Step S32: For the second target unit in the unit to be allocated, determine the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determine the circuit layer with a smaller area as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width in the unit to be allocated except the first target unit; until the target circuit layers of all units in the unit to be allocated are determined.

[0083] It is understandable that the sequence numbers of the above steps are only for explaining the steps and do not limit the order of the steps, that is, step S32 is not executed immediately after the target circuit layer of the first target unit is determined.

[0084] Step S4: based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection of the 3D integrated circuit is the shortest as the target position;

[0085] As an optional method, step S4 may include:

[0086] Step S41: determining the preset position of the unit to be allocated according to the position of the laid-out unit in the target circuit layer;

[0087] The laid out cells are all cells in the target circuit layer whose target positions have been determined; the preset positions are arranged along the circumference of the laid out cells, and the preset positions are in contact with one side of the laid out cells; or the preset positions partially overlap with the cells in the laid out cells. It should be noted that "the preset position is in contact with one side of the laid out cells" means that when the laid out cells are placed horizontally, the preset position is in contact with any side of the laid out cells, and the side is a surface composed of the width side or height side and thickness of the laid out cells. The preset position is the position where the unit to be allocated can be placed, and "the preset position partially overlaps with the cells in the laid out cells" means that the unit to be allocated can be placed at the position where the laid out cells have been laid out. If the position satisfies the shortest total length of the connection, the unit to be allocated is placed at the position, and then the laid out cells originally located at the position are moved to a position in contact with the side of the unit to be allocated.

[0088] Step S42: Calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information;

[0089] Step S43: determining the preset position corresponding to the minimum total length of the connection line as the target position.

[0090] As an optional manner, the above step S42 may include:

[0091] Determine a first port and a second port connected to each other according to the connection information;

[0092] According to the first port and the second port, the port coordinates of the first port are converted into the coordinates of the first port in the 3D integrated circuit coordinate system, and the port coordinates of the second port are converted into the coordinates of the second port in the 3D integrated circuit coordinate system. Based on the coordinates of the first port in the 3D integrated circuit coordinate system and the coordinates of the second port in the 3D integrated circuit coordinate system, a semi-perimeter model is used to calculate the connection length between the first port and the second port, as shown in formula (1):

[0093] H=|X1-X2|+|Y1-Y2|(1)

[0094] Wherein, H is the length of the connection between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port; it should be understood that the target horizontal coordinate of the first port is the horizontal coordinate of the first port in the entire 3D integrated circuit coordinate system, the target horizontal coordinate of the second port is the horizontal coordinate of the second port in the entire 3D integrated circuit coordinate system, the target vertical coordinate of the first port is the vertical coordinate of the first port in the entire 3D integrated circuit coordinate system, and the target vertical coordinate of the second port is the vertical coordinate of the second port in the entire 3D integrated circuit coordinate system, that is, X1, X2, Y1 and Y2 are all values ​​in the same coordinate system.

[0095] The total length of the wires is determined as the sum of the lengths of all wires.

[0096] Step S5: sequentially determine the target circuit layers and target positions of the remaining units to complete the 3D integrated circuit layout.

[0097] As an optional manner, the integrated circuit to be laid out includes a plurality of root cells; and sequentially determining the target circuit layers and target positions of the remaining cells includes:

[0098] Determine a second root unit among the remaining unallocated units; the second root unit is the unit with the largest number of connected units except the first root unit;

[0099] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0100] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0101] As an optional manner, when the remaining unallocated units include multiple second root units with the same number of connected units, the unit with the smallest unit width among the multiple second root units is first used as the currently determined root unit for unit allocation.

[0102] As another optional method, the integrated circuit to be laid out includes only one root unit. After the root unit and the units connected to the root unit are allocated, the target circuit layer and target position of the remaining units not connected to the root unit are determined until all the units are allocated and the layout of the 3D integrated circuit is output.

[0103] First determine whether the cells connected to the root are arranged: Check whether the cells connected to the root are arranged. If there are omissions, it will affect the entire circuit. If the cells connected to the root are arranged, continue the process to the next step to check whether all cells are arranged. If not, jump to step S3.

[0104] Then determine whether all the cells have been arranged. In a circuit, one root can rarely connect all the cells. Therefore, after arranging the cells connected to the root, it is necessary to check whether there are other unarranged cells. If all the cells have been arranged, the whole process ends. If not, jump to step S2 to continue the process.

[0105] Exemplarily, the integrated circuit to be laid out includes only one root unit: for example, the integrated circuit to be laid out includes only the root unit and the units connected to the root unit; or the number of units connected to the remaining units not connected to the root unit is the same.

[0106] As an optional manner, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0107] Through the above steps, it can be known that the present invention first determines the root unit, and then arranges the units connected to the root in order of unit width from small to large, first allocates the unit with the smallest unit width, and then determines the smallest unit except the unit with the smallest unit width, that is, allocates the unit with the smallest unit width each time, and allocates the root unit and the unit connected to the root unit before allocating other units. Such an allocation order can effectively reduce the total length of the connection of the 3D integrated circuit, and when allocating, each time it is allocated to the circuit layer with a small area, and the area size of the two circuit layers of the 3D integrated circuit finally obtained is similar, which meets the preset conditions and can effectively reduce the area of ​​the formed 3D integrated circuit. In addition, each time the position with the smallest total length of the connection is determined as the target position, which can also shorten the total length of the connection of the 3D integrated circuit. The present invention can directly generate a 3D integrated circuit layout based on the unit information, without the need to convert it into a 2D circuit, and the method is simple.

[0108] The technical solution of the present invention is described in detail below by way of examples.

[0109] The integrated circuit to be laid out is an SRAM circuit, including three sizes of inverters, inv2, inv3, and inv8, and a PG transmission gate. The unit information is as follows: the unit heights of inv2, inv3, inv8, and PG are consistent, and the unit height is 11.88, in μm.

[0110] inv2: width 9.755, in(1.06, 5.35), out(8.925, 6.595)

[0111] inv3: width 11.09, in(1.42, 5.375), out(10.18, 5.835)

[0112] inv8: width 25.36, in(1.145, 5.645), out(23.59, 5.555)

[0113] PG: width 41.28, P1 (40.37, 5.89), P2 (1.3, 5.89)

[0114] The integrated circuit to be laid out includes 2 inv3s: inv3_1 and inv3_2, 2 inv8s: inv8_1 and inv8_2, and 1 PG. The number of cells connected to inv3_1 is the largest, including the three cells: inv2, inv3_2, and inv8_1.

[0115] In this example, the number of rows of cells in the circuit layer is limited, and each circuit layer can only arrange components in one row, so the preset positions are only the left and right sides of any cell in the laid-out cells.

[0116] It should be noted that the coordinates in the above brackets are the coordinates of the port in this unit, the horizontal coordinate is the width value of the port in this unit, the vertical coordinate is the height value of the port in this unit, and the coordinate origin is the vertex at the lower right corner of the unit.

[0117] Step 1: Place inv3_1 in the first circuit layer of the lower layer. The area of ​​the second circuit layer is 0, the area of ​​the first circuit layer is 11.09*11.88, and place inv2 in the second circuit layer. Figure 5 As shown, the layer where inv2 is located is the second circuit layer, and the layer where inv3_1 is located is the first circuit layer. What needs to be understood is Figure 5 This is just a schematic diagram, and it is arranged in this way to facilitate the display of the connection length. Since the vertical line connecting two points is the shortest, the length of the connection between inv2 and inv3_1 is: inv2-inv3_1=(6.595-5.375)+1=2.22

[0118] Step 2: Place inv3_2. The area of ​​the second circuit layer is 9.755*11.88<the area of ​​the first circuit layer is 11.09*11.88, so place inv3_2 on the second circuit layer. Figure 6 As shown, placing inv3_2 on the left side of inv2 can ensure the shortest total length of the connection. The length of the connection between inv3_1 and inv3_2 is: inv3_1-inv3_2=(10.18-1.42)+(9.755-8.925)+1.42+1=7.51.

[0119] Step 3: Place inv8_1. The area of ​​the second circuit layer is (9.755+11.09)*11.88> the area of ​​the first circuit layer is 11.09*11.88. Place inv8_1 on the first circuit layer. Figure 7As shown, since the out ports of inv8_1 and inv3_1 are connected, when inv8_1 is placed close to the out port of inv3_1, the total length of the connection is the shortest, and the length of the connection between inv3_1 and inv8_1 is: inv3_1-inv8_1=(11.09-10.18+1.145)+|5.835-5.645|=2.245.

[0120] The arrangement is completed with inv3_1 as the root, and inv8_2 and PG are left. Since the number of connection units of inv3_2 and inv8_2 is 2, the unit width of inv3_2 is smaller than the unit width of inv8_1, inv8_2 is arranged with inv3_2 as the root.

[0121] Step 4: Place inv8_2. The area of ​​the second circuit layer is (9.755+11.09)*11.88<the area of ​​the first circuit layer is (11.09+25.36)*11.88. Place inv8_2 on the second circuit layer. There are two locations where it can be placed. Figure 8 and Fig. 9 The dotted line position in Figure 8 The length of the line at the position in is: inv3_1-inv3_2=7.51

[0122] inv3_2-inv8_2=(11.09-10.18)+(25.36-1.145)+(5.835-5.645)=25.315

[0123] Fig. 9 The length of the line connecting the positions in is:

[0124] inv3_1-inv3_2=(1.42+25.36+(9.755-8.925))-(10.18-1.42)+1=19.85

[0125] inv3_2-inv8_2=10.18+1.145+|5.835-5.645|=11.515

[0126] Since: 7.51+25.315>19.85+11.515, Fig. 9 The length of the line connecting the positions in is less than Figure 8 The length of the connection at the position in the Fig. 9 At the dotted line position in .

[0127] Step 5: Place PG. The area of ​​the second circuit layer (11.09+9.755+25.36)*11.88> the area of ​​the first circuit layer (25.36+11.09)*11.88. Place PG in the first circuit layer. There are three positions for placement, such as Figure 10-12 As shown by the dotted line in .

[0128] in, Fig.10 The length of the line connecting the positions in is:

[0129] inv8_1-PG=(25.36-23.59)+1.3+|5.555-5.89|=3.405

[0130] inv8_2-PG=(40.37+25.36+11.09-1.42)-((9.755-8.925)+(25.36-23.59))+|5.555-5.89|+1=74.135

[0131] Fig.11 The length of the line connecting the positions in is:

[0132] inv8_1-PG=(23.59+11.09+41.28-1.3)+|5.555-5.89|=74.995

[0133] inv8_2-PG=(25.36-23.59)+(9.755-8.925)+1.42+(41.28-40.37)+|5.555-5.89|+1=6.265

[0134] Because: 3.405+74.134<74.995+6.265, Fig.10 The total length of the line corresponding to the position in is less than Fig.11 The total length of the lines at the locations in .

[0135] Fig.12 The length of the line connecting the positions in is:

[0136] inv8_1-inv3_1=(1.145+41.28+(11.09-10.18))+|5.645-5.835|=43.67

[0137] inv8_1-PG=(23.59+(41.28-1.3))+|5.89-5.555|=63.905

[0138] inv8_2-PG=(40.37+(11.09-1.42))-((25.36-23.59)+(9.755-8.925))

[0139] +|5.89-5.555|+1=48.775

[0140] Since: 74.135+3.405+2.245<43.67+63.905+48.775, therefore, Fig.10 The position in is the target placement position of the PG.

[0141] Minimum width arrangement total length = 2.22 + 2.245 + 19.85 + 11.515 + 3.405 + 74.134 = 113.369

[0142] The 3D layout SRAM circuit obtained by the above method is about 45% smaller in area than the 2D layout. In terms of performance, the write 0 time and write 1 time are both shortened by about half compared with the 2D SRAM circuit.

[0143] The embodiment of the present invention can divide the functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present invention is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0144] In the case of dividing each functional module into corresponding functional modules, Fig.13 The schematic diagram of the structure of a monolithic 3D integrated circuit layout device provided by the present invention. Fig.13 As shown, the device comprises:

[0145] The unit information acquisition module 111 is used to acquire unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0146] A first root unit and to-be-allocated unit determination module 112 is configured to determine a first root unit and to-be-allocated units according to the connection information; the first root unit is a unit with the largest number of connected units; the to-be-allocated units are multiple units connected to the first root unit;

[0147] The target circuit layer determination module 113 is used to determine the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the cells to be allocated, and determine the circuit layer with a smaller area as the target circuit layer for placing the cell to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in the 3D integrated circuit;

[0148] A target position determination module 114 is used to determine the position of the unit to be allocated in the target circuit layer when the total length of the connection of the 3D integrated circuit is the shortest as the target position based on the connection information and the port coordinates;

[0149] The loop module 115 is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

[0150] Optionally, the target circuit layer determination module 113 may include:

[0151] A target circuit layer determination unit for a first target unit is used to determine the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for a first target unit in the units to be allocated, and determine the circuit layer with a smaller area as the target circuit layer for placing the first target unit; the first target unit is the unit with the smallest cell width in the units to be allocated;

[0152] The target circuit layer determination unit of the next target unit is used to determine the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height for the second target unit in the unit to be allocated, and determine the circuit layer with a smaller area as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the units to be allocated are determined.

[0153] Optionally, the target location determination module 114 may include:

[0154] A preset position determination unit is used to determine the preset position of the unit to be allocated according to the position of the laid out unit in the target circuit layer; the laid out unit is all the units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the laid out unit, and the preset position is in contact with one side of the laid out unit; or the preset position partially overlaps with the unit in the laid out unit.

[0155] A total length calculation unit for calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information;

[0156] The target position determination unit is used to determine the preset position corresponding to the minimum total length of the connection line as the target position.

[0157] Optionally, the total line length calculation unit may be specifically used for:

[0158] Determine a first port and a second port connected to each other according to the connection information;

[0159] Based on the first and second ports, the formula is:

[0160] H=|X1-X2|+|Y1-Y2

[0161] Calculate the length of the connection between the first port and the second port;

[0162] Wherein, H is the length of the connection line between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port;

[0163] The total length of the wires is determined as the sum of the lengths of all wires.

[0164] Optionally, the first circuit layer is located below the second circuit layer; the device also includes a first root unit placement unit, which is used to place the first root unit in the first circuit layer.

[0165] Optionally, the integrated circuit to be laid out includes a plurality of root units; the loop module 115 may be used to:

[0166] Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out except the first root unit;

[0167] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0168] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0169] Optionally, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0170] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between various modules. It can be understood that in order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of various functions. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0171] In the case of using the corresponding integrated unit, Fig.14 The present invention provides a schematic diagram of the structure of a single-chip 3D integrated circuit layout device. Fig.14 As shown, the device includes:

[0172] A communication unit / communication interface, used to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0173] A processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is a unit having the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0174] For any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0175] Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position;

[0176] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0177] like Fig.14 As shown, the processor may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. The communication interface may be one or more. The communication interface may use any transceiver-like device for communicating with other devices or communication networks.

[0178] like Fig.14 As shown, the terminal device may further include a communication line. The communication line may include a path to transmit information between the components.

[0179] Optional, such as Fig.14 As shown, the terminal device may further include a memory. The memory is used to store computer-executable instructions for executing the solution of the present invention, and the execution is controlled by the processor. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0180] like Fig.14 As shown, the memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor through a communication line. The memory may also be integrated with the processor.

[0181] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0182] In a specific implementation, as an example, Fig.14 As shown, the processor may include one or more CPUs, such as Fig.14 CPU0 and CPU1 in.

[0183] In a specific implementation, as an example, Fig.14 As shown, the terminal device may include multiple processors, such as Fig.14 Each of these processors can be a single-core processor or a multi-core processor.

[0184] On the one hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed, the above-mentioned monolithic 3D integrated circuit layout method is implemented.

[0185] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present invention is executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD).

[0186] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0187] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A monolithic 3D integrated circuit layout method, characterized in that: include: Obtaining unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; Determine a first root unit and a unit to be allocated according to the connection information; the first root unit is a unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit; For any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit; Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position; The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

2. The monolithic 3D integrated circuit layout method according to claim 1, characterized in that: The method of determining the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the cells to be allocated, and determining the circuit layer with a smaller area as the target circuit layer for placing the cell to be allocated, comprises: For a first target cell among the cells to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the cell width and the cell height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated; For the second target unit in the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the units to be allocated are determined.

3. The monolithic 3D integrated circuit layout method according to claim 1, characterized in that: The step of determining, based on the connection information and the port coordinates, the position of the to-be-allocated unit in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position comprises: The preset position of the unit to be allocated is determined according to the position of the laid out unit in the target circuit layer; the laid out unit is all the units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the laid out unit, and the preset position contacts one side of the laid out unit. Calculate the total length of the connection corresponding to each preset position according to the port coordinates and connection information; The preset position corresponding to the minimum total length of the connection line is determined as the target position.

4. The monolithic 3D integrated circuit layout method according to claim 3, characterized in that: Calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information includes: Determine a first port and a second port connected to each other according to the connection information; Based on the first and second ports, the formula is: H=|X1-X2|+|Y1-Y2 Calculate the length of the connection between the first port and the second port; Wherein, H is the length of the connection line between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port; The total length of the wires is determined as the sum of the lengths of all wires.

5. The monolithic 3D integrated circuit layout method according to claim 4, characterized in that: The first circuit layer is located below the second circuit layer; and before the step of determining the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the units to be allocated, and determining the circuit layer with a smaller area as the target circuit layer for placing the unit to be allocated, the step further includes: The first root cell is placed in a first circuit layer.

6. The monolithic 3D integrated circuit layout method according to claim 3, characterized in that: The integrated circuit to be laid out includes a plurality of root cells; and sequentially determining the target circuit layers and target positions of the remaining cells includes: Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out except the first root unit; sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit; Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

7. A monolithic 3D integrated circuit layout method, characterized in that: When the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

8. A monolithic 3D integrated circuit layout device, characterized in that: include: A unit information acquisition module, used to acquire unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; A first root unit and to-be-allocated unit determination module, configured to determine a first root unit and to-be-allocated units according to the connection information; the first root unit is a unit with the largest number of connected units; the to-be-allocated units are multiple units connected to the first root unit; a target circuit layer determination module, for determining the areas of the current first circuit layer and the second circuit layer according to the cell width and the cell height for any one of the cells to be allocated, and determining the circuit layer with a smaller area as the target circuit layer for placing the cell to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit; a target position determination module, configured to determine, based on the connection information and the port coordinates, a position of the unit to be allocated in the target circuit layer when the total length of the connection of the 3D integrated circuit is the shortest as a target position; The loop module is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

9. A monolithic 3D integrated circuit layout device, characterized in that: include: A communication unit / communication interface, used to obtain unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; A processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is a unit having the largest number of connected units; the units to be allocated are multiple units connected to the first root unit; For any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with a smaller area is determined as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit; Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position; The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed, the monolithic 3D integrated circuit layout method according to any one of claims 1 to 7 is implemented.

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