Accelerator apparatus and method of controlling accelerator apparatus

Abstract

An accelerator device includes an interface circuit that communicates with an external device, a memory that stores first data received through the interface circuit, a polarization encoder that performs polarization encoding on the first data provided from the memory and outputs a result of the polarization encoding as second data, and an accelerator core that loads the second data. The first data is compressed weight data, the second data is decompressed weight data, the accelerator core is configured to perform machine learning-based reasoning based on the second data, and a length of the first data is variable.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to electronic devices, and more particularly, to accelerator devices and methods of controlling accelerator devices. Background Art

[0002] A computing device is an electronic device that can execute various applications based on an operating system. A computing device may include a central processing unit, an application processor, etc. as a main processor that executes an operating system and applications.

[0003] As the types of tasks performed in computing devices become more diverse, accelerator devices configured to support a main processor may be added to the computing device. For example, the accelerator device may include an image processor, a graphics processor, etc. The accelerator device may be implemented in a separate semiconductor package independent of the main processor, or the accelerator device and the main processor may be implemented as different cores in the same semiconductor package.

[0004] As a task performed in a computing device, machine learning-based reasoning can be added. Machine learning-based reasoning requires multiple parallel operations and can be performed by using a graphics processor that supports parallel operations. However, because the graphics processor is not a processor designed for machine learning, the graphics processor may have limitations in supporting machine learning. Summary of the invention

[0005] Embodiments of the present disclosure provide an accelerator device that supports machine learning-based inference while improving operation speed and reducing power consumption, and a method of controlling the accelerator device.

[0006] According to some example embodiments, an accelerator device includes: an interface circuit that communicates with an external device; a memory that stores first data received through the interface circuit; and a polarization encoder that performs polarization encoding on the first data provided from the memory and outputs a result of the polarization encoding as second data; and an accelerator core that loads the second data. The first data is compressed weight data, the second data is decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the length of the first data is variable.

[0007] According to some example embodiments, an accelerator device includes: an interface circuit that communicates with an external device; a memory that stores first data received through the interface circuit; a polarization encoder that performs polarization encoding on the first data provided from the memory and outputs a result of the polarization encoding as second data; and an accelerator core that loads the second data. The first data is compressed weight data, the second data is decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the length of the second data is variable.

[0008] According to some example embodiments, a method of controlling an accelerator device including a polar encoder and an accelerator core includes: inputting first data to the polar encoder; performing polar encoding on the first data at the polar encoder to generate second data; loading the second data into the accelerator core; and performing machine learning-based reasoning based on the second data at the accelerator core. The first data is compressed weight data, the second data is decompressed weight data, and a length of one of the first data and the second data is variable. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0010] Figure 1 An accelerator device according to some example embodiments of the present disclosure is shown.

[0011] Figure 2 An operating method of a variable length polar encoder according to some example embodiments of the present disclosure is shown.

[0012] Figure 3 A first example of an operating method of a variable length polar encoder according to some example embodiments of the present disclosure is shown.

[0013] Figure 4 A variable length polar encoder according to a first embodiment of the present disclosure is shown.

[0014] Figure 5 An operating method of a variable length polar encoder according to some example embodiments of the present disclosure is shown.

[0015] FIG. 6A to FIG. 6D An example of the process of processing data blocks in the buffer, parser, and input generator is shown.

[0016] 7A to 7D Another example of the process of processing data blocks in the buffer, parser, and input generator is shown.

[0017] Figure 8 Weight data according to some example embodiments of the present disclosure are shown.

[0018] Fig. 9 is a block diagram illustrating an electronic device according to some example embodiments of the present disclosure.

[0019] Fig.10 is a diagram illustrating a first example of an operating method of an electronic device according to some example embodiments of the present disclosure.

[0020] Fig.11A and Fig. 11BAn example of a process in which an electronic device performs compression and decompression while changing the number of frozen bits is shown.

[0021] Fig.12 A second example of an operating method of a variable length polar encoder according to some example embodiments of the present disclosure is shown.

[0022] Fig.13 A variable length polar encoder according to a second embodiment of the present disclosure is shown.

[0023] Fig.14 is a diagram illustrating a second example of an operating method of an electronic device according to some example embodiments of the present disclosure.

[0024] Fig.15A and Fig. 15B An example of a process in which an electronic device performs compression and decompression while changing the number of frozen bits is shown.

[0025] Fig.16 Another example of an operating method of an electronic device according to some example embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0026] Hereinafter, exemplary embodiments of the present disclosure will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the present disclosure.

[0027] Figure 1 An accelerator device 100 according to some example embodiments of the present disclosure is shown. Figure 1 , the accelerator device 100 may include an interface circuit 110 , a memory 120 , a variable-length polar encoder 130 , and an accelerator core 140 .

[0028] The interface circuit 110 may communicate with an external device. For example, the interface circuit 110 may communicate with an external host processor such as a central processing unit or an external memory such as a main memory of a central processing unit. The interface circuit 110 may provide data transmitted from an external device to the memory 120. The interface circuit 110 may provide data stored in the memory 120 to the external device.

[0029] For example, the interface circuit 110 may receive compressed weight data for machine learning-based reasoning or input data for machine learning-based reasoning from an external device, and may store the received data in the memory 120. The interface circuit 110 may provide the result of the machine learning-based reasoning stored in the memory 120 to the external device.

[0030] The memory 120 may store data transmitted from the interface circuit 110. The memory 120 may provide the stored data to the accelerator core 140 through the first path P1, or may provide the stored data to the variable length polar encoder 130 through the second path P2. The memory 120 may store data transmitted from the accelerator core 140. The memory 120 may provide the stored data to the interface circuit 110.

[0031] For example, the memory 120 may provide input data for machine learning-based reasoning to the accelerator core 140 through the first path P1. The memory 120 may provide compressed weight data CWD for machine learning-based reasoning to the variable-length polar encoder 130 through the second path P2. The memory 120 may receive and store machine learning-based reasoning results from the accelerator core 140 through the first path P1.

[0032] In some example embodiments, the memory 120 may be implemented together with a memory controller (not shown). The memory controller may provide a channel between the memory 120 and components (e.g., the interface circuit 110, the variable length polar encoder 130, and the accelerator core 140). In some example embodiments, the memory 120 may include a dynamic random access memory (DRAM), a static RAM (SRAM), a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a flash memory, etc.

[0033] The variable length polar encoder 130 may receive the compressed weight data CWD from the memory 120 . The variable length polar encoder 130 may generate the weight data WD by decompressing the compressed weight data CWD. The variable length polar encoder 130 may provide the weight data WD to the accelerator core 140 .

[0034] In some example embodiments, one of the compressed weight data CWD and the weight data WD may have a variable length. Since one of the compressed weight data CWD and the weight data WD has a variable length, it can be ensured that the weight data WD has no defects (or no errors). For example, the variable length may indicate that the size (e.g., the number of bits) of the data is variable, and may indicate that the size (e.g., the number of bits) of the valid information included in the data is variable.

[0035] The accelerator core 140 may receive weight data WD from the variable length polar encoder 130. The accelerator core 140 may load (or update) a machine learning based reasoning model (or module) by loading the weight data WD. The accelerator core 140 may receive input data based on machine learning from the memory 120. The accelerator core 140 may perform inference based on machine learning based on the input data and the weight data WD. The accelerator core 140 may store the inference result based on machine learning in the memory 120.

[0036] The variable length polar encoder 130 can generate the weight data WD by decompressing the compressed weight data CWD with reduced complexity. Therefore, the power and time required to decompress the compressed weight data CWD can be reduced. In addition, by receiving the compressed weight data CWD through the interface circuit 110 and storing the compressed weight data CWD in the memory 120 when ensuring that the weight data WD has no defects, the power and time required to use the interface circuit 110 and the memory 120 can be reduced.

[0037] For example, according to some example embodiments, based on the above methods, the speed, accuracy and / or power efficiency of communication and operation of the device can be improved. Therefore, the improved device and method overcome the shortcomings of traditional devices and methods using weight data through neural networks, artificial intelligence, etc., while reducing resource consumption and complexity, improving data accuracy, speeding up operation, and improving data clarity.

[0038] Figure 2 The operating method of the accelerator device 100 according to some example embodiments of the present disclosure is shown. Figure 1 and Figure 2 In operation S110, the accelerator device 100 may receive compressed weight data CWD. For example, the accelerator device 100 may sequentially receive first data blocks corresponding to a bandwidth (e.g., a communication bandwidth) of the interface circuit 110 in synchronization with a communication frequency of an external device. The compressed weight data CWD may be included in one of the first data blocks, or may be distributed and included in two or more first data blocks.

[0039] In operation S120, the accelerator device 100 may store the compressed weight data CWD received through the interface circuit 110 in the memory 120. For example, the accelerator device 100 may store the first data block including the compressed weight data CWD in the memory 120.

[0040] In operation S130, the accelerator device 100 may read the compressed weight data CWD from the memory 120. For example, the accelerator device 100 may sequentially receive second data blocks corresponding to a bandwidth (e.g., a communication bandwidth) of the memory 120 in synchronization with a communication frequency of the memory 120. The compressed weight data CWD may be included in one of the second data blocks, or may be distributed and included in two or more second data blocks.

[0041] In operation S140, the accelerator device 100 may perform decompression based on the variable length. For example, the variable length polar encoder 130 of the accelerator device 100 may perform decompression by detecting the variable length of the compressed weight data CWD or the weight data WD included in the second data block and performing polar encoding based on the detected variable length.

[0042] In operation S150, the accelerator device 100 may load the decompressed weight data WD into the accelerator core 140. Thereafter, based on the loaded weight data WD or a machine learning-based reasoning model (or module) corresponding to the weight data WD, the accelerator core 140 may perform machine learning-based reasoning on input data received from an external device through the interface circuit 110, the memory 120, and the first path P1.

[0043] Figure 3 A first example of a method of operation of the variable length polar encoder 130 according to some example embodiments of the present disclosure is shown. Figure 1 and Figure 3 In operation S210, the variable length polar encoder 130 may read a data block corresponding to the bandwidth. For example, the variable length polar encoder 130 may read a data block corresponding to the communication bandwidth of the memory 120 (for example, referring to Figure 2 The second data block described).

[0044] In operation S220, the variable length polar encoder 130 may extract length information. For example, the variable length polar encoder 130 may extract length information at a given position of the read data block. Alternatively, the variable length polar encoder 130 may extract length information at a given position of the data buffered in the variable length polar encoder 130. The length information may indicate the length of the compressed weight data. For example, the given position may mean a given number of leading bits of the data block or the buffered data.

[0045] When the length information does not exist at a given position of the read data block or buffered data, the variable-length polar encoder 130 may omit the extraction of the length information. For example, when the length information extracted from the previous data block is still valid (for example, when the entire compression weight data corresponding to the length information has not been collected), the length information may not exist at a given position of the current data block or buffered data.

[0046] In operation S230, the variable length polar encoder 130 may collect the compression weight data CWD corresponding to the length information. For example, the compression weight data CWD corresponding to the length information may be collected from one data block, or may be collected from two or more data blocks.

[0047] When the compressed weight data CWD corresponding to the length information is collected, the variable length polar encoder 130 may perform decompression by performing polar encoding in operation S240. When performing decompression, the variable length polar encoder 130 may discard the length information and may update the length information by extracting the next length information. In addition, when performing decompression, the variable length polar encoder 130 may output the weight data WD.

[0048] Figure 4 FIG. 2 shows a variable length polar encoder 200 according to a first embodiment of the present disclosure. In some example embodiments, the variable length polar encoder 200 may correspond to Figure 1 A variable length polar encoder 130 is provided.

[0049] refer to Figure 1 and Figure 4 , the variable length polar encoder 200 may include a preprocessor 210 and an encoding core 220. The preprocessor 210 may sequentially receive data blocks DC from the memory 120. At least one data block DC may include variable length compressed weight data CWD_V. The preprocessor 210 may convert the variable length compressed weight data CWD_V included in the data block DC into fixed length compressed weight data CWD_F. For example, the length of the fixed length compressed weight data CWD_F may correspond to the encoding unit of the encoding core 220.

[0050] The preprocessor 210 may include a buffer 211, a parser 213, and an input generator 215. The buffer 211 may store the data block DC. The buffer 211 may output the stored data as first buffered data BD1.

[0051] The parser 213 may receive the first buffered data BD1 from the buffer 211. The parser 213 may extract the length information LI from the first buffered data BD1. For example, the parser 213 may extract the length information LI from a given position of the first buffered data BD1, for example, extract the length information LI from a given number of leading bits of the first buffered data BD1. The parser 213 may generate the second buffered data BD2 excluding the length information LI from the first buffered data BD1. The parser 213 may output the length information LI and the second buffered data BD2 to the input generator 215.

[0052] The input generator 215 can extract the variable-length compressed weight data CWD_V from the second buffer data BD2 based on the length information LI. The input generator 215 can generate the fixed-length compressed weight data CWD_F from the variable-length compressed weight data CWD_V. For example, the input generator 215 can generate the fixed-length compressed weight data CWD_F by filling the variable-length compressed weight data CWD_V with bits having a given value or an arbitrary value.

[0053] The input generator 215 may store the remaining data RD of the second buffered data BD2 again in the buffer 211, the remaining data RD not corresponding to the variable length compressed weight data CWD_V. For example, the remaining data RD may correspond to the variable length compressed weight data CWD_V as the next polar encoding target.

[0054] The encoding core 220 may receive the compressed weight data CWD_F of fixed length from the preprocessor 210. The encoding core 220 may perform decompression by performing polar encoding on the compressed weight data CWD_F of fixed length. The encoding core 220 may output the weight data WD_F of fixed length as the decompression result. For example, the weight data WD_F of fixed length may correspond to the weight data WD transmitted from the variable length polar encoder 130 to the accelerator core 140.

[0055] Figure 5 An operating method of the variable length polar encoder 200 according to some example embodiments of the present disclosure is shown. Figure 5 An example of a method of operation of the input generator 215 of the variable length polar encoder 200 is shown in FIG.

[0056] Reference Figure 4 and Figure 5 , in operation S310 , the input generator 215 may receive the second buffered data BD2 .

[0057] In operation S320, the input generator 215 may determine whether data corresponding to the length information LI is collected. When data corresponding to the length information LI is not collected, in operation S330, the input generator 215 may further include second buffer data BD2 in operation S310, in which the second buffer data BD2 is stored. When data corresponding to the length information LI is collected, that is, when the amount of data is greater than or equal to the length information LI, operation S340 is performed.

[0058] In operation S340, the input generator 215 may output compressed weight data. For example, the input generator 215 may identify data corresponding to the length information LI as compressed weight data CWD_V of variable length. The input generator 215 may generate compressed weight data CWD_F of fixed length by padding a given bit or an arbitrary bit to the compressed weight data CWD_V of variable length. The input generator 215 may output compressed weight data CWD_F of fixed length.

[0059] In operation S350, the input generator 215 may determine whether the remaining data RD exists. When the remaining data RD exists, in operation S360, the input generator 215 may store the remaining data RD in the buffer 211. Thereafter, operation S370 is performed. When the remaining data RD does not exist, operation S370 is performed.

[0060] In operation S370, it may be determined whether the decompression is completed. When the decompression is not completed, in operation S310, the input generator 215 may receive the second buffered data BD2. When the decompression is completed, the input generator 215 may end the process.

[0061] FIG. 6A to FIG. 6D 2 shows an example of the process of processing a data block in buffer 211, parser 213 and input generator 215. In some example embodiments, FIG. 6A to FIG. 6D An example in which the size of a data block is smaller than the size of the variable-length compression weight data CWD_V is shown.

[0062] Reference Fig. 6A , the first data block DC1, the second data block DC2, and the third data block DC3 may be sequentially input to the buffer 211. The first data block DC1 may include the first length information LI1 and the 1a-th compressed weight data CWD1a. The second data block DC2 may include the 1b-th compressed weight data CWD1b, the second length information LI2, and the 2a-th compressed weight data CWD2a. The third data block DC3 may include the 2b-th compressed weight data CWD2b, the third length information LI3, and the 3a-th compressed weight data CWD3a.

[0063] The 1ath and 1bth compressed weight data CWD1a and CWD1b may correspond to one variable-length compressed weight data CWD_V. The first length information LI1 may indicate the total length of the 1ath and 1bth compressed weight data CWD1a and CWD1b, and may indicate, for example, "9".

[0064] The 2ath and 2bth compressed weight data CWD2a and CWD2b may correspond to one variable-length compressed weight data CWD_V. The second length information LI2 may indicate the total length of the 2ath and 2bth compressed weight data CWD2a and CWD2b, and may indicate, for example, "6".

[0065] The 3a compressed weight data CWD3a may correspond to a variable length compressed weight data CWD_V and any other compressed weight data (e.g., the 3b compressed weight data). The third length information LI3 may indicate the total length of the 3a compressed weight data CWD3a and other compressed weight data, and may indicate, for example, "7".

[0066] Reference Figure 6B In operation S411 , the buffer 211 may receive the first data block DC1 and may store the first data block DC1 as first buffered data BD1 . The buffer 211 may output the first buffered data BD1 to the parser 213 .

[0067] In operation S412, the parser 213 may extract the first length information LI1 from a given position of the first buffered data BD1, for example, extract the first length information LI1 from a given number of leading bits of the first buffered data BD1. The parser 213 may remove the first length information LI1 from the first buffered data BD1 to generate the second buffered data BD2. The parser 213 may output the first length information LI1 and the second buffered data BD2 to the input generator 215.

[0068] In operation S413 , the input generator 215 may receive second buffered data BD2 including the first length information LI1 and the 1a-th compressed weight data CWD1a . Since all data corresponding to the first length information LI1 are not collected, the input generator 215 may not output the compressed weight data CWD_F having a fixed length.

[0069] Reference Figure 6C In operation S421 , the buffer 211 may receive the second data block DC2 and may store the second data block DC2 as the first buffered data BD1 . The buffer 211 may output the first buffered data BD1 to the parser 213 .

[0070] In operation S422, the parser 213 may determine whether the length information exists at a given position of the first buffered data BD1, for example, a given number of leading bits of the first buffered data BD1. Since the length information does not exist at the given position of the first buffered data BD1, the parser 213 may output the received data as the second buffered data BD2 to the input generator 215. The parser 213 may omit the output of the length information.

[0071] In operation S423, the input generator 215 may receive the second buffered data BD2. The input generator 215 may collect data corresponding to the first length information LI1 based on data previously stored in the input generator 215 and the second buffered data BD2.

[0072] In operation S424, the input generator 215 may output the 1ath compressed weight data CWD1a and the 1bth compressed weight data CWD1b corresponding to the first length information LI1 as the compressed weight data CWD_F with a fixed length. For example, when the length "9" indicated by the first length information LI1 corresponds to a fixed length, the input generator 215 may output the compressed weight data CWD_V with a variable length, which includes the 1ath compressed weight data CWD1a and the 1bth compressed weight data CWD1b, as the compressed weight data CWD_F with a fixed length without padding.

[0073] In operation S425 , the input generator 215 may store the second length information LI2 and the 2a-th compressed weight data CWD2 a in the buffer 211 again as the residual data RD.

[0074] Reference Fig.6D In operation S431, the buffer 211 may receive and store the third data block DC3. The buffer 211 may output the second length information LI2 and the 2a-th compressed weight data CWD2a constituting the remaining data RD of the second data block DC2 and the 2b-th compressed weight data CWD2b, the third length information LI3 and the 3a-th compressed weight data CWD3a of the third data block DC3 as the first buffered data BD1 to the parser 213.

[0075] In operation S432, the parser 213 may extract the second length information LI2 from a given position of the first buffered data BD1, for example, extract the second length information LI2 from a given number of leading bits of the first buffered data BD1. The parser 213 may remove the second length information LI2 from the first buffered data BD1 to generate the second buffered data BD2. The parser 213 may output the second length information LI2 and the second buffered data BD2 to the input generator 215.

[0076] In operation S433, the input generator 215 may receive the second buffer data BD2. The input generator 215 may collect data corresponding to the second length information LI2 based on the second buffer data BD2.

[0077] In operation S434, the input generator 215 may output the compressed weight data CWD_F of a fixed length obtained by adding the padding data PD to the 2a-th compressed weight data CWD2a and the 2b-th compressed weight data CWD2b corresponding to the second length information LI2. For example, the padding data PD may have a given value or an arbitrary value. The length of the padding data PD may be different from that of the encoding core 220 (refer to Figure 4 ) corresponds to the difference between the length of the coding unit and the length of the variable-length compression weight data CWD_V.

[0078] In operation S435 , the input generator 215 may store the third length information LI3 and the third compression weight data CWD3 a in the buffer 211 again as the residual data RD.

[0079] 7A to 7D Another example of the process of processing a data block in the buffer 211, the parser 213, and the input generator 215 is shown. 7A to 7D An example is shown in which the size of the data block is larger than the size of the variable-length compression weight data CWD_V.

[0080] Reference Fig. 7A , the fourth data block DC4, the fifth data block DC5, and the sixth data block DC6 may be sequentially input to the buffer 211. The fourth data block DC4 may include fourth length information LI4, fourth compression weight data CWD4, fifth length information LI5, and 5a-th compression weight data CWD5a. The fifth data block DC5 may include 5b-th compression weight data CWD5b, sixth length information LI6, and 6a-th compression weight data CWD6a. The sixth data block DC6 may include 6b-th compression weight data CWD6b, seventh length information LI7, and seventh compression weight data CWD7.

[0081] The fourth compression weight data CWD4 may correspond to one variable-length compression weight data CWD_V. The fourth length information LI4 may indicate the total length of the fourth compression weight data CWD4, and may indicate, for example, "3".

[0082] The 5ath and 5bth compressed weight data CWD5a and CWD5b may correspond to one variable-length compressed weight data CWD_V. The fifth length information LI5 may indicate the total length of the 5ath and 5bth compressed weight data CWD5a and CWD5b, and may indicate, for example, "4".

[0083] The 6ath and 6bth compressed weight data CWD6a and CWD6b may correspond to one variable-length compressed weight data CWD_V. The sixth length information LI6 may indicate the total length of the 6ath and 6bth compressed weight data CWD6a and CWD6b, and may indicate, for example, "5".

[0084] The seventh compression weight data CWD7 may correspond to one variable-length compression weight data CWD_V. The seventh length information LI7 may indicate the total length of the seventh compression weight data CWD7, and may indicate, for example, "4".

[0085] Reference Figure 7B In operation S511 , the buffer 211 may receive the fourth data block DC4 and may store the fourth data block DC4 as the first buffered data BD1 . The buffer 211 may output the first buffered data BD1 to the parser 213 .

[0086] In operation S512, the parser 213 may extract the fourth length information LI4 from a given position of the first buffered data BD1, for example, extract the fourth length information LI4 from a given number of leading bits of the first buffered data BD1. The parser 213 may remove the fourth length information LI4 from the first buffered data BD1 to generate the second buffered data BD2. The parser 213 may output the fourth length information LI4 and the second buffered data BD2 to the input generator 215.

[0087] In operation S513, the input generator 215 may receive the second buffered data BD2 including the fourth length information LI4 and the fourth compression weight data CWD4. Since all data corresponding to the fourth length information LI4 is collected, in operation S514, the input generator 215 may output the compression weight data CWD_F having a fixed length obtained by adding the padding data PD to the fourth compression weight data CWD4.

[0088] In operation S515 , the input generator 215 may store the fifth length information LI5 and the 5a th compressed weight data CWD5 a in the buffer 211 again as the residual data RD.

[0089] Reference Figure 7CIn operation S521, the buffer 211 may receive and store the fifth data block DC5. The buffer 211 may output the fifth length information LI5 and the 5a-th compressed weight data CWD5a constituting the remaining data RD of the fourth data block DC4 and the 5b-th compressed weight data CWD5b, the sixth length information LI6 and the 6a-th compressed weight data CWD6a of the fifth data block DC5 to the parser 213 as the first buffered data BD1.

[0090] In operation S522, the parser 213 may extract the fifth length information LI5 from a given position of the first buffer data BD1, for example, extract the fifth length information LI5 from a given number of leading bits of the first buffer data BD1. The parser 213 may remove the fifth length information LI5 from the first buffer data BD1 to generate the second buffer data BD2. The parser 213 may output the fifth length information LI5 and the second buffer data BD2 to the input generator 215. In some example embodiments, when the first buffer data BD1 includes a plurality of length information (such as the first buffer data BD1 including the length information LI5 and the length information LI6), only the length information encountered initially (or for the first time) may be extracted (for example, only the length information LI5 is extracted without extracting the length information LI6). In some example embodiments, specific length information may be selected or desired based on user preferences, operating parameters, or other information. In operation S523, the input generator 215 may collect data corresponding to the fifth length information LI5 based on the second buffer data BD2.

[0091] In operation S524, the input generator 215 may output the compressed weight data CWD_F of a fixed length obtained by adding the padding data PD to the 5a-th compressed weight data CWD5a and the 5b-th compressed weight data CWD5b corresponding to the fifth length information LI5. For example, the padding data PD may have a given value or an arbitrary value. The length of the padding data PD may be different from that of the encoding core 220 (refer to Figure 4 ) corresponds to the difference between the length of the coding unit and the length of the variable-length compression weight data CWD_V.

[0092] In operation S525 , the input generator 215 may store the sixth length information LI6 and the 6a th compressed weight data CWD6 a in the buffer 211 again as the residual data RD.

[0093] Reference Fig.7DIn operation S531, the buffer 211 may receive and store the sixth data block DC6. The buffer 211 may output the sixth length information LI6 and the 6a-th compressed weight data CWD6a constituting the remaining data RD of the fifth data block DC5, the 6b-th compressed weight data CWD6b of the sixth data block DC6, the seventh length information LI7, and the seventh compressed weight data CWD7 as the first buffered data BD1 to the parser 213.

[0094] In operation S532, the parser 213 may extract the sixth length information LI6 from a given position of the first buffered data BD1, for example, extract the sixth length information LI6 from a given number of leading bits of the first buffered data BD1. The parser 213 may remove the sixth length information LI6 from the first buffered data BD1 to generate the second buffered data BD2. The parser 213 may output the sixth length information LI6 and the second buffered data BD2 to the input generator 215.

[0095] In operation S533 , the input generator 215 may collect data corresponding to the sixth length information LI6 based on the second buffered data BD2 .

[0096] In operation S534, the input generator 215 may output the compressed weight data CWD_F of a fixed length obtained by adding padding data PD to the 6a-th compressed weight data CWD6a and the 6b-th compressed weight data CWD6b corresponding to the sixth length information LI6. In operation S535, the input generator 215 may store the seventh length information LI7 and the seventh compressed weight data CWD7 in the buffer 211 again as the residual data RD.

[0097] Figure 8 2 shows weight data WD according to some example embodiments of the present disclosure. Figure 1 and Figure 8 , the first weight WT1 to the nth weight WTn (n is a positive integer) may be loaded into the accelerator core 140. Each of the first weight WT1 to the nth weight WTn may include a first weight bit B1 to an mth weight bit Bm (m is a positive integer). In some example embodiments, the kth weight bit (k is a positive integer less than or equal to m) of the first weight WT1 to the nth weight WTn may constitute one weight data WD.

[0098] For example, the variable length polar encoder 130 may output the first weight bits B1 of the first weight WT1 to the n-th weight WTn. The accelerator core 140 may load the first weight bits B1 of the first weight WT1 to the n-th weight WTn. When the variable length polar encoder 130 sequentially outputs the weight bits of the first weight WT1 to the n-th weight WTn in columns, the weight bits of the first weight WT1 to the n-th weight WTn may be sequentially loaded into the accelerator core 140.

[0099] In some example embodiments, among the first to nth weights WT1 to WTn, valid weights and invalid weights may be distinguished from each other according to the kind of machine learning-based inference model (or module) loaded into the accelerator core 140. The valid weights may be weights necessary (or used) for performing machine learning-based inference. The invalid weights may be weights unnecessary (or not used) for performing machine learning-based inference.

[0100] Fig. 9 is a block diagram illustrating an electronic device 300 according to some example embodiments of the present disclosure. Fig. 9 , the electronic device 300 may include a processor 310 , a random access memory 320 , a device driver 330 , a storage device 340 , a modem 350 , and a user interface 360 ​​.

[0101] The processor 310 may include, for example, at least one general-purpose processor, such as a central processing unit (CPU) 311 or an application processor (AP) 312. In addition, the processor 310 may also include at least one dedicated processor, such as a neural processing unit (NPU) 313, a neuromorphic processor (NP) 314, or a graphics processing unit (GPU) 315. The processor 310 may include two or more processors of the same type.

[0102] At least one of the processors 310 may include the compression and decompression module 400 as a hardware component, or may execute the compression and decompression module 400 as a software component. For example, the compression and decompression module 400 may be used to compress the weights of the inference based on machine learning by polar decoding, and decompress the compressed weights by polar encoding. The compression and decompression module 400 may be used to generate a variable-length compressed weight data CWD_V (reference numeral 404) to be transmitted to the accelerator device 100. Figure 1 ).

[0103] The random access memory 320 may be used as a working memory of the processor 310, and may be used as a main memory or a system memory of the electronic device 300. The random access memory 320 may include a volatile memory such as a dynamic random access memory or a static random access memory, or a nonvolatile memory such as a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, or a resistive random access memory.

[0104] The device driver 330 may control the following peripheral devices according to a request of the processor 310: a storage device 340, a modem 350, and a user interface 360. The storage device 340 may include a fixed storage device such as a hard disk drive or a solid state drive, or a removable storage device such as an external hard disk drive, an external solid state drive, or a removable memory card.

[0105] The modem 350 may provide remote communication with an external device. The modem 350 may perform wired or wireless communication with an external device. The modem 350 may communicate with an external device based on at least one of various communication schemes such as Ethernet, wireless fidelity (Wi-Fi), long term evolution (LTE), and fifth generation (5G) mobile communication.

[0106] The user interface 360 ​​may receive information from the user and may provide information to the user. The user interface 360 ​​may include at least one user output interface, such as a display 361 or a speaker 362, and at least one user input interface, such as a mouse 363, a keyboard 364 or a touch input device 365.

[0107] Fig.10 A first example of an operating method of an electronic device 300 according to some exemplary embodiments of the present disclosure is shown. For example, Fig.10 The method of controlling the accelerator device 100 by the electronic device 300 is shown in FIG. Fig. 9 and Fig.10 , in operation S610, the electronic device 300 may receive source weight data (or original weight data) SWD.

[0108] In operation S620, the electronic device 300 may arrange the source weight data SWD based on the frozen bit and the weight validity. For example, the position of the frozen bit and the error rate of each bit may be determined according to the structure of the encoding and decoding matrix. The electronic device 300 may arrange the source weight data SWD so that the invalid weight bit of the source weight data SWD corresponds to the position of the frozen bit.

[0109] In operation S630, the electronic device 300 may perform polarization decoding to generate compressed weight data CWD. For example, the compression and decompression module 400 of the electronic device 300 may generate compressed weight data CWD by performing polarization decoding on the source weight data SWD thus arranged.

[0110] In operation S640, the electronic device 300 may perform polar coding to generate decompressed weight data PWD. For example, the compression and decompression module 400 of the electronic device 300 may generate decompressed weight data PWD by performing polar coding on the compressed weight data CWD.

[0111] In operation S650, the electronic device 300 may compare the source weight data SWD and the decompressed weight data PWD. For example, the electronic device 300 may compare the effective weight bits of the source weight data SWD and the effective weight bits of the decompressed weight data PWD.

[0112] When it is determined in operation S660 that the source weight data SWD and the decompressed weight data PWD are not identical to each other, the electronic device 300 may perform operation S670. In some example embodiments, when the valid weight bits of the source weight data SWD and the valid weight bits of the decompressed weight data PWD are different from each other, an error may have occurred at the valid weight bits during compression (e.g., polar decoding) and decompression (e.g., polar encoding).

[0113] When an error occurs at a valid weight bit during compression and decompression, the electronic device 300 may reduce the number of frozen bits in operation S670. For example, the electronic device 300 may repeatedly perform operations S630 to S670 until the valid weight bits of the source weight data SWD and the valid weight bits of the decompressed weight data PWD are identical to each other.

[0114] When it is determined in operation S660 that the source weight data SWD and the decompressed weight data PWD are identical to each other, the electronic device 300 may perform operation S680. In operation S680, the electronic device 300 may confirm the compressed weight data CWD. For example, the electronic device 300 may confirm the compressed weight data CWD corresponding to the case where the effective weight bits of the source weight data SWD and the effective weight bits of the decompressed weight data PWD are identical to each other. For example, the electronic device 300 may allow the accelerator device 100 to perform inference based on machine learning by inputting the compressed weight data CWD to the accelerator device 100.

[0115] Fig.11A and Fig. 11B FIG. 3 shows an example of a process in which the electronic device 300 performs compression and decompression while changing the number of frozen bits. Fig. 9 , Fig.10 and Fig.11A , compression (eg, polar decoding) and decompression (eg, polar encoding) may be performed by using a generator matrix GM. The generator matrix GM may include a plurality of exclusive OR (XOR) gates connected between paths connecting the first node N1 and the second node N2.

[0116] The electronic device 300 may determine the position of the frozen bit FB of the first node N1 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively high error rate among the first nodes N1 may be determined as the position of the frozen bit FB.

[0117] The electronic device 300 may determine the position of the second weight bit WB2 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively high error rate in the second node N2 may be determined as the position of the second weight bit WB2. The second weight bit WB2 may be an invalid weight bit.

[0118] Alternatively, the electronic device 300 may determine the position of the first weight bit WB1 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively low error rate in the second node N2 may be determined as the position of the first weight bit WB1. The first weight bit WB1 may be a valid weight bit.

[0119] In some example embodiments, the number of frozen bits FB may be 4, the number of first weight bits WB1 may be 4, and the number of second weight bits WB2 may be 4.

[0120] During compression (e.g., polarization decoding), the electronic device 300 may load the first weight bit WB1 of the source weight data SWD into some second nodes N2, and may load the second weight bit WB2 into other nodes. The electronic device 300 may designate some first nodes N1 as frozen bits FB, and may obtain compressed weight bits CWB from other nodes. When the number of frozen bits FB is 4, four compressed weight bits CWB may be obtained. The compressed weight bits CWB may constitute compressed weight data CWD.

[0121] During decompression (e.g., polarization coding), the electronic device 300 may designate some first nodes N1 as frozen bits FB, and may load compressed weight bits CWB of the compressed weight data CWD into other nodes. The electronic device 300 may obtain the first weight bits WB1 of the decompressed weight data PWD from some second nodes N2.

[0122] When the first weight bit WB1 of the source weight data SWD and the first weight bit WB1 of the decompressed weight data PWD are identical to each other, the electronic device 300 can confirm the compressed weight data CWD. When the first weight bit WB1 of the source weight data SWD and the first weight bit WB1 of the decompressed weight data PWD are different from each other, the electronic device 300 can reduce the number of frozen bits FB.

[0123] Reference Fig. 9 , Fig.10 and Fig. 11B , the number of frozen bits FB of the first node N1 can be reduced to 3. The number of compressed weight bits CWB can be increased to 5. That is, the length of the compressed weight data CWD can be increased to 5.

[0124] As reference Fig.10 , Fig.11A and Fig. 11B As described above, the electronic device 300 can repeat compression and decompression while reducing the number of frozen bits FB until no error occurs. Therefore, compressed weight data CWD having a variable length and no defects can be obtained.

[0125] Compared with other error correction encoders, the complexity of the polar encoder is relatively low. Figure 1 ) may include a polar encoder, and compressed weight data CWD without defects may be decompressed by using the polar encoder. Therefore, in the process of decompressing the compressed weight data CWD, power consumption and time may be reduced. In addition, because the decompression process and the process of loading the decompressed weight data WD into the accelerator core 140 are performed in an instant scheme (optionally, as needed or desired), the time spent loading multiple weight data into the accelerator core 140 may be shortened.

[0126] Fig.12 A second example of the method of operation of the variable length polar encoder 130 according to some example embodiments of the present disclosure is shown. Figure 1 and Fig.12 In operation S710, the variable length polar encoder 130 may read a data block corresponding to a bandwidth. For example, the variable length polar encoder 130 may read a data block corresponding to a communication bandwidth of the memory 120 (eg, reference Figure 2 The second data block described).

[0127] In operation S720, the variable length polar encoder 130 may extract length information. For example, the variable length polar encoder 130 may extract length information at a given position of the read data block. The length information may indicate the length of the weight data. For example, the given position may mean a given number of leading bits of the data block.

[0128] When the length information does not exist at a given position of the read data block, the variable length polar encoder 130 may omit the extraction of the length information. For example, when the length information extracted from the previous data block is still valid (for example, when the entire weight data corresponding to the length information has not been collected), the length information may not exist at a given position of the current data block or the buffered data.

[0129] In operation S730, the variable length polar encoder 130 may perform decompression by performing polar encoding. When performing decompression, the variable length polar encoder 130 may discard length information and may update length information by extracting next length information.

[0130] In operation S740, the variable-length polar encoder 130 may collect weight data WD corresponding to the length information. For example, the weight data WD corresponding to the length information may be collected from one data block, or may be collected from two or more data blocks.

[0131] When the weight data WD corresponding to the length information is collected, the variable-length polar encoder 130 may output the weight data WD.

[0132] Fig.13 FIG. 5 shows a variable length polar encoder 500 according to a second embodiment of the present disclosure. In some example embodiments, the variable length polar encoder 500 may correspond to Figure 1 A variable length polar encoder 130 is provided.

[0133] refer to Figure 1 and 13 The variable length polar encoder 500 may include a pre-processor 510 , an encoding core 520 , and a post-processor 530 .

[0134] The preprocessor 510 may sequentially receive data blocks DC from the memory 120. At least one data block DC may include fixed-length compressed weight data CWD_F. For example, based on the bandwidth of the memory 120, the fixed-length compressed weight data CWD_F may be received through one data block DC or may be received through two or more data blocks DC.

[0135] The preprocessor 510 may include a parser 511. The parser 511 may extract length information LI from the data block DC. The length information LI may be received together with the compression weight data CWD_F of fixed length. When a compression weight data CWD_F of fixed length is received through two data blocks, the first data block may include the length information LI, and the second data block may not include the length information LI.

[0136] The parser 511 may output the extracted length information LI to the post-processor 530. The parser 511 may output the compressed weight data CWD_F of a fixed length to the encoding core 520.

[0137] The encoding core 520 may receive the fixed-length compressed weight data CWD_F from the preprocessor 510. The encoding core 520 may decompress the fixed-length compressed weight data CWD_F by performing polar encoding on the fixed-length compressed weight data CWD_F. The encoding core 520 may generate the fixed-length weight data WD_F as a decompression result. The encoding core 520 may output the fixed-length weight data WD_F to the postprocessor 530.

[0138] In some example embodiments, when the fixed-length compressed weight data CWD_F is received through two or more data blocks DC, the fixed-length compressed weight data CWD_F may be buffered in the preprocessor 510 or the encoding core 520 until the entire fixed-length compressed weight data CWD_F is collected.

[0139] The post-processor 530 may receive fixed-length weight data WD_F from the encoding core 520. Some bits of the fixed-length weight data WD_F may be weight bits (e.g., including valid weight bits and invalid weight bits), and the remaining bits thereof may be invalid bits (e.g., dummy bits or padding bits). The length information LI may include information about the length (or number) of the weight bits.

[0140] The post-processor 530 may include an output generator 531. The output generator 531 may remove invalid bits from the weight data WD_F of fixed length based on the length information LI. The length of the invalid bits may vary according to the weight data WD_F of fixed length. By removing the invalid bits, the output generator 531 may collect the weight data WD_V of variable length. The output generator 531 may output the weight data WD_V of variable length.

[0141] Fig.14 is a diagram illustrating a second example of an operating method of an electronic device according to some example embodiments of the present disclosure. For example, Fig.14 The method of controlling the accelerator device 100 by the electronic device 300 is shown in FIG. Fig. 9 and Fig.14 , in operation S810, the electronic device 300 may receive source weight data SWD.

[0142] In operation S820, the electronic device 300 may arrange the source weight data SWD based on the frozen bit and the weight validity. For example, the position of the frozen bit and the error rate of each bit may be determined according to the structure of the encoding and decoding matrix. The electronic device 300 may arrange the source weight data SWD so that the invalid weight bit of the source weight data SWD corresponds to the position of the frozen bit.

[0143] In operation S830, the electronic device 300 may perform polarization decoding to generate compressed weight data CWD. For example, the compression and decompression module 400 of the electronic device 300 may generate compressed weight data CWD by performing polarization decoding on the source weight data SWD arranged in this way.

[0144] In operation S840, the electronic device 300 may perform polar coding to generate decompressed weight data PWD. For example, the compression and decompression module 400 of the electronic device 300 may generate decompressed weight data PWD by performing polar coding on the compressed weight data CWD.

[0145] In operation S850, the electronic device 300 may compare the source weight data SWD and the decompressed weight data PWD. For example, the electronic device 300 may compare the effective weight bits of the source weight data SWD and the effective weight bits of the decompressed weight data PWD.

[0146] When it is determined in operation S860 that the source weight data SWD and the decompressed weight data PWD are not identical to each other, the electronic device 300 may perform operation S870. In some example embodiments, when the valid weight bits of the source weight data SWD and the valid weight bits of the decompressed weight data PWD are different from each other, an error may have occurred at the valid weight bits during compression (e.g., polar decoding) and decompression (e.g., polar encoding).

[0147] When an error occurs at a valid weight bit during compression and decompression, in operation S870, the electronic device 300 may replace the valid weight bit with an invalid weight bit. That is, the electronic device 300 may reduce the number of valid weight bits and may increase the number of invalid weight bits. For example, the electronic device 300 may repeatedly perform operations S830 to S870 until the valid weight bits of the source weight data SWD and the valid weight bits of the decompressed weight data PWD are identical to each other.

[0148] When it is determined in operation S860 that the source weight data SWD and the decompressed weight data PWD are identical to each other, the electronic device 300 may perform operation S880. In operation S880, the electronic device 300 may confirm the compressed weight data CWD. For example, the electronic device 300 may confirm the compressed weight data CWD corresponding to the case where the effective weight bits of the source weight data SWD and the effective weight bits of the decompressed weight data PWD are identical to each other. For example, the electronic device 300 may allow the accelerator device 100 to perform inference based on machine learning by inputting the compressed weight data CWD into the accelerator device 100.

[0149] Fig.15A and Fig. 15B FIG. 3 shows an example of a process in which the electronic device 300 performs compression and decompression while changing the number of frozen bits. Fig. 9 , Fig.10 and Fig.15A , compression (e.g., polar decoding) and decompression (e.g., polar encoding) can be performed by using a generator matrix GM. The generator matrix GM may include a plurality of XOR gates connected between paths connecting the first node N1 and the second node N2.

[0150] The electronic device 300 may determine the position of the frozen bit FB of the first node N1 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively high error rate among the first nodes N1 may be determined as the position of the frozen bit FB.

[0151] The electronic device 300 can determine the position of the second weight bit WB2 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively high error rate among the second nodes N2 can be determined as the position of the second weight bit WB2. The second weight bit WB2 can be an invalid weight bit.

[0152] Alternatively, the electronic device 300 may determine the position of the first weight bit WB1 based on the structure and characteristics of the generator matrix GM. For example, a node with a relatively low error rate in the second node N2 may be determined as the position of the first weight bit WB1. The first weight bit WB1 may be a valid weight bit.

[0153] In some example embodiments, the number of frozen bits FB may be 4, the number of first weight bits WB1 may be 4, and the number of second weight bits WB2 may be 4.

[0154] During compression (e.g., polarization decoding), the electronic device 300 may load the first weight bit WB1 of the source weight data SWD into some second nodes N2, and may load the second weight bit WB2 into other nodes. The electronic device 300 may designate some first nodes N1 as frozen bits FB, and may obtain compressed weight bits CWB from other nodes. When the number of frozen bits FB is 4, four compressed weight bits CWB may be obtained. The compressed weight bits CWB may constitute compressed weight data CWD.

[0155] During decompression (e.g., polarization coding), the electronic device 300 may designate some first nodes N1 as frozen bits FB, and may load compressed weight bits CWB of the compressed weight data CWD into other nodes. The electronic device 300 may obtain the first weight bits WB1 of the decompressed weight data PWD from some second nodes N2.

[0156] When the first weight bit WB1 of the source weight data SWD and the first weight bit WB1 of the decompressed weight data PWD are identical to each other, the electronic device 300 may confirm the compressed weight data CWD. When the first weight bit WB1 of the source weight data SWD and the first weight bit WB1 of the decompressed weight data PWD are different from each other, the electronic device 300 may reduce the number of the first weight bits WB1 and may increase the number of the second weight bits WB2.

[0157] Reference Fig. 9 , Fig.10 and Fig. 15B , the number of the first weight bits WB1 of the second node N2 may be reduced to 3. The number of the second weight bits WB2 of the second node N2 may be increased to 5. The number of compressed weight bits CWB may be maintained at 4. That is, the length of the compressed weight data CWD may be maintained at 4.

[0158] As reference Fig.10 , 15A As described in FIG. 15B , the electronic device 300 can repeat compression and decompression while reducing the number of first weight bits WB1 and increasing the number of second weight bits WB2 until no error occurs. Therefore, compressed weight data CWD having a fixed length and no defects can be obtained.

[0159] In some example embodiments, the first weight bit WB1 replaced during the compression process may be compressed together with the next source weight data SWD.

[0160] Compared with other error correction encoders, the polar encoder reduces complexity. Figure 1) may include a polar encoder, and compressed weight data CWD without defects may be decompressed by using the polar encoder. Therefore, in the process of decompressing the compressed weight data CWD, power consumption and time may be reduced. In addition, because the decompression process and the process of loading the decompressed weight data WD into the accelerator core 140 are performed in an instant scheme (or, optionally, as needed or desired), the time spent loading multiple weight data into the accelerator core 140 may be shortened.

[0161] Fig.16 Another example of an operating method of the electronic device 300 according to some exemplary embodiments of the present disclosure is shown. Figure 1 , Fig. 9 and Fig.16 In some example embodiments, the electronic device 300 may include the accelerator device 100 as one of the processors 310. For the sake of brief description, operations between the central processing unit CPU (or 311) in the processor 310, the accelerator device ACC (or 100), and the random access memory RAM (or 320) will be described.

[0162] In operation S910, the central processing unit CPU may request the accelerator device ACC to enable automatic decryption. The accelerator device ACC may enable automatic decryption in response to the request of the central processing unit CPU.

[0163] In operation S920, the central processing unit CPU may request to load a model. For example, the central processing unit CPU may request to load a first machine learning-based reasoning.

[0164] In response to the request of the central processing unit CPU, the accelerator device ACC may receive a plurality of compressed weight data CWD from the random access memory RAM in operation S930. In operation S940, the central processing unit CPU may perform decryption and loading on the plurality of compressed weight data CWD.

[0165] In operation S950, the central processing unit CPU may request the accelerator device ACC to disable automatic decryption. The accelerator device ACC may disable automatic decryption in response to the request of the central processing unit CPU.

[0166] In operation S960, the central processing unit CPU may request to load a model. For example, the central processing unit CPU may request to load a second machine learning-based reasoning.

[0167] In response to the request of the central processing unit CPU, the accelerator device ACC may receive a plurality of weight data WD from the random access memory RAM in operation S970. In operation S980, the central processing unit CPU may perform loading on the plurality of weight data CWD.

[0168] As described above, the accelerator device ACC can enable or disable automatic decryption in response to a request from the central processing unit CPU. When automatic decryption is enabled, the accelerator device ACC can perform loading after decompressing the data received as weight data. When automatic decryption is disabled, the accelerator device ACC can perform loading without decompressing the data received as weight data.

[0169] When the size of the weight data WD is relatively small, the weight data WD may not be compressed, and thus the power and time required for the accelerator device ACC to perform decompression may be reduced. When the size of the weight data WD is relatively large, the weight data WD may be compressed, and thus the power, bandwidth, and time required to communicate the weight data WD with the accelerator device ACC may be reduced.

[0170] In the above exemplary embodiments, components according to the present disclosure are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. do not refer to any form of order or numerical meaning.

[0171] In the above example embodiments, components according to embodiments of the present disclosure are referenced by using boxes. These blocks can be implemented with various hardware devices, such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in hardware devices, software such as applications, or a combination of hardware devices and software. In addition, these blocks can include circuits implemented with semiconductor elements in integrated circuits, or circuits registered as intellectual property (IP).

[0172] As described herein, any electronic device and / or portion thereof according to any example embodiment may include, may be included in, and / or may be implemented by one or more instances of a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program, such as a DRAM device, and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof and / or any portion thereof according to any example embodiment.

[0173] According to an example embodiment of the present disclosure, an accelerator device may include a variable length polar encoder, and the variable length polar encoder may decompress compressed weight data losslessly. Since the compressed weight data may be decompressed with reduced complexity, an accelerator device that supports reasoning based on machine learning while increasing operation speed and reducing power consumption and a method for controlling the accelerator device are provided.

[0174] While the present invention has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. An accelerator device for supporting machine learning-based inference, comprising: an interface circuit configured to communicate with an external device; Memory, configured as: storing first data received through the interface circuit, the first data being compressed weight data and having a variable length; Polar encoder, configured as: performing polar encoding on first data provided from the memory, and outputting a result of the polarization encoding as second data, where the second data is decompressed weight data; as well as The accelerator core is configured as: loading the second data, and A machine learning-based inference is performed based on the second data.

2. The accelerator device according to claim 1, wherein: The polar encoder is configured to access the first data as a first data block together with the second compressed weight data based on a bandwidth of the memory.

3. The accelerator device according to claim 2, wherein: The first data block includes first length information corresponding to the first data, and The polar encoder is configured as: extracting first length information from the first data block; and First data is collected from the first data block based on the first length information.

4. The accelerator device according to claim 3, wherein: The polar encoder is configured as: adding padding data to the first data to generate third data of a fixed length; and Polar encoding is performed on the third data to generate second data.

5. The accelerator device according to claim 2, wherein: The polar encoder is configured as: The second length information is extracted from the second compressed weight data included in the first data block and the second data block subsequent to the first data block.

6. The accelerator device according to claim 1, wherein: The polar encoder is configured to access the first data divided into at least two data blocks based on a bandwidth of the memory.

7. The accelerator device according to claim 6, wherein: The polar encoder is configured as: Extracting first length information from a first data block among the at least two data blocks; as well as Data blocks are received until data corresponding to the first length information is collected.

8. An accelerator device for supporting machine learning-based inference, comprising: an interface circuit configured to communicate with an external device; A memory configured to store first data received through the interface circuit, the first data being compressed weight data; Polar encoder, configured as: performing polar encoding on first data provided from the memory, and Outputting a result of polar coding as second data, where the second data is decompressed weight data and has a variable length; as well as The accelerator core is configured as: loading the second data, and A machine learning-based inference is performed based on the second data.

9. The accelerator device according to claim 8, wherein: The polar encoder is configured to access first data included in the first data block based on a bandwidth of the memory.

10. The accelerator device according to claim 9, wherein: The first data block also includes first length information corresponding to the first data, and The polar encoder is configured as: Extracting first length information from the first data block; performing polarization encoding on the first data to generate third data; and The second data is extracted from the third data based on the first length information.

11. The accelerator device according to claim 8, wherein: The polar encoder is configured to access the first data divided into at least two data blocks based on a bandwidth of the memory.

12. The accelerator device according to claim 11, wherein: A first data block among the at least two data blocks includes first length information corresponding to the first data, and The polar encoder is configured to repeat the following operations: Extracting first length information from the first data block; receiving data blocks until data corresponding to the first length information is collected; and Polar encoding is performed on each data block.

13. A method of controlling an accelerator device, the accelerator device comprising a polarization encoder and an accelerator core, the method comprising: Inputting first data into a polar encoder, wherein the first data is compressed weight data; At a polar encoder, performing polar encoding on the first data to generate second data, the second data being decompressed weight data; loading second data into the accelerator core; as well as performing, at the accelerator core, machine learning-based inference based on the second data, One of the first data and the second data has a variable length.

14. The method according to claim 13, further comprising: Generate first data, The generation of the first data includes: performing polarization decoding on the source weight data to generate third data; performing polarization encoding on the third data to generate fourth data; comparing the source weight data and the fourth data; and Based on the partial data of the source weight data matching the partial data of the fourth data, which corresponds to the partial data of the source weight data, the remaining bits except the frozen bits of the third data are determined as the first data.

15. The method according to claim 14, wherein: Generating the first data further includes: Based on the fact that part of the source weight data does not match part of the fourth data, the number of frozen bits of the third data is reduced.

16. The method according to claim 15, wherein: Generating the first data further includes: While the number of frozen bits is sequentially reduced, generation of the third data, generation of the fourth data, and comparison are performed until partial data of the source weight data matches partial data of the fourth data.

17. The method according to claim 14, wherein: Generating the first data further includes: Based on the partial data of the source weight data not matching the partial data of the fourth data, the size of the partial data of the source weight data is reduced.

18. The method according to claim 17, wherein: Generating the first data further includes: While the size of the source weight data is sequentially reduced, generation of the third data, generation of the fourth data, and comparison are performed until partial data of the source weight data matches partial data of the fourth data.

19. The method according to claim 14, wherein: Part of the source weight data includes weight data required for the accelerator core to perform machine learning-based reasoning.

20. The method according to claim 19, wherein: The location of the partial data of the source weight data changes depending on the kind of the machine learning based module corresponding to the source weight data.

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