Storage device and operating method of storage device

Abstract

There is provided a storage device including: a storage device including a plurality of memory blocks, each memory block including a plurality of memory cells; a controller configured to control a program operation of the storage device in response to a write request received from a host; and a temperature sensor configured to measure an internal temperature, in which the controller is further configured to activate one of the plurality of memory blocks as a risk block based on a first temperature measured by the temperature sensor, and then control a high reliability programming operation using the risk block, or activating one of the plurality of memory blocks as a first normal block, and then controlling the normal program operation using the first normal block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0131936 filed with the Korean Intellectual Property Office on October 4, 2023, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] The inventive concept relates to a storage device for performing a memory operation according to a request from a host and an operating method of the storage device.

[0004] The storage system includes a host (or host device) and a storage device, and the host and the storage device are connected to each other through various interface standards, such as Universal Flash Storage (UFS), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), or Embedded Multimedia Card (MMC) (eMMC). The storage device includes a storage device and a controller configured as a non-volatile memory, and the non-volatile memory may include flash memory, magnetoresistive random access memory (MRAM), phase change RAM (PRAM), ferroelectric RAM (FeRAM), etc.

[0005] In order to meet the standards according to the reliability evaluation procedures of electronic components supplied to automobiles, stable performance in a wide temperature range needs to be guaranteed. However, due to the limitations of the physical characteristics of non-volatile memory cells (e.g., NAND flash memory cells) of storage devices included in electronic components, when the difference between the temperature when a programming operation is performed on specific data and the temperature when a read operation is performed on the data changes, the error probability of the data increases, which may cause the performance of the storage device to deteriorate.

[0006] Therefore, research on a storage device capable of performing memory operations with guaranteed reliability even in a wide temperature range is being actively conducted. Summary of the invention

[0007] The inventive concept provides an electronic device capable of providing improved reliability by selectively performing a high reliability program operation and a normal program operation based on an internal temperature of a storage device, and an operating method of the electronic device.

[0008] According to some embodiments conceived by the present invention, there is provided a storage device, comprising: a storage device including a plurality of storage blocks, each storage block including a plurality of storage cells; a controller configured to control a programming operation of the storage device in response to a write request received from a host; and a temperature sensor configured to measure an internal temperature, wherein the controller is further configured to activate one of the plurality of storage blocks as a risk block and then control a high-reliability programming operation using the risk block, or to activate one of the plurality of storage blocks as a first normal block and then control a normal programming operation using the first normal block, based on a first temperature measured by the temperature sensor.

[0009] According to some embodiments conceived in the present invention, there is provided a storage device, comprising: a storage device including a first storage block operated as a single-level cell and a second storage block operated as a multi-level cell; a controller configured to control a programming operation of the storage device in response to a write request received from a host; and a temperature sensor configured to measure an internal temperature, wherein the programming operation of the storage device in response to the write request includes programming data corresponding to the write request into the first storage block, and based on a first temperature measured by the temperature sensor within a preset time period, activating one of the second storage blocks as a risk block and then controlling a high-reliability data migration operation on the data by using the risk block, or activating one of the second storage blocks as a normal block and then controlling a normal data migration operation on the data by using the normal block.

[0010] According to some embodiments conceived by the present invention, there is provided a storage device, comprising: a storage device including a plurality of storage blocks, each storage block including a plurality of storage cells; a controller configured to control a programming operation of the storage device in response to at least one write request received from a host; and a temperature sensor configured to measure an internal temperature, wherein the controller is further configured to activate one of the plurality of storage blocks as a risk block and then use the risk block to control a high-reliability programming operation, or activate one of the plurality of storage blocks as a normal block and then use the normal block to control a normal programming operation, based on at least one of a first temperature measured by the temperature sensor or whether the environment is restricted during a programming time period.

[0011] According to another aspect of the inventive concept, there is provided an operating method of a storage device, the operating method comprising: measuring a current internal temperature in response to a write request received from a host; determining whether the measured current internal temperature is within a normal range; dynamically activating one of a risk block or a normal block based on a result of the determination; and selectively performing one of a high-reliability programming operation using the risk block or a normal programming operation using the normal block based on the result of the activation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram schematically illustrating a storage system according to some embodiments;

[0014] Figure 2 According to some embodiments Figure 1 Detailed block diagram of the controller;

[0015] Figure 3 According to some embodiments Figure 1 A detailed block diagram of a storage device;

[0016] Figure 4A and Figure 4B It is used to describe the Figure 1 A diagram of a three-dimensional V-NAND structure of a storage device;

[0017] Figure 5 is a flowchart for describing a method of operating a storage device according to some embodiments;

[0018] Figure 6 It is used to describe in detail Figure 5 A flowchart of an operation method of a storage device in operation S130;

[0019] Figure 7 is a diagram for describing in detail a programming operation according to some embodiments;

[0020] Fig. 8A and Figure 8B is a diagram for describing in detail first and second high reliability programming operations according to some embodiments;

[0021] Fig.9A A method of operating a storage device in a high temperature range according to some embodiments is shown, and Fig. 9B and Fig. 9C is a diagram for describing a block management table according to some embodiments;

[0022] Fig.10 is a flowchart for describing a method of operating a storage device according to some embodiments;

[0023] Fig.11 is a flow chart for describing a garbage collection operation of a storage device according to some embodiments;

[0024] Fig. 12A and Fig. 12B Is used to describe Fig.11 A flowchart of a method for operating a storage device in operation S410;

[0025] Fig.13Aand Fig. 13B It is used to describe in detail Fig.11 A flowchart of a method for operating a storage device in operation S410;

[0026] Fig.14 is a flow chart for describing a garbage collection operation of a storage device according to some embodiments;

[0027] Fig.15A and Fig. 15B is a diagram for describing a garbage collection operation of a storage device according to some embodiments;

[0028] Fig.16 is a diagram for describing a garbage collection operation of a storage device according to some embodiments;

[0029] Fig.17 is a flowchart for describing a method of operating a storage device according to some embodiments;

[0030] Fig.18A and Fig.18B is a flowchart for describing operations for managing a data refresh table of a storage device according to some embodiments;

[0031] Fig.19 It is used to describe in detail Fig.17 A flowchart of an operation method of a storage device in operation S550;

[0032] Fig. 20 is a flowchart for describing a data refresh operation of a storage device according to some embodiments;

[0033] Fig.21 is a flowchart for describing a method of operating a storage device according to some embodiments;

[0034] Fig. 22 is a block diagram illustrating a memory card system according to some embodiments; and

[0035] Fig.23 is a block diagram illustrating a solid state drive system according to some embodiments. DETAILED DESCRIPTION

[0036] Figure 1 1 is a block diagram schematically illustrating a storage system 10 according to some embodiments. The storage system 10 may be a computing system configured to process various information, such as a personal computer (PC), a notebook computer, a laptop computer, a server, a workstation, a tablet computer, a smart phone, a digital camera, or a dashboard camera. In this specification, an example in which the storage system 10 is implemented as a vehicle computing system for performing high reliability operations in a wide temperature range will be described, but the concept of the present invention may also be applied to computing systems in other industries.

[0037] Reference Figure 1 , the storage system 10 may include a host 11 and a storage device 100 .

[0038] The host 11 may control the overall operation of the storage system 10. For example, the host 11 may store data in the storage device 100, or read data stored in the storage device 100.

[0039] The storage device 100 may include a controller 110, a storage device 120, and a temperature sensor 130. The controller 110 may control a first memory operation of the storage device 120 in response to a request from the host 11. For example, the controller 110 may program data received from the host 11 into the storage device 120 in response to a write request from the host 11, or provide data read from the storage device 120 to the host 11 in response to a read request from the host 11. In addition, the controller 110 may control a second memory operation on the storage device 120 to increase the reliability of data stored in the storage device 120 or to increase the utilization rate of the storage space of the storage device 120. For example, the controller 110 may control a garbage collection operation or a data migration operation on the storage device 120.

[0040] The inventive concept relates to an embodiment of a storage device 100 for: performing programming by using a programming scheme matching a high temperature range or a low temperature range to maintain the reliability of data stored in the storage device 120 for as long as possible at a temperature within an abnormal range other than a normal range; and then performing a garbage collection operation or a data migration operation to prevent reliability degradation due to degradation of data stored in the storage device 120 at a temperature within the abnormal range. Hereinafter, a detailed embodiment of the storage device 100 will be described, but it will be fully understood that Figure 1 The components in the storage device 100 shown in the drawings or other drawings are merely examples, and the inventive concept is not limited thereto. In this specification, a normal range may be referred to as a normal temperature range, and an abnormal range may be referred to as an abnormal temperature range.

[0041] In some embodiments, the controller 110 may include a risk block management circuit 111 and a block management table 113. In addition, in some embodiments, the storage device 120 may include a storage cell array 121 and a programming control circuit 123. In some embodiments, the storage device 120 may be a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, and a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In addition, the storage device 120 may be implemented in a three-dimensional array structure. In addition, the storage device 120 may be a flash memory whose charge storage layer includes a conductive floating gate, or a charge trap flash memory (CTF) whose charge storage layer includes an insulating layer. In the following, some embodiments in which the storage device 120 is a NAND flash memory will be mainly described, but the inventive concept is not limited thereto.

[0042] In some embodiments, the risk block management circuit 111 may receive the current temperature of the storage device 100 measured by the temperature sensor 130 to perform an operation according to a write request received from the host 11 .

[0043] In some embodiments, when the current temperature is within the abnormal range, the risk block management circuit 111 may activate any one of the plurality of storage blocks included in the storage cell array 121 as a risk block. The risk block management circuit 111 may use the activated risk block to control the high reliability programming operation. In this specification, a risk block is defined as a storage block on which programming is performed within the abnormal range, and may also be referred to as a risk temperature buffer or a risk temperature block. In addition, in this specification, activating any storage block as a risk block by the risk block management circuit 111 may include: selecting a storage block on which a high reliability programming operation is to be performed from a plurality of storage blocks, and storing information indicating that a high reliability programming operation has been performed on the selected storage block in the block management table 113.

[0044] In some embodiments, the risk block management circuit 111 may control a high reliability programming operation for storing data received together with a write request from the host 11 in an activated risk block. For example, the risk block management circuit 111 may provide a first programming command for controlling a high reliability programming operation, an address and data of an activated risk block to the storage device 120. In response to the first programming command, the program control circuit 123 may program data into a risk block indicated by the received address in a storage block of the storage cell array 121. In some embodiments, the first programming command is a command pre-agreed between the controller 110 and the storage device 120 for indicating that the current temperature is within an abnormal range and therefore a high reliability programming operation needs to be performed, and may be different from a second programming command for a normal programming operation. However, in some embodiments, the risk block management circuit 111 may additionally provide the program control circuit 123 with temperature information indicating the current temperature and a program command common to the high reliability programming operation and the normal programming operation, and select and execute any one of the high reliability programming operation and the normal programming operation based on the temperature information.

[0045] In some embodiments, the abnormal range may include a high temperature range and a low temperature range, and the high reliability programming operation may include a first high reliability programming operation corresponding to the high temperature range and a second high reliability programming operation corresponding to the low temperature range. The first high reliability programming operation may be based on a first programming scheme considering a first degradation characteristic of a memory cell of the memory cell array 121 in the high temperature range, and the second high reliability programming operation may be based on a second programming scheme considering a second degradation characteristic of a memory cell of the memory cell array 121 in the low temperature range.

[0046] In detail, the first degradation characteristic may correspond to a characteristic that the retention period of charges in a memory cell programmed in a high temperature range degrades rapidly according to temperature changes, and the second degradation characteristic may correspond to a characteristic that the threshold voltage distribution of a memory cell in an erased state in a programmed memory cell widens in a low temperature range.

[0047] In some embodiments, the first programming scheme may be used to make the first threshold voltage distribution of the memory cell into which data is programmed sharper than the second threshold voltage distribution formed by the normal programming operation, and may be a scheme for preventing read interference or disturbance when reading from the memory cell due to the first degradation characteristic. In addition, the second programming scheme is used to make the first gap between the threshold voltage distribution in the erased state and the threshold voltage distribution in the first programming state in the first threshold voltage distribution of the memory cell into which data is programmed greater than the second gap between the threshold voltage distribution in the erased state and the threshold voltage distribution in the first programming state in the second threshold voltage distribution formed by the normal programming operation, and may be a scheme for preventing read interference caused by the second degradation characteristic. The detailed embodiments of the above will be described below.

[0048] In some embodiments, in order to enable the programming control circuit 123 to perform a first high-reliability programming operation based on a first programming scheme or a second high-reliability programming operation based on a second programming scheme, multiple programming parameter values ​​corresponding to the number of programming loops, the voltage level of the programming or verification voltage, etc. for the first high-reliability programming operation or the second high-reliability programming operation can be pre-set in the programming control circuit 123.

[0049] As another example, when the current temperature is within the normal range, the risk block management circuit 111 may activate any one of the plurality of memory blocks included in the memory cell array 121 as a normal block. The risk block management circuit 111 may control a normal programming operation using the activated normal block. In this specification, activating any memory block as a normal block by the risk block management circuit 111 may include: selecting a memory block on which a normal programming operation is to be performed from a plurality of memory blocks, and storing information indicating that a normal programming operation has been performed on the selected memory block in the block management table 113.

[0050] In some embodiments, the risk block management circuit 111 may collect at least one of a change trend of the temperature measured by the temperature sensor 130, a cell characteristic of a memory cell of the memory cell array 121, and a program / erase (P / E) cycle, and adjust a normal range and an abnormal range of the temperature based on the collection result. As a specific example, the risk block management circuit 111 may expand or reduce a specific range based on the collection result, and further deactivate a function corresponding to the range.

[0051] In some embodiments, the storage device 100 may include more storage devices, and the risk block management circuit 111 may differently set the normal range and the abnormal range for each storage device based on at least one of a storage unit characteristic and a P / E cycle.

[0052] In some embodiments, the block management table 113 may include information indicating a storage block corresponding to a risk block type and a storage block corresponding to a normal block type among a plurality of storage blocks of the storage cell array 121. In this specification, a storage block activated as a risk block may be defined as having a risk block type, and a storage block activated as a normal block may be defined as having a normal block type. The block management table 113 may be managed by the risk block management circuit 111. In some embodiments, the block management table 113 may be stored in a buffer memory of the controller 110, and the block management table 113 may be backed up in the storage device 120.

[0053] In some embodiments, the risk block management circuit 111 can identify a risk block from a plurality of storage blocks of the storage cell array 121 by referring to the block management table 113, and control a garbage collection operation on the identified risk block. A risk block is a storage block that is programmed at a temperature within a high temperature range or a low temperature range, and may require intensive management after programming to improve reliability. Therefore, the risk block management circuit 111 can control a garbage collection operation specifically for the risk block, rather than a garbage collection operation that takes into account the number of invalid pages of the existing storage blocks. The specialized garbage collection operation may be referred to as a recycling garbage collection operation.

[0054] In some embodiments, when the number of error bits of the risk block identified by the block management table 113 is greater than a threshold number, the risk block management circuit 111 may control a garbage collection operation on the risk block. In some embodiments, even when the number of error bits of the identified risk block is greater than a threshold number, the risk block management circuit 111 may not immediately control the garbage collection operation on the risk block, but may control the garbage collection operation only when a predetermined condition is met. For example, the predetermined condition may include at least one of the following: a condition that the current temperature measured by the temperature sensor 130 for performing the garbage collection operation is within a normal range, and / or a condition that the garbage collection operation is urgently needed. The detailed embodiments of the above will be described below.

[0055] In some embodiments where a plurality of storage blocks of a storage cell array 121 of a storage device 120 are operated as different level cells, the concept of the present invention may be applied as follows. In the following embodiments, the following is described as a premise, but this is a non-limiting example, and the concept of the present invention is not limited thereto: a plurality of storage blocks of a storage cell array 121 include a first storage block operated as a single-level cell so that data containing 1 bit is stored in one storage cell and a second storage block operated as a multi-level cell so that data containing 2 bits is stored in one storage cell. In addition, the second storage block may be operated as a three-level cell, a four-level cell, etc., but in the following embodiments, examples where they are operated as multi-level cells will be mainly described.

[0056] In some embodiments, in response to a write request received from the host 11, the risk block management circuit 111 may perform control so that the data received together with the write request is preferentially programmed into the first storage block of the memory cell array 121. That is, the risk block management circuit 111 may use the first storage block as a buffer to preferentially store the data in the first storage block regardless of the current temperature. In some embodiments, as described above, when the first storage block is unavailable due to its capacity limitation, the risk block management circuit 111 may activate any one of the second storage blocks as a risk block or a normal block based on the current temperature, and control the programming operation corresponding to the activated block.

[0057] In some embodiments, the risk block management circuit 111 may control an operation of migrating data temporarily stored in the first storage block to any one of the second storage blocks of the storage cell array 121 within a preset time period. As a specific example, the risk block management circuit 111 may receive the current temperature of the storage device 100 from the temperature sensor 130 for the data migration operation. When the current temperature is within an abnormal range, the risk block management circuit 111 may activate any one of the second storage blocks as a risk block, and then control the high-reliability data migration operation by using the risk block. In addition, when the current temperature is within a normal range, the risk block management circuit 111 may activate any one of the second storage blocks as a normal block, and then control the normal data migration operation by using the normal block.

[0058] In some embodiments, the high-reliability data migration operation may include the high-reliability programming operation described above, and the normal data migration operation may include the normal programming operation described above.

[0059] In some embodiments, each of the risk block management circuit 111 and the program control circuit 123 can be implemented as a software component, a hardware component, or a component of a combination of software and hardware. In addition, the operation of the risk block management circuit 111 can be understood as the operation of the controller 110, and the operation of the program control circuit 123 can be understood as the operation of the storage device 120.

[0060] When the temperature at the time point of performing the programming operation is within the abnormal range, the storage device 100 according to some embodiments can dynamically activate the risk block and adaptively perform a high reliability programming operation or a data migration operation using the activated risk block, thereby ensuring the maximum reliability of the data programmed in the abnormal range. In addition, the storage device 100 can improve the reliability of the data programmed in the abnormal range by performing a garbage collection operation specifically for the risk block. Therefore, even under temperature conditions outside the normal range, the storage device 100 can improve the overall performance of the storage system 10 by ensuring an excellent level of data reliability.

[0061] Figure 2 According to some embodiments Figure 1 Detailed block diagram of the controller 110.

[0062] refer to Figure 2 , the controller 110 may include a risk block management circuit 111, a processor 112, a block management table 113, a volatile memory device 114, an error correction code (ECC) engine 115, a host interface circuit 116, a command manager 117, a memory interface circuit 118, and a bus 119. In some embodiments, the controller 110 may be referred to as a storage controller or a memory controller. Each of the risk block management circuit 111, the ECC engine 115, and the command manager 117 may be implemented as a software component, a hardware component, or a component of a combination of software and hardware. In some embodiments, in the case where at least one of the risk block management circuit 111, the ECC engine 115, and the command manager 117 is implemented as a software component, the software component may be loaded into the volatile memory device 114 and then executed by the processor 112. In addition, the block management table 113 may be stored in the volatile memory device 114 and managed by the risk block management circuit 111.

[0063] In some embodiments, the processor 112 may control the overall operation of the controller 110. The processor 112 may include a flash translation layer (FTL) component, and may perform logic mapping, existing garbage collection, wear leveling, bad block management, error handling, flash memory recovery (data recovery), etc. through the FTL component.

[0064] In some embodiments, in order to control the response from the host 11 (see Figure 1 ) write request, the risk block management circuit 111 may be based on the storage device 100 (see Figure 1 ) will cause the temperature of the memory cell array 121 (see Figure 1 ) is dynamically activated as a risk block. The risk block management circuit 111 may store information indicating that the storage block is activated as a risk block in the block management table 113. The risk block management circuit 111 may control the high reliability programming operation on the risk block.

[0065] In some embodiments, the risk block management circuit 111 may control the garbage collection operation on the risk block by referring to the block management table 113. The risk block management circuit 111 may read the data stored in the risk block and correct errors in the read data through the ECC engine 115. The risk block management circuit 111 may count the number of error bits between the corrected data and the read data, and when the number of error bits is greater than a threshold number, initiate the garbage collection operation on the risk block.

[0066] In some embodiments, in order to control the data migration operation, the risk block management circuit 111 may be based on the storage device 100 (see Figure 1 ) will cause the temperature of the memory cell array 121 (see Figure 1 ) is dynamically activated as a risk block. The risk block management circuit 111 may store information indicating that the storage block is activated as a risk block in the block management table 113. The risk block management circuit 111 may control the high reliability data migration operation on the risk block.

[0067] In some embodiments, since a high reliability programming operation using a risk block requires a longer programming period than a normal programming operation using a normal block, even if the current temperature is within an abnormal range, the risk block management circuit 111 may control a normal programming operation when a specific condition is satisfied. For example, the specific condition refers to an environment in which a time period for programming is limited, and may be determined based on whether the amount of data requested to be input / output per unit time by the host 11 is greater than or equal to a threshold value.

[0068] Command manager 117 may generate instructions to be sent by storage device 120 (see Figure 1 ) commands for various operations performed by the command manager 117. In some embodiments, the command manager 117 may generate a first program command for controlling a high reliability programming operation and a second program command for controlling a normal programming operation. The mode of the first program command and the mode of the second program command may be different from each other. In addition, the first program command may include different modes when controlling a first high reliability programming operation corresponding to a high temperature range and when controlling a second high reliability programming operation corresponding to a low temperature range.

[0069] The controller 110 can communicate with the host 11 (see Figure 1 ) communication. In some embodiments, the host interface circuit 116 may be implemented based on at least one of various interfaces such as Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), or Universal Flash Storage (UFS).

[0070] The controller 110 can communicate with the storage device 120 (see Figure 1 In some embodiments, the memory interface circuit 118 may be implemented based on a NAND interface.

[0071] Figure 2 The implementation example of the controller 110 shown in is a non-limiting example, and the inventive concept is not limited thereto, and according to the present disclosure, the controller 110 may be implemented in various ways to effectively control operations to ensure reliability.

[0072] Figure 3 According to some embodiments Figure 1 Detailed block diagram of the storage device 120.

[0073] refer to Figure 3 , the memory device 120 may include a memory cell array 121 , a control logic 122 , a voltage generator 124 , a row decoder 125 , a page buffer unit 126 , a column decoder 127 , and an input / output (I / O) circuit 128 .

[0074] In some embodiments, control logic 122 may include programming control circuit 123. Control logic 122 may be controlled from controller 110 (see Figure 1 ) receives a command CMD and an address ADD. The command CMD may be a signal indicating a read operation, a program operation (eg, a high reliability program operation or a normal program operation), an erase operation, etc. The address ADD may include a row address ADDR and a column address ADDC.

[0075] In some embodiments, the program control circuit 123 may perform any of the above-mentioned high reliability programming operations and / or normal programming operations for performing a temperature-based programming operation. For example, the program control circuit 123 may perform a first high reliability programming operation based on a programming parameter set to a first value in a high temperature range, may perform a second high reliability programming operation based on a programming parameter set to a second value in a low temperature range, and may perform a normal programming operation based on a programming parameter set to a third value in a normal range. In addition, the operation of the program control circuit 123 may be understood as the operation of the control logic 122.

[0076] In some embodiments, the programming parameters may include parameters related to adjustable points in the programming operation, such as parameters related to the number of programming loops or parameters related to the voltage level of the programming voltage or the verification voltage. In some embodiments, the first value, the second value, or the third value of the programming parameter may be adjusted according to the operating environment of the storage device 120, for example, the P / E cycle, the operating temperature, or the characteristics of the storage cell. In addition, the value of the programming parameter may be preset so that the high temperature range or the low temperature range is subdivided into sub-ranges, so that a high reliability programming operation corresponding to each sub-range may be performed by the programming control circuit 123.

[0077] The voltage generator 124 may control a voltage (eg, a program voltage, a verification voltage, or an erase voltage) applied to the memory cell array 121 through the row decoder 125 under the control of the control logic 122 .

[0078] The row decoder 125 may receive a row address ADDR from the control logic 122. The row decoder 125 may be connected to the memory cell array 121 through a string selection line SSL, a word line WL, and a ground selection line GSL. The row decoder 125 may decode the row address ADDR and control voltages applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on a result of the decoding and a voltage received from the voltage generator 124.

[0079] The memory cell array 121 may include a plurality of memory blocks BLK1 to BLKi. The memory blocks BLK1 to BLKi may be physical erase units of the memory device 120. In this specification, an embodiment of controlling a high reliability programming operation by performing management in memory block units is mainly disclosed, but the inventive concept is not limited thereto, and a high reliability programming operation may be performed by performing management in page units, word line units, sub-block units, etc.

[0080] The memory blocks BLK1 to BLKi may include a plurality of memory cells. In some embodiments, each of the memory blocks BLK1 to BLKi may be operated as any one of a single level cell, a multi level cell, a triple level cell, a quad level cell, etc.

[0081] The page buffer unit 126 may include a plurality of page buffers. The page buffer unit 126 may be connected to the memory cell array 121 through the bit line BL. The page buffer unit 126 may read data from the memory cell array 121 in units of pages by detecting the voltage of the bit line BL under the control of the control logic 122.

[0082] The column decoder 127 may receive a column address ADDC from the control logic 122. The column decoder 127 may decode the column address ADDC, and provide the data read by the page buffer unit 126 to the I / O circuit 128 based on the result of the decoding. In addition, the column decoder 127 may receive data DATA from the I / O circuit 128 through the data line DL. The column decoder 127 may decode the column address ADDC, and provide the data DATA received from the I / O circuit 128 to the page buffer unit 126 based on the result of the decoding. The page buffer unit 126 may store the data provided from the I / O circuit 128 through the bit line BL in the memory cell array 121 in units of pages.

[0083] The I / O circuit 128 can be connected to the column decoder 127 through the data line DL. The I / O circuit 128 can be connected to the column decoder 127 through the data line DL. Figure 1 ) is transmitted to the column decoder 127. The I / O circuit 128 may output the data DATA received through the data line DL to the controller 110 (see Figure 1 ).

[0084] Figure 4A and Figure 4B It is used to describe the Figure 1 Diagram of a three-dimensional V-NAND structure of storage device 100. Figure 4A and Figure 4B Show Figure 3 The structure of the storage block BLKi.

[0085] Reference Figure 4A , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. For the sake of simplicity of the drawings, Figure 4A It is illustrated that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8 , but the inventive concept is not limited thereto.

[0086] The string selection transistor SST may be connected to the corresponding string selection line SSL1, SSL2, or SSL3. A plurality of memory cells MC1 to MC8 may be connected to the corresponding gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1-GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the corresponding ground selection line GSL1, GSL2, or GSL3. The string selection transistor SST may be connected to the corresponding bit line BL1, BL2, or BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0087] Gate lines (eg, GTL1 ) of the same height may be connected in common, and ground selection lines GSL1 , GSL2 , and GSL3 and string selection lines SSL1 , SSL2 , and SSL3 may be separated from each other. Figure 4A It is shown that the memory block BLKi is connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 , BL2 , and BL3 , but the inventive concept is not limited thereto.

[0088] Further references Figure 4B , the memory blocks BLKi are formed in a direction perpendicular to the substrate SUB. The memory cells included in the memory NAND strings NS11 to NS33 are formed by stacking on a plurality of semiconductor layers.

[0089] A common source line CSL extending in a first direction (Y direction) is provided on a substrate SUB. A plurality of insulating layers IL extending in the first direction may be sequentially provided in a region between two adjacent common source lines CSL of the substrate SUB in a third direction (Z direction), and the plurality of insulating layers IL may be spaced apart from each other by a specific distance along the third direction (Z direction). A plurality of pillars P may be sequentially arranged in a region between two adjacent common source lines CSL of the substrate SUB in a first direction (Y direction) to penetrate the plurality of insulating layers IL in the third direction (Z direction). The plurality of pillars P may penetrate the plurality of insulating layers IL to contact the substrate SUB. The surface layer S of each pillar P may include a silicon material doped to a first conductivity type and may be used as a channel region.

[0090] The inner layer I of each pillar P may include an insulating material, such as silicon oxide, or an air gap. In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surfaces of the insulating layer IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunnel insulating layer"), a charge trapping layer, and a blocking insulating layer. In addition, in the region between two adjacent common source lines CSL, gate electrodes GE such as selection lines GSL and SSL and word lines WL1 to WL8 are provided on the exposed surface of the charge storage layer CS. Drains or drain contacts DR may be provided on a plurality of pillars P, respectively. Bit lines BL1 to BL3 extending in the second direction (X direction) and spaced a certain distance from each other in the first direction (Y direction) may be provided on the drain contact DR.

[0091] like Figure 4B As shown, each of the memory NAND strings NS11 to NS33 can be implemented in a structure of stacking a first memory stack ST1 and a second memory stack ST2. The first memory stack ST1 is connected to a common source line CSL, the second memory stack ST2 is connected to bit lines BL1 to BL3, and the first memory stack ST1 and the second memory stack ST2 are stacked to share channel holes with each other.

[0092] Figure 5 is a flowchart for describing a method of operating a storage device according to some embodiments.

[0093] refer to Figure 5 , in operation S100 , the storage device may receive a write request from a host.

[0094] In operation S110, the storage device may measure a current temperature of the storage device before controlling a program operation in response to a received write request. The storage device may measure the temperature of the storage device by at least one temperature sensor disposed therein.

[0095] In operation S120, the storage device may determine whether the current temperature measured in operation S110 is within a normal range. A normal range and an abnormal range may be preset, and a temperature outside the normal range may be determined to be within the abnormal range. As described above, the abnormal range may include a high temperature range and a low temperature range.

[0096] When the determination result in operation S120 is "no", in operation S130, the storage device may activate the risk block to perform the high reliability programming operation according to the write request. In detail, the storage device may dynamically select any one storage block of the storage device as a risk block, perform the high reliability programming operation by using the selected storage block, and store information indicating that the selected storage block has been selected as a risk block in the block management table.

[0097] When the determination result in operation S120 is "yes", in operation S140, the storage device may activate the normal block to perform a normal programming operation according to the write request. In detail, the storage device may dynamically select any one storage block of the storage device as a normal block, perform a normal programming operation by using the selected storage block, and store information indicating that the selected storage block has been selected as a normal block in the block management table.

[0098] Figure 6 It is used to describe in detail Figure 5 FIG. 1 is a flowchart of an operating method of a storage device in operation S130.

[0099] Reference Figure 6 , Figure 5 Operation S130 may include operations S131 to S133.

[0100] In operation S131, the storage device may determine Figure 5 Whether the current temperature measured in operation S110 is within the high temperature range.

[0101] When the determination result in operation S131 is “yes”, in operation S132 , the storage device may activate the risk block to perform a first high-reliability program operation.

[0102] When the determination result in operation S131 is “No”, in operation S133 , the storage device may determine that the current temperature is within the low temperature range and activate the risk block to perform the second high reliability program operation.

[0103] Figure 7 is a diagram for describing a programming operation according to some embodiments in detail. Figure 7 An example of a program operation on a memory cell operating as a triple level cell is shown, but the inventive concept is not limited thereto and may also be applied to a program operation on a memory cell operating as a single level cell, a multi level cell, a quad level cell, etc.

[0104] refer to Figure 7 The temperature range in which the storage device can operate may include a normal range TEMP_NR, a high temperature range TEMP_HR, and a low temperature range TEMP_LR, and the high temperature range TEMP_HR and the low temperature range TEMP_LR may be included in the abnormal range. The high temperature range TEMP_HR may be determined according to a first threshold temperature HT_TH, and the low temperature range TEMP_LR may be determined according to a second threshold temperature LT_TH.

[0105] In some embodiments, the storage device may perform a first high reliability programming operation at a temperature within a high temperature range TEMP_HR, a second high reliability programming operation at a temperature within a low temperature range TEMP_LR, and a normal programming operation at a temperature within a normal range TEMP_NR.

[0106] In some embodiments, threshold voltage distributions of the erase state E and program states P1 to P7 formed by the first high reliability program operation may have sharper shapes than threshold voltage distributions formed by the second high reliability program operation and the normal program operation.

[0107] In some embodiments, a gap between the threshold voltage distribution of the erase state E formed by the second high reliability program operation and the threshold voltage distribution of the first program state P1 may be greater than gaps in the first high reliability program operation and the normal program operation.

[0108] In some embodiments, when programming the same amount of data, the second programming period tPROG2 required to perform the second high reliability programming operation may be longer than the third programming period tPROG3 required to perform the normal programming operation, and the first programming period tPROG1 required to perform the first high reliability programming operation may be longer than the second programming period tPROG2.

[0109] In some embodiments, when the same amount of data is programmed, the number of programming loops performed in the second high-reliability programming operation may be greater than the number of programming loops performed in the normal programming operation, and the number of programming loops performed in the first high-reliability programming operation may be greater than the number of programming loops performed in the second high-reliability programming operation.

[0110] Furthermore, in some embodiments, in the first high reliability programming operation, the second high reliability programming operation, and the normal programming operation, at least one of a voltage offset in an incremental step pulse programming (ISPP) scheme, a level of a programming voltage, and a voltage level of a verification voltage may be different from each other.

[0111] Fig. 8A and Figure 8Bis a diagram for describing in detail first and second high-reliability programming operations according to some embodiments.

[0112] refer to Fig. 8A The high temperature range TEMP_HR may include a first sub-range SR1 and a second sub-range SR2. The memory device may perform a first high reliability program operation based on a first setting in the first sub-range SR1 and a second high reliability program operation based on a second setting in the second sub-range SR2.

[0113] In some embodiments, the threshold voltage distribution of the erased state E and the program states P1 to P7 formed by the first high reliability programming operation based on the first setting may have a sharper shape than the threshold voltage distribution formed by the first low high reliability programming operation based on the second setting. In addition, when programming the same amount of data, the first programming time period tPROG1_1 required to perform the first high reliability programming operation based on the first setting may be longer than the second programming time period tPROG1_2 required to perform the first high reliability programming operation based on the second setting.

[0114] To this end, the first setting may be set to have a greater number of program loops than the second setting, and further, in the ISPP scheme, the first setting may be set to have a smaller voltage offset than the second setting.

[0115] Fig. 8A The illustrated embodiment is an example, and the inventive concept is not limited thereto, and the memory device may subdivide the high temperature range TEMP_HR into three sub-ranges or more in order to perform the first high reliability program operation according to various settings.

[0116] Further references Figure 8B The low temperature range TEMP_LR may include a third sub-range SR3 and a fourth sub-range SR4. The storage device may perform a second high reliability program operation based on a third setting in the third sub-range SR3 and a second high reliability program operation based on a fourth setting in the fourth sub-range SR4.

[0117] In some embodiments, a first gap D1 between a threshold voltage distribution of an erased state E and a threshold voltage distribution of a first program state P1 formed by a second high reliability program operation based on the third setting may be greater than a second gap D2 in a second high reliability program operation based on the fourth setting. In addition, when the same amount of data is programmed, a second programming time period tPROG2_1 required to perform a second high reliability program operation based on the third setting may be longer than a second programming time period tPROG2_2 required to perform a second high reliability program operation based on the fourth setting.

[0118] To this end, the third setting may be set so that the voltage level of the verification voltage for distinguishing between the erase state E and the first program state P1 is higher than that of the fourth setting, and further, the third setting may be set to have a greater number of program loops than the fourth setting.

[0119] Figure 8B The illustrated embodiment is an example, and the inventive concept is not limited thereto, and the storage device may subdivide the low temperature range TEMP_LR into three sub-ranges or more in order to perform the second high reliability program operation according to various settings.

[0120] Fig.9A A method of operating a storage device in a high temperature range according to some embodiments is shown, and Fig. 9B and Fig. 9C is a diagram for describing block management tables TB1_1A and TB1_1B according to some embodiments.

[0121] refer to Fig.9A In operation S200, when the current temperature is within the high temperature range, the storage device may select any one of the plurality of storage blocks as a target of a high reliability programming operation. That is, the storage device may activate any one of the plurality of storage blocks as a risk block.

[0122] In operation S210 , the storage device may store the selection result of operation S200 in a block management table.

[0123] Further references Fig. 9B , the block management table TB1_1A may include a block number for identifying a corresponding storage block and a type indication of a corresponding storage block type. In some embodiments, the block management table TB1_1A may include information indicating that a storage block with a block number of “#1” is a normal block type TYPE_1, and information indicating that storage blocks with block numbers of “#2” and “#3” are risk block type TYPE_2.

[0124] Further references Fig. 9C ,and Fig. 9B In some embodiments, the block management table TB1_1B may include information that distinguishes between storage blocks activated as risk blocks in a high temperature range and storage blocks activated as risk blocks in a low temperature range. In some embodiments, the block management table TB1_1B may include information indicating that a storage block with a block number of "#2" is a risk block type TYPE_2 activated in a high temperature range, and information indicating that a storage block with a block number of "#3" is a risk block type TYPE_3 activated in a low temperature range.

[0125] Fig.10 is a flowchart for describing a method of operating a storage device according to some embodiments.

[0126] refer to Fig.10 , in operation S300 , the storage device may receive a write request from a host.

[0127] In operation S310, in response to the write request received in operation S300, the storage device may preferentially program data received from the host into a single-level cell (SLC) block among a plurality of memory blocks of the storage device. In this specification, an SLC block may be defined as a memory block operating as an SLC.

[0128] In operation S320, before performing an operation of migrating data stored in an SLC block to a multi-level cell (MLC) block, the storage device may determine whether the current temperature is within a normal range. In this specification, an MLC block may be defined as a storage block operated as an MLC. In some embodiments, an MLC block as a destination of a data migration operation may be replaced with a triple-level cell (TLC) block or a quad-level cell (QLC) block. In addition, in some embodiments, an SLC block on which a programming operation is preferentially performed may be replaced with an MLC block, and in this case, an MLC block as a destination of a data migration operation may be replaced with a storage block operated as a higher-level cell than an MLC.

[0129] When the determination result in operation S320 is “No”, in operation S330 , the storage device may wait for a preset period of time so that the temperature within the abnormal range is stabilized.

[0130] When the determination result in operation S320 is "yes", in operation S340, the storage device may activate the normal block to perform a normal data migration operation. As a specific example, the storage device may activate any one of the plurality of storage blocks as a normal block and migrate the data stored in the SLC block to the activated normal block as a destination. The normal data migration operation may include the above-mentioned normal programming operation using the normal block.

[0131] In operation S350 , the storage device may determine again whether the temperature after waiting in operation S330 is within a normal range.

[0132] When the result of the determination in operation S350 is "No", in operation S360, the storage device may activate the risk block to perform a high reliability data migration operation. As a specific example, the storage device may activate any one of the plurality of storage blocks as a risk block and migrate the data stored in the SLC block to the activated risk block as a destination. The high reliability data migration operation may include the above-mentioned high reliability programming operation using the risk block.

[0133] When the determination result in operation S350 is "yes", operation S340 may be performed. A detailed description of operation S340 is described above, and thus a description thereof will be omitted.

[0134] Fig.11 is a flow chart for describing garbage collection operations of a storage device according to some embodiments.

[0135] refer to Fig.11 In operation S400, the storage device may identify a risk block based on a block management table. As a specific example, the block management table may include information indicating whether any one of a plurality of storage blocks of the storage device is a normal block type or a risk block type, and the storage device may identify a block number of a storage block of the risk block type from the block management table.

[0136] In operation S410, the storage device may perform an error bit counting operation on the risk block identified in operation S400. As a specific example, the storage device may read data stored in the risk block and correct errors in the read data. The storage device may count different bits between the error correction data and the read data as error bits.

[0137] In operation S420 , the storage device may determine whether the number of error bits counted in operation S410 is greater than a threshold number.

[0138] When the determination result in operation S420 is “yes”, in operation S430 , the storage device may perform a garbage collection operation on the risk block.

[0139] When the determination result in operation S420 is "No", operation S410 may be performed after a preset period of time.

[0140] Fig. 12A and Fig. 12B Is used to describe Fig.11 FIG. 1 is a flowchart of an operating method of a storage device in operation S410.

[0141] Reference Fig. 12A , Fig.11 Operation S410 may include operations S411A and S412A.

[0142] In operation S411A, the storage device may measure a current temperature of the storage device for performing the garbage collection operation.

[0143] In operation S412A, the storage device may adjust the threshold number based on the temperature measured in operation S411A. As a specific example, the storage device may adjust the threshold number to decrease when the measured temperature increases. In some embodiments, the storage device may adjust the threshold number to increase when the measured temperature increases. In this way, the storage device may adjust the conditions for performing garbage collection operations on risk blocks according to the measured temperature.

[0144] Further references Fig. 12B , Fig.11 Operation S410 may include operations S411B and S412B.

[0145] In operation S411B, the storage device may measure a current temperature of the storage device for performing the garbage collection operation and identify a change trend of a previously measured temperature.

[0146] In operation S412B, the storage device may adjust the threshold number based on the trend identified in operation S411B. As a specific example, the storage device may adjust the threshold number to decrease when the temperature tends to change rapidly. Therefore, the storage device may ensure a certain level of data reliability by quickly responding to sudden changes in temperature to perform garbage collection operations.

[0147] Fig.13A and Fig. 13B It is used to describe in detail Fig.11 FIG. 1 is a flowchart of an operating method of a storage device in operation S410.

[0148] Reference Fig.13A , Fig.11 Operation S410 may include operations S413A and S414A.

[0149] In operation S413A, the storage device may read data stored in a plurality of pages of the risk block.

[0150] In operation S414A, the storage device may perform error correction on the data read in operation S413A to count error bits.

[0151] Further references Fig. 13B , Fig.11 Operation S410 may include operations S413B and S414B.

[0152] In operation S413B, the storage device may read data stored in some pages of the plurality of pages of the risk block. In some embodiments, the pages from which the data is read may include memory cells having poor characteristics and may be predetermined.

[0153] In operation S414B, the storage device may perform error correction on the data read in operation S413B to count error bits. In this way, the storage device may perform a fast and accurate error bit counting operation by concentrating on using data in pages with poor characteristics. At the same time, Fig.13A The threshold number in can be greater than Fig. 13B The number of thresholds in .

[0154] Fig.14 is a flow chart for describing garbage collection operations of a storage device according to some embodiments.

[0155] refer to Fig.14 , in operation S431, the storage device may determine whether to perform a garbage collection operation on the risk block.

[0156] In operation S432, the storage device may measure a current temperature for performing a garbage collection operation, and determine whether the measured current temperature is within a normal range.

[0157] When the determination result in operation S432 is "yes", in operation S433, the storage device may activate the normal block to perform a normal garbage collection operation. In some embodiments, the normal garbage collection operation may include a normal program operation using the target block.

[0158] When the determination result in operation S432 is "No", in operation S434, the storage device may determine whether a garbage collection operation is urgently needed. In some embodiments, the storage device may determine whether a garbage collection operation is urgently needed considering a request from the host, available data capacity of the storage device, and temperature status of the storage device.

[0159] When the determination result in operation S434 is "No", in operation S435, the storage device may wait for a preset period of time so that the temperature within the abnormal range is stabilized. Operation S435 may be followed by operation S432. A detailed description of operation S432 is described above, so its description will be omitted.

[0160] When the determination result in operation S434 is “yes”, in operation S436 , the storage device may activate the risk block to perform a high reliability garbage collection operation. In some embodiments, the high reliability garbage collection operation may include a high reliability program operation using the target block.

[0161] Fig.15A and Fig. 15B is a diagram for describing a garbage collection operation of a storage device according to some embodiments. Fig.15A Shown in Fig.14 The normal garbage collection operation is performed in operation S433, and Fig. 15B Shown in Fig.14 The high reliability garbage collection operation is performed in operation S436.

[0162] refer to Fig.15A The storage device may select a storage block with a block number of "#1" and corresponding to the risk block type TYPE_2 as the victim block VB by referring to the block management table TB1_2A. The storage device may select an empty storage block with a block number of "#2" from multiple storage blocks as the target block TB.

[0163] In some embodiments, the storage device may perform a normal garbage collection operation by using the victim block VB and the target block TB. Specifically, the storage device may store data A' and B' in the target block TB by copying data A and B of the victim block VB to the target block TB according to a normal programming operation, and erase the victim block VB. In some embodiments, the storage device may store data A' and B' generated by performing an error correction operation on data A and B of the victim block VB in the target block TB according to a normal programming operation.

[0164] In some embodiments, the storage device may update the block management table TB1_2A after performing a normal garbage collection operation. Specifically, the storage device may initialize the type indication of the storage block with block number "#1" in the block management table TB1_2A, and store the type of the storage block with block number "#2" as the normal block type TYPE_1.

[0165] Further references Fig. 15B ,and Fig.15A Different from the example shown, the storage device can perform a high-reliability garbage collection operation by using the victim block VB and the target block TB. Specifically, the storage device can store data A" and B" in the target block TB by copying the data A and B of the victim block VB according to the high-reliability programming operation, and erase the victim block VB. In some embodiments, the storage device can store data A" and B" generated by performing an error correction operation on the data A and B of the victim block VB in the target block TB according to the high-reliability programming operation.

[0166] In some embodiments, the storage device may update the block management table TB1_2B after performing a high reliability garbage collection operation. Specifically, the storage device may initialize the type indication of the storage block with block number "#1" in the block management table TB1_2B, and store the type of the storage block with block number "#2" as the risk block type TYPE_2.

[0167] Fig.16 is a diagram for describing a garbage collection operation of a storage device according to some embodiments. Fig.16 Shown in Fig.14 The garbage collection operation performed in operation S433 or operation S436.

[0168] refer to Fig.16 , the storage device can select the storage block with block number "#1" corresponding to the risk block type TYPE_2 and the storage block with block number "#2" corresponding to the risk block type TYPE_2 as the first victim block VB1 and the second victim block VB2 by referring to the block management table TB1_2C. The storage device can select an empty storage block with block number "#3" from multiple storage blocks as the target block TB.

[0169] In some embodiments, the storage device may perform a garbage collection operation by using the first victim block VB1 and the second victim block VB2 and the target block TB. Specifically, the storage device may store data A', B', C', and D' in the target block TB by copying the data A, B, C, and D of the first victim block VB1 and the second victim block VB2 to the target block TB according to a normal or high reliability programming operation, and erase the victim block VB (i.e., the first victim block VB1 and the second victim block VB2). In some embodiments, the storage device may store data A', B', C', and D' generated by performing error correction on the data A, B, C, and D of the first victim block VB1 and the second victim block VB2 in the target block TB.

[0170] In some embodiments, the storage device may update the block management table TB1_2C after performing the garbage collection operation. Specifically, the storage device may initialize the type indications of the storage blocks with block numbers "#1" and "#2" in the block management table TB1_2C, and store the type of the storage block with block number "#3" as a normal block type TYPE_1 or a risk block type TYPE_2.

[0171] Meanwhile, in some embodiments, the second victim block VB2 is a normal block and may include multiple invalid pages, and through a garbage collection operation, data C and D of valid pages of the second victim block VB2 may be stored in the target block TB together with data A and B of the first victim block VB1 as a risk block.

[0172] Fig.17 is a flowchart for describing a method of operating a storage device according to some embodiments.

[0173] refer to Fig.17 , in operation S500, the storage device may receive a write request from a host.

[0174] In operation S510 , the storage device may measure a current temperature of the storage device before controlling a program operation in response to a received write request.

[0175] In operation S520 , the storage device may determine whether the current temperature measured in operation S510 is within a normal range.

[0176] When the result of the determination in operation S520 is "No", in operation S530, the storage device may predict the amount of data requested to be input / output per unit time by the host. In some embodiments, the storage device may predict the amount of data requested to be input / output per unit time based on the number of requests received from the host within a preset time period. In some embodiments, the storage device may predict the amount of data requested to be input / output per unit time based on a signal received from the host.

[0177] The reason why the storage device predicts the amount of data requested for input / output per unit time and considers the prediction in the programming operation is that when the amount of data requested for input / output per unit time is greater than or equal to the threshold, supporting fast delay is the most important. That is, as described above, when the amount of data requested for input / output per unit time is greater than or equal to the threshold, it can be determined that the environment has a limited time period for programming, and therefore, a normal programming operation requiring a relatively short programming time period can be performed. However, this is only some embodiments, and the inventive concept is not limited thereto, and an environment in which the time period for programming is limited can be determined in various ways based on various criteria.

[0178] When the determination result in operation S520 is “yes”, in operation S540 , the storage device may activate the normal block to perform a normal program operation according to the write request.

[0179] In operation S550 , the storage device may determine whether the amount of data requested to be input / output predicted in operation S530 is less than a threshold value.

[0180] When the result of the determination in operation S550 is "No", in operation S560, the storage device may store information indicating that the predicted data amount of the requested input / output is greater than or equal to the threshold value in the data refresh table, and thus, perform a normal program operation with a fast delay even at a temperature within the abnormal range. In some embodiments, the data refresh table may be included in Figure 1 The block management table 113 and can be Figure 1 The risk block management circuit 111 manages. Thereafter, operation S540 may be performed, a detailed description of which is as described above and thus will be omitted.

[0181] When the determination result in operation S550 is “yes”, in operation S570 , the storage device may activate the risk block to perform the high reliability program operation.

[0182] Fig.18A and Fig.18B is a flowchart for describing operations of managing a data refresh table of a storage device according to some embodiments. Fig.18A Shown in Fig.17 The normal programming operation performed in operation S540 is performed after operation S560, and Fig.18B Shown in Fig.17 The high reliability programming operation is performed in step S570.

[0183] Reference Fig.18A, the storage device may perform a normal programming operation by using the second storage block BLK2 having a block number of “#2” among the plurality of storage blocks BLK1 to BLKi. Thereafter, the storage device may store information indicating that the second storage block BLK2 having a block number of “#2” corresponds to the normal block type TYPE_1 in the block management table TB1, and store a value “V2” indicating that a data refresh operation is required for the second storage block BLK2 having a block number of “#2” in the data refresh table TB2.

[0184] Further references Fig.18B , the storage device may perform a high reliability programming operation by using the second storage block BLK2 with a block number of “#2” among the plurality of storage blocks BLK1 to BLKi. Thereafter, the storage device may store information indicating that the second storage block BLK2 with a block number of “#2” corresponds to the risk block type TYPE_2 in the block management table TB1, and store a value “V1” indicating that a data refresh operation is not required for the second storage block BLK2 with a block number of “#2” in the data refresh table TB2. In the present specification, the data refresh operation may include a garbage collection operation.

[0185] Fig.19 It is used to describe in detail Fig.17 FIG. 5 is a flowchart of an operating method of a storage device in operation S550.

[0186] Reference Fig.19 , Fig.17 Operation S550 may include operation S551.

[0187] In operation S551, the storage device may be based on the Fig.17 ) in the storage device. As a specific example, the storage device can adjust the threshold value to decrease when the measured temperature increases. In some embodiments, the storage device can adjust the threshold value to increase when the measured temperature increases. In this way, the storage device can adjust the environment where the time period for programming is limited according to the measured temperature.

[0188] Fig. 20 is a flowchart for describing a data refresh operation of a storage device according to some embodiments.

[0189] refer to Fig. 20 In operation S600, the storage device may select at least one victim block based on the data refresh table. Specifically, the storage device may select at least one normal block on which a normal program operation has been performed in the abnormal range as at least one victim block by referring to the data refresh table.

[0190] In operation S610 , as part of a data refresh operation, a storage device may measure a current temperature for performing a garbage collection operation.

[0191] In operation S620, the storage device may determine whether the current temperature measured in operation S610 is within a normal range.

[0192] When the determination result in operation S620 is “yes”, in operation S630 , the storage device may perform a garbage collection operation on the at least one victim block selected in operation S600 .

[0193] When the determination result in operation S620 is "No", operation S610 may be performed after a preset period of time.

[0194] Fig.21 is a flowchart for describing a method of operating a storage device according to some embodiments.

[0195] refer to Fig.21 In operation S700, the storage device may collect at least one of storage cell characteristics of a plurality of storage cells of the storage device, a P / E cycle of the storage device, and / or a temperature change trend.

[0196] In operation S710, the storage device may adjust the range related to the temperature based on the collected results in operation S700. In some embodiments, the storage device may adjust the width, position on the temperature axis, etc. of at least one of the normal range and the abnormal range based on the collected results. In addition, the storage device may adjust the width, position on the temperature axis, etc. of at least one of the high temperature range and the low temperature range based on the collected results.

[0197] Fig. 22 is a block diagram illustrating a memory card system 1000 according to some embodiments.

[0198] Reference Fig. 22 , the memory card system 1000 may include a host 1100 and a memory card 1200. The memory card 1200 may be an application Figure 1 The host 1100 may include a host controller 1110 and a host connection unit 1120 . The memory card 1200 may include a card connection unit 1210 , a card controller 1220 , and a flash memory 1230 .

[0199] The host 1100 may write data to the memory card 1200 or read data stored in the memory card 1200. The host controller 1110 may send a request (e.g., a write request), a clock signal CLK generated by a clock generator in the host 1100, and data DATA to the memory card 1200 through the host connection unit 1120. In response to the write request received through the card connection unit 1210, the card controller 1220 may store data in the flash memory 1230 in synchronization with the clock signal generated by the clock generator in the card controller 1220. The flash memory 1230 may store data sent from the host 1100.

[0200] The card controller 1220 according to some embodiments may measure the internal temperature of the memory card 1200, and based on the measured temperature, activate a risk block among the memory blocks of the flash memory 1230 to control any one of a high reliability programming operation, a high reliability data migration operation, and a high reliability garbage collection operation. In addition, the card controller 1220 may manage a block management table for seamlessly controlling the above-mentioned high reliability memory operations.

[0201] Fig.23 is a block diagram illustrating a solid state drive (SSD) system 2000 according to some embodiments.

[0202] refer to Fig.23 , the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may be an application Figure 1 and storage devices of the embodiments shown in other figures.

[0203] The SSD 2200 may exchange signals with the host 2100 through a signal connector 2211, and may receive power through a power connector 2221. The SSD 2200 may include a plurality of flash memories 2201, 2202, ..., 220n, an SSD controller 2210, and an auxiliary power supply 2220. The plurality of flash memories 2201, 2202, ..., 220n may be used as storage media of the SSD 2200. In addition to the flash memory, the SSD 2200 may also use a nonvolatile storage device such as a PRAM, an MRAM, a resistive RAM (ReRAM), or a FRAM.

[0204] A plurality of flash memories 2201, 2202, ..., 220n may be connected to the SSD controller 2210 through a plurality of channels CH1 to CHn. One or more flash memories may be connected to one channel. The flash memories connected to one channel may be connected to the same data bus. The SSD controller 2210 may exchange signals SGL with the host 2100 through a signal connector 2211. Here, the signal SGL may include a request, an address, data, etc. In response to a request from the host 2100, the SSD controller 2210 may program data into the corresponding flash memory or read data from the corresponding flash memory.

[0205] The auxiliary power supply 2220 may be connected to the host 2100 through the power connector 2221. The auxiliary power supply 2220 may receive the power PWR from the host 2100 and be charged. Meanwhile, the auxiliary power supply 2222 may be inside or outside the SSD 2200. For example, the auxiliary power supply 2220 may be located on the mainboard and may provide auxiliary power to the SSD 2200.

[0206] In some embodiments, the SSD controller 2210 may measure the internal temperature of the SSD 2200, and based on the measured temperature, activate a risk block of any one of the plurality of flash memories 2201, 2202, ..., 220n to control any one of a high reliability programming operation, a high reliability data migration operation, and a high reliability garbage collection operation. In addition, the SSD controller 2210 may manage a block management table for seamlessly controlling the above-mentioned high reliability memory operations.

[0207] In some embodiments, the SSD controller 2210 may classify the flash memory by channel and activate or deactivate the function of each classified flash memory according to the concept of the present invention.

[0208] Embodiments have been described herein and illustrated in the accompanying drawings. Although embodiments have been described herein by using specific terms, they are only used for the purpose of explaining the inventive concept and are not used to limit the meaning or scope of the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments can be derived from the embodiments described herein. Therefore, the true technical protection scope of the inventive concept should be determined by the appended claims.

[0209] As used herein, the terms "comprises," "comprising," "including," "containing," "having," and "having" and any other variations thereof specify the presence of the features, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure.

[0210] While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: A storage device, comprising a plurality of storage blocks, each storage block comprising a plurality of storage units; a controller configured to control a programming operation of a storage device in response to a write request received from a host; as well as A temperature sensor configured to measure the internal temperature, Wherein, the controller is further configured to, based on a first temperature measured by a temperature sensor, activate one of the multiple storage blocks as a risk block and then use the risk block to control a high-reliability programming operation, or activate one of the multiple storage blocks as a first normal block and then use the first normal block to control a normal programming operation.

2. The storage device according to claim 1, wherein: The controller is also configured to perform operations including: when the first temperature is within the high temperature range, controlling a first high reliability programming operation based on a first degradation characteristic of a plurality of memory cells in the high temperature range; When the first temperature is within the low temperature range, controlling a second high reliability program operation based on a second degradation characteristic of the plurality of memory cells in the low temperature range; and When the first temperature is within a normal range, a normal programming operation is controlled.

3. The storage device according to claim 2, wherein: When programming the same amount of data, a programming period for performing a second high reliability programming operation is greater than a programming period for performing a normal programming operation, and a programming period for performing a first high reliability programming operation is greater than a programming period for performing a second high reliability programming operation.

4. The storage device according to claim 2, wherein: The first high reliability programming operation is based on a first programming scheme for making a first threshold voltage distribution of memory cells into which data is programmed sharper than a second threshold voltage distribution formed by a normal programming operation, and In which, the second high-reliability programming operation is based on a second programming scheme, which is used to make the first gap between the threshold voltage distribution in the erased state and the threshold voltage distribution in the first programming state in the first threshold voltage distribution greater than the second gap between the threshold voltage distribution in the erased state and the threshold voltage distribution in the first programming state in the second threshold voltage distribution.

5. The storage device according to claim 2, wherein: The high temperature range includes a plurality of first sub-ranges, and The controller is further configured to control the first high-reliability programming operation based on a setting corresponding to a first sub-range to which the first temperature belongs in the plurality of first sub-ranges.

6. The storage device according to claim 5, wherein: The plurality of first sub-ranges respectively correspond to settings different from each other in at least one of a number of program loops or a voltage shift in an incremental step pulse programming (ISPP) scheme.

7. The storage device according to claim 5, wherein: The low temperature range includes a plurality of second sub-ranges different from the plurality of first sub-ranges, and The controller is further configured to control a second high reliability programming operation based on a setting corresponding to a second sub-range to which the first temperature belongs in the plurality of second sub-ranges.

8. The storage device according to claim 7, wherein: The plurality of second sub-ranges respectively correspond to settings different from each other in voltage levels of verification voltages for distinguishing a threshold voltage distribution in an erase state from a threshold voltage distribution in a first program state.

9. The storage device according to claim 1, wherein: The controller is further configured to activate one of the plurality of memory blocks as a risk block by selecting a memory block that is a target of the high reliability program operation from the plurality of memory blocks and storing information indicating that the high reliability program operation has been performed on the selected memory block in a block management table.

10. The storage device according to claim 1, wherein: The controller is further configured to: identify a risk block based on a block management table, the block management table indicating whether each of the plurality of memory blocks is a risk block type or a normal block type; And when the number of error bits of the identified risk block is greater than a threshold number, a garbage collection operation on the risk block is controlled.

11. The storage device according to claim 10, wherein: The risk block includes a first risk block, and Wherein, the controller is further configured to: based on a second temperature measured by the temperature sensor and at least one of whether a garbage collection operation is urgently needed, activate one of the multiple storage blocks as a second risk block, and then use the second risk block to control a high-reliability garbage collection operation, or activate one of the multiple storage blocks as a second normal block, and then use the second normal block to control a normal garbage collection operation.

12. A storage device comprising: A memory device comprising a first memory block operated as a single level cell and a second memory block operated as a multi-level cell; a controller configured to control a programming operation of a storage device in response to a write request received from a host; as well as A temperature sensor configured to measure the internal temperature, Among them, the programming operation of the storage device in response to the write request includes programming data corresponding to the write request into a first storage block, and based on a first temperature measured by a temperature sensor within a preset time period, activating one of the second storage blocks as a risk block and then controlling a high-reliability data migration operation on the data by using the risk block, or activating one of the second storage blocks as a normal block and then controlling a normal data migration operation on the data by using the normal block.

13. The storage device according to claim 12, wherein: The controller is also configured to perform operations including: controlling a first high reliability programming operation based on first degradation characteristics of a plurality of memory cells included in the second memory block in the high temperature range included in the high reliability data migration operation when the internal temperature is in the high temperature range; When the internal temperature is within the low temperature range, controlling a second high reliability programming operation based on second degradation characteristics of a plurality of memory cells within the low temperature range included in the high reliability data migration operation; and When the internal temperature is within a normal range, a normal programming operation including a normal data migration operation is controlled.

14. The storage device according to claim 12, wherein: The controller is also configured to, when data cannot be stored in the first storage block, activate one of the second storage blocks as a risk block based on a second temperature measured by the temperature sensor and then control a high-reliability programming operation to store the data in the risk block, or activate one of the plurality of second storage blocks as a normal block and then control a normal programming operation to store the data in the normal block.

15. A storage device comprising: A storage device, comprising a plurality of storage blocks, each storage block comprising a plurality of storage units; a controller configured to control a programming operation of the storage device in response to at least one write request received from a host; as well as A temperature sensor configured to measure the internal temperature, Wherein, the controller is further configured to, based on at least one of a first temperature measured by a temperature sensor or whether the environment is restricted during a time period for programming, activate one of the multiple storage blocks as a risk block and then use the risk block to control a high-reliability programming operation, or activate one of the multiple storage blocks as a normal block and then use the normal block to control a normal programming operation.

16. The storage device according to claim 15, wherein: The controller is also configured to perform operations including: When the first temperature is within a normal range, controlling a normal programming operation; and When the first temperature is within the abnormal range, it is determined whether the environment is restricted in a time period for programming, and based on a result of the determination, one of a high reliability program operation or a normal program operation is selectively controlled.

17. The storage device according to claim 16, wherein: The controller is further configured to perform operations including: determining that the environment is restricted in a time period for programming when an amount of data requested to be input / output by the host per unit time is greater than or equal to a threshold value; and When the environment is restricted in the time period for programming, a normal program operation is controlled, and when the environment is not restricted in the time period for programming, a high reliability program operation is controlled.

18. The storage device according to claim 15, wherein: When programming the same amount of data, a programming period for performing a high reliability program operation is greater than a programming period for performing a normal program operation.

19. The storage device according to claim 15, wherein: The controller is further configured to register the normal block in the data refresh table to indicate that a garbage collection operation on the normal block is required when the first temperature is within an abnormal range and a normal programming operation is controlled while the environment is restricted in a time period for programming.

20. The storage device according to claim 19, wherein The controller is further configured to: select a normal block as a victim block based on the data refresh table; and control a garbage collection operation on the victim block when a second temperature measured by the temperature sensor is within a normal range.

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