Thinning method for planarizing front surface of wafer

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a thinning method for planarizing the front surface of a wafer, which comprises the following steps of: 1) spin-coating positive photoresist on the front surface of the wafer to be thinned, arranging a plurality of passivation layers which are arranged at intervals on the front surface of the wafer to be thinned, and enabling the thickness of the photoresist to be equal to that of the passivation layers; (2) the positive photoresist on the passivation layer is removed; (3) a protective film is pasted on the front face of the wafer to be thinned; according to the method, the number and the degree of cracks after the wafer is thinned are reduced, the silicon thickness fluctuation in the wafer is reduced, particularly, the silicon thickness difference in a single chip on the wafer is reduced, meanwhile, the operation is remarkably simplified, and the operation is more convenient.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a thinning method for flattening the front side of a wafer. Background Art

[0002] Power semiconductor chips, such as IGBT (insulated gate bipolar transistor), FRD (fast recovery diode), etc., need to be thinned to improve the performance of the chip, such as reducing the conduction loss. When the thickness of the wafer is less than 200μm (micrometer), the thick wafer is usually thinned by taiko to reach the target thickness. At present, the industry mainly uses mechanical grinding to achieve thinning. Specifically, the grinding wheel of the thinning machine thins the wafer fixed on the grinding table of the thinning machine through high-speed grinding. In order to avoid relative sliding between the wafer and the grinding wheel, the grinding wheel needs to apply a certain pressure to the wafer during the process. Due to the presence of the passivation layer on the front of the wafer, it is uneven and has ups and downs. Cracks are prone to occur near the ups and downs during the wafer thinning process; in addition, the ups and downs cause the thickness of the wafer to fluctuate after thinning, which has an adverse effect on the parameters of the chip. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a thinning method for flattening the front side of the wafer, reducing the crack rate of the wafer after thinning, reducing the fluctuation of silicon thickness in the wafer, especially the thickness uniformity within a single chip on the wafer, while significantly simplifying the operation and making it more convenient.

[0004] The embodiment of the present invention provides a thinning method for planarizing the front side of a wafer, comprising the following steps: 1) Spin-coating a positive photoresist on the front side of the wafer to be thinned, wherein the front side of the wafer to be thinned is provided with a plurality of passivation layers arranged at intervals, and the thickness of the photoresist is equal to the thickness of the passivation layer; 2) removing the positive photoresist on the passivation layer; 3) A protective film is attached to the front side of the wafer to be thinned; 4) Thinning the back side of the wafer to be thinned; 5) Remove the protective film; 6) Remove the positive photoresist to obtain a thinned wafer.

[0005] Optionally, the method for removing the positive photoresist on the passivation layer is to use a mask corresponding to the front side of the wafer to be thinned, and utilize exposure and development processes to remove the positive photoresist on the passivation layer, leaving the positive photoresist between the passivation layers. Since the thickness of the positive photoresist is equal to the thickness of the passivation layer, the entire wafer surface is ultimately flattened.

[0006] Optionally, the shape of the mask corresponds to the passivation layer on the front side of the wafer to be thinned, so that during exposure and development, only the positive photoresist above the passivation layer is exposed and developed.

[0007] Optionally, the thinning method is a taiko thinning process, other conventional thinning processes are also possible, and the taiko thinning process is more preferred.

[0008] Optionally, step 6) is to remove the positive photoresist by cleaning.

[0009] Optionally, the cleaning agent used for cleaning is a solvent that can dissolve the positive photoresist and does not react with the passivation layer.

[0010] Optionally, the size of the wafer is 6-12 inches.

[0011] Optionally, the positive photoresist is an I-Line or KrF photoresist that matches the thickness of the passivation layer.

[0012] Optionally, the distance between the passivation layers is 5-2000 μm.

[0013] Optionally, the specific steps of the exposure and development process are: using a mask so that only a region of the passivation layer is exposed during the exposure process, and the photoresist on the passivation layer is removed after development.

[0014] Optionally, the protective film is a thinned protective tape (BG Tape).

[0015] The beneficial effect of the present invention is that, through the process of the present invention, the step height of the wafer surface can be reduced, and the probability of cracks during the thinning process can be reduced, especially the probability of microcracks in 8-inch and 12-inch thin slices (<200 microns).

[0016] Through the process of the present invention, the thickness consistency of wafers after film lamination can be improved, especially 8-inch and 12-inch large-size wafers, thereby improving the thickness consistency within and between wafers after thinning, especially the thickness uniformity within a single chip on the wafer.

[0017] After filling the photoresist, the present invention only needs to remove the photoresist above the passivation layer to flatten the wafer. The mask for forming the passivation layer is used, the cost is low, and the operation is simple and convenient.

[0018] The solution provided by the present invention has strong applicability and is applicable to all chip manufacturing fields that have high requirements on the thickness consistency of wafers after thinning. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of wafer and surface passivation layer; Figure 2Schematic diagram of spin coating positive photoresist on wafer surface; Figure 3 Schematic diagram of a wafer that has been planarized after exposure and development; Figure 4 Schematic diagram of a wafer with a protective film on the front side; Figure 5 This is a schematic diagram of a wafer after thinning, taking a taiko wafer as an example, the same is true for flat wafers; Figure 6 Schematic diagram of a wafer that has been planarized after exposure and development, using taiko wafer as an example, but the same is true for flat wafers; Figure 7 Schematic diagram of a complete wafer with positive photoresist completely removed, using Taiko wafer as an example. The same is true for flat wafers.

[0020] In the figure, 101 is a wafer body, 102 is a passivation layer, 103 is a positive photoresist, and 104 is a protective film. DETAILED DESCRIPTION

[0021] In order to highlight the features of the present invention, the embodiments focus on describing the process flow of the embodiments of the present invention and the composition of the execution device thereof, while some technical features known in the art are not described.

[0022] Example 1 like Figure 1 As shown, there is a passivation layer 102 with a thickness of H0 on the surface of the wafer body 101, which causes the wafer surface to be uneven.

[0023] A thinning method for planarizing the front side of a wafer comprises the following steps: S1, such as Figure 2 As shown, a layer of positive photoresist 103 is spin-coated on the uneven front surface of the wafer, and the thickness H1 of the positive photoresist 103 is consistent with the thickness H0 of the passivation layer 102 on the front surface of the wafer body 101. The positive photoresist needs to be selected according to the thickness of the passivation layer 102 to ensure that the thickness of the spin-coated positive photoresist 103 can reach the thickness of the passivation layer 102, that is, the thickness of the positive photoresist 103 between the passivation layers 102 is equal to the thickness of the passivation layer 102.

[0024] S2, using exposure and development processes, remove the positive photoresist 103 on the passivation layer 102 to make the front side of the wafer flat. Figure 3 The photoresist (mask) used in the exposure process is designed according to the graphic structure of the passivation layer 102 to ensure that during the exposure process, the positive photoresist 103 on the passivation layer 102 is exposed, and the remaining positive photoresist 103 is not exposed. The positive photoresist 103 on the passivation layer 102 can be removed through the development process, and finally the entire wafer surface is flat.

[0025] S3, such as Figure 4 As shown, a protective film 104 is attached to the front side.

[0026] S4, such as Figure 5 As shown, the back side of the wafer is thinned, and the thinned wafer is taken as an example of a Taiko wafer.

[0027] S5, such as Figure 6 As shown, the wafer front side protection film 104 is torn off.

[0028] The wafer film attaching, thinning and film peeling processes described in S3-S5 are all mature process flows and are necessary process steps in the embodiments, and are not within the scope of protection of the present invention.

[0029] S6, removing the positive photoresist 103 on the front side of the wafer by cleaning, wherein the cleaning solution used to remove the positive photoresist 103 by cleaning is the solvent of the positive photoresist, and it is necessary to confirm that the cleaning solution does not react with the passivation layer 102 on the front side of the wafer. After the positive photoresist 103 is cleaned, the following is finally obtained: Figure 7 The thinned wafer is shown in FIG. 1 , and this embodiment takes a taiko wafer as an example.

[0030] The positive photoresist is I-Line matching the thickness of the passivation layer.

[0031] The distance between the passivation layers is 100 μm.

[0032] The specific steps of the exposure and development process are: using a mask so that only the area of ​​the passivation layer is exposed during the exposure process, and the photoresist on the passivation layer is removed after development.

[0033] The protective film is a thinned protective tape (BG Tape).

[0034] The solution provided by the present invention can effectively reduce the probability of cracks occurring during the thinning process by flattening the wafer surface before thinning and film lamination, and can improve the consistency of thickness within the wafer and between wafers after thinning, which has a significant effect on improving product yield.

[0035] The solution provided by the present invention involves lithography processes (film coating, exposure, and development) that are all commonly used processes in the semiconductor manufacturing industry. The cleaning process can also be implemented using a film coating and development machine. The implementation of this solution does not require the addition of additional new equipment, which greatly reduces the difficulty of process implementation.

[0036] Comparative Example 1 A thinning method for planarizing the front side of a wafer comprises the following steps: S1, spin-coating a layer of negative photoresist on the uneven front side of the wafer, the thickness of the negative photoresist is greater than the thickness of the passivation layer on the front side of the wafer body, so the height of the negative photoresist between the passivation layers is greater than the height of the passivation layer.

[0037] S2, performing wafer edge exposure, so that the negative photoresist covering the wafer edge is exposed to light, and the negative photoresist covering the wafer edge will be insoluble in the developer; S3, the negative photoresist in the grooves between the passivation layers is exposed to light, and the negative photoresist above the passivation layer is not exposed to light, so that after exposure, the negative photoresist in the grooves will not dissolve in the developer, and the negative photoresist above the passivation layer will dissolve in the developer.

[0038] S4, performing development, curing and ashing operations to remove the negative photoresist outside the wafer edge and the groove area, and curing the negative photoresist at the wafer edge and in the groove.

[0039] S3-5 is the same as Example 1.

[0040] S6, removing the negative photoresist on the front side of the wafer by cleaning, wherein the cleaning solution used to remove the negative photoresist by cleaning is the solvent of the negative photoresist, and it is necessary to confirm that the cleaning solution does not react with the passivation layer on the front side of the wafer.

[0041] In the scheme of comparative example 1, after the passivation layer is deposited, a negative photoresist is coated on the passivation layer, exposed through a mask of a predetermined shape, developed to form a photoresist layer, and etched using the photoresist layer as a mask. In the above process, the photoresist of the portion where the groove is to be formed is exposed.

[0042] After the step of filling the grooves, the photoresist on the passivation layer needs to be removed. Since a mask of a predetermined shape is required for the photolithography process, the groove area is exposed, and the groove area needs to be filled, so the photoresist of the exposed part needs to be retained, so a negative photoresist is selected as the filling layer.

[0043] If the photoresist is not filled and the thinning process is directly performed, the silicon thickness fluctuates by 3 μm. By using the solutions of Comparative Example 1 and Example 1, the thickness fluctuation can be reduced to within 0.5 μm, and Example 1 can further reduce the thickness fluctuation to within 0.4 μm.

[0044] For the case where the photoresist is not filled and the thinning process is directly performed, the micro crack rate after thinning is 0.08%. After using Example 1, the crack rate is reduced to 0.01%.

[0045] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0046] One or more embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A thinning method for flattening the front side of a wafer, characterized in that: The following steps are included: 1) Spin-coating a positive photoresist on the front side of the wafer to be thinned, wherein the front side of the wafer to be thinned is provided with a plurality of passivation layers arranged at intervals, and the thickness of the photoresist is equal to the thickness of the passivation layer; 2) removing the positive photoresist on the passivation layer; 3) A protective film is attached to the front side of the wafer to be thinned; 4) Thinning the back side of the wafer to be thinned; 5) Remove the protective film; 6) Remove the positive photoresist to obtain a thinned wafer.

2. The thinning method for flattening the front side of a wafer as claimed in claim 1, characterized in that: The method for removing the positive photoresist on the passivation layer is to use a mask corresponding to the front side of the wafer to be thinned, and utilize exposure and development processes to remove the positive photoresist on the passivation layer, leaving the positive photoresist between the passivation layers.

3. The thinning method for flattening the front side of a wafer as claimed in claim 2, characterized in that: The shape of the mask corresponds to the passivation layer on the front side of the wafer to be thinned, so that during exposure and development, only the positive photoresist above the passivation layer is exposed and developed.

4. The thinning method for flattening the front side of a wafer according to any one of claims 1 to 3, characterized in that: Step 6) is to remove the positive photoresist by cleaning.

5. The thinning method for flattening the front side of a wafer as claimed in claim 4, characterized in that: The cleaning agent used for cleaning is a solvent that can dissolve the positive photoresist and does not react with the passivation layer.

6. The thinning method for flattening the front side of a wafer according to any one of claims 1 to 3, characterized in that: The size of the wafer is 6-12 inches.

7. The thinning method for flattening the front side of a wafer according to any one of claims 1 to 3, characterized in that: The positive photoresist is I-Line or KrF photoresist matching the thickness of the passivation layer.

8. The thinning method for flattening the front side of a wafer according to any one of claims 1 to 3, characterized in that: The distance between the passivation layers is 5-2000 μm.

9. The thinning method for planarizing the front side of a wafer as claimed in claim 2, characterized in that: The specific steps of the exposure and development process are: using a mask so that only the area of ​​the passivation layer is exposed during the exposure process, and the photoresist on the passivation layer is removed after development.

10. The thinning method for flattening the front side of a wafer according to any one of claims 1 to 3, characterized in that: The protective film is a thinned protective tape.

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