A power module and a manufacturing method thereof

Abstract

The present invention discloses a power module and a manufacturing method thereof, and relates to the technical field of power modules. The method of the present invention comprises the following steps: S1: bonding the drain electrode of the power chip to the surface of the substrate through an adhesive; S2: contacting the first mold with the surface of the power chip; forming a packaged power module cavity between the first mold and the power chip; then filling the packaged power module cavity with plastic packaging material to complete the plastic packaging process; S3: removing the first mold; S4: covering the second mold between the source electrode and the gate electrode on the surface of the power chip, performing double-sided seed layer sputtering to obtain a seed layer; S5: removing the second mold, immersing the power chip with the seed layer in the electroplating solution for deposition, and forming an electroplated metal layer on the surface of the power chip seed layer to obtain a power module. The method of the present invention can achieve laser-free drilling, avoid damage to the chip surface electrode caused by laser drilling, and reduce steps such as cleaning and activation.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to a power module and a manufacturing method thereof. Background Art

[0002] The power chip is the core component of the power module. Based on a specific functional combination, the power chip is assembled through solder printing, die placement, welding, wire bonding, housing installation, and sealing and curing to form a power module capable of power conversion. When the IGBT module is operating normally, the chip generates power loss, causing the IGBT module to operate at elevated temperatures. During the turn-on and turn-off processes, the high stray inductance of traditional packaging methods results in greater voltage overshoot and oscillation under extremely high di / dt. Furthermore, due to mismatched thermal expansion coefficients between layers within the module, the materials expand and contract in varying volumes, causing shear stress and bending deformation, ultimately leading to thermal fatigue failure of the IGBT module.

[0003] Common forms of thermal fatigue failure in IGBT modules include wire bond failure and solder layer fatigue. Wire bond failure primarily results from the delamination and detachment of the bond wires at the aluminum-silicon interface between the power chip and the power chip. When one bond wire detaches, it accelerates the failure of the remaining bond wires. Solder layer fatigue failure occurs when repeated alternating thermal stresses cause cracks and voids to form at the physical interface between the chip solder layer and the substrate solder layer. Solder layer fatigue increases the thermal resistance of the IGBT module, further raising the device's operating junction temperature, accelerating power module failure, and impacting module reliability.

[0004] To improve the reliability of IGBT power modules, researchers are conducting research on novel packaging processes focused on enhancing module heat dissipation efficiency and reducing package stray inductance and thermal resistance. These include press-fit, three-dimensional interconnection, and chip-embedded packaging. Press-fit requires high pressure uniformity and precision control, and carries the potential for mechanical stress damage, so it's only used in specialized scenarios. To reduce parasitic inductance, researchers have developed a three-dimensional interconnection packaging approach. This approach places the power chips face-to-face, interconnecting them electrically via two DBC substrates and a four-layer PCB. Current paths and capacitors are integrated onto the PCB, significantly reducing parasitic parameters. However, this approach involves complex fabrication and high production costs. Chip-embedded packaging embeds the power chip onto a ceramic substrate or PCB, interconnecting the chip to the outer package via laser drilling and metallized microvias. This packaging approach improves power module integration and reduces parasitic inductance, but requires laser drilling and multi-step photolithography and development, reducing production efficiency and increasing costs. Therefore, it is necessary to propose a new packaging structure to improve the heat dissipation performance of the power module while increasing production efficiency and reducing costs. Summary of the Invention

[0005] The present invention aims to overcome the shortcomings of the prior art and provides a power module and a method for manufacturing the same. The power module manufacturing method proposed in the present invention utilizes a mold that serves as a masking layer, enabling laser-free drilling, thereby avoiding damage to the chip surface electrodes caused by laser drilling and reducing the number of cleaning and activation steps. To achieve the above objectives, the present invention employs the following technical solutions:

[0006] In a first aspect, the present invention provides a method for manufacturing a power module, comprising the following steps:

[0007] S1: Bonding the drain electrode of the power chip to the surface of the substrate through an adhesive;

[0008] S2: Engage the first mold with the substrate and contact it with the surface of the power chip to form a packaged power module cavity between the first mold and the power chip; then fill the packaged power module cavity with molding compound, and solidify and demold the molding compound; the first mold is designed according to the structure of the power chip and the substrate and is provided with positioning holes and brackets for engaging with the substrate;

[0009] S3: removing the first mold;

[0010] S4: Covering the second mold between the source electrode and the gate electrode on the surface of the power chip to form a masking layer for the sputtering seed layer, and then placing the power chip and the second mold together in a vacuum chamber of a sputtering device to perform double-sided seed layer sputtering;

[0011] S5: The second mold is removed, and then the power chip with the seed layer is immersed in an electroplating solution containing metal ions for deposition, so as to form an electroplated metal layer on the surface of the seed layer of the power chip, thereby obtaining a power module.

[0012] The manufacturing method of the power module described in the present invention is as follows: first, the power chip is connected to the substrate, and then the chip structure and circuit layout are estimated to design and process the first mold, the source electrode and the gate electrode are shielded with openings to prevent the source electrode and the gate electrode from being covered by the subsequent plastic packaging material, and then the first mold is aligned with the chip and filled with plastic packaging material, and the first mold is removed after curing. Then, the second mold is covered on the surface of the power chip to form a masking layer for the sputtering seed layer, and then the power chip and the second mold are placed together in the vacuum chamber of the sputtering equipment for double-sided seed layer sputtering, and the sputtering time and power are controlled to obtain a seed layer of the desired thickness. The second mold is then removed, and the power device with the seed layer is then immersed in an electroplating solution containing metal ions. The metal ions are deposited from the electroplating solution onto the seed layer to form an electroplated metal layer, thereby realizing the production of the power module.

[0013] This invention utilizes an electroplating process to design and fabricate a power module. This technical solution offers the advantages of solder-free operation, high thermal conductivity, high integration, and wafer-level integration. The invention utilizes a first mold and a second mold as masking layers, eliminating the need for wire bonding and a ceramic substrate as a thermally conductive medium. This reduces heterogeneous interface connections and the length of the heat dissipation path, thereby enhancing the reliability and heat dissipation performance of the power module.

[0014] Preferably, in step S1, the adhesive includes at least one of a resin adhesive, a rubber adhesive, a polyvinyl acetate emulsion adhesive, an epoxy resin adhesive, and a UV adhesive.

[0015] More preferably, the resin adhesive includes a phenolic resin adhesive or a urea-formaldehyde resin adhesive.

[0016] More preferably, the rubber adhesive includes styrene-butadiene rubber adhesive or chloroprene rubber adhesive.

[0017] Because the above-mentioned materials contain a large amount of carbon or benzene rings (containing carbon) in their molecular structure, they may undergo thermal decomposition at high temperatures, producing gases such as carbon dioxide, which affects the adhesion performance. When using UV glue, the cured UV glue is again exposed to long-term or high-intensity ultraviolet radiation, and its bonding strength will decrease. This is because under the action of excessive ultraviolet rays, the chemical bonds inside the glue may undergo reactions such as breakage or degradation, causing its structure and performance to change, thereby reducing the bonding strength. Therefore, the present invention uses the above-mentioned materials as adhesives to make it easier for the power chip to fall off from the substrate surface.

[0018] Preferably, the substrate includes one of a glass substrate, an organic polyimide (PI) substrate, a ceramic substrate, a glass fiber reinforced resin (FR-4) substrate, a BT packaging substrate, an ABF packaging substrate, and an MIS packaging substrate.

[0019] Preferably, in step S2, the molding compound includes at least one of polyimide, phenolic resin, and polyparaxylene.

[0020] Preferably, the first mold and the second mold are made of steel, graphite or ceramic.

[0021] Preferably, in step S4, the sputtering time is 0.5-10 min, and the sputtering power is 50-1000 W.

[0022] Preferably, in step S5, the material of the electroplated metal layer may be one of copper, nickel, zinc, silver, chromium and gold.

[0023] Preferably, in step S5, the thickness of the electroplated metal layer is 0.5-50 μm.

[0024] In a second aspect, the present invention further provides a power module manufactured by the above method.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) The present invention can not only completely avoid the packaging process and operations such as die bonding, wire bonding, photolithography and development, but also realize wafer-level packaging and double-sided connection and heat dissipation of power chips, greatly improving production efficiency and reducing costs.

[0027] (2) The present invention avoids traditional high-cost processes such as wire bonding, die bonding, photolithography development, and laser drilling by using temporary adhesives, mask fixtures, and electroplating processes, and realizes the packaging and manufacturing integration of power devices at the wafer level by first potting and then connecting wiring, meeting the requirements of heat dissipation and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure after the power chip is bonded to the surface of the substrate in the present invention.

[0029] Figure 2 It is a schematic structural diagram of the present invention after the first mold and the substrate are engaged.

[0030] Figure 3 It is a structural diagram of the present invention used to illustrate the first mold.

[0031] Figure 4 It is a schematic diagram of the structure after the first mold is removed in Example 1 of the present invention.

[0032] Figure 5 It is a schematic diagram of the structure after the substrate and the power chip are separated in the present invention.

[0033] Figure 6 It is a schematic structural diagram of the present invention after the second mold covers the power chip.

[0034] Figure 7 It is a schematic structural diagram of the present invention after double-sided seed layer sputtering of the power chip and the second mold.

[0035] Figure 8 It is a schematic structural diagram of the present invention after the second mold is removed.

[0036] Figure 9 It is a structural schematic diagram of forming an electroplated metal layer on the surface of a power chip seed layer according to the present invention.

[0037] Figure 10 It is a schematic structural diagram of the power module manufactured according to Example 2 of the present invention.

[0038] Figure 11 Schematic diagram of the structure of the power module manufactured in Comparative Example 7 of the present invention.

[0039] Figure 1-11 In the figure, 1 is the gate electrode; 2 is the source electrode; 3 is the power chip; 4 is the drain of the power chip; 5 is the adhesive; 6 is the substrate; 7 is the first mold; 8 is the plastic sealant; 9 is the second mold; 10 is the seed layer; 11 is the electroplated metal layer; and 12 is the base plate. DETAILED DESCRIPTION

[0040] In order to better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below with reference to specific embodiments, but the protection scope and implementation methods of the present invention are not limited thereto.

[0041] Unless otherwise specified, the materials and reagents used in the following examples are commercially available.

[0042] Example 1

[0043] A method for manufacturing a power module, comprising the following steps:

[0044] S1: Power chip connection process

[0045] like Figure 1 As shown, according to the layout design of the power chip, the side of the power chip drain 4 close to the substrate 6 is adhered to the surface of the substrate 6 through the adhesive 5. In this embodiment, the adhesive is a phenolic resin adhesive and the substrate is a glass substrate.

[0046] In other embodiments, the adhesive may be a urea-formaldehyde resin adhesive, a styrene-butadiene rubber adhesive, a chloroprene rubber adhesive, a polyvinyl acetate emulsion adhesive or an epoxy resin adhesive; the substrate may be a PI film, a ceramic substrate, an organic polyimide substrate, a glass fiber reinforced resin substrate, a BT packaging substrate, an ABF packaging substrate or an MIS packaging substrate.

[0047] S2: Hole masking and plastic injection process

[0048] Design and process the mask jig according to the chip structure and circuit layout, then perform opening shielding on the source electrode 2 and the gate electrode 1 to prevent the source electrode and the gate electrode from being covered by the subsequent plastic packaging material, then align the first mold 7 with the power chip and fill it with plastic packaging material, and remove the first mold 7 after curing.

[0049] like Figure 2As shown, the customized first mold 7 is embedded with the substrate 6 through the positioning holes and the bracket, and the first mold 7 as a masking layer is in close contact with the surface of the gate electrode 1 and the source electrode 2. The first mold 7 for forming the opening mask above the electrode is designed according to the chip layout and the distribution of the electrodes, and the alignment and nesting of the mold and the power module are achieved by nesting the first mold 7 with the packaging substrate 6. The first mold 7 has the function of aligning and positioning according to the substrate, such as Figure 3 The bracket in the design can be embedded in the positioning hole of the substrate, so that a precise opening is formed above the power chip after the subsequent plastic encapsulation compound is filled.

[0050] In this embodiment, the material of the first mold is steel, and its structure is as follows Figure 3 7 in FIG. In other embodiments, the material of the first mold may be graphite or ceramic. Subsequently, a molding compound is poured into the packaged power module cavity. The molding compound forms a flow-wrapped seal around the bare chip and substrate, isolating them from the external environment. After curing, a protective layer of plastic sealant 8 is formed. In this embodiment, the molding compound is phenolic resin; in other embodiments, it may be polyimide or parylene.

[0051] like Figure 4 As shown, the first mold 7 is removed. Since the first mold 7 forms a mask above the chip electrodes, a hole is opened on the surface of the power chip 3 without damage.

[0052] S3: Separate the substrate from the power chip

[0053] like Figure 5 As shown, the bonding strength of the adhesive 5 connecting the power chip 3 and the substrate 6 is reduced by high temperature, so that the substrate 6 can be separated from the power chip 3 more easily.

[0054] S4: Gate-source electrical isolation process for power chips

[0055] like Figure 6 As shown, the second mold 9 is customized according to the position of the source electrode 2 and the gate electrode 1. The second mold 9 covers the surface of the plastic sealant between the gate electrode 1 and the source electrode 2 as a masking layer for achieving electrical isolation between the gate and source electrodes to prevent electrical contact between the source electrode 2 and the gate electrode 1 during the subsequent electroplating process. In this embodiment, the material of the second mold is steel. In other embodiments, the material of the second mold can be graphite or ceramic. The second mold is mainly used to achieve precise alignment and opening with the power chip. Therefore, a positioning bracket with the same function as the first mold is used to achieve interlocking with the positioning hole on the substrate.

[0056] like Figure 7As shown, the cleaned power chip 3 and the second mold 9 are then placed together in the vacuum chamber of the sputtering equipment for double-sided seed layer sputtering, and the sputtering time is controlled to be 0.5-10min and the power is 50W-1000W to obtain the seed layer 10 of the required thickness, which is 5-100nm.

[0057] S5: Metal Deposition Process

[0058] like Figure 8 、 9 As shown, the second mold 9 is removed, and the power device with the seed layer 10 is immersed in a metal ion electroplating solution. The metal ions are deposited from the electroplating solution onto the seed layer 10 to form a uniform and dense electroplated metal layer 11. The material of the electroplated metal layer can be copper, gold, nickel, zinc, silver, or chromium, with a thickness between 0.5 μm and 50 μm. Depending on the type of metal, the electroplating process parameters such as current density, temperature, and electroplating time are adjusted to ultimately achieve full copper coverage of the power module. The material of the metal layer deposited by the electroplating process in this step is copper, and in other embodiments it can be gold, nickel, zinc, silver, or chromium.

[0059] Among them, ① the main components of copper electroplating solution include copper sulfate (100-250g / L), sulfuric acid (50-200g / L), and also contain additives such as brightener (1-10ml / L), leveler (0.5-5ml / L), etc.; ② gold electroplating solution: generally contains a solution of gold salt (such as potassium gold cyanide, 1-10g / L), and also contains citric acid (5-50g / L), phosphate buffer (10-100g / L), etc.; ③ nickel electroplating solution is mainly composed of nickel sulfate (200-350g / L), nickel chloride (30-70g / L) and boric acid (30-50g / L). The current density during the electroplating process is 0.5-10A / dm 2 between.

[0060] If you want to use the all-copper power module as a module unit, you can use a grinding wheel or laser to cut the batch-prepared all-copper power module array, and use the cut all-copper module as the smallest unit of the power module.

[0061] Example 2

[0062] A method for manufacturing a power module, comprising the following steps:

[0063] S1: Power chip connection process

[0064] First, it is connected to the ceramic substrate after sintering with metal solder. This process keeps the drain side of the power chip close to the substrate, so that the drain electrode of the power chip forms a metal connection with the patterned copper layer of the ceramic substrate.

[0065] S2: The hole masking and plastic sealant injection processes are the same as those in Example 1.

[0066] S3: Take away the first mold.

[0067] S4: Gate-source electrical isolation process for power chips

[0068] A second mold (made of steel) is customized according to the position of the source electrode and the gate electrode. In the same way as the first mold, the second mold is embedded and covered on the surface of the power chip to form a masking layer for the sputtering seed layer, thereby spatially isolating the source electrode and the gate electrode to avoid electrical contact between the source electrode and the gate electrode during the subsequent electroplating process.

[0069] S5: Metal Deposition Process

[0070] The cleaned power chip and the second mold are placed together in the vacuum chamber of the sputtering equipment for seed layer sputtering. The type of sputtered metal is determined by the type of electroplated metal, which can be gold, nickel, zinc, silver, or chromium. The sputtering time is controlled to be 30 seconds to 10 minutes and the power is controlled to be 50 to 1000W to obtain the required thickness of the seed layer, which is 5 to 100nm.

[0071] The second mold is then removed, and the power device with the seed layer is then placed in an electroplating tank. Metal ions are deposited from the electroplating solution onto the seed layer to form a uniform and dense electroplated metal layer (the electroplated metal can be copper, gold, nickel, zinc, silver, or chromium, and the thickness of the electroplated metal layer is between 0.5 μm and 50 μm), thereby realizing the production of an all-copper module. The material of the metal layer deposited by the electroplating process in this step is copper. This module spatially extends the gate, source, and drain of the power chip, which is conducive to wafer-level power module packaging. The structure of the power module finally manufactured is as follows: Figure 10 shown.

[0072] The method described in this embodiment does not remove the substrate 6 and the bottom plate 13 (the bottom plate is usually a metal flat plate, which is located at the bottom of the power module and mainly serves the functions of heat dissipation and mechanical support). It can realize the design and production of a solder-free power module with a thermally conductive substrate.

[0073] Comparative Example 1

[0074] A method for manufacturing a power module differs from embodiment 1 in that, in step S2, a first mold is not used to engage with a substrate, but a laser is used to open a hole.

[0075] In this comparative example, since the first mold is not used for masking in step S2 but laser drilling is performed instead, not only the electrodes on the chip surface are damaged, but also the production efficiency is low and the cost is high.

[0076] Comparative Example 2

[0077] A method for manufacturing a power module differs from that of embodiment 1 in that a second mold is not used to cover the surface of the power chip in step S4.

[0078] In this comparative example, since the second mold is not used for masking in step S4, the gate electrode of the power chip and the source electrode of the power chip cannot be electrically isolated, which ultimately results in a failed power module.

[0079] Comparative Example 3

[0080] A method for manufacturing a power module differs from that of Example 1 in that, in step S4, the sputtering time is 15 minutes.

[0081] In this comparative example, the sputtering time is longer than 10 minutes, which causes problems such as changes in film properties, material waste and increased costs, and increased surface roughness. For some materials, sputtering for too long may change the crystal structure of the seed layer.

[0082] Comparative Example 4

[0083] A method for manufacturing a power module differs from that of embodiment 1 in that, in step S4, the sputtering time is 25 seconds.

[0084] In this comparative example, a sputtering time of less than 30 seconds resulted in insufficient film thickness, poor coverage, and weak adhesion. Sputtering times that short can result in a too-thin seed layer, preventing the subsequent metal layer from growing properly in uncovered areas, impacting device performance and reliability.

[0085] Comparative Example 5

[0086] A method for manufacturing a power module is different from that of embodiment 1 in that, in step S4, the sputtering power is 1100W.

[0087] In this comparative example, the sputtering power exceeded 1000W, resulting in degraded film quality (manifested by poor crystal quality and reduced film density), substrate damage, and compositional deviations. High sputtering power means the sputtered particles have higher energy, and these high-energy particles may cause physical damage to the substrate when they impact the substrate surface.

[0088] Comparative Example 6

[0089] A method for manufacturing a power module is different from that of embodiment 1 in that, in step S4, the sputtering power is 40W.

[0090] In this comparative example, the sputtering power is lower than 50 W, resulting in problems such as too low deposition rate, weak film adhesion, and uneven coverage.

[0091] Comparative Example 7

[0092] A method for manufacturing a power module differs from that of embodiment 1 in that, in step S4, the thickness of the electroplated metal layer is 0.4 μm.

[0093] like Figure 11 As shown, the thickness of the electroplated metal layer 11 in this comparative example is less than 0.5 μm, which prevents the source and gate electrodes of the power chip from extending to the module surface, making it impossible to form a fully copper-covered wafer-level package. Furthermore, too low a thickness prevents the metal layer from conducting high currents, thereby limiting the current flow capacity and current rating of the power module.

[0094] Comparative Example 8

[0095] A method for manufacturing a power module differs from that of embodiment 1 in that, in step S4, the thickness of the electroplated metal layer is 55 μm.

[0096] In this comparative example, the thickness of the electroplated metal layer is higher than 50 μm, which results in an increase in the electrode thickness of the power module, resulting in an increase in parasitic capacitance and series resistance. In addition, the thick electrode may generate greater stress during the manufacturing process or under temperature changes, thereby causing stress problems.

[0097] In summary, the present invention adopts a wafer-level full electroplating manufacturing method to achieve chip gate, source and drain rearrangement and connection, completely remove the solid crystal and wire bonding process, thereby avoiding the reliability problems caused by the heterogeneous interface thermal stress mismatch of traditional wire bonding and chip solid crystal. In addition, the electroplating process of the present invention can obtain a double-sided all-copper connection packaging structure, improve the heat dissipation efficiency of the device and reduce the junction temperature, and the wafer-level electroplating process has high production efficiency and can effectively reduce manufacturing and production costs. At the same time, the present invention introduces a wafer-level mask structure to replace the traditional laser opening and photolithography development process, which not only avoids the heat loss of high-energy laser to the chip, but also realizes a wafer-level one-time opening operation, thereby greatly improving production efficiency and reducing costs.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a power module, characterized in that: The following steps are involved: S1: Bonding the drain electrode of the power chip to the surface of the substrate through an adhesive; S2: The first mold is fitted with the substrate and brought into contact with the surface of the power chip, forming a packaged power module cavity between the first mold and the power chip; then, a molding compound is filled into the packaged power module cavity, and the molding compound is cured and demolded; the first mold is designed according to the structure of the power chip and the substrate and is provided with positioning holes and brackets for fitting with the substrate; the first mold is in close contact with the surfaces of the gate electrode and the source electrode; S3: The first mold is removed. Since the first mold forms a mask above the chip electrodes, a hole is opened on the surface of the power chip without damage. S4: Covering the second mold between the source electrode and the gate electrode on the surface of the power chip to form a masking layer for the sputtering seed layer, and then placing the power chip and the second mold together in a vacuum chamber of a sputtering device to perform double-sided seed layer sputtering; S5: The second mold is removed, and then the power chip with the seed layer is immersed in an electroplating solution containing metal ions for deposition, so as to form an electroplated metal layer on the surface of the seed layer of the power chip, thereby obtaining a power module.

2. The method for manufacturing a power module according to claim 1, wherein: In step S1, the adhesive includes at least one of a resin adhesive, a rubber adhesive, a polyvinyl acetate emulsion adhesive, an epoxy resin adhesive, and a UV adhesive.

3. The method for manufacturing a power module according to claim 2, wherein: The resin adhesive includes a phenolic resin adhesive or a urea-formaldehyde resin adhesive; and / or the rubber adhesive includes a styrene-butadiene rubber adhesive or a chloroprene rubber adhesive.

4. The method for manufacturing a power module according to claim 1, wherein: The substrate includes one of a glass substrate, an organic polyimide substrate, a ceramic substrate, a glass fiber reinforced resin substrate, a BT packaging substrate, an ABF packaging substrate, and an MIS packaging substrate.

5. The method for manufacturing a power module according to claim 1, wherein: In step S2, the molding compound includes at least one of polyimide, phenolic resin, and polyparaxylene.

6. The method for manufacturing a power module according to claim 1, wherein: The first mold and the second mold are made of steel, graphite or ceramic.

7. The method for manufacturing a power module according to claim 1, wherein: In step S4, the sputtering time is 0.5-10 min, and the sputtering power is 50-1000 W.

8. The method for manufacturing a power module according to claim 1, wherein: In step S5, the material of the electroplated metal layer can be one of copper, nickel, zinc, silver, chromium, and gold.

9. The method for manufacturing a power module according to claim 1, wherein: In step S5, the thickness of the electroplated metal layer is 0.5-50 μm.

10. A power module manufactured by the method for manufacturing a power module according to any one of claims 1 to 9.

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