Board level packaging method and packaging structure

Abstract

The embodiment of the present disclosure provides a board-level packaging method and a packaging structure. The method comprises the following steps: providing a square panel, a first surface of the square panel is provided with a plurality of grooves; fixing a plurality of bridge chips on the corresponding grooves; forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip; forming a plurality of conductive columns through the thickness of the square panel; forming a second redistribution layer on the second surface of the square panel and electrically connected with the conductive column; forming a power management module on the second redistribution layer and a chip operation module on the first redistribution layer. The large-area square panel is used as a carrier plate to realize high computing power integration of the board-level packaging structure. The square panel is provided with grooves, and a plurality of bridge chips are arranged in the grooves to reduce the packaging height of the whole packaging structure. The chip operation module realizes high-density interconnection with the aid of the plurality of bridge chips. A plurality of conductive columns are formed through the thickness of the square panel to effectively shorten the transmission path.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a board-level packaging method and packaging structure. BACKGROUND

[0002] SoW (System on wafer) is to integrate a certain number of computing chips onto a whole wafer as a whole to form a HPC (High Performance Computing) chip system.

[0003] SoW is to reconfigure computing chips into a wafer by using FO technology with a glass carrier as a carrier, to complete interconnection between chips through plastic packaging and re-wiring, to peel off the carrier, and to form the whole SoW system by interconnecting power devices with computing chips in a flip-chip manner on the reconfigured wafer.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to provide a board-level packaging method and packaging structure which are reasonable in design and effective in solving the above problems. SUMMARY

[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a board-level packaging method and packaging structure.

[0007] The embodiment of the present disclosure provides a board-level packaging method, which comprises:

[0008] A square panel is provided, and a plurality of grooves are arranged on a first surface of the square panel;

[0009] A plurality of bridge chips are fixed on the grooves corresponding to the bridge chips;

[0010] A first re-wiring layer is formed on the first surface of the square panel and a functional surface of the bridge chip;

[0011] A plurality of conductive pillars are formed in the square panel and penetrate the thickness of the square panel;

[0012] A second re-wiring layer is formed on a second surface of the square panel and is electrically connected with the conductive pillars;

[0013] A power management module is formed on the second re-wiring layer, and a chip operation module is formed on the first re-wiring layer.

[0014] Optionally, the plurality of conductive pillars formed in the square panel and penetrating the thickness of the square panel comprise:

[0015] A plurality of through holes penetrating the thickness of the square panel are formed by drilling along the second surface of the square panel.

[0016] electroplating a conductive material in the through hole to form the conductive pillar.

[0017] Optionally, the forming the plurality of conductive pillars through the thickness of the square panel further comprises:

[0018] when providing the square panel, the first surface of the square panel is provided with a plurality of blind holes extending to the second surface thereof, and the blind holes are provided with a conductive material;

[0019] after forming the first redistribution layer, the second surface of the square panel is thinned to expose the blind holes, forming the conductive pillars through the thickness of the square panel.

[0020] Optionally, the forming the power management module on the second redistribution layer comprises:

[0021] forming a plurality of power management chips and a plurality of first connectors on the second redistribution layer.

[0022] Optionally, the forming the chip operation module on the first redistribution layer comprises:

[0023] forming a chip operation layer and a plurality of second connectors on the first redistribution layer, wherein the chip operation layer comprises at least a plurality of computing chips.

[0024] Optionally, the forming the chip operation module on the first redistribution layer further comprises:

[0025] forming a chip operation layer and a plurality of photoelectric conversion chips on the first redistribution layer, wherein the chip operation layer comprises at least a plurality of computing chips.

[0026] Optionally, the fixing the non-functional surface of the plurality of bridge chips in the corresponding groove comprises:

[0027] attaching the non-functional surface of the plurality of bridge chips to the bottom wall of the corresponding groove, and the bridge chip and the side wall of the groove have a gap therebetween.

[0028] the forming the first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip comprises:

[0029] forming a first dielectric layer on the gap, the first surface of the square panel and the functional surface of the bridge chip;

[0030] patterning the first dielectric layer on the first surface of the square panel and the functional surface of the bridge chip to form a plurality of first openings on the first dielectric layer;

[0031] forming a first metal layer in the first opening and electrically connected with the bridge chip.

[0032] Optionally, the second redistribution layer formed on the second surface of the square panel and electrically connected with the conductive column includes:

[0033] forming a second dielectric layer on the second surface of the square panel;

[0034] patterning the second dielectric layer to form a plurality of second openings on the second dielectric layer;

[0035] forming a second metal layer in the second opening and electrically connected with the conductive column.

[0036] Optionally, the square panel is a glass panel.

[0037] Another aspect of the embodiments of the present disclosure provides a board-level packaging structure packaged by the board-level packaging method described above.

[0038] The board-level packaging method and structure of the embodiments of the present disclosure, in which a square panel is provided, a board-level packaging structure is formed on the square panel, and a large-area square panel is used as a carrier, which significantly improves the chip capacity, area utilization rate and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high-computing-power integration of the board-level packaging structure; the square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the square panel corresponding thereto, which reduces the packaging height of the entire packaging structure; the chip computing module realizes high-density interconnection with the aid of the plurality of bridge chips, and no longer needs to rely on the construction of fine line structures in the RDL; a plurality of conductive columns penetrating through the thickness of the square panel are formed on the square panel, which realizes vertical interconnection of the packaging structure and vertical power supply on the back surface of the square panel, and effectively shortens the transmission path. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 a flowchart of a board-level packaging method of an embodiment of the present disclosure;

[0040] Figures 2 to 15 a process flowchart of a board-level packaging method of an embodiment of the present disclosure;

[0041] Figures 16 to 29 a process flowchart of a board-level packaging method of another embodiment of the present disclosure;

[0042] Figure 30 a structure diagram of a board-level packaging system of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.

[0044] As shown in Figure 1 An aspect of the embodiments of the present disclosure provides a board-level packaging method S100, which comprises the following steps:

[0045] S110, providing a square panel, a first surface of the square panel being provided with a plurality of grooves.

[0046] S120, fixing a plurality of bridge chips non-functional surfaces in the grooves corresponding thereto.

[0047] S130, forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip.

[0048] S140, forming a plurality of conductive pillars penetrating the thickness of the square panel.

[0049] S150, forming a second redistribution layer electrically connected with the conductive pillars on the second surface of the square panel.

[0050] S160, forming a power management module on the second redistribution layer and a chip operation module on the first redistribution layer.

[0051] The board-level packaging method and packaging structure of the embodiments of the present disclosure, the method provides a square panel, and a board-level packaging structure is formed on the square panel. A large-area square panel is used as a carrier, which significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration of the board-level packaging structure. The square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the square panel corresponding thereto, which reduces the packaging height of the entire packaging structure. The chip operation module realizes high-density interconnection with the aid of the plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL. A plurality of conductive pillars penetrating the thickness of the square panel are formed on the square panel, vertical interconnection of the packaging structure is realized, back vertical power supply of the square panel is realized, and the transmission path is effectively shortened.

[0052] The specific process of a board-level packaging method S100 of the embodiments of the present disclosure is specifically described below in combination with several embodiments.

[0053] Embodiment 1

[0054] In step S110, as shown in Figure 2As shown, a square panel 22 is provided, and a first surface of the square panel 22 is provided with a plurality of recesses 44. In the process of providing the square panel 22, the first surface of the square panel 22 is provided with a plurality of blind holes 46' extending to a second surface thereof, and the blind holes 46' are provided with conductive materials.

[0055] In this embodiment, a large-area square panel is used as a carrier panel, which significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration of a board-level packaging structure.

[0056] In step S120, as shown in the figure, Figure 3 the non-functional surfaces of the plurality of bridge chips 24 are fixed to the recesses 44 corresponding thereto.

[0057] Specifically, as shown in the figure, Figure 3 the non-functional surfaces of the plurality of bridge chips 24 are fixed to the bottom walls of the recesses 44 corresponding thereto. There is a gap between the bridge chips 24 and the side walls of the recesses 44. It should be noted that the number of bridge chips 24 is not specifically limited and can be limited according to actual needs.

[0058] In step S130, as shown in the figure, Figure 4 and Figure 5 a first redistribution layer is formed on the first surface of the square panel 22 and the functional surfaces of the bridge chips 24.

[0059] The process of forming the first redistribution layer can be as follows:

[0060] Specifically, as shown in the figure, Figure 4 a first dielectric layer 28 is formed in the gap, on the first surface of the square panel 22 and the functional surfaces of the bridge chips 24. In this embodiment, the first dielectric layer 28 can be a PI layer.

[0061] The first dielectric layer 28 on the first surface of the square panel 22 and the functional surfaces of the bridge chips 24 is patterned to form a plurality of first openings on the first dielectric layer 28.

[0062] As shown in the figure, Figure 5 a first metal layer 30 electrically connected to the bridge chips 24 is formed in the first openings. In this embodiment, the first metal layer 30 can be a copper layer.

[0063] As shown in the figure, Figure 6 the first redistribution layer is fixed to the carrier panel 50 by temporary bonding glue. As shown in the figure, Figure 7 the carrier panel 50 is turned over to be located at the lower side as a support.

[0064] In step S140, a plurality of conductive pillars are formed through the thickness of the square panel.

[0065] Specifically, as shown in Figure 7 the second surface of the square panel 22 is thinned by grinding or the like to expose the blind holes, forming a plurality of conductive pillars 46 through the thickness of the square panel 22. That is, the conductive pillars 46 are TGVs.

[0066] In this embodiment, by forming a plurality of conductive pillars through the thickness of the square panel, vertical interconnection on both sides of the square panel can be achieved, effectively shortening the transmission path.

[0067] In step S150, as shown in Figure 8 a second redistribution layer electrically connected to the conductive pillars 46 is formed on the second surface of the square panel 22.

[0068] The process of forming the second redistribution layer can be as follows:

[0069] As shown in Figure 8 a second dielectric layer 52 is formed on the second surface of the square panel 22 using coating or other processes. In this embodiment, the second dielectric layer 52 can be a PI layer.

[0070] The second dielectric layer 52 is patterned using photolithography and etching or other processes to form a plurality of second openings on the second dielectric layer 52.

[0071] As shown in Figure 8 a second metal layer 54 electrically connected to the conductive pillars 46 is formed in the second openings using electroplating or other processes. The second metal layer 54 can be a copper layer.

[0072] In step S160, as shown in Figures 9 to 15 a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0073] The power management module formed on the second redistribution layer specifically includes:

[0074] As shown in Figure 9 a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second redistribution layer. Specifically, a plurality of power management chips 56 and a plurality of first connectors 34 are formed on the second metal layer 54. The first connectors 34 are provided with first cables 36. The power management chips 56 are used to power the board-level package structure, and the first connectors 34 can realize electrical connection between a plurality of board-level package structures.

[0075] It should be noted that the first connector 34 and the power management chip 56 can be arranged alternately. Alternatively, the first connector 34 can be located on the second wiring layer at the edge of the square panel 22 to facilitate electrical connections between multiple board-level package structures. The number and distribution of the first connector 34 and the power management chip 56 are not specifically limited and can be selected according to actual needs.

[0076] Specifically, the chip computing module formed on the first interconnect layer may include:

[0077] like Figure 10 As shown, Figure 9 The intermediate package is clamped onto fixture 58 to achieve structural suspension. For example... Figure 11 As shown, Figure 10 The intermediate package shown is flipped over, and the carrier plate 50 is removed. (As shown) Figure 12 As shown, a chip computing layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein second cables 36' are disposed on the second connectors 34'. The chip computing layer 32 includes at least a plurality of computing chips. The chip computing layer 32 may also include memory chips or other types of computing chips. The second connectors 34' are used for electrical connections between multiple board-level package structures.

[0078] In this embodiment, the chip computing layer 32 is located on the second wiring layer in the central area of ​​the square panel 22, and the second connector 34' is located on the second wiring layer in the edge area of ​​the square panel, which facilitates electrical connection with the adjacent packaging structure.

[0079] Specifically, the chip computing module formed on the first wiring layer may further include:

[0080] like Figure 13 As shown, a chip computing layer 32 and multiple photoelectric conversion chips 38 are formed on the first redistribution layer, wherein optical fibers 40 are disposed on the photoelectric conversion chips 38. The optical fibers 40 on the photoelectric conversion chips 38 are used for electrical connections between multiple board-level package structures. The chip computing layer 32 includes at least multiple computing chips. The chip computing layer 32 may also include memory chips or other types of computing chips.

[0081] In this embodiment, the chip computing layer 32 is located on the second wiring layer in the central area of ​​the square panel 22, and the photoelectric conversion chip 38 is located on the second wiring layer in the edge area of ​​the square panel, which facilitates electrical connection with the adjacent packaging structure.

[0082] It should be noted that this embodiment does not specifically limit the type of connector in the chip's computing module; it can be selected according to needs.

[0083] likeFigure 14 and Figure 15 The removal of the jig 58 produces a board-level packaging structure.

[0084] Exemplarily, in the present embodiment, the square panel 22 can be a glass panel.

[0085] In the prior art, the carrier plate is peeled off during packaging, and the final packaging structure does not contain the carrier plate. However, the board-level packaging structure of the present embodiment retains the square glass panel, and effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, thereby solving the problem of mismatch between the large-area EMC and the CTE of the chip in the prior art, and improving the reliability of the board-level packaging structure. In addition, a plurality of conductive pillars are arranged on the retained square panel, thereby realizing vertical interconnection of the packaging structure and effectively shortening the transmission path.

[0086] Embodiment 2

[0087] In step S110, as shown in Figure 16 , a square carrier plate 22 is provided, and a first surface of the square panel 22 is provided with a plurality of grooves 44.

[0088] In the present embodiment, a large-area square panel is used as a carrier plate, which significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration of the board-level packaging structure.

[0089] In step S120, as shown in Figure 17 , the non-functional surface of the plurality of bridge chips 24 is fixedly attached to the bottom wall of the corresponding groove 44. It should be noted that the number of bridge chips 24 is not specifically limited and can be limited according to actual needs.

[0090] In step S130, as shown in Figure 18 and Figure 19 , a first redistribution layer is formed on the first surface of the square panel 22 and the functional surface of the bridge chip 24.

[0091] The process of forming the first redistribution layer can be as follows:

[0092] Specifically, as shown in Figure 4 , a first dielectric layer 28 is formed in the gap, on the first surface of the square panel 22 and on the functional surface of the bridge chip 24. In the present embodiment, the first dielectric layer 28 can be a PI layer.

[0093] The first dielectric layer 28 located on the first surface of the square panel 22 and the functional surface of the bridge chip 24 is patterned to form a plurality of first openings on the first dielectric layer 28.

[0094] As shown in FIG. 5, the first redistribution layer is fixed to the carrier plate 50 by temporary bonding glue. Figure 20 As shown in FIG. 6, the carrier plate 50 is turned over so that it is located at the lower side as a support. Figure 21

[0095] In step S140, a plurality of conductive columns are formed through the thickness of the square panel.

[0096] As shown in FIG. 7, the specific process of forming the conductive column 46 can be as follows: drilling along the second surface of the square panel 22 to form a plurality of through holes through the thickness of the square panel; and electroplating a conductive material in the through holes to form the conductive column 46. Figure 21 In this embodiment, by forming a plurality of conductive columns through the thickness of the square panel, vertical interconnection on both sides of the square panel can be achieved, and the transmission path can be effectively shortened.

[0097] In step S150, as shown in FIG. 8, a second redistribution layer electrically connected to the conductive column 46 is formed on the second surface of the square panel 22.

[0098] Figure 22 The specific process of forming the second redistribution layer includes: forming a second dielectric layer 52 on the second surface of the square panel 22, patterning the second dielectric layer 52 to form a plurality of second openings, and forming a second metal layer 54 in the second openings, wherein the second metal layer 54 is electrically connected to the conductive column 46.

[0099] As shown in FIG. 9, the second dielectric layer 52 can be a PI layer, and the second metal layer 54 can be a copper layer. Figure 22 In step S160, as shown in FIG. 10, a power management module is formed on the second redistribution layer, and a chip operation module is formed on the first redistribution layer.

[0100] Figures 23 to 29 The specific process of forming the power management module on the second redistribution layer includes:

[0101] As shown in FIG. 11, the specific process of forming the power management module on the second redistribution layer includes: forming a power management chip 56 on the second redistribution layer, and forming a plurality of power management circuits 58 on the power management chip 56.

[0102] As shown in FIG. 12, the specific process of forming the chip operation module on the first redistribution layer includes: forming a chip 60 on the first redistribution layer, and forming a plurality of chip operation circuits 62 on the chip 60. Figure 23 ​​​As shown, multiple power management chips 56 and multiple first connectors 34 are formed on the second redistribution layer. Specifically, multiple power management chips 56 and multiple first connectors 34 are formed on the second metal layer 54. Each first connector 34 has a first cable 36 mounted on it. The power management chips 56 supply power to the board-level package structure, and the first connectors 34 enable electrical connections between multiple board-level package structures.

[0103] It should be noted that the first connector 34 and the power management chip 56 can be arranged alternately. Alternatively, the first connector 34 can be located on the second wiring layer at the edge of the square panel 22 to facilitate electrical connections between multiple board-level package structures. The number and distribution of the first connector 34 and the power management chip 56 are not specifically limited and can be selected according to actual needs.

[0104] Specifically, the chip computing module formed on the first interconnect layer may include:

[0105] like Figure 24 As shown, Figure 23 The intermediate package is clamped onto fixture 58 to achieve structural suspension. For example... Figure 25 As shown, Figure 24 The intermediate package shown is flipped over, and the carrier plate 50 is removed. (As shown) Figure 28 As shown, a chip computing layer 32 and a plurality of second connectors 34' are formed on the first redistribution layer, wherein second cables 36' are disposed on the second connectors 34'. The chip computing layer 32 includes at least a plurality of computing chips. The chip computing layer 32 may also include memory chips or other types of computing chips. The second connectors 34' are used for electrical connections between multiple board-level package structures.

[0106] In this embodiment, the chip computing layer 32 is located on the second wiring layer in the central area of ​​the square panel 22, and the second connector 34' is located on the second wiring layer in the edge area of ​​the square panel, which facilitates electrical connection with the adjacent packaging structure.

[0107] Specifically, the chip computing module formed on the first wiring layer may further include:

[0108] like Figure 27 As shown, a chip computing layer 32 and multiple photoelectric conversion chips 38 are formed on the first redistribution layer, wherein optical fibers 40 are disposed on the photoelectric conversion chips 38. The optical fibers 40 on the photoelectric conversion chips 38 are used for electrical connections between multiple board-level package structures. The chip computing layer 32 includes at least multiple computing chips. The chip computing layer 32 may also include memory chips or other types of computing chips.

[0109] In the embodiment, the chip operation layer 32 is located on the second rewiring layer in the central region of the square panel 22, and the photoelectric conversion chip 38 is located on the second rewiring layer in the edge region of the square panel, facilitating electrical connection between the adjacent packaging structures.

[0110] It should be noted that the type of connector in the chip operation module is not specifically limited in the embodiment, and can be selected as needed.

[0111] As shown in Figure 28 and Figure 29 , the removal tool 58 is prepared to obtain the board-level packaging structure.

[0112] For example, in the embodiment, the square panel 22 can be a glass panel.

[0113] In the prior art, the carrier plate is peeled off during packaging, and the final packaging structure does not contain the carrier plate. The board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of mismatching between the large-area EMC and the chip CTE in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of second conductive pillars are provided on the retained square panel, realizing vertical interconnection of the packaging structure and effectively shortening the transmission path.

[0114] Another aspect of the embodiment of the present disclosure provides a board-level packaging structure, which is packaged by using the board-level packaging method S100 described above. Wherein, the specific steps of the board-level packaging method S100 have been described in detail above, and will not be repeated here.

[0115] The board-level packaging structure of the embodiment of the present disclosure uses a large-area square panel as a carrier plate, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration of the board-level packaging structure; The square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the square panel corresponding thereto, thereby reducing the packaging height of the entire packaging structure; The chip operation module realizes high-density interconnection with the help of the plurality of bridge chips, and no longer needs to rely on constructing fine line structures in the RDL; A plurality of conductive pillars penetrating the thickness of the square panel are formed on the square panel, realizing vertical interconnection of the packaging structure and vertical power supply on the back of the square panel, and effectively shortening the transmission path.

[0116] As shown in Figure 30 , another aspect of the embodiment of the present disclosure provides a board-level packaging system A, which includes at least one board-level packaging structure 100 described above. Wherein, the specific structural features of the board-level packaging structure 100 have been described in detail above, and will not be repeated here.

[0117] When the board-level packaging system A includes a plurality of board-level packaging structures 100, the plurality of board-level packaging structures 100 are electrically connected through the first connector 34 and the second connector 34' and the optoelectronic conversion chip 38.

[0118] In an embodiment, the first surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the first cables 36 of the first connector 34, and the second surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the second cables 36' of the second connector 34', forming the board-level packaging system A shown in FIG. 1. Figure 30

[0119] In another embodiment, the first surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the first cables 36 of the first connector 34, and the second surfaces between the plurality of board-level packaging structures 100 can be electrically connected through the optical cables 40 of the optoelectronic conversion chip 38, forming the board-level packaging system A shown in FIG. 2. Figure 30

[0120] It should be noted that in the present embodiment, the electrical connection mode between the plurality of board-level packaging structures 100 is not specifically limited, and can be selected according to actual needs.

[0121] It should be further noted that the number of board-level packaging structures 100 in the board-level packaging system A is not specifically required, and can be selected according to the size of the board-level packaging structure.

[0122] The board-level packaging system of the present embodiment includes at least one board-level packaging structure as described above, which uses a large-area square panel as a carrier board, significantly improving the chip capacity, area utilization rate and I / O density, significantly improving the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high-computing-power integration of the board-level packaging structure. The square panel is provided with a plurality of grooves, and a plurality of bridge chips are arranged in the grooves of the square panel corresponding thereto, thereby reducing the packaging height of the entire packaging structure. The chip computing module realizes high-density interconnection with the aid of the plurality of bridge chips, and no longer needs to rely on the construction of fine line structures in the RDL. A plurality of conductive columns penetrating the thickness of the square panel are formed on the square panel, realizing vertical interconnection of the packaging structure and vertical power supply on the back of the square panel, and effectively shortening the transmission path.

[0123] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present embodiment, and the present embodiment is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present embodiment, and these modifications and improvements are also considered within the protection scope of the present embodiment.​​

Claims

1. A method of packaging a board, characterized by, The method comprises: providing a square panel, a first surface of the square panel being provided with a plurality of grooves; fixing a plurality of bridge chips non-functional surfaces to the corresponding grooves; forming a first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip; forming a plurality of conductive pillars through the thickness of the square panel; forming a second redistribution layer on the second surface of the square panel and electrically connected with the conductive pillars; forming a power management module on the second redistribution layer and a chip operation module on the first redistribution layer; wherein, forming a power management module on the second redistribution layer specifically comprises: forming a plurality of power management chips and a plurality of first connectors on the second redistribution layer, the first connectors being spaced apart from the power management chips; forming a chip operation module on the first redistribution layer specifically comprises: forming a chip operation layer and a plurality of second connectors on the first redistribution layer, and / or forming a chip operation layer and a plurality of photoelectric conversion chips on the first redistribution layer, wherein the chip operation layer at least comprises a plurality of computing chips.

2. The method of claim 1, wherein, The forming of the plurality of conductive pillars through the thickness of the square panel comprises: drilling along the second surface of the square panel to form a plurality of through holes through the thickness of the square panel; electroplating a conductive material in the through holes to form the conductive pillars.

3. The method of claim 1, wherein, The forming of the plurality of conductive pillars through the thickness of the square panel further comprises: when the square panel is provided, the first surface of the square panel is provided with a plurality of blind holes extending to the second surface thereof, and the blind holes are provided with a conductive material; after the first redistribution layer is formed, the second surface of the square panel is thinned to expose the blind holes, and the conductive pillars through the thickness of the square panel are formed.

4. The method of claim 1 to 3, wherein, The fixing of the plurality of bridge chips non-functional surfaces to the corresponding grooves comprises: attaching the non-functional surfaces of the plurality of bridge chips to the bottom walls of the corresponding grooves, and the bridge chips have a gap with the side walls of the grooves; The forming of the first redistribution layer on the first surface of the square panel and the functional surface of the bridge chip comprises: forming a first dielectric layer on the gap, the first surface of the square panel and the functional surface of the bridge chip; patterning the first dielectric layer on the first surface of the square panel and the functional surface of the bridge chip to form a plurality of first openings on the first dielectric layer; forming a first metal layer electrically connected with the bridge chip in the first opening.

5. The method of claim 1 to 3, wherein, The forming of the second redistribution layer on the second surface of the square panel and electrically connected with the conductive pillars comprises: forming a second dielectric layer on the second surface of the square panel; patterning the second dielectric layer to form a plurality of second openings on the second dielectric layer; forming a second metal layer electrically connected with the conductive pillars in the second opening.

6. The method of claim 1 to 3, wherein, The square panel adopts a glass panel.

7. The method of claim 1 to 3, wherein, The operation chip is located on the second redistribution layer in the central region of the square panel; The second connector and the photoelectric conversion chip are located on the second redistribution layer of the square panel edge region.

8. A board-level packaging structure, characterized in that, The board level packaging method of any one of claims 1 to 7 is adopted to form packaging.

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