Bonding defect detection method, detection equipment and storage medium

Abstract

The present disclosure provides a detection method, a detection device, and a storage medium; wherein the detection method includes providing a plurality of first chips and a wafer; detecting first chip defects of the plurality of first chips, and obtaining a first distance between each first chip defect and a corresponding chip corner of the first chip; bonding a plurality of the first chips on the wafer; wherein a bonding interface is formed between the plurality of first chips and the wafer; detecting bonding defects of the bonding interface, and obtaining the coordinates of each bonding defect; based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect, determining whether the first chip defect matches the bonding defect. Thus, a complex image alignment process is avoided, and fast, accurate, and low-resource defect tracing is achieved.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a bonding defect detection method, detection equipment, and storage medium. Background Art

[0002] In the semiconductor manufacturing process, the bonding between chips and wafers is one of the key technologies. However, various defects such as voids and cracks may occur during the bonding process, which will seriously affect the performance and reliability of semiconductor devices.

[0003] Existing detection methods usually rely on direct scanning and analysis of the bonding interface, but this method often cannot accurately distinguish bonding defects from defects in the chip itself, resulting in a high rate of misjudgment. Therefore, a method is needed that can accurately detect and distinguish bonding defects from defects in the chip itself. Defect detection plays a vital role in the manufacturing process of integrated circuits. In related technologies, bonding defects are usually traced back to the defects of the previous layer by means of an overlay scheme, which has a large error. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a bonding defect detection method, a detection device, and a storage medium to quickly, accurately, and less resource-intensively trace defects.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] An embodiment of the present disclosure provides a detection method, including: providing a plurality of first chips and a wafer; detecting first chip defects of the plurality of first chips, and obtaining a first distance between each first chip defect and a corresponding chip corner of the first chip; bonding the plurality of first chips on the wafer; wherein a bonding interface is formed between the plurality of first chips and the wafer; detecting bonding defects at the bonding interface, and obtaining coordinates of each bonding defect; and determining whether the first chip defect and the bonding defect match based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect.

[0007] In the above scheme, multiple second chips are formed on the wafer; the detection method also includes: before bonding multiple first chips on the wafer, detecting second chip defects of multiple second chips, and obtaining the second distance between each second chip defect and the corresponding chip corner of the second chip; based on the coordinates of each of the bonding defects and the second distance corresponding to each of the second chip defects, determining whether the second chip defect and the bonding defect match.

[0008] In the above scheme, the image of the bonding interface includes image contours of multiple first chips; based on the coordinates of each of the bonding defects and the first distance corresponding to each of the first chip defects, determining whether the first chip defect and the bonding defect match, including: determining the first chip defect to be determined based on the coordinates of each of the bonding defects; confirming the coverage range of the first chip defect to be determined on the image of the bonding interface; if at least a part of the image contour of the first chip corresponding to the bonding defect is within the coverage range, determining that the first chip defect and the bonding defect match each other; or, if the image contour of the first chip corresponding to the bonding defect is not within the coverage range, determining that the chip defect and the bonding defect do not match.

[0009] In the above scheme, the coverage range of the first chip defect that needs to be judged is confirmed on the image of the bonding interface, including: on the image of the bonding interface, a circle is drawn with the coordinates of the bonding defect as the center and the first distance of each first chip defect that needs to be judged as the radius to determine the coverage range of each first chip defect that needs to be judged.

[0010] In the above scheme, based on the coordinates of each of the bonding defects, determining the first chip defects that need to be judged includes: obtaining arrangement information of multiple first chips on the wafer; wherein the arrangement information includes chip spacing and row and column values ​​of each first chip; based on the coordinates of each of the bonding defects and the chip spacing, determining the row and column values ​​of the first chip corresponding to each of the bonding defects; based on the row and column values ​​of the first chip corresponding to each of the bonding defects, confirming a first chip corresponding to the bonding defect, and regarding all the first chip defects of a first chip corresponding to the bonding defect as the first chip defects that need to be judged.

[0011] In the above scheme, obtaining the first distance between each of the chip defects and the corresponding chip corner includes: performing laser scanning or electron beam scanning on multiple first chips to generate multiple images of the first chips; establishing a first coordinate system with the chip corner as the origin on the image of each first chip; determining all of the first chip defects of each of the first chips, and obtaining the coordinates of all of the first chip defects on the first coordinate system, and regarding the distance from the coordinates of each of the first chip defects to the origin of the first coordinate system as the first distance of each of the first chip defects.

[0012] In the above scheme, the bonding defects of the bonding interface are detected, and the coordinates of each of the bonding defects are obtained, including: performing ultrasonic scanning or infrared scanning on the bonding interface to generate an image of the bonding interface; on the image of the bonding interface, establishing a second coordinate system with any two mutually perpendicular tangent directions of the image of the bonding interface as coordinate axes; and obtaining the coordinates of each of the bonding defects on the second coordinate system.

[0013] The embodiment of the present disclosure also provides a detection device, including: a first detection unit, a second detection unit, a wafer bonding unit and a data processing unit; wherein the wafer bonding unit is configured to bond multiple first chips on a wafer; wherein a bonding interface is formed between the multiple first chips and the wafer; the first detection unit is configured to detect first chip defects of the multiple first chips before bonding, and obtain a first distance between each first chip defect and the corresponding chip corner of the first chip; the second detection unit is configured to detect bonding defects of the bonding interface, and obtain the coordinates of each bonding defect; the data processing unit is configured to determine whether the first chip defect and the bonding defect match based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect.

[0014] In the above scheme, multiple second chips are formed on the wafer; the first detection unit is also configured to detect second chip defects of multiple second chips before bonding the multiple first chips on the wafer, and obtain the second distance between each second chip defect and the corresponding chip corner of the second chip; the data processing unit is also configured to determine whether the second chip defect and the bonding defect match based on the coordinates of each bonding defect and the second distance corresponding to each second chip defect.

[0015] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program or instructions stored thereon, wherein when the computer program or instructions are executed, the computer executes the detection method according to any one of the above-mentioned solutions.

[0016] The embodiment of the present disclosure provides a detection method, including: providing a plurality of first chips and a wafer; detecting first chip defects of the plurality of first chips, and obtaining a first distance between each first chip defect and a corresponding chip corner of the first chip; bonding a plurality of the first chips on the wafer; wherein a bonding interface is formed between the plurality of first chips and the wafer; detecting bonding defects of the bonding interface, and obtaining the coordinates of each bonding defect; and determining whether the first chip defect and the bonding defect match based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect. In this way, the present disclosure determines whether the first chip defect and the bonding defect are close in space through the position information of the first chip defect of the first chip and the bonding defect on the bonding interface, and further determines whether the first chip defect on the first chip is the cause of the bonding defect. Therefore, compared with the related art, by directly recording and analyzing the position information of the bonding defect and the first chip defect, the complex image alignment process is avoided, thereby realizing fast, accurate and low-resource defect tracing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The process of the detection method provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic diagram of the structure of a detection device provided in an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of a first chip provided in an embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram of the structure of wafer bonding provided in an embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of the bonding interface provided by the embodiment of the present disclosure Figure 1 ;

[0022] Figure 6 The process of the detection method provided in the embodiment of the present disclosure Figure 2 ;

[0023] Figure 7 Schematic diagram of the bonding interface provided by the embodiment of the present disclosure Figure 2 ;

[0024] Figure 8 Schematic diagram of the bonding interface provided by the embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0026] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] If similar descriptions of “first / second” appear in the application documents, the following description is added. In the following description, the terms “first / second / third” involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that “first / second / third” can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0029] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, detection method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, detection method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, detection method, article or device including the element.

[0030] Figure 1 is a flow chart of an optional detection method provided in an embodiment of the present disclosure, Figure 2 is a schematic diagram of the structure of an optional detection device 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 2 The detection device 100 shown in the figure can be used to implement Figure 1 The detection method shown in Figure 1 The steps shown are explained.

[0031] S101. Provide a plurality of first chips and wafers.

[0032] S102 , detecting first chip defects of a plurality of first chips, and acquiring a first distance between each first chip defect and a chip corner of a corresponding first chip.

[0033] In the embodiments of the present disclosure, reference Figure 2 The first inspection unit 10 can inspect the plurality of first chips using defect inspection techniques such as optical inspection and electron beam inspection to identify defects such as scratches, particle contamination, pits, and uneven material removal on the plurality of first chips.

[0034] Figure 3 is a schematic diagram of an optional first chip 110 provided in an embodiment of the present disclosure. It should be noted that: Figure 3 Only the first chip defects A1 and A2 are illustrated in the figure, and the remaining first chip defects of the first chip 110 can be referred to Figure 3 The first chip defects A1 and A2 are shown for easy understanding and will not be described in detail here.

[0035] In the present disclosure, Figure 2 and Figure 3 , the die corner O1 may be a physical corner specified on the first chip 110. The first detection unit 10 may establish a first coordinate system XO1Y with the die corner O1 as the origin, and obtain the coordinate information of all first chip defects on the first chip 110, and then calculate the first distances of all first chip defects through the coordinate information of all first chip defects on the first chip 110, so as to use the first distance of each first chip defect as the reference information of the position of the first chip defect. For example, the first detection unit 10 may obtain the coordinates (X1, Y1) of the first chip defect A1, and then calculate the first distance L1 between the first chip defect A1 and the die corner O1 of the first chip, and use the first distance L1 as the reference information of the position of the first chip defect A1.

[0036] It should also be noted that the first distance of each first chip defect may also include multiple values. For example, the first distance of each first chip defect includes four values, namely: the distance between the first chip defect and the four physical corners of the first chip. For another example, the first distance of each first chip defect includes two values, namely: the distance between the first chip defect and two physical corners on the first chip that are diagonally opposite to each other.

[0037] S103 , bonding a plurality of first chips on the wafer; wherein a bonding interface is formed between the plurality of first chips and the wafer.

[0038] Figure 4 FIG. 1 shows a schematic diagram of bonding a plurality of first chips 110 on a wafer 120. It should be noted that: Figure 4The bonding method shown is D2W (Die to Wafer), and the bonding method between the wafer 120 and the plurality of first chips 110 may also be W2W (Wafer to Wafer), etc., which is not limited here.

[0039] In the present disclosure, in combination Figure 2 and Figure 4 The wafer bonding unit 20 can bond the plurality of first chips 110 to the wafer 120 . A bonding interface 130 is formed between the plurality of first chips 110 and the wafer 120 .

[0040] S104, detecting bonding defects at the bonding interface, and obtaining the coordinates of each bonding defect.

[0041] In the embodiments of the present disclosure, reference Figure 2 The second detection unit 30 can detect the bonding interface 130 by using infrared (IR) microscopy technology and ultrasonic scanning technology, and identify bonding defects such as bonding bubbles and cracks on the bonding interface 130.

[0042] Figure 5 is a schematic diagram of an optional bonding interface provided by an embodiment of the present disclosure. It should be noted that: Figure 5 The image profile 110a shown in the example is Figure 3 and Figure 4 The image profile of the first chip 110 in FIG. 130a is shown as follows: Figure 4 The image profile of the bonding interface 130 is shown in FIG. Figure 5 Only one bonding defect B is shown in the figure. The remaining bonding defects of the bonding interface can be referred to Figure 5 The above is for your understanding and will not be elaborated here.

[0043] The present disclosure embodiment, combined with Figure 2 and Figure 5 , the second detection unit 30 can be established as follows Figure 5 The second coordinate system XO2Y shown, and then, the coordinates (X2, Y2) of the bonding defect B in the second coordinate system XO2Y are obtained.

[0044] S105 . Determine whether the first chip defect matches the bonding defect based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect.

[0045] It should be noted that in the semiconductor manufacturing process, defects are found in the back-end process of the wafer. In order to determine the source of these defects, it is necessary to trace back to the front-end process, and even trace back to the links of raw materials and production equipment. Furthermore, through detailed records, analysis and comparison, it can be determined at which specific link of the front-end process the defects found in the back-end process are caused, as well as the possible reasons. In other words, in the case of a bonding defect at the bonding interface, the embodiment of the present disclosure needs to trace the first chip defect of the first chip before bonding to determine the cause of the bonding defect.

[0046] It should also be noted that in the related art, defects are usually traced through an overlay solution, that is, by comparing images or data of different processes to identify and analyze the source of the defect. However, this overlay solution has problems such as slow processing speed, high resource consumption and insufficient accuracy. For example, the overlay solution requires the alignment of images of different processes, which will process a large number of images or data, resulting in problems such as slow processing speed and high resource consumption. For another example, in the process of aligning images of different processes, due to various reasons such as noise and image quality, the alignment accuracy may be insufficient, making it difficult to accurately trace.

[0047] In the present disclosure, in combination Figure 2 and Figure 5 , the data processing unit 40 can determine the correlation between the first chip defect and the bonding defect through the spatial position relationship. That is, the data processing unit 40 can compare the position information of the first chip defect and the bonding defect to determine whether the first bonding defect on the first chip causes a bonding defect at the bonding interface during the bonding process.

[0048] For example, combined with Figure 2 and Figure 5 The data processing unit 40 can establish a Figure 3 The coverage range 110b of the first chip defect A1 in the image. The coverage range 110b can be a circle with the coordinates (X2, Y2) of the bonding defect B as the center and the first distance L1 of the first chip defect A1 as the radius. At this time, the positional relationship between the first chip defect A1 and the bonding defect B can be determined based on the coverage relationship between the coverage range 110b of the first chip defect A1 and the image contour 110a of the first chip. If the coverage range 110b of the first chip defect A1 intersects with the image contour 110a, the first chip defect and the bonding defect are close in space, and then, the first chip defect A1 matches the bonding defect B, that is, the first chip defect A1 is the cause of the bonding defect B.

[0049] It can be understood that the embodiment of the present disclosure accurately measures and records the position information of the first chip defect on the first chip and the bonding defect on the bonding interface. In this way, the embodiment of the present disclosure determines whether the first chip defect and the bonding defect are close in space through the position information of the first chip defect on the first chip and the bonding defect on the bonding interface, and then determines whether the first chip defect on the first chip is the cause of the bonding defect. Therefore, compared with the related art, the embodiment of the present disclosure avoids the complicated image alignment process by directly recording and analyzing the position information of the bonding defect and the first chip defect, thereby achieving fast, accurate and low-resource defect tracing.

[0050] In some embodiments of the present disclosure, Figure 6 S201 to S203 shown are implemented Figure 1 S104 shown will be described in conjunction with each step.

[0051] S201. Determine a first chip defect that needs to be judged based on the coordinates of each bonding defect.

[0052] Figure 7 is a schematic diagram of another optional image of the bonding interface 130 provided in the embodiment of the present disclosure. It should be noted that, Figure 7 Image outlines of a plurality of first chips are shown.

[0053] In the embodiments of the present disclosure, reference Figure 2 and Figure 7 The data processing unit 40 can determine a first chip corresponding to the bonding defect B among the multiple first chips bonded to the wafer, and then determine all first chip defects on the first chip. In other words, the first chip defects that may be related to the bonding defect B are screened out by the first chip corresponding to the bonding defect B.

[0054] S202: confirming the coverage of the first chip defect to be determined on the image of the bonding interface.

[0055] In the present disclosure, Figure 2 and Figure 7 The data processing unit 40 can obtain an image of the bonding interface and mark the coverage of the first chip defect to be determined on the image. This range can be a circular or rectangular area with a certain size centered on the bonding defect, which is used for subsequent comparison with the image contour of the first chip.

[0056] S203. If at least a portion of the image contour of the first chip corresponding to the bonding defect is within the coverage range, it is determined that the first chip defect and the bonding defect match each other; or, if the image contour of the first chip corresponding to the bonding defect is not within the coverage range, it is determined that the chip defect and the bonding defect do not match each other.

[0057] In the present disclosure, Figure 2 and Figure 7 , compare the image contour of the first chip corresponding to the bonding defect with the above coverage range. If at least a part of the image contour is within the coverage range, it is considered that the first chip defect may have caused a defect in the bonding interface during the bonding process, that is, the two match each other; conversely, if the image contour is not within the coverage range, it is determined that the two do not match.

[0058] In some embodiments of the present disclosure, S301 can also be used to implement Figure 6 S202 shown will be described in conjunction with each step.

[0059] S301. On the image of the bonding interface, draw a circle with the coordinates of the bonding defect as the center and the first distance of each first chip defect to be determined as the radius, to determine the coverage range of each first chip defect to be determined.

[0060] In the present disclosure, Figure 2 and Figure 7 , the data processing unit 40 can use the coordinates of the bonding defect as the center of the circle and the first distance of the first chip defect that may be associated with the bonding defect as the radius to draw a circular area. This circular area represents the possible impact range of the first chip defect that needs to be determined. In this way, the embodiment of the present disclosure achieves an intuitive display and precise definition of the impact range of the first chip defect by accurately calculating and drawing the circular area. This helps to accurately analyze the correlation between chip defects and bonding defects in the subsequent process, and improves the accuracy and efficiency of defect matching.

[0061] In some embodiments of the present disclosure, S401 to S403 can also be used to implement Figure 6 S201 shown will be explained in combination with each step.

[0062] S401, obtaining arrangement information of a plurality of first chips on a wafer; wherein the arrangement information includes chip spacing and row and column values ​​of each first chip.

[0063] S402: Based on the coordinates of each bonding defect and the chip spacing, determine the row and column values ​​of the first chip corresponding to each bonding defect.

[0064] In the present disclosure, Figure 2 and Figure 4The data processing unit 40 may obtain the arrangement information of the plurality of first chips 110 on the wafer 130 from the wafer bonding unit 20. For example, the data processing unit 40 may obtain the spacing between the plurality of first chips 110 and the row and column position of each first chip 110.

[0065] Then, the data processing unit 40 can use the known coordinates of the bonding defects and the chip spacing to infer through calculation which first chip each bonding defect is approximately located above or near, and further determine the row and column values ​​of the corresponding first chip.

[0066] S403 . Based on the row and column values ​​of the first chip corresponding to each bonding defect, identify a first chip corresponding to the bonding defect, and regard all first chip defects of the first chip corresponding to the bonding defect as first chip defects that need to be determined.

[0067] In the present disclosure, in combination Figure 2 and Figure 4 The data processing unit 40 can accurately find the specific first chip corresponding to the bonding defect based on the determined row and column values, and assume that all first chip defects on the first chip may be related to the bonding defect, so these first chip defects on the first chip are regarded as first chip defects that need to be determined.

[0068] In some embodiments of the present disclosure, S501 to S503 can also be used to implement Figure 1 S102 shown will be described in conjunction with each step.

[0069] S501 , performing laser scanning or electron beam scanning on a plurality of first chips to generate images of the plurality of first chips.

[0070] In the embodiments of the present disclosure, reference Figure 2 The first detection unit 10 can use laser scanning or electron beam scanning technology to perform high-precision scanning on multiple first chips to generate their images.

[0071] Then, the first detection unit 10 can be Figure 3 As shown, on the image of each first chip 110 , a first coordinate system XO1Y is established with the chip corner O1 as the origin. The first coordinate system XO1Y is used to subsequently determine the specific position of the first chip defect on the first chip 110 .

[0072] S502 , establishing a first coordinate system on the image of each first chip with the chip corner as the origin.

[0073] S503, determining all first chip defects of each first chip, and obtaining coordinates of all first chip defects in the first coordinate system, and considering the distance from the coordinates of each first chip defect to the origin of the first coordinate system as the first distance of each first chip defect.

[0074] In the embodiments of the present disclosure, reference Figure 2 The first detection unit 10 can determine all first chip defects on each first chip through image processing and analysis technology, and obtain the coordinates of these first chip defects in the first coordinate system. Subsequently, the first detection unit 10 can calculate the distance from each first defect coordinate to the origin of the coordinate system, and this distance is regarded as the first distance of each first chip defect.

[0075] In some embodiments of the present disclosure, S601 to S603 can also be used to implement Figure 1 S104 shown will be described in combination with various steps.

[0076] S601 , performing ultrasonic scanning or infrared scanning on the bonding interface to generate an image of the bonding interface.

[0077] S602. On the image of the bonding interface, a second coordinate system is established with any two mutually perpendicular tangent directions of the image of the bonding interface as coordinate axes.

[0078] S603. Obtain the coordinates of each bonding defect in the second coordinate system.

[0079] In the embodiments of the present disclosure, reference Figure 2 The second detection unit 30 can select ultrasonic scanning or infrared scanning technology to scan the bonding interface and generate its image. Ultrasonic scanning uses the difference in the propagation speed of sound waves in different media to detect the interface structure, while infrared scanning detects based on the property of infrared radiation of the object.

[0080] Then, on the generated bonding interface image, select any two mutually perpendicular tangent directions as coordinate axes and establish Figure 7 The second coordinate system XO2Y is used to determine the specific location of the bonding defect later. Figure 7 As shown, the second detection unit 30 can obtain the coordinates of each bonding defect on the second coordinate system XO2Y through image processing and analysis technology.

[0081] In some embodiments of the present disclosure, the detection method may also be implemented through S701 to S702, which will be described in conjunction with each step.

[0082] S701. Before bonding a plurality of first chips on a wafer, detect second chip defects of a plurality of second chips, and obtain a second distance between each second chip defect and a chip corner of a corresponding second chip.

[0083] In the present disclosure, Figure 2 and Figure 4 , a plurality of second chips may be formed on the wafer 120. The first detection unit 10 may also detect second chip defects of a plurality of second chips on the wafer before bonding a plurality of first chips 110 on the wafer 120, and obtain a second distance between each second chip defect and a chip corner of the corresponding second chip. The method for obtaining the second distance may be understood with reference to the first distance, and will not be described in detail here.

[0084] S702: Based on the coordinates of each bonding defect and the second distance corresponding to each second chip defect, determine whether the second chip defect matches the bonding defect.

[0085] Figure 8 is a schematic diagram of an optional bonding interface provided by an embodiment of the present disclosure. It should be noted that: Figure 8 The image profile 110a shown in the example is Figure 3 and Figure 4 The image profile of the first chip 110 in FIG. 130a is shown as follows: Figure 4 The image profile of the bonding interface 130 , the illustrated image profile 120 a is the image profile of the second chip formed on the wafer.

[0086] In the present disclosure, Figure 2 and Figure 8 In the process of determining whether the second chip defect matches the bonding defect, it is first necessary to determine based on the coordinates of each bonding defect B and the second distance L2 corresponding to each second chip defect. Figure 8 As shown, the data processing unit 40 establishes a coverage range 120b for each second chip defect on the image 130a of the bonding interface, and the range is a circle with the coordinates of the bonding defect B as the center and the second distance L2 of the second chip defect as the radius. Then, by comparing the coverage relationship between the coverage range 120b and the image contour 120a of the second chip, the positional relationship between the second chip defect and the bonding defect can be determined. If the coverage range 120b intersects with the image contour 120a of the second chip, it indicates that the second chip defect and the bonding defect B are close in spatial position, so it can be determined that the second chip defect matches the bonding defect B, that is, the second chip defect is the cause of the bonding defect B.

[0087] In some embodiments of the present disclosure, reference Figure 2, the detection device 100 includes: a first detection unit 10, a second detection unit 30, a wafer bonding unit 20 and a data processing unit 40. Among them, the wafer bonding unit 20 is configured to bond multiple first chips on a wafer; wherein a bonding interface is formed between the multiple first chips and the wafer. The first detection unit 10 is configured to detect the first chip defects of the multiple first chips before bonding, and obtain the first distance between each first chip defect and the chip corner of the corresponding first chip. The second detection unit 30 is configured to detect the bonding defects of the bonding interface, and obtain the coordinates of each bonding defect; the data processing unit 40 is configured to determine whether the first chip defect and the bonding defect match based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect. In this way, the embodiment of the present disclosure directly records and analyzes the position information of the bonding defect and the first chip defect. Therefore, compared with the related art, the complex image alignment process is avoided, thereby achieving fast, accurate and low-resource defect tracing.

[0088] In some embodiments of the present disclosure, reference Figure 2 , a plurality of second chips are formed on the wafer. The first detection unit 10 is also configured to detect second chip defects of the plurality of second chips before bonding the plurality of first chips on the wafer, and obtain a second distance between each second chip defect and the chip corner of the corresponding second chip. The data processing unit 40 is also configured to determine whether the second chip defect and the bonding defect match based on the coordinates of each bonding defect and the second distance corresponding to each second chip defect. Thus, compared with the related art, the complex image alignment process is avoided, thereby achieving fast, accurate and low-resource defect tracing.

[0089] Based on the aforementioned embodiments, the embodiments of the present disclosure further provide a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the detection method provided in the aforementioned embodiments.

[0090] It should be noted that the above-mentioned computer-readable storage medium can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various electronic devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0091] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, detection method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, detection method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, detection method, article or device including the element.

[0092] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The detection methods disclosed in the several detection method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new detection method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several detection method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new detection method embodiments or device embodiments.

[0093] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A method for detecting bonding defects, characterized in that: include: providing a plurality of first chips and wafers; Detecting first chip defects of a plurality of the first chips, and acquiring a first distance between each of the first chip defects and a corresponding chip corner of the first chip; Bonding a plurality of the first chips on the wafer; wherein a bonding interface is formed between the plurality of the first chips and the wafer; Detecting bonding defects at the bonding interface, and obtaining coordinates of each bonding defect; Based on the coordinates of each of the bonding defects and the first distance corresponding to each of the first chip defects, it is determined whether the first chip defect matches the bonding defect.

2. The detection method according to claim 1, characterized in that: in, A plurality of second chips are formed on the wafer; The detection method further comprises: Before bonding the plurality of the first chips on the wafer, detecting second chip defects of the plurality of the second chips, and acquiring a second distance between each of the second chip defects and a chip corner of the corresponding second chip; Based on the coordinates of each of the bonding defects and the second distance corresponding to each of the second chip defects, it is determined whether the second chip defect matches the bonding defect.

3. The detection method according to claim 1, characterized in that: The image of the bonding interface includes a plurality of image outlines of the first chips; Determining whether the first chip defect matches the bonding defect based on the coordinates of each of the bonding defects and the first distance corresponding to each of the first chip defects includes: Determining the first chip defect that needs to be determined based on the coordinates of each of the bonding defects; Confirming the coverage of the first chip defect to be determined on the image of the bonding interface; If at least a portion of the image contour of the first chip corresponding to the bonding defect is within the coverage range, it is determined that the first chip defect and the bonding defect match each other; alternatively, if the image contour of the first chip corresponding to the bonding defect is not within the coverage range, it is determined that the chip defect and the bonding defect do not match each other.

4. The detection method according to claim 3, characterized in that: Confirming the coverage of the first chip defect to be determined on the image of the bonding interface includes: On the image of the bonding interface, a circle is drawn with the coordinates of the bonding defect as the center and the first distance of each first chip defect that needs to be determined as the radius to determine the coverage range of each first chip defect that needs to be determined.

5. The detection method according to claim 3, characterized in that: Determining the first chip defect that needs to be determined based on the coordinates of each of the bonding defects includes: Acquire arrangement information of the plurality of first chips on the wafer; wherein the arrangement information includes chip spacing and row and column values ​​of each first chip; Based on the coordinates of each bonding defect and the chip spacing, determining the row and column values ​​of the first chip corresponding to each bonding defect; Based on the row and column values ​​of the first chip corresponding to each bonding defect, one first chip corresponding to the bonding defect is identified, and all the first chip defects of one first chip corresponding to the bonding defect are regarded as the first chip defects that need to be determined.

6. The detection method according to claim 1, characterized in that: Acquiring the first distance between each chip defect and the corresponding chip corner includes: Performing laser scanning or electron beam scanning on the plurality of the first chips to generate images of the plurality of the first chips; On each image of the first chip, establish a first coordinate system with the chip corner as the origin; Determine all of the first chip defects of each of the first chips, obtain coordinates of all of the first chip defects in the first coordinate system, and regard the distance from the coordinates of each of the first chip defects to the origin of the first coordinate system as the first distance of each of the first chip defects.

7. The detection method according to claim 1, characterized in that: Detecting the bonding defects of the bonding interface and obtaining the coordinates of each bonding defect includes: Performing ultrasonic scanning or infrared scanning on the bonding interface to generate an image of the bonding interface; On the image of the bonding interface, a second coordinate system is established with any two mutually perpendicular tangent directions of the image of the bonding interface as coordinate axes; The coordinates of each of the bonding defects in the second coordinate system are obtained.

8. A detection device, characterized in that: include: A first detection unit, a second detection unit, a wafer bonding unit and a data processing unit; wherein, The wafer bonding unit is configured to bond a plurality of first chips on a wafer; wherein a bonding interface is formed between the plurality of first chips and the wafer; The first detection unit is configured to detect first chip defects of the plurality of first chips before bonding, and obtain a first distance between each first chip defect and a chip corner of the corresponding first chip; The second detection unit is configured to detect bonding defects of the bonding interface and obtain the coordinates of each bonding defect; The data processing unit is configured to determine whether the first chip defect matches the bonding defect based on the coordinates of each bonding defect and the first distance corresponding to each first chip defect.

9. The detection device according to claim 8, characterized in that: A plurality of second chips are formed on the wafer; The first detection unit is further configured to detect second chip defects of a plurality of second chips before bonding the plurality of first chips on the wafer, and obtain a second distance between each second chip defect and a chip corner of the corresponding second chip; The data processing unit is further configured to determine whether the second chip defect matches the bonding defect based on the coordinates of each bonding defect and the second distance corresponding to each second chip defect.

10. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instructions are executed, the computer is caused to perform the detection method according to any one of claims 1 to 7.

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