SOI wafer and forming method thereof

Abstract

According to the SOI wafer and the forming method thereof provided by the invention, the plasma treatment process is executed before the bonding process, the plasma treatment is performed on the second buried oxide layer on the device wafer, and the process time and the plasma power in the plasma treatment process meet the preset conditions; then, a bonding process is executed, and the supporting wafer and the device wafer are bonded to form an SOI wafer; and performing a thinning process to thin the thickness of one surface of the device wafer of the SOI wafer, which is far away from the support wafer, and the edge step of the support wafer has no silicon island and the center of the device wafer has no bubble. The plasma power and time are adjusted to meet the preset conditions, the thickness of SiO2 generated in the plasma treatment process is reduced, meanwhile, the hydrophilicity of the device wafer surface is properly improved, a silicon island is prevented from being formed on an edge step of the supporting wafer, and then particles are prevented from being formed in the later process and adsorbed on the silicon island surface of the supporting wafer, so that the device wafer quality is improved. And therefore, the yield of the subsequent process is seriously influenced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an SOI wafer and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuit technology, the application of bulk silicon substrates in integrated circuits is getting closer and closer to the limit, so SOI substrates came into being. Compared with bulk silicon substrates, SOI substrates have great advantages, such as: reducing parasitic capacitance and increasing operating speed; reducing leakage and having lower power consumption; eliminating latch-up effects, etc. In addition, SOI substrates are compatible with existing bulk silicon integrated circuit technology, so SOI substrates can be quickly and widely used in the field of integrated circuits. Therefore, it is extremely important to prepare high-quality SOI substrates. The silicon islands formed on the edge steps of the SOI substrate will seriously affect the application of the SOI substrate in the subsequent integrated circuit manufacturing. Therefore, the problem of silicon islands cannot be ignored in the manufacture of SOI substrates.

[0003] Figure 1 It is a side view of a SOI wafer in the prior art. Figure 2 yes Figure 1 Top view of the device wafer at point A close to the support wafer. Figure 3 yes Figure 1A top view of the support wafer at point B in the middle, close to the device wafer side. When the bonding force between the device wafer 20 and the support wafer 10 is insufficient, bubbles 201 will appear on the surface edge of the device wafer 20 close to the support wafer 10 side, and the diameter of the bubbles 201 is usually less than 0.5 mm, that is, small bubbles. At present, a plasma treatment process is performed before performing the bonding process to increase the hydrophilicity of the bonding surface of the support wafer 10 and the device wafer 20, thereby enhancing the bonding force between the device wafer 20 and the support wafer 10. However, the plasma treatment process treats the surface of the device wafer 20, and in addition to increasing the hydrophilicity of the surface of the device wafer 20, it also reacts with Si to generate SiO2, and the number of dangling bonds on the surface of the device wafer 20 is greater. Therefore, in the bonding process, the edges of the device wafer 20 and the support wafer 10 are in closer contact, thereby forming a strong bonding force, so the impact on the device wafer 20 with a thick buried oxide layer is more significant. During the stripping process, the area where the device wafer edge rolls off will partially remain at the edge of the supporting wafer to form a silicon island. The area where the device wafer edge rolls off refers to the device wafer edge being arc-shaped and not at the same height. There will be a height drop, that is, the device wafer edge area is uneven. In the subsequent thinning process, the thinning process is a non-contact flattening process, including first performing an oxidation process and then using a wet etching process to remove the oxide layer. After the thinning process, the silicon island 101 on the edge step of the supporting wafer 10 is prone to fall off and form particles adsorbed on the surface of the SOI wafer, causing device failure and seriously affecting the yield of the subsequent process. Summary of the invention

[0004] The object of the present invention is to provide an SOI wafer and a method for forming the same, so as to solve the problem that the silicon island on the edge step of the supporting wafer of the SOI wafer causes device failure and seriously affects the yield rate of the subsequent process.

[0005] In order to solve the above technical problems, the present invention provides a method for forming an SOI wafer, comprising:

[0006] Provide support wafers and device wafers;

[0007] Performing a thermal oxidation process to form a first buried oxide layer on the support wafer and a second buried oxide layer on the device wafer;

[0008] Performing a plasma treatment process to perform a plasma treatment process on the second buried oxide layer on the device wafer to form dangling bonds on the surface of the second buried oxide layer, and the process time and plasma power in the plasma treatment process meet preset conditions;

[0009] Performing a bonding process to bond the support wafer and the device wafer to form an SOI wafer;

[0010] A thinning process is performed to thin the thickness of the device wafer of the SOI wafer away from the support wafer, and there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the support wafer.

[0011] Optionally, the process time and plasma power in the plasma treatment process satisfy the preset conditions:

[0012] [4000 / (P-90)+7]≤T≤[3000 / (P-120)+24]

[0013] Wherein, P is plasma power, in W, and the range of plasma power P is 200 W to 550 W, and T is process time, in s.

[0014] Optionally, the gas used in the plasma treatment process is oxygen, nitrogen or helium.

[0015] Optionally, before performing the bonding process, an ion implantation process is performed to form an implantation damage layer below the second buried oxide layer of the device wafer and close to the interface between the second buried oxide layer and the device wafer.

[0016] Optionally, the ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions.

[0017] Optionally, after performing the bonding process, a stripping process is performed, and the device wafer is stripped at the implantation damage layer to reduce the thickness of the device wafer, and a step is formed at the edge of the support wafer.

[0018] Optionally, the thickness of the second buried oxide layer on the device wafer is 1000 angstroms to 2000 angstroms.

[0019] Optionally, the thickness of the first buried oxide layer on the support wafer is 18000 angstroms to 19000 angstroms.

[0020] Optionally, the initial total thickness variation of the support wafer and the device wafer is less than 0.5 μm.

[0021] Based on the same inventive concept, the present invention also provides an SOI wafer, which is prepared by any of the above-mentioned methods for forming an SOI wafer.

[0022] In the method for forming an SOI wafer provided by the present invention, a thermal oxidation process is first performed to form a first buried oxide layer on a support wafer, and a second buried oxide layer is formed on a device wafer; then a plasma treatment process is performed to plasma treat the second buried oxide layer on the device wafer to form hanging bonds on the surface of the second buried oxide layer, and the process time and plasma power in the plasma treatment process meet preset conditions; a bonding process is performed to bond the support wafer and the device wafer to form an SOI wafer; finally, a thinning process is performed to thin the thickness of the device wafer of the SOI wafer away from the side of the support wafer, and there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the side of the support wafer. The present invention adjusts the plasma power and process time in the plasma treatment process so that the plasma power and process time meet preset conditions, so that there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the side of the support wafer. By reducing the thickness of SiO2 generated during plasma treatment and appropriately increasing the hydrophilicity of the device wafer surface, the formation of silicon islands on the edge steps of the support wafer can be avoided, thereby avoiding the formation of particles adsorbed on the silicon island surface of the support wafer in the subsequent process, causing device failure and seriously affecting the yield of the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0024] Figure 1 It is a side view of a SOI wafer in the prior art.

[0025] Figure 2 yes Figure 1 Top view of the device wafer at point A close to the support wafer.

[0026] Figure 3 yes Figure 1 Top view of the support wafer at point B, close to the device wafer.

[0027] Figure 4 It is a flow chart of a method for forming an SOI wafer according to an embodiment of the present invention.

[0028] Figures 5 to 10 It is a schematic diagram of the structure corresponding to the steps of the method for forming an SOI wafer according to an embodiment of the present invention.

[0029] Fig.11 1 is a graph showing the relationship between process time and power and silicon islands on a supporting wafer in a plasma treatment process according to an embodiment of the present invention.

[0030] In the attached figure:

[0031] 10-support wafer; 20-device wafer;

[0032] 101-Silicon Island; 201-Bubble;

[0033] 11-first buried oxide layer; 21-second buried oxide layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0035] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] Figure 4 FIG. 1 is a flow chart of a method for forming an SOI wafer according to an embodiment of the present invention. Figure 4 As shown, this embodiment provides a method for forming an SOI wafer, comprising:

[0037] Step S10, providing a support wafer and a device wafer;

[0038] Step S20, performing a thermal oxidation process to form a first buried oxide layer on the support wafer and a second buried oxide layer on the device wafer;

[0039] Step S30, performing a plasma treatment process to perform plasma treatment on the second buried oxide layer on the device wafer to form dangling bonds on the surface of the second buried oxide layer, and the process time and plasma power in the plasma treatment process meet preset conditions;

[0040] Step S40, performing a bonding process to bond the support wafer and the device wafer to form an SOI wafer;

[0041] Step S50, performing a thinning process to thin the thickness of the device wafer of the SOI wafer away from the support wafer, and there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the support wafer.

[0042] Figures 5 to 10 1 is a schematic diagram of the structure corresponding to the steps of the method for forming an SOI wafer according to an embodiment of the present invention. Figures 5 to 10 The specific embodiments of the present invention are described in detail.

[0043] like Figure 5 As shown, a support wafer 10 is provided, and the support wafer 10 is used to support the device wafer 20 when the device wafer 20 is thinned. The thickness of the support wafer 10 is, for example, 773μm to 777μm. The total thickness variation (Total Thickness Variation, TTV) of the support wafer 10 is less than 0.5μm. TTV refers to the maximum thickness difference between the thickest point and the thinnest point of the wafer on its surface. TTV is used to evaluate the thickness uniformity of the wafer to ensure that the thickness of the wafer is evenly distributed during processing to avoid affecting the performance of subsequent process steps and the final product.

[0044] like Figure 6 As shown, a device wafer 20 is provided, and the device wafer 20 provides an operating platform for subsequent processes. It can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate of the device wafer 20 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the device wafer 20 is a silicon wafer. The thickness of the device wafer 20 is, for example, 773μm to 777μm. The total thickness variation (TTV) of the device wafer 20 is less than 0.5μm.

[0045] Please continue to refer to Figure 5 and Figure 6 , performing a thermal oxidation process to form a first buried oxide layer 11 on the support wafer 10, and to form a second buried oxide layer 21 on the device wafer 20. The thickness of the first buried oxide layer 11 on the support wafer 10 is, for example, 18000 angstroms to 19000 angstroms. The thickness of the second buried oxide layer on the device wafer 20 is, for example, 1000 angstroms to 2000 angstroms.

[0046] like Figure 7 As shown, an ion implantation process is performed to form an implantation damage layer below the second buried oxide layer 21 of the device wafer 20 and near the interface between the second buried oxide layer 21 and the device wafer 20. The ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions. The implantation depth of the ion implantation process is 0.2 μm to 0.3 μm.

[0047] like Figure 8 As shown, a plasma treatment process is performed to perform a plasma treatment process on the second buried oxide layer 21 on the device wafer 20 to form dangling bonds on the surface of the second buried oxide layer 21, thereby enhancing the bonding force between the device wafer 20 and the support wafer 10 in the subsequent bonding process. The gas of the plasma treatment process is one of oxygen, nitrogen or argon. When the gas of the plasma treatment process is oxygen, performing a plasma treatment process on the device wafer 20 increases the hydrophilicity of the surface of the device wafer 20, and also additionally increases the thickness of the second buried oxide layer 21, thereby increasing the number of dangling bonds in the second buried oxide layer 21, which is beneficial to enhancing the bonding force between the device wafer 20 and the support wafer 10 in the subsequent bonding process. However, due to the increase in the thickness of the second buried oxide layer 21, the first buried oxide layer 11 at the edge step portion of the device wafer 20 and the support wafer 10 will be in closer contact during the bonding process, thereby forming a stronger bonding force at the edge of the device wafer 20 and the support wafer 10, resulting in the formation of silicon islands on the edge steps of the support wafer 10 during the subsequent SOI wafer manufacturing process. In order to balance the bonding force and silicon island issues, the process parameters of the plasma treatment process are adjusted when the device wafer 20 is subjected to a plasma treatment process, such as reducing the power of the plasma treatment process, shortening the process time of the plasma treatment process, etc., to reduce the bonding force at the edge step portion of the SOI wafer and reduce the thickness of the generated second buried oxide layer, thereby reducing or even eliminating the silicon island. Therefore, in this embodiment, there is no silicon island on the edge step of the support wafer of the SOI wafer, and there is no bubble at the center of the side of the device wafer close to the support wafer. The process time and plasma power in the plasma treatment process meet the preset conditions;

[0048] [4000 / (P-90)+7]≤T≤[3000 / (P-120)+24]

[0049] Wherein, P is plasma power, in watts (W), and the range of plasma power P is 200 W to 550 W, and T is process time, and the unit of process time is seconds (S). That is, when the process time and plasma power in the plasma treatment process meet the preset conditions, it is ensured that there is no silicon island on the edge step of the support wafer of the SOI wafer in this embodiment, and there is no bubble on the center of the side of the device wafer close to the support wafer.

[0050] like Fig. 9 As shown, a bonding process is performed to bond the support wafer 10 and the device wafer 20 to form an SOI wafer.

[0051] like Fig.10 As shown, a stripping process is performed, and the device wafer 20 is stripped at the implantation damage layer to reduce the thickness of the device wafer 20. Since the bonding force of the step portion of the edge of the SOI wafer is relatively small, when the device wafer 20 on the implantation damage layer is stripped, the device wafer 20 on the edge of the SOI wafer is also stripped at the same time. After stripping, the support wafer 10 at the edge of the SOI wafer forms a step shape with the device wafer 20, and there is no silicon island on the edge step of the support wafer 10.

[0052] After the stripping process is performed, a thinning process is performed to thin the thickness of the device wafer 20 away from the support wafer 10, and there is no silicon island on the edge step of the support wafer 10, and there is no Picots (bubble) in the center of the side of the device wafer 20 close to the support wafer 10. The thinning process includes first performing an oxidation process to form an oxide layer on the surface of the device wafer 20 away from the support wafer 10, and then using a wet etching process to remove the oxide layer. The solution of the wet etching process includes hydrofluoric acid. After the thinning process, there is no silicon island on the edge step of the support wafer 10.

[0053] like Fig.10 As shown, this embodiment also provides an SOI wafer, which is prepared by any of the above-mentioned methods for forming an SOI wafer. It includes a support wafer 10 and a device wafer 20 located on the support wafer 10 and bonded to the support wafer 10, the support wafer 10 is used to support the device wafer 20, and a first buried oxide layer 11 and a second buried oxide layer 21 are formed in the support wafer 10 and the device wafer 20. The edges of the support wafer 10 and the device wafer 20 are stepped. There is no silicon island on the edge step of the support wafer 10, and there is no bubble in the center of the surface of one side of the device wafer 20 close to the support wafer.

[0054] The inventor conducted an experiment on the effect of plasma treatment process on silicon islands and bubbles in SOI wafers. The experiment was set up as five groups, each with four groups, for a total of 20 groups. The power of the plasma treatment process in each group is the same, and the power of the plasma treatment process between different groups is different, namely 550W, 500W, 400W, 300W and 200W. The process time of the plasma treatment process in each group is different. The process time in the three groups of 550W, 500W and 400W is 10s, 20s, 30s and 40s. As the power of the plasma treatment process decreases, the process time is increased to meet the bonding force between the support wafer 10 and the device wafer 20. The process time in the 300W experimental group is 20s, 30s, 40s and 50s. The process time in the 200W experimental group is 40s, 50s, 60s and 70s. In this embodiment, the thickness of the first buried oxide layer 11 of the support wafer 10 is, for example, 19000 angstroms, and the thickness of the second buried oxide layer 21 on the device wafer 20 is, for example, 1000 angstroms. The remaining experimental steps and parameters are the same as those in the above embodiment and will not be repeated here.

[0055]

[0056]

[0057] Fig.11 This is a relationship diagram of the influence of process time and power on silicon islands and bubbles on a supporting wafer in a plasma treatment process according to an embodiment of the present invention. Fig.11 This is also an experimental data graph. Fig.11 In the figure, the horizontal axis is Power (power), the unit is watt (W). The vertical axis is Time (time), the unit is second (s). The red diamond is a silicon island with no small holes (bubbles), the green five-pointed star is a silicon island without small holes (bubbles), and the red triangle is a silicon island without small holes (bubbles). Fig.11It can be seen that the silicon islands in the edge step area of ​​the final SOI wafer in Experiment Groups 1-4 and 2-4 are the most serious. The density of silicon islands in the edge step area of ​​the final SOI wafer in Experiment Groups 3-4, 4-4 and 5-4 is reduced. That is, as the power of the plasma treatment process decreases, the density of silicon islands in the edge step area of ​​the final SOI wafer decreases successively. For the same plasma treatment process power and the experimental group with the shortest process time, bubbles will appear in the final SOI wafer. Therefore, in order to balance the problems of silicon islands and bubbles, the process parameters of the plasma treatment process are adjusted when the device wafer 20 is plasma treated, such as reducing the plasma power, shortening the plasma treatment time, etc., to reduce the bonding force of the edge step part of the SOI wafer and reduce the thickness of the generated second buried oxide layer, thereby reducing or even eliminating silicon islands. However, if the power is too small or the time is too short, bubbles will appear in the SOI wafer. Therefore, the process time and plasma power in the plasma treatment process in this embodiment meet the preset conditions;

[0058] [4000 / (P-90)+7]≤T≤[3000 / (P-120)+24]

[0059] Wherein, P is plasma power, in W, and the range of plasma power P is 200 W to 550 W, and T is process time, and the unit of process time is second (S). In this embodiment, the process time and plasma power in the plasma treatment process are adjusted to meet the preset conditions, so that the device wafer and the support wafer meet the bonding force while no silicon island is formed, that is, there are neither bubbles nor silicon islands in the SOI wafer.

[0060] In summary, in the method for forming an SOI wafer provided in an embodiment of the present invention, a thermal oxidation process is first performed to form a first buried oxide layer on a support wafer, and a second buried oxide layer is formed on a device wafer; then a plasma treatment process is performed to plasma treat the second buried oxide layer on the device wafer to form hanging bonds on the surface of the second buried oxide layer, and the process time and plasma power in the plasma treatment process meet preset conditions; a bonding process is performed to bond the support wafer and the device wafer to form an SOI wafer; finally, a thinning process is performed to thin the thickness of the device wafer of the SOI wafer away from the side of the support wafer, and there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the side of the support wafer. The present invention adjusts the plasma power and process time in the plasma treatment process so that the plasma power and process time meet preset conditions, so that there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the side of the support wafer. By reducing the thickness of SiO2 generated during plasma treatment and appropriately increasing the hydrophilicity of the device wafer surface, the formation of silicon islands on the edge steps of the support wafer can be avoided, thereby avoiding the formation of particles adsorbed on the silicon island surface of the support wafer in the subsequent process, causing device failure and seriously affecting the yield of the subsequent process.

[0061] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming an SOI wafer, characterized in that: include: Provide support wafers and device wafers; Performing a thermal oxidation process to form a first buried oxide layer on the support wafer and a second buried oxide layer on the device wafer; Performing a plasma treatment process to perform plasma treatment on the second buried oxide layer on the device wafer to form dangling bonds on the surface of the second buried oxide layer, and the process time and plasma power in the plasma treatment process meet preset conditions; Performing a bonding process to bond the support wafer and the device wafer to form an SOI wafer; A thinning process is performed to thin the thickness of the device wafer of the SOI wafer away from the support wafer, and there is no silicon island on the edge step of the support wafer, and there is no bubble on the center of the device wafer close to the support wafer.

2. The method for forming an SOI wafer according to claim 1, characterized in that: The process time and plasma power in the plasma treatment process satisfy the preset conditions: [4000 / (P-90)+7]≤T≤[3000 / (P-120)+24] Wherein, P is plasma power, in W, and the range of plasma power P is 200 W to 550 W, and T is process time, in s.

3. The method for forming an SOI wafer according to claim 1, characterized in that: The gas used in the plasma treatment process is oxygen, nitrogen or helium.

4. The method for forming an SOI wafer according to claim 1, wherein: Before performing the bonding process, an ion implantation process is performed to form an implantation damage layer below the second buried oxide layer of the device wafer and close to the interface between the second buried oxide layer and the device wafer.

5. The method for forming an SOI wafer according to claim 4, characterized in that: The ions implanted in the ion implantation process are hydrogen ions or hydrogen-helium mixed ions.

6. The method for forming an SOI wafer according to claim 4, characterized in that: After the bonding process is performed, a stripping process is performed, wherein the device wafer is stripped at the implantation damage layer to reduce the thickness of the device wafer, and a step is formed at the edge of the support wafer.

7. The method for forming an SOI wafer according to claim 1, characterized in that: The thickness of the second buried oxide layer on the device wafer is 1000 angstroms to 2000 angstroms.

8. The method for forming an SOI wafer according to claim 1, characterized in that: The thickness of the first buried oxide layer on the supporting wafer is 18000 angstroms to 19000 angstroms.

9. The method for forming an SOI wafer according to claim 1, characterized in that: The initial total thickness variation of the support wafer and the device wafer is less than 0.5 μm.

10. An SOI wafer, characterized in that: The SOI wafer is prepared by the method for forming the SOI wafer as described in any one of claims 1 to 9.

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