Chip packaging structure and chip packaging method

Abstract

The invention discloses a chip packaging structure and a chip packaging method, the chip packaging structure comprises a plurality of chips, a packaging sleeve assembly, a first rewiring layer and a second rewiring layer, the chips comprise a first chip and a second chip, the first chip is provided with a plurality of first interconnection pins and a plurality of first external connection pins, and the second chip is provided with a plurality of second external connection pins; the second chip is provided with a plurality of second interconnection pins and a plurality of second external connection pins, the second interconnection pins are located on the side, close to the first chip, of the second chip and electrically connected with the first interconnection pins, and the second external connection pins are located on the side, away from the first chip, of the second chip and electrically connected with the first rewiring layer; the first chip comprises an overlapping part and a protruding part, the projection of the protruding part is located on the outer side of the projection of the second chip in the direction perpendicular to the stacking direction, a receding area is formed in the packaging sleeve assembly and located below the protruding part, and a conductive piece extending in the stacking direction is arranged in the receding area. And the first external connection pin is electrically connected with the first rewiring layer through the second rewiring layer and the conductive piece.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] With the continuous development of microelectronics technology, users have higher and higher requirements for system miniaturization, multi-function, low power consumption, etc., especially the blowout of market demand for portable handheld terminals in recent years, such as smart phones, tablet computers and various wearable devices, which require higher integration and interconnection capabilities. Three-dimensional stacking packaging is a very effective technical approach to meet the above requirements.

[0003] The existing three-dimensional stacked packaging structure, especially the three-dimensional fan-out packaging structure, often needs to adopt two or more plastic sealing processes to achieve wafer reconstruction and plastic sealing protection. The three-dimensional stacked packaging structure includes at least two chips, and a large number of pins need to be led out. However, in the existing chip packaging structure, the pins used to connect the chips and the pins used to connect with external components are usually routed on the same side of the chip packaging structure. The large number of pins greatly increases the risk of crossing the wiring. In order to reduce the risk of crossing the wiring, the area of ​​the chip packaging structure is usually increased to provide a larger wiring space, and the wiring will be selected between different layers. However, this will increase the thickness of the chip packaging structure, and ultimately lead to a larger overall volume of the packaging structure, which is not conducive to miniaturization. Summary of the invention

[0004] In view of this, the present invention provides a chip packaging structure and a chip packaging method to solve the problem that the overall volume of the existing packaging structure is too large and is not conducive to miniaturization.

[0005] On the one hand, the present application provides a chip packaging structure, comprising a plurality of stacked chips, a packaging sleeve component for packaging the plurality of chips therein, and a first redistribution layer and a second redistribution layer, wherein the chip comprises a first chip and a second chip arranged along a stacking direction, a first interconnection pin and a first external connection pin are provided on a side of the first chip close to the second chip, and a second interconnection pin and a second external connection pin are provided on the second chip; the first redistribution layer is located on a side of the second chip away from the first chip, and the second redistribution layer is located between the first chip and the second chip;

[0006] The second interconnect pin is located at a side of the second chip close to the first chip and is directly electrically connected to the first interconnect pin through the second redistribution layer, and the second external connection pin is located at a side of the second chip away from the first chip and is electrically connected to the first redistribution layer;

[0007] The first chip includes an overlapping portion and a protruding portion. In a direction perpendicular to the stacking direction, the projection of the overlapping portion is located on the inner side of the projection of the second chip, and the projection of the protruding portion is located on the outer side of the projection of the second chip. A clearance area is formed in the packaging sleeve assembly at a position corresponding to the protruding portion. A conductive member extending along the stacking direction is provided in the clearance area. The first external connection pin of the first chip is electrically connected to the conductive member through the second redistribution layer, and is electrically connected to the first redistribution layer through the conductive member. Compared with the first interconnection pin, the first external connection pin is closer to the side of the protruding portion away from the overlapping portion.

[0008] In some embodiments, the first interconnection pin is located at the overlapping portion, and the first interconnection pin is arranged opposite to the corresponding second interconnection pin; and / or,

[0009] The protruding parts are respectively provided on opposite sides of the overlapping part, and the packaging sleeve component forms the giving area at the corresponding position of each protruding part. The conductive part is provided in each giving area, and the first chip includes the first external connection pins respectively arranged corresponding to the conductive parts.

[0010] In some embodiments, the second chip partially protrudes beyond the outer edge of the overlapping portion, and the direction in which the second chip protrudes beyond the outer edge of the overlapping portion is different from the direction in which the protruding portion protrudes beyond the outer edge of the second chip, and part of the second external connection pins are arranged at the position where the second chip protrudes beyond the overlapping portion.

[0011] In some embodiments, the first redistribution layer is a multi-layer structure, the second redistribution layer is a single-layer structure, and a thickness of the second redistribution layer is less than a thickness of the first redistribution layer.

[0012] In some embodiments, a shielding member is disposed in the packaging sleeve assembly, the shielding member surrounds the outer periphery of the second chip, and the shielding member is at least partially located in the clearance area.

[0013] In some embodiments, the shielding member includes a plurality of shielding columns arranged at intervals, the packaging sleeve assembly is provided with a plurality of mounting holes spaced apart from each other, the plurality of mounting holes are arranged around the periphery of the second chip, and each of the shielding columns is respectively received in a corresponding mounting hole.

[0014] On the other hand, the present application provides a chip packaging method, comprising:

[0015] providing a substrate;

[0016] forming a photoresist layer on the substrate and disposing a first redistribution layer on the photoresist layer;

[0017] Disposing a plurality of conductive members on the first redistribution layer and forming a chip mounting position between the plurality of conductive members;

[0018] sequentially completing the connection and packaging of the second chip and the connection and packaging of the first chip;

[0019] The substrate and the photoresist layer are removed to obtain a chip packaging structure.

[0020] In some embodiments, the step of disposing a first redistribution layer on the photoresist layer includes:

[0021] Disposing a first conductive layer on the photoresist layer and a dielectric layer encapsulating the first conductive layer inside;

[0022] Disposing a second conductive layer in the dielectric layer, with one side of the second conductive layer connected to the first conductive layer and the other side exposed to the surface of the dielectric layer;

[0023] A third conductive layer is disposed on a side of the dielectric layer away from the photoresist layer, and one side of the third conductive layer is electrically connected to the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer together form the first redistribution layer.

[0024] In some embodiments, the sequentially completing the connection and packaging of the second chip and the connection and packaging of the first chip includes:

[0025] Mounting the second chip to the chip mounting position, and electrically connecting the second external pin of the second chip close to the first redistribution layer to the first redistribution layer;

[0026] Preparing a second packaging sleeve on the dielectric layer, and packaging the second chip and the conductive member inside the second packaging sleeve;

[0027] Thinning the second packaging sleeve to expose the conductive member and the second interconnect pins of the second chip;

[0028] Disposing a second redistribution layer on the second packaging sleeve, and electrically connecting the second redistribution layer to the conductive member and the second interconnection pin;

[0029] The first chip is stacked on the second redistribution layer and covers the conductive member, so that the first interconnection pin and the first external connection pin of the first chip are electrically connected to the second redistribution layer respectively;

[0030] A first packaging sleeve is prepared on the second packaging sleeve, and the second redistribution layer and the first chip are packaged inside the first packaging sleeve.

[0031] In some embodiments, the step of providing a conductive member on the first redistribution layer further includes:

[0032] Select the same material as the conductive member to prepare the shielding member, and surround the outer periphery of the conductive member with the shielding member; and / or,

[0033] The substrate comprises a carrier plate and a release layer on the carrier plate, and the photoresist layer is located above the release layer; the step of removing the substrate and the photoresist layer comprises:

[0034] The release layer is removed by etching with an etching solution, so that the carrier is separated from the photoresist layer;

[0035] The photoresist layer is removed by a developer to expose the first redistribution layer.

[0036] The chip packaging structure provided by the present invention makes the second external connection pin and the second interconnection pin respectively located on the opposite sides of the second chip, and the second interconnection pin is located on the side of the second chip close to the first chip, so that the second redistribution layer connecting the first interconnection pin and the second interconnection pin is located between the first chip and the second chip, and the first redistribution layer connected to the first external connection pin and the second external connection pin is located on the side of the second chip away from the first chip, finally forming an effect that the pins for interconnection and the pins for external connection are designed to be routed on different sides of the second chip, thereby reducing the risk of crossing, which is beneficial to reducing the space required for routing, and further reducing the circumferential size and thickness of the chip packaging structure, so as to achieve the effect of reducing the overall volume of the chip packaging structure. Secondly, the convex part of the first chip The protruding portion protrudes beyond the outer edge of the second chip to form a clearance area at a position corresponding to the protruding portion in the packaging sleeve, and a conductive member can be arranged in the clearance area. The clearance area is located on the outside of the second chip, so the conductive member will not be blocked by the second chip when extending along the stacking direction. The first external connection pin can be electrically connected to the first redistribution layer through the conductive member located under the first chip, and there is no need to lead the first external connection pin to the circumferential outside of the first chip, thereby further reducing the circumferential size of the chip packaging structure to achieve miniaturization of the product. Moreover, the first external connection pin is closer to the side of the protruding portion away from the overlapping portion than the first interconnection pin. Therefore, when the first external connection pin is routed outward to be electrically connected to the conductive member, it will not be interfered by the first interconnection pin, thereby facilitating the electrical connection between the first external connection pin and the conductive member. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention;

[0038] Figure 2 for Figure 1 a bottom view of the first chip and the second chip when exploded;

[0039] Figure 3 for Figure 2 A schematic diagram of a first chip and a second chip being assembled together and connected to a first redistribution layer and a second redistribution layer;

[0040] Figure 4 A schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention from another direction;

[0041] Figure 5 A flowchart of a chip packaging method provided by an embodiment of the present invention;

[0042] Figure 6 The present invention is a flowchart of a chip packaging method provided by another embodiment of the present invention.

[0043] In the figure: 10, chip packaging structure; 12, packaging sleeve assembly; 13, first redistribution layer; 15, second redistribution layer; 14, first chip; 141, first interconnection pin; 142, first external connection pin; 143, overlapping portion; 144, protrusion; 16, second chip; 161, second interconnection pin; 162, second external connection pin; 24, yield area; 25, conductive member; 26, first packaging sleeve; 28, second packaging sleeve; 30, dielectric layer; 32, shielding member; 34, shielding column; 36, mounting hole; 131, first conductive layer; 132, second conductive layer; 133, third conductive layer; 44, substrate; 46, photoresist layer; 48, carrier; 50, release layer. DETAILED DESCRIPTION

[0044] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0045] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, inside, outside, top, bottom...) are only used to explain the relative position relationship between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0046] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, the element may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0047] See also Figure 1A chip packaging structure 10 provided by an embodiment of the present invention includes a plurality of stacked chips, a packaging sleeve assembly 12 for packaging the plurality of chips inside, and a first redistribution layer 13 and a second redistribution layer 15. The chip includes a first chip 14 and a second chip 16 spaced apart from each other in a stacking direction. The first redistribution layer 13 is located on a side of the second chip 16 away from the first chip 14. The second redistribution layer 15 is located between the first chip 14 and the second chip 16. The first chip 14 is electrically connected to the second chip 16 through the second redistribution layer 15. The first chip 14 is electrically connected to the first redistribution layer 13 through the second redistribution layer 15. The second chip 16 is directly electrically connected to the first redistribution layer 13. The first redistribution layer 13 is used to electrically connect to external components such as circuit boards, chips, etc., so as to realize electrical connection between the first chip 14 and the second chip 16 and external components.

[0048] It should be noted that the first redistribution layer 13 is connected to the external elements by providing pads or contacts on the first redistribution layer 13 to directly connect the external elements electrically, or by providing a connecting portion so that the first redistribution layer 13 is indirectly connected to the external elements electrically through the connecting portion.

[0049] In an optional example, the chip packaging structure 10 also includes a connecting portion, which is exposed on the surface of the chip packaging structure 10. The connecting portion can be a solder pad or a contact, etc. The connecting portion is located on the side of the second chip 16 away from the first chip 14, and the first redistribution layer 13 is electrically connected to external components through the connecting portion.

[0050] Further reading Figure 2 and Figure 3 , Figure 2 for Figure 1 The bottom view of the first chip 14 and the second chip 16 when they are decomposed, bottom view refers to Figure 1 In the direction from the second chip 16 to the first chip 14, that is, from bottom to top, the first interconnection pin 141 and the first external connection pin 142 are respectively arranged on the bottom surface of the first chip 14, the second external connection pin 162 is arranged on the bottom surface of the second chip 16, and is therefore represented by a solid line, and the second interconnection pin 161 is arranged on the top surface of the second chip 16, and is therefore represented by a dotted line. Figure 3 for Figure 2 Schematic diagram of the first chip 14 and the second chip 16 assembled together, in which the first interconnect pin 141 is directly connected to the second interconnect pin 161 through the second redistribution layer 15, the first external pin 142 is connected to the first redistribution layer 13 through the second redistribution layer 15 and the conductive member 25, and the second external pin 162 is directly electrically connected to the first redistribution layer 13.

[0051] The first chip 14 is provided with a plurality of first interconnect pins 141 and a plurality of first external connection pins 142, wherein the first interconnect pins 141 and the first external connection pins 142 are both located on a side of the first chip 14 close to the second chip 16, wherein the first interconnect pins 141 are used for electrical connection with the second chip 16, and the first external connection pins 142 are used for electrical connection with external components.

[0052] The second chip 16 is provided with a plurality of second interconnection pins 161 and a plurality of second external connection pins 162. The second interconnection pins 161 are located on a side of the second chip 16 close to the first chip 14, and are directly electrically connected to the first interconnection pins 141 through the second redistribution layer 15 to achieve the interconnection between the first chip 14 and the second chip 16. The second external connection pins 162 are located on a side of the second chip 16 away from the first chip 14, and are directly electrically connected to the first redistribution layer 13 to achieve the electrical connection between the second chip 16 and external elements. That is, the first interconnection pins 141 and the second interconnection pins 161 are pins for achieving the interconnection between the first chip 14 and the second chip 16, the first external connection pins 142 are pins for achieving the external connection of the first chip 14, and the second external connection pins 162 are pins for achieving the external connection of the second chip 14.

[0053] By arranging the second interconnection pin 161 on the side of the second chip 16 close to the first chip 14, and the second external connection pin 162 on the side of the second chip 16 away from the first chip 14, the first redistribution layer 13 and the second redistribution layer 15 are respectively located on the opposite sides of the second chip 16, so that the pins for interconnection and the pins for external connection are respectively designed to be routed on different sides of the second chip 16, thereby reducing the risk of crossing of the first redistribution layer 13 and the second redistribution layer 15 during routing, which is beneficial to reducing the space required for routing, and further reducing the circumferential size and thickness of the chip packaging structure, thereby achieving the effect of reducing the overall volume of the chip packaging structure 10, so as to achieve miniaturization of the product.

[0054] The specific number of chips is not limited, for example, two, three or more than three, and the multiple chips can be chips of the same type or chips of different types. In this embodiment, the number of chips is two. For the convenience of distinguishing the description, the two chips are respectively referred to as the first chip 14 and the second chip 16. In an optional example, the first chip 14 is a CMOS (Complementary Metal Oxide Semiconductor) chip, which can be used as a controller, and the second chip 16 is an analog chip, such as a radio frequency chip, and the first chip 14 can be used to control the second chip 16.

[0055] Taking the chip packaging structure 10 formed by the first chip 14 being a CMOS chip and the second chip 16 being a radio frequency chip as an example, the CMOS chip can be connected to the first rewiring layer 13 through the first external connection pin 142, and connected to the external signal input terminal through the first rewiring layer 13 to obtain the input signal, and generate a control signal according to the input signal; the CMOS chip transmits the control signal to the radio frequency chip through the first interconnection pin 141, the second interconnection pin 161 of the radio frequency chip, and the second rewiring layer 15 connecting the first interconnection pin 141 and the second interconnection pin 161 to control the working process of the radio frequency chip. The radio frequency chip can be connected to the first rewiring layer 13 through the second external connection pin 162, and connected to the external signal input terminal through the first rewiring layer 13 to obtain the input radio frequency signal from the outside, or it can be connected to the external signal output terminal through the first rewiring layer 13 to output the radio frequency signal.

[0056] In some embodiments, the package sleeve assembly 12 includes a first package sleeve 26 and a second package sleeve 28. The first package sleeve 26 is provided corresponding to the first chip 14 to package the first chip 14 therein, and the second package sleeve 28 is provided corresponding to the second chip 16 to package the second chip 16 therein. It can be understood that the first package sleeve 26 and the second package sleeve 28 can be made of the same or different packaging materials, and are usually made in different steps in the manufacture of the chip package structure 10.

[0057] Optionally, the projection of the first packaging sleeve 26 at right angles to the stacking direction coincides with the projection of the second packaging sleeve 28 at right angles to the stacking direction. Both the first packaging sleeve 26 and the second packaging sleeve 28 are made of EMC (Electromagnetic Compatibility) plastic packaging materials. The first packaging sleeve 26 and the second packaging sleeve 28 respectively have a certain electromagnetic shielding effect on the first chip 14 and the second chip 16 therein, thereby improving the reliability of the first chip 14 and the second chip 16.

[0058] Optionally, the chip packaging structure 10 further includes a dielectric layer 30, which is attached to a side of the second packaging sleeve 28 away from the first packaging sleeve 26, and the first redistribution layer 13 is at least partially located in the dielectric layer 30. Optionally, the dielectric layer 30 is made of an insulating material, so as to protect the first redistribution layer 13 while also providing an insulating effect on different parts of the first redistribution layer 13.

[0059] Please refer again Figure 1In one embodiment, the first chip 14 includes an overlapping portion 143 and a protruding portion 144. The protruding portion 144 is located outside the overlapping portion 143 in the circumferential direction. In the direction perpendicular to the stacking direction, the projection of the overlapping portion 143 is located inside the projection of the second chip 16. The protruding portion 144 protrudes from the outer edge of the second chip 16, so that the projection of the protruding portion 144 is located outside the second chip 16. A clearance area 24 is formed in the package sleeve component 12 at a position corresponding to the protruding portion 144. A conductive member 25 extending along the stacking direction is provided in the clearance area 24. The first external connection pin 142 is closer to the side of the protruding portion 144 away from the overlapping portion 143 than the first interconnection pin 141. The first external connection pin 142 is electrically connected to the first redistribution layer 13 through the second redistribution layer 15 and the conductive member 25.

[0060] In an optional example, the conductive member 25 is located inside the second packaging sleeve 28, and the make way area 24 is located inside the second packaging sleeve 28 and at the periphery of the second chip 16. In this way, the conductive member 25 can extend in a straight line along the stacking direction and will not be blocked by the second chip 16. At this time, it is convenient for the first chip 14 to set the first external connection pin 142 at the position of the protrusion 144. The first external connection pin 142 is directly connected to the conductive member 25 through the second redistribution layer 15, and then electrically connected to the first redistribution layer 13 through the conductive member 25. There is no need to lead the first external connection pin 142 or the second redistribution layer 15 electrically connected to the first external connection pin 142 to the circumferential outside of the first chip 14, thereby achieving the effect of reducing the circumferential size of the chip packaging structure 10, so as to achieve miniaturization of the product. In addition, the first external connection pin 142 is closer to the side of the protrusion 144 away from the overlapping portion 143 than the first interconnection pin 141, so that the first external connection pin 142 is closer to the conductive member 25 than the first interconnection pin 141. Therefore, when the first external connection pin 142 is in contact with the conductive member 25, it will not be affected by the first interconnection pin 141. By setting the relative positions of the first external connection pin 142, the conductive member 25 and the first interconnection pin 141, the free space formed by the stacked chips in the chip packaging structure 10 can be fully utilized to conveniently complete the electrical connection between chips and the electrical connection between the chip packaging structure 10 as a whole and external components.

[0061] It should be noted that the first external connection pin 142 is closer to the side of the protrusion 144 away from the overlapping portion 143 than the first interconnection pin 141. It can mean that the first external connection pin 142 is arranged on the protrusion 144 and the first interconnection pin 141 is arranged on the overlapping portion 143, so that the first external connection pin 142 is closer to the conductive member 25. It can also mean that the first external connection pin 142 and the first interconnection pin 141 are both arranged on the overlapping portion 143, and the first external connection pin 142 is arranged at the overlapping portion 143 close to the protrusion 144, which can also make the first external connection pin 142 closer to the conductive member 25.

[0062] Optionally, the first interconnect pin 141 is arranged in the overlapping portion 143, and the first interconnect pin 141 is arranged relative to the corresponding second interconnect pin 161, so that the second redistribution layer 15 will not cross in the process of connecting the first interconnect pin 141 and the second interconnect pin 161, thereby reducing the difficulty of routing and the space required for routing, and also reducing the thickness of the second redistribution layer 15, thereby reducing the overall volume of the chip packaging structure 10.

[0063] The first interconnect pin 141 and the corresponding second interconnect pin 161 are arranged relative to each other, which means that the second redistribution layer 15 will not cross when connecting the first interconnect pin 141 and the corresponding second interconnect pin 161. At this time, the first interconnect pin 141 and the corresponding second interconnect pin 161 can be directly opposite to each other, or there can be a certain distance in the horizontal direction. For example, multiple first interconnect pins 141 and corresponding second interconnect pins 161 are arranged in rows and columns.

[0064] It should be noted that the number of the protrusions 144 on the first chip 14 can be one or more. In the present embodiment, the number of the protrusions 144 is two, and the two protrusions 144 are respectively located on the opposite sides of the overlapping portion 143, that is, the opposite sides of the first chip 14 respectively protrude beyond the outer edge of the second chip 16, and the packaging sleeve assembly 12 forms a clearance area 24 under each protrusion 144, and each clearance area 24 is provided with a conductive member 25. The two protrusions 144 are respectively provided with a first external connection pin 142, which plays a role in dispersing the first external connection pin 142 and avoiding the risk of the first external connection pin 142 being too concentrated and causing wiring difficulties.

[0065] See also Figure 3, in one embodiment, a part of the second chip 16 protrudes beyond the outer edge of the overlapping portion 143, and the direction in which the second chip 16 protrudes beyond the outer edge of the overlapping portion 143 is different from the direction in which the protruding portion 144 protrudes beyond the outer edge of the second chip 16. A part of the second external connection pins 162 is provided at the portion where the second chip 16 protrudes beyond the overlapping portion 143. In the chip package structure 10, the first chip 14 and the second chip 16 are usually of different types, so the sizes of the first chip 14 and the second chip 16 are usually not the same either. When forming the chip package structure 10, according to the relative sizes of the first chip 14 and the second chip 16, the direction in which the second chip 16 protrudes beyond the outer edge of the first chip 14 and the direction in which the first chip 14 protrudes beyond the outer edge of the second chip 16 can be set not to be in the same direction, so that the chip package structure 10 can take into account the balance of the sizes in two different directions, avoiding the problem that the size of the chip package structure 10 in one direction is too small while the size in another different direction is too large. The pins, conductive components, etc. are arranged in the staggered areas in the two directions to complete the electrical connection, so as to make full use of the idle space in the chip package structure 10 and achieve the design purpose of making the overall structure of the product more compact and miniaturized.

[0066] In some embodiments, the first chip 14 and the second chip 16 are respectively rectangular. In a first direction in a plane perpendicular to the stacking direction, the opposite sides of the first chip 14 in the first direction respectively protrude beyond the outer edge of the second chip 16 to form two protruding portions 144. In a second direction in a plane perpendicular to the stacking direction, the opposite sides of the second chip 16 in the second direction respectively protrude beyond the outer edge of the first chip 14. The first direction and the second direction are perpendicular to each other and are respectively the width direction and the length direction of the chip package structure 10. Along the width direction of the chip package structure 10, the opposite sides of the first chip 14 protrude beyond the outer edge of the second chip 16. Along the length direction of the chip package structure 10, the opposite sides of the second chip 16 respectively protrude beyond the outer edge of the first chip 14, so that the projections of the first chip 14 and the second chip 16 on a plane perpendicular to the stacking direction form a shape similar to the Chinese character '中' (zhong). While achieving the effect of reducing the overall volume of the chip package structure 10, the sizes of the chip package structure 10 in different directions are taken into account.

[0067] Please refer to Figure 1 and Figure 4In one embodiment, a shielding member 32 is provided in the package sleeve assembly 12. The shielding member 32 surrounds the outer periphery of the second chip 16, and the shielding member 32 is at least partially located in the clearance area 24. The shielding member 32 surrounds the outer periphery of the second chip 16, and can form an electromagnetic shielding effect for the second chip 16 located inside it, reduce the electromagnetic interference between the second chip 16 and external components, and improve the reliability of the second chip 16. The shielding member 32 can be partially or completely disposed in the clearance area 24 to reduce the space occupied by the shielding member 32 and avoid the influence of the setting of the shielding member 32 on the volume of the chip packaging structure 10. In this embodiment, the shielding member 32 is disposed as a whole in the second package sleeve 28.

[0068] The specific shape of the shielding member 32 is not limited, and it can be a complete annular structure, or it can be composed of multiple parts arranged at intervals along the circumference of the second chip 16. The shielding member 32 can surround the outer periphery of the second chip 16 to form an electromagnetic shielding effect relative to the second chip 16. In this embodiment, the shielding member 32 includes a plurality of shielding columns 34 arranged at intervals along the outer periphery of the second chip 16, and the packaging sleeve assembly 12 is provided with a plurality of mutually spaced mounting holes 36, and the mounting holes 36 correspond to the shielding columns 34 one by one, and each shielding column 34 is respectively received in a corresponding mounting hole 36. Specifically, the shielding column 34 is provided in the second packaging sleeve 28, and the mounting hole 36 penetrates the second packaging sleeve 28 along the stacking direction. The shielding member 32 is formed by a plurality of shielding columns 34 arranged at intervals, and a plurality of mounting holes 36 arranged at intervals are correspondingly provided on the second packaging sleeve 28. Therefore, the portion of the second packaging sleeve 28 located on the inner side of the shielding member 32 and the portion of the second packaging sleeve 28 located on the outer side of the shielding member 32 are connected through the portion between adjacent mounting holes 36, and the portion located on the inner side of the shielding member 32 is not completely separated from the portion located on the outer side of the shielding member 32, thereby reducing the influence of the installation of the shielding member 32 on the overall strength of the second packaging sleeve 28.

[0069] In an optional example, the shielding member 32 and the conductive member 25 are made of the same material and are manufactured in the same step through the same process, which helps to shorten the production process and reduce production costs.

[0070] Please refer again Figure 1 In one embodiment, the first redistribution layer 13 is a multi-layer structure, the second redistribution layer 15 is a single-layer structure, and the thickness of the second redistribution layer 15 is less than the thickness of the first redistribution layer 13. Since the first interconnection pin 141 and the second interconnection pin 161 are located between the first chip 14 and the second chip 16 and are arranged opposite to each other, the distance between the two is small, and the routing will not cross, the first redistribution layer can be set to a single-layer structure to reduce the thickness of the first redistribution layer, thereby reducing the thickness of the chip packaging structure.

[0071] Optionally, the first redistribution layer 13 is a three-layer structure, which includes a first conductive layer 131, a second conductive layer 132 and a third conductive layer 133. The second conductive layer 132 is located between the first conductive layer 131 and the third conductive layer 133, and is electrically connected to the first conductive layer 131 and the third conductive layer 133. The first conductive layer 131 is located on the side of the second conductive layer 132 away from the second chip 16, and is used to be electrically connected to external components. The third conductive layer 133 is located on the side of the second conductive layer 132 close to the second chip 16, and is electrically connected to the conductive member 25 and the second external pin 162.

[0072] See also Figure 5 and Figure 6 The present invention also provides a chip packaging method for obtaining the chip packaging structure of the above embodiment, the chip packaging method comprising:

[0073] S101, providing a substrate;

[0074] S102, forming a photoresist layer on the substrate and disposing a first redistribution layer on the photoresist layer;

[0075] S103, disposing a plurality of conductive members on the first redistribution layer, and forming a chip mounting position between the plurality of conductive members;

[0076] S104, completing the connection and packaging of the second chip and the connection and packaging of the first chip in sequence;

[0077] S105, removing the substrate and the photoresist layer to obtain a chip packaging structure.

[0078] The substrate 44 can provide support during the production process. A photoresist layer 46 is first formed on the substrate 44, and then the first redistribution layer 13 is arranged on the photoresist layer 46. The photoresist layer 46 has a certain viscosity and can form a positioning effect on the first redistribution layer 13 during the production process to prevent its position from shifting during the production process. In addition, the photoresist layer 46 can separate the first redistribution layer 13 from the substrate 44 to prevent the first redistribution layer 13 from being affected during the process of removing the substrate 44. Then, a conductive member 25 is arranged on the first redistribution layer 13 at a position for connecting to the first external connection pin 142, so that the conductive member 25 is electrically connected to the first redistribution layer 13, and then the second chip 16 is connected and packaged, and the second chip 16 is installed at the chip installation position, avoiding the conductive member 25, so that the conductive member 25 is on the circumferential outside of the second chip 16, and at the same time, the second chip 16 and the conductive member 25 are encapsulated inside, and finally the first chip 14 is connected and packaged.

[0079] It can be understood that the first redistribution layer 13 can be formed first and then set on the photoresist layer 46, or the first redistribution layer 13 can be prepared on the photoresist layer 46, for example, the first redistribution layer 13 is prepared on the surface of the photoresist layer 46 through a deposition process; similarly, the conductive element 25 can be formed first and then set on the first redistribution layer 13, or it can be directly prepared through deposition and other processes.

[0080] In some embodiments, the step of disposing a first redistribution layer on the photoresist layer includes:

[0081] A first conductive layer and a dielectric layer encapsulating the first conductive layer are arranged on the photoresist layer;

[0082] A second conductive layer is arranged in the dielectric layer, and one side of the second conductive layer is connected to the first conductive layer and the other side is exposed to the surface of the dielectric layer;

[0083] A third conductive layer is disposed on a side of the dielectric layer away from the photoresist layer, and one side of the third conductive layer is electrically connected to the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer together form a first redistribution layer.

[0084] The third conductive layer 133 is located on the surface of the dielectric layer 30 and is electrically connected to the first conductive layer 131 through the second conductive layer 132. The second conductive layer 132 is composed of a plurality of conductive pillars spaced apart from each other. The dielectric layer 30 has an insulating effect, which insulates the plurality of conductive pillars from each other, so that the first conductive layer 131 and the third conductive layer 133 are conductive only at the positions of the conductive pillars.

[0085] After the third conductive layer 133 is formed, a conductive member 25 is set at a position on the third conductive layer 133 for electrical connection with the first external connection pin 142, and a chip mounting position is formed between multiple conductive members 25, leaving a position for accommodating the second chip 16, so that after the second chip 16 is installed at the mounting position, the conductive member 25 is located on the circumferential outside of the second chip 16.

[0086] It can be understood that the second conductive layer 132 can be directly made on the dielectric layer 30 by deposition and other processes. For example, a hole can be dug at a corresponding position on the dielectric layer 30 so that the hole extends from the side of the dielectric layer 30 away from the photoresist layer 46 to the first conductive layer 131, and then the second conductive layer 132 is formed in the hole by a deposition process, so that one side of the second conductive layer 132 contacts the first conductive layer 131 to form an electrical connection.

[0087] In some embodiments, the forming of the connection and packaging of the second chip includes:

[0088] Mounting the second chip at the chip mounting position, and electrically connecting the second external pin of the second chip close to the first redistribution layer to the first redistribution layer;

[0089] Preparing a second packaging sleeve on the dielectric layer, and packaging the second chip and the conductive member inside the second packaging sleeve;

[0090] The second packaging sleeve is thinned to expose the conductive member and the second interconnection pins of the second chip.

[0091] After the second external connection pin 162 is electrically connected to the first redistribution layer 13, a second packaging sleeve 28 is prepared to encapsulate the second chip 16 and the conductive member 25 therein for protection. When preparing the second packaging sleeve 28, the thickness of the second packaging sleeve 28 can be made to exceed the preset height of the conductive member 25 and the second chip 16 to ensure that the second packaging sleeve 28 completely encapsulates the conductive member 25 and the second chip 16 inside. Then, the second packaging sleeve 28 is thinned to expose only the surface of the conductive member 25 and the second interconnect pin 161 so as to connect with the first chip 14.

[0092] The height of the second chip 16 is the same as that of the conductive member 25 . The top surface of the second interconnect pin 161 is at the same height as that of the conductive member 25 . Therefore, when the conductive member 25 is exposed, the second interconnect pin 161 is also exposed. The second external connection pin 162 is at the same height as the bottom surface of the conductive member 25 .

[0093] In some embodiments, the forming of the connection and packaging of the first chip includes:

[0094] Disposing a second redistribution layer on the second packaging sleeve, and electrically connecting the second redistribution layer to the conductive member and the second interconnection pin;

[0095] The first chip is stacked on the second redistribution layer and covered with the conductive member, so that the first interconnection pin and the first external connection pin of the first chip are electrically connected to the second redistribution layer respectively;

[0096] A first packaging sleeve is prepared on the second packaging sleeve, and the first wiring layer and the first chip are packaged inside the first packaging sleeve.

[0097] When the first chip 14 is stacked on the first wiring layer 38, part of the first chip 14 protrudes beyond the outer edge of the second chip 16, and the second packaging sleeve 28 forms a clearance area 24 below the part of the first chip 14 protruding beyond the outer edge of the second chip 16. The conductive member 25 is located in the clearance area 24, so that the part of the first chip 14 protruding beyond the outer edge of the second chip 16 covers the conductive member 25, that is, the conductive member 25 is located below the first chip 14, so that the first external connection pin 142 can be electrically connected to the conductive member 25 below the first chip 14 without extending to the circumferential outside of the first chip 14, which is beneficial to reducing the overall volume.

[0098] In some embodiments, the substrate includes a carrier and a release layer on the carrier, and the photoresist layer is located above the release layer, that is, on a side away from the carrier; the step of removing the base and the photoresist layer includes:

[0099] The release layer is removed by etching with an etching solution, so that the carrier plate is separated from the photoresist layer;

[0100] The photoresist layer is removed by a developer to expose the first redistribution layer.

[0101] The carrier 48 can be a glass plate or a silicon wafer, which mainly plays a supporting role. The release layer 50 and the photoresist layer 46 serve as sacrificial layers and can be removed after the desired structure is formed. The release layer 50 is first corroded by a corrosive liquid to automatically separate the carrier 48 from the photoresist layer 46. In addition, during the process of the corrosive liquid corroding the release layer 50, the photoresist layer 46 can prevent the corrosive liquid from contacting the first redistribution layer 13 to avoid corrosion of the first redistribution layer 13 and causing damage. Then, the developer is used to dissolve the photoresist layer 46 to expose the surface of the first redistribution layer 13 for bonding with the photoresist layer 46. At the same time, the developer will not corrode the first redistribution layer 13. After removing the photoresist layer 46 and the release layer 50, the chip packaging structure 10 can be obtained.

[0102] In some embodiments, the chip packaging structure further includes a shielding member surrounding the outer periphery of the second chip; and in the step of selecting to set a conductive member on the target connection, further includes:

[0103] The shielding member is made of the same material as the conductive member, and the shielding member is surrounded on the outer circumference of the conductive member.

[0104] In the above embodiment, in the process of preparing the conductive member 25, the shielding member 32 is prepared synchronously using the same material and the same process, which can shorten the production process and reduce the production cost. After the second chip 16 is connected and packaged, the shielding member 32 surrounding the outer periphery of the second chip 16 is provided, so that the shielding member 32 can be used to form an electromagnetic shield for the second chip 16, thereby reducing the electromagnetic interference between the second chip 16 and external components.

[0105] Optionally, the shielding member 32 includes a plurality of shielding posts 34 manufactured synchronously, and the plurality of shielding posts 34 are arranged at intervals along an annular track.

[0106] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A chip packaging structure, characterized in that: The invention comprises a plurality of chips which are stacked, a packaging sleeve component (12) for packaging the plurality of chips therein, and a first redistribution layer (13) and a second redistribution layer (15); the chips comprise a first chip (14) and a second chip (16) arranged along a stacking direction; a first interconnection pin (141) and a first external connection pin (142) are provided on a side of the first chip (14) close to the second chip (16); and a second interconnection pin (161) and a second external connection pin (162) are provided on the second chip (16); the first redistribution layer (13) is located on a side of the second chip (16) away from the first chip (14); and the second redistribution layer (15) is located between the first chip (14) and the second chip (16); The second interconnect pin (161) is located on a side of the second chip (16) close to the first chip (14) and is directly electrically connected to the first interconnect pin (141) through the second redistribution layer (15); the second external connection pin (162) is located on a side of the second chip (16) away from the first chip (14) and is electrically connected to the first redistribution layer (13); The first chip (14) comprises an overlapping portion (143) and a protruding portion (144); in a direction perpendicular to the stacking direction, the projection of the overlapping portion (143) is located on the inner side of the projection of the second chip (16), and the projection of the protruding portion (144) is located on the outer side of the projection of the second chip (16); a clearance area (24) is formed in the packaging sleeve component (12) at a position corresponding to the protruding portion (144); a conductive member (25) extending along the stacking direction is provided in the clearance area (24); the first external connection pin (142) of the first chip (14) is electrically connected to the conductive member (25) through the second redistribution layer (15), and is electrically connected to the first redistribution layer (13) through the conductive member (25); the first external connection pin (142) is closer to the protruding portion (144) and farther from the overlapping portion (143) than the first interconnection pin (141).

2. The chip packaging structure according to claim 1, characterized in that: The first interconnection pin (141) is located in the overlapping portion (143), and the first interconnection pin (141) is arranged opposite to the corresponding second interconnection pin (161); and / or, The protruding portions (144) are respectively provided on opposite sides of the overlapping portion (143); the packaging sleeve assembly (12) is respectively formed with the making way area (24) at a corresponding position of each protruding portion (144); each of the making way areas (24) is provided with the conductive member (25); and the first chip (14) includes the first external connection pins (142) respectively provided corresponding to the conductive members (25).

3. The chip packaging structure according to claim 1, characterized in that: The second chip (16) partially protrudes beyond the outer edge of the overlapping portion (143), and the direction in which the second chip (16) protrudes beyond the outer edge of the overlapping portion (143) is different from the direction in which the protruding portion (144) protrudes beyond the outer edge of the second chip (16), and part of the second external connection pins (162) are arranged at the position where the second chip (16) protrudes beyond the overlapping portion (143).

4. The chip packaging structure according to claim 1, characterized in that: The first redistribution layer (13) is a multi-layer structure, the second redistribution layer (15) is a single-layer structure, and the thickness of the second redistribution layer (15) is smaller than the thickness of the first redistribution layer (13).

5. The chip packaging structure according to claim 1, characterized in that: A shielding component (32) is provided in the packaging sleeve assembly (12), the shielding component (32) surrounds the outer periphery of the second chip (16), and the shielding component (32) is at least partially located in the clearance area (24).

6. The chip packaging structure according to claim 5, characterized in that: The shielding component (32) includes a plurality of shielding columns (34) arranged at intervals, and the packaging sleeve assembly (12) is provided with a plurality of mounting holes (36) spaced apart from each other. The plurality of mounting holes (36) are arranged around the periphery of the second chip (16), and each of the shielding columns (34) is respectively received in a corresponding mounting hole (36).

7. A chip packaging method, characterized in that: include: providing a substrate; forming a photoresist layer on the substrate and disposing a first redistribution layer on the photoresist layer; Disposing a plurality of conductive members on the first redistribution layer and forming a chip mounting position between the plurality of conductive members; sequentially completing the connection and packaging of the second chip and the connection and packaging of the first chip; The substrate and the photoresist layer are removed to obtain a chip packaging structure.

8. The chip packaging method according to claim 7, characterized in that: The step of providing a first redistribution layer on the photoresist layer comprises: Disposing a first conductive layer on the photoresist layer and a dielectric layer encapsulating the first conductive layer inside; Disposing a second conductive layer in the dielectric layer, with one side of the second conductive layer connected to the first conductive layer and the other side exposed to the surface of the dielectric layer; A third conductive layer is disposed on a side of the dielectric layer away from the photoresist layer, and one side of the third conductive layer is electrically connected to the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer together form the first redistribution layer.

9. The chip packaging method according to claim 8, characterized in that: The method of sequentially completing the connection and packaging of the second chip and the connection and packaging of the first chip includes: Mounting the second chip to the chip mounting position, and electrically connecting the second external pin of the second chip close to the first redistribution layer to the first redistribution layer; Preparing a second packaging sleeve on the dielectric layer, and packaging the second chip and the conductive member inside the second packaging sleeve; Thinning the second packaging sleeve to expose the conductive member and the second interconnect pins of the second chip; Disposing a second redistribution layer on the second packaging sleeve, and electrically connecting the second redistribution layer to the conductive member and the second interconnection pin; The first chip is stacked on the second redistribution layer and covers the conductive member, so that the first interconnection pin and the first external connection pin of the first chip are electrically connected to the second redistribution layer respectively; A first packaging sleeve is prepared on the second packaging sleeve, and the second redistribution layer and the first chip are packaged inside the first packaging sleeve.

10. The chip packaging method according to claim 7, characterized in that: The step of providing a conductive member on the first redistribution layer further includes: Select the same material as the conductive member to prepare the shielding member, and surround the outer periphery of the conductive member with the shielding member; and / or, The substrate comprises a carrier plate and a release layer on the carrier plate, and the photoresist layer is located above the release layer; the step of removing the substrate and the photoresist layer comprises: The release layer is removed by etching with an etching solution, so that the carrier is separated from the photoresist layer; The photoresist layer is removed by a developer to expose the first redistribution layer.

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