Semiconductor package and method of manufacturing the same

Abstract

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package may include a lower structure and an upper structure on the lower structure. The lower structure may include a first semiconductor substrate, a first pad on the first semiconductor substrate, and a first insulating layer surrounding the first pad. The upper structure includes a second semiconductor substrate, a second pad on the second semiconductor substrate, and a second insulating layer surrounding the second pad. The side surface of the lower structure and the side surface of the upper structure form a stepped structure near a bonding surface between the lower structure and the upper structure. The first insulating layer includes a protruding portion extending to a height higher than a top surface of the first insulating layer and inserted into the second insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package and a method for manufacturing the same. Background Art

[0002] A semiconductor package includes a semiconductor chip provided as part of an electronic product. In general, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip mounted on the PCB and electrically connected to the PCB using bonding wiring or bumps. With the development of the electronics industry, various studies are being conducted to improve the reliability and durability of semiconductor packages.

[0003] In the semiconductor industry, various packaging technologies have been developed to meet the requirements of large capacity, thin thickness and small size for semiconductor devices and / or electronic products. For example, packaging technology for vertically stacked semiconductor chips has been proposed to achieve a high-density chip stacking structure. Compared with typical packages provided in the form of a single semiconductor chip, this technology makes it possible to integrate semiconductor chips with various functions in a small area. Summary of the invention

[0004] In general, in some aspects, the present disclosure relates to a semiconductor package having improved structural stability and a method of making the same.

[0005] In general, according to some aspects, the present disclosure relates to a semiconductor package having a lower structure and an upper structure located on the lower structure. The lower structure may include a first semiconductor substrate, a first pad located on the first semiconductor substrate, and a first insulating layer disposed on the first semiconductor substrate to surround the first pad. The upper structure may include a second semiconductor substrate, a second pad located on the second semiconductor substrate, and a second insulating layer disposed on the second semiconductor substrate to surround the second pad. The side surface of the lower structure and the side surface of the upper structure may form a stepped structure near the bonding surface between the lower structure and the upper structure. The first insulating layer may include a protrusion extending to a height higher than the top surface of the first insulating layer and inserted into the second insulating layer. The protrusion may contact the side surface of the lower structure. Each first pad in the first pad and the corresponding second pad in the second pad may be in direct contact with each other, and may be formed of the same material to form a single object.

[0006] According to some aspects of the present disclosure, a semiconductor package may include a lower structure and an upper structure located on the lower structure. The lower structure may include a first semiconductor substrate, a first pad located on the first semiconductor substrate, and a first insulating layer disposed on the first semiconductor substrate to surround the first pad. The upper structure may include a second semiconductor substrate, a second pad located on the second semiconductor substrate, a second insulating layer disposed on the second semiconductor substrate to surround the second pad, and a slit structure vertically penetrating the second insulating layer. The first insulating layer may include a protrusion extending upward from the top surface of the first insulating layer and inserted into the second insulating layer. The first side surface of the protrusion may be exposed to the outside near the side surface of the lower structure. The slit structure may be exposed to the outside near the bottom surface of the second insulating layer and may be in contact with the top surface of the protrusion. Each first pad in the first pad and the corresponding second pad in the second pad may be in direct contact with each other and may be formed of the same material to form a single object.

[0007] According to some aspects of the present disclosure, a semiconductor package may include: a substrate; a first semiconductor chip, the first semiconductor chip is disposed on the substrate; a chip stack, the chip stack includes a plurality of second semiconductor chips, the plurality of second semiconductor chips are vertically stacked on the substrate and horizontally spaced apart from the first semiconductor chip; and a molding layer, the molding layer is disposed on the substrate to surround the first semiconductor chip and the chip stack. Each of the plurality of second semiconductor chips may include: a semiconductor substrate; an upper pad, the upper pad is disposed on the top surface of the semiconductor substrate; an upper insulating layer, the upper insulating layer is disposed on the top surface of the semiconductor substrate to surround the upper pad; a lower pad, the lower pad is disposed on the bottom surface of the semiconductor substrate; and a lower insulating layer, the lower insulating layer is disposed on the bottom surface of the semiconductor substrate to surround the lower pad. The upper insulating layer may include a protruding portion extending upward from the top surface of the upper insulating layer. Adjacent second semiconductor chips in the plurality of second semiconductor chips may contact each other. At the contact surface between the plurality of second semiconductor chips, the lower pad and the upper pad may contact each other and may be formed of the same material to form a single object. When viewed in a plan view, the protruding portion may extend along an edge of the second semiconductor chip and may have a closed loop shape. A width of the protruding portion may range from 1 μm to 3 μm.

[0008] According to some aspects of the present disclosure, a method for manufacturing a semiconductor package may include: forming a lower structure, the lower structure including a first semiconductor substrate having a device region and a scribe lane region between the device regions, a first pad disposed on the device region of the first semiconductor substrate, and a first insulating layer disposed on the first semiconductor substrate to surround the first pad; forming a protrusion extending upward from a top surface of the first insulating layer on the first insulating layer on the scribe lane region; forming an upper structure, the upper structure including a second semiconductor substrate, a second pad disposed on the second semiconductor substrate, and a second insulating layer disposed on the second semiconductor substrate to surround the second pad, the first pad and the second pad including the same metal material; arranging the upper structure on the lower structure so that the first pad contacts the second pad, and inserting the protrusion into the second insulating layer; performing a heat treatment process on the lower structure and the upper structure to combine the first pad and the second pad, thereby forming a single object; and forming a crack in the scribe lane region of the first semiconductor substrate. The crack may extend from the first semiconductor substrate to pass through the first insulating layer, the protrusion, the second insulating layer, and the second semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0010] Figures 2 to 4 is a diagram showing that according to some embodiments Figure 1 An enlarged view of an example of portion "A".

[0011] Figure 5 is a plan view illustrating an example of a semiconductor package according to some embodiments.

[0012] Figure 6 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0013] Figure 7 is a diagram showing that according to some embodiments Figure 6 An enlarged view of an example of portion "B".

[0014] Figure 8 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0015] Fig. 9 is a diagram showing that according to some embodiments Figure 8 An enlarged view of an example of portion "C".

[0016] Fig.10 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0017] Fig.11 is a diagram showing that according to some embodiments Fig.10 An enlarged view of an example of portion "D".

[0018] Fig.12 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0019] Fig.13 is a diagram showing that according to some embodiments Fig.12 An enlarged view of an example of portion "E".

[0020] Fig.14 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0021] Fig.15 is a diagram showing that according to some embodiments Fig.14 An enlarged view of an example of portion "F".

[0022] Fig.16 is a plan view illustrating an example of a semiconductor package according to some embodiments.

[0023] Fig.17 is a diagram showing that according to some embodiments Fig.16 An enlarged view of an example of portion "G".

[0024] Fig.18 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0025] Fig.19 is a diagram showing that according to some embodiments Fig.18 An enlarged view of an example of portion "H".

[0026] Fig. 20 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0027] Fig.21 is a diagram showing that according to some embodiments Fig. 20 An enlarged view of an example of portion "I".

[0028] Fig. 22 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments.

[0029] Fig.23 is a diagram showing that according to some embodiments Fig. 22 An enlarged view of an example of a portion of the FIG.

[0030] Fig.24 is a cross-sectional view illustrating an example of a semiconductor module according to some embodiments.

[0031] Figures 25 to 39 is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0032] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Figures 2 to 4 is a diagram showing that according to some embodiments Figure 1 An enlarged view of an example of portion "A". Figure 5 is a plan view illustrating an example of a semiconductor package according to some embodiments.

[0034] exist Figure 1 In the embodiment of the present invention, the semiconductor device may include a lower structure 10 and an upper structure 30 stacked on the lower structure 10. The lower structure 10 may include a first substrate 12, a first circuit layer 14, a first insulating layer 16, and a first pad 20.

[0035] The first substrate 12 may be a semiconductor substrate (e.g., a semiconductor wafer). The first substrate 12 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer grown using a selective epitaxial growth (SEG) technique. The first substrate 12 may be formed of or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). Alternatively, the first substrate 12 may be an insulating substrate (e.g., a printed circuit board (PCB)).

[0036] The first circuit layer 14 may be disposed on the top surface of the first substrate 12. The first circuit layer 14 may include a first circuit pattern disposed on the first substrate 12 and a first interlayer insulating layer covering the first circuit pattern. The first circuit pattern may be a memory circuit having one or more transistors, a logic circuit having one or more transistors, or a combination thereof. Alternatively, the first circuit pattern may include at least one of a passive device (e.g., a resistor, an inductor, or a capacitor).

[0037] The first pad 20 may be disposed on the top surface of the first circuit layer 14. The first pad 20 may be electrically connected to the first circuit pattern of the first circuit layer 14. The first pad 20 may have substantially the same thickness. For example, the first pad 20 may have a plate-like structure. In some embodiments, the first pad 20 may include a via portion and a pad portion, and the pad portion is disposed on the via portion and connected to the via portion. Here, the via portion and the pad portion of the first pad 20 may have a T-shaped cross-section and may form a single object. The width of the first pad 20 may be substantially constant regardless of the distance from the first substrate 12. Alternatively, Figure 1 , the width of the first pad 20 may decrease as the distance from the first substrate 12 decreases. The first pad 20 may be arranged in a rectangular shape or a honeycomb shape. However, the first pad 20 is not limited to this example. The planar shape of the first pad 20 may be circular. Alternatively, the planar shape of the first pad 20 may be a quadrilateral, an octagon, or a polygon. However, the inventive concept is not limited to these examples, and in an embodiment, if necessary, the planar shape of the first pad 20 may be changed differently. The first pad 20 may include a metal material. For example, the first pad 20 may be formed of copper (Cu) or include copper (Cu).

[0038] The first pad 20 may be electrically connected to the first circuit pattern of the first circuit layer 14. Figure 1 As shown in , the first connection pattern 15 may be disposed in the first circuit layer 14. The first connection pattern 15 may be a through-via (e.g., a through-silicon via) disposed to vertically penetrate the first interlayer insulating layer in the first circuit layer 14. The first connection pattern 15 may extend vertically in the first circuit layer 14 and may be coupled to the first pad 20. The first connection pattern 15 may electrically connect the first circuit pattern to the first pad 20. Figure 1 In the embodiment, various conductive patterns for interconnection between the first circuit pattern and the first connection pattern 15 may be further provided. Figure 1 Unlike the structure shown in FIG. 1 , the first connection pattern 15 may be an under-pad pattern or a redistribution pattern provided in the first circuit layer 14 in an insulating pattern. Various conductive patterns for interconnection between the first circuit pattern and the first connection pattern 15 may be further provided. However, the conductive pattern is not limited to this example, and if necessary, the shape of the first circuit layer 14 may be variously changed, and the electrical interconnection between the first pad 20 and the first circuit layer 14 may be achieved by other various structures.

[0039] The first pad 20 may have a damascene structure in the first insulating layer 16. For example, the first pad 20 may further include a seed / barrier pattern covering the side surface and the bottom surface of the first pad 20. The seed / barrier pattern may conformally cover the side surface and the bottom surface of the first pad 20. When the seed / barrier pattern is used as a seed pattern, the seed / barrier pattern may include a metal material (e.g., gold (Au)). In the case where the seed / barrier pattern is used as a barrier pattern, the seed / barrier pattern may be formed of or include at least one of a metal material (e.g., titanium (Ti) and tantalum (Ta)) or a metal nitride material (e.g., titanium nitride (TiN) and tantalum nitride (TaN)).

[0040] The first insulating layer 16 may be disposed on the top surface of the first circuit layer 14 to surround the first pad 20. The top surface of the first pad 20 may be exposed to the outside of the first insulating layer 16. For example, when viewed in a plan view, the first insulating layer 16 may surround the first pad 20 and may not cover the first pad 20. The top surface of the first insulating layer 16 and the top surface of the first pad 20 may be substantially flat and may be substantially coplanar with each other. The first insulating layer 16 may include an oxide, nitride or oxynitride material containing an element included in the first substrate 12 or the first circuit layer 14. The first insulating layer 16 may include at least one of an insulating material (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN)). In some embodiments, the first insulating layer 16 may be formed of silicon oxide (SiO) or include silicon oxide.

[0041] The first insulating layer 16 may include a protruding portion 18. The protruding portion 18 may be arranged at a height higher than the top surface 16u of the first insulating layer 16. The protruding portion 18 may be disposed near the side surface 16s of the first insulating layer 16. As an example, the protruding portion 18 may be in contact with the side surface 16s of the first insulating layer 16 (i.e., the side surface of the lower structure 10). Therefore, the side surface 18s of the protruding portion 18 may be exposed to the outside of the first insulating layer 16 near the side surface 16s of the first insulating layer 16. The protruding portion 18 may be a part of the first insulating layer 16, but, for ease of description, in the present disclosure, different reference numerals may be used to describe the protruding portion 18 and the first insulating layer 16, respectively. Therefore, the side surface 18s of the protruding portion 18 may be arranged on the side surface 16s of the first insulating layer 16, and the side surface 18s of the protruding portion 18 and the side surface 16s of the first insulating layer 16 may form a single surface corresponding to the entire side surface of the first insulating layer 16. Side surfaces 16s and 18s may be substantially planar and may be substantially coplanar with each other.

[0042] like Figure 2As shown in , the cross-sectional shape of the protrusion 18 can be rectangular or square. In some embodiments, the protrusion 18 can have a cross-sectional shape such as Figure 3 A trapezoidal cross section whose top width is less than its bottom width as shown in Figure 4 . However, the protrusion 18 is not limited to this example, and the cross-sectional shape of the protrusion 18 may be one of various other shapes (e.g., a triangle) with an upwardly pointed portion. The width W of the protrusion 18 may range from 1 μm to 3 μm. The height H of the protrusion 18 may range from 1 μm to 5 μm.

[0043] exist Figure 5 In the embodiment of the present invention, the protruding portion 18 may extend along the side surface of the lower structure 10. For example, when viewed in a plan view, the protruding portion 18 may have a closed loop shape extending along the edge of the lower structure 10. In the present disclosure, the term "closed loop shape" may refer not only to a closed shape without a sharp portion, but also to other closed shapes (e.g., a quadrilateral or polygonal ring) with a sharp portion.

[0044] exist Figure 1 and Figure 2 In the embodiment, the upper structure 30 may be disposed on the lower structure 10. The upper structure 30 may include a second substrate 32, a second circuit layer 34, a second insulating layer 36, and a second pad 40.

[0045] The second substrate 32 may be a semiconductor substrate (e.g., a semiconductor wafer). The second substrate 32 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer grown using a selective epitaxial growth (SEG) technique. The second substrate 32 may be formed of or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs). Alternatively, the second substrate 32 may be an insulating substrate (e.g., a printed circuit board (PCB)).

[0046] The second circuit layer 34 may be disposed on the bottom surface of the second substrate 32. The second circuit layer 34 may include a second circuit pattern disposed on the second substrate 32 and a second interlayer insulating layer covering the second circuit pattern. The second circuit pattern may be a memory circuit having one or more transistors, a logic circuit having one or more transistors, or a combination thereof. Alternatively, the second circuit pattern may include a passive device (e.g., a resistor, an inductor, or a capacitor).

[0047] The second pad 40 may be disposed on the bottom surface of the second circuit layer 34. The second pad 40 may be a pad of a second circuit pattern electrically connected to the second circuit layer 34. The second pad 40 may have substantially the same thickness. For example, the second pad 40 may have a plate-like structure. In some embodiments, the second pad 40 may include a via portion and a pad portion, the pad portion being disposed below the via portion and connected to the via portion, and here, the via portion and the pad portion of the second pad 40 may have a cross-section in the shape of an inverted letter "T", and may form a single object. The width of the second pad 40 may be substantially constant regardless of the distance from the second substrate 32. Alternatively, the width of the second pad 40 may decrease as the distance from the second substrate 32 decreases. The second pad 40 may be arranged in a rectangular shape or a honeycomb shape. The second pad 40 may have a circular, quadrilateral, octagonal or polygonal plane shape. The second pad 40 may be formed of at least one of metal materials, or include at least one of metal materials. For example, the second pad 40 may be formed of copper (Cu) or include copper (Cu).

[0048] The second pad 40 may be electrically connected to the second circuit pattern of the second circuit layer 34. Figure 1 As shown in , the second connection pattern 35 may be disposed in the second circuit layer 34. The second connection pattern 35 may be a through-via (e.g., a through-silicon via) disposed to vertically penetrate the second interlayer insulating layer in the second circuit layer 34. The second connection pattern 35 may extend vertically in the second circuit layer 34 and may be coupled to the second pad 40. The second connection pattern 35 may electrically connect the second circuit pattern to the second pad 40. Figure 1 In the embodiment, various conductive patterns for interconnection between the second circuit pattern and the second connection pattern 35 may be further provided. Figure 1 Unlike the structure shown in FIG. 1 , the second connection pattern 35 may be an under-pad pattern or a redistribution pattern provided in the second circuit layer 34 in an insulating pattern. In addition, various conductive patterns for interconnection between the second circuit pattern and the second connection pattern 35 may be further provided. However, the conductive pattern is not limited to this example, and if necessary, the shape of the second circuit layer 34 may be variously changed, and the electrical interconnection between the second pad 40 and the second circuit layer 34 may be achieved by other various structures.

[0049] The second pad 40 may have a damascene structure. For example, the second pad 40 may further include a seed / barrier pattern covering the side surface and the top surface of the second pad 40, respectively. The seed / barrier pattern may conformally cover the side surface and the top surface of the second pad 40. In the case where the seed / barrier pattern is used as a seed pattern, the seed / barrier pattern may be formed of at least one of the metal materials (e.g., gold (Au)) or include at least one of the metal materials (e.g., gold (Au)). In the case where the seed / barrier pattern is used as a barrier pattern, the seed / barrier pattern may be formed of at least one of the metal materials (e.g., titanium (Ti) and tantalum (Ta)) or metal nitride materials (e.g., titanium nitride (TiN) and tantalum nitride (TaN)) or include at least one of them.

[0050] The second insulating layer 36 may be disposed on the bottom surface of the second circuit layer 34 to surround the second pad 40. The bottom surface of the second pad 40 may be exposed to the outside of the second insulating layer 36. For example, when viewed in a plan view, the second insulating layer 36 may surround the second pad 40, but may not cover the second pad 40. The top surface of the second insulating layer 36 and the top surface of the second pad 40 may be substantially flat and may be substantially coplanar with each other. However, the second insulating layer 36 is not limited to this example. The second insulating layer 36 may include an oxide, nitride or oxynitride material containing an element included in the second substrate 32 or the second circuit layer 34. The second insulating layer 36 may include at least one of an insulating material (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN)). For example, the second insulating layer 36 may be formed of silicon oxide (SiO) or include silicon oxide.

[0051] The upper structure 30 may be disposed on the lower structure 10. The first pads 20 of the lower structure 10 and the second pads 40 of the upper structure 30 may be vertically aligned with each other. The lower structure 10 and the upper structure 30 may contact each other.

[0052] The upper structure 30 may be connected to the lower structure 10. For example, the lower structure 10 and the upper structure 30 may contact each other. The first pad 20 of the lower structure 10 and the second pad 40 of the upper structure 30 may be electrically connected to each other. For example, the lower structure 10 and the upper structure 30 may contact each other. At the interface between the lower structure 10 and the upper structure 30, the first pad 20 of the lower structure 10 may be bonded to the second pad 40 of the upper structure 30. Here, the first pad 20 and the second pad 40 may form a metal-to-metal hybrid bonding structure. In the present disclosure, the hybrid bonding structure may indicate a bonding structure formed by two materials belonging to the same kind and melted at the interface between them. For example, the first pad 20 and the second pad 40 bonded to each other may have a continuous structure, and the interface between the first pad 20 and the second pad 40 may not be visible or observable. For example, the first pad 20 and the second pad 40 may be formed of the same material, and in this case, there may be no visible or observable interface between the first pad 20 and the second pad 40. In some embodiments, the first pad 20 and the second pad 40 may be provided as a single object. For example, the first pad 20 and the second pad 40 may be combined to form a single object.

[0053] The first insulating layer 16 and the second insulating layer 36 may contact each other due to the bonding of the lower structure 10 and the upper structure 30. In some embodiments, the protruding portion 18 of the first insulating layer 16 may be inserted into the second insulating layer 36.

[0054] The side surface of the lower structure 10 may be vertically aligned with the side surface of the upper structure 30. For example, the side surface of the lower structure 10 may be coplanar with the side surface of the upper structure 30. The side surface 16s of the first insulating layer 16 may be coplanar with the side surface 36s of the second insulating layer 36.

[0055] According to some embodiments, the first insulating layer 16 of the lower structure 10 may be configured to include a protruding portion 18. The protruding portion 18 may prevent process failures in a singulation process performed as part of a semiconductor package manufacturing process (e.g., a detachment problem between the first insulating layer 16 and the second insulating layer 36 caused by horizontal crack extension). The first insulating layer 16 and the second insulating layer 36 may be firmly bonded to each other, and the lower structure 10 and the upper structure 30 may be firmly bonded to each other. Therefore, the structural stability of the semiconductor package may be improved.

[0056] In the description of the embodiments described below, in order to make the description concise, the previous reference Figures 1 to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0057] Figure 6is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Figure 7 is a diagram showing that according to some embodiments Figure 6 An enlarged view of an example of portion "B". Figure 8 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig. 9 is a diagram showing that according to some embodiments Figure 8 An enlarged view of an example of portion "C".

[0058] Figures 1 to 5 An embodiment is shown in which the side surface of the lower structure 10 is vertically aligned with the side surface of the upper structure 30. However, Figures 1 to 5 The embodiments are not limited to this configuration.

[0059] exist Figure 6 and Figure 7 In the embodiment of the present invention, the side surface of the lower structure 10 and the side surface of the upper structure 30 may form a stepped structure near the bonding surface between the lower structure 10 and the upper structure 30. The lower structure 10 may protrude outward from the side surface of the upper structure 30. For example, the first insulating layer 16 may protrude outward from the side surface 36s of the second insulating layer 36. The side surface 36s of the second insulating layer 36 may be located on the top surface 18u of the protruding portion 18. For example, the side surface 36s of the second insulating layer 36 may be located between the outer side surface 18s and the inner side surface of the protruding portion 18. Therefore, on the side surface 36s of the second insulating layer 36, a portion of the top surface 18u of the protruding portion 18 may be exposed to the outside.

[0060] exist Figure 8 and Fig. 9 In the embodiment, the side surface of the lower structure 10 and the side surface of the upper structure 30 may form a stepped structure near the bonding surface between the lower structure 10 and the upper structure 30. The lower structure 10 may protrude outward from the side surface of the upper structure 30. The side surface 36s of the second insulating layer 36 may be aligned with the inner side surface of the protruding portion 18. Therefore, on the side surface 36s of the second insulating layer 36, the entire top surface 18u of the protruding portion 18 may be exposed to the outside.

[0061] Fig.10 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.11 is a diagram showing that according to some embodiments Fig.10 An enlarged view of an example of portion "D".

[0062] exist Fig.10 and Fig.11, the side surface of the lower structure 10 and the side surface of the upper structure 30 may form a stepped structure near the bonding surface between the lower structure 10 and the upper structure 30. The upper structure 30 may protrude outward from the side surface of the lower structure 10. For example, the second insulating layer 36 may protrude outward from the side surface 16s of the first insulating layer 16. The entire top surface 18u of the protruding portion 18 may be in contact with the second insulating layer 36. Therefore, on the side surface 16s of the first insulating layer 16, a portion of the bottom surface 36b of the second insulating layer 36 may be exposed to the outside.

[0063] Fig.12 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.13 is a diagram showing that according to some embodiments Fig.12 An enlarged view of an example of portion "E".

[0064] exist Fig.12 and Fig.13 In the embodiment of the present invention, a plurality of protrusions 18 may be provided. The protrusions 18 may be spaced apart from each other horizontally. For example, the protrusions 18 may be spaced apart from each other in a direction from a side surface of the lower structure 10 toward a central portion of the lower structure 10. When viewed in a plan view, each protrusion 18 may extend along an edge of the lower structure 10 and may have a closed loop shape. The side surface 18s of the outermost protrusion of the protrusion 18 may be coplanar with the side surface 16s of the first insulating layer 16.

[0065] The side surface 36s of the second insulating layer 36 may be located on the top surface of one of the protruding portions 18. Fig.12 and Fig.13 In the embodiment, the side surface 36s of the second insulating layer 36 is located on the top surface of the outermost protrusion of the protrusion 18, but the inventive concept is not limited to this example. For example, the side surface 36s of the second insulating layer 36 may be disposed on the top surface of another protrusion of the protrusion 18.

[0066] Fig.14 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.15 is a diagram showing that according to some embodiments Fig.14 An enlarged view of an example of portion "F". Fig.16 is a plan view illustrating an example of a semiconductor package according to some embodiments. Fig.17 is a diagram showing that according to some embodiments Fig.16 An enlarged view of an example of portion "G".

[0067] exist Figures 14 to 17In the embodiment of the present invention, the upper structure 30 may further include a slit structure 38. The slit structure 38 may be disposed in the second insulating layer 36. The slit structure 38 may vertically penetrate the second insulating layer 36 and may be exposed through the bottom surface of the second insulating layer 36. The slit structures 38 may be horizontally spaced apart from each other. For example, the slit structures 38 may be spaced apart from each other in a direction from the side surface of the upper structure 30 toward the central portion of the upper structure 30. When viewed in a plan view, each slit structure 38 may extend along an edge of the upper structure 30 and may have a closed loop shape.

[0068] At the bonding surface between the lower structure 10 and the upper structure 30, at least one of the slit structures 38 may be in contact with the top surface 18u of the protruding portion 18. On the inner side surface of the protruding portion 18 facing the central portion of the lower structure 10, the other slit structures 38 may be in contact with the top surface 16u of the first insulating layer 16. However, the slit structure 38 is not limited to this example, and the entire slit structure 38 may be arranged on the top surface 18u of the protruding portion 18. The slit structure 38 may be an empty space filled with air, or may be formed of or include an insulating material.

[0069] According to some embodiments, the slit structure 38 may be disposed in the second insulating layer 36 of the upper structure 30. The slit structure 38 may suppress horizontal crack expansion in a singulation process performed as part of a semiconductor package manufacturing process. For example, process failures caused by horizontal crack expansion (e.g., detachment issues between the first insulating layer 16 and the second insulating layer 36) may be suppressed. Therefore, the first insulating layer 16 and the second insulating layer 36 may be firmly bonded to each other, and the lower structure 10 and the upper structure 30 may be firmly bonded to each other. In other words, the structural stability of the semiconductor package may be improved.

[0070] Fig.18 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.19 is a diagram showing that according to some embodiments Fig.18 An enlarged view of an example of portion "H".

[0071] exist Fig.18 and Fig.19In the embodiment, the side surface of the lower structure 10 and the side surface of the upper structure 30 may form a stepped structure near the bonding surface between the lower structure 10 and the upper structure 30. The lower structure 10 may protrude outward from the side surface of the upper structure 30. For example, the first insulating layer 16 may protrude outward from the side surface 36s of the second insulating layer 36. The side surface 36s of the second insulating layer 36 may be located on the top surface 18u of the protruding portion 18. The slit structure 38 may be provided in the second insulating layer 36. Some of the slit structures 38 may be arranged on the top surface 18u of the protruding portion 18, and other of the slit structures 38 may be arranged on the inner side surface of the protruding portion 18. In some embodiments, the slit structure 38 may not be provided on the top surface 18u of the protruding portion 18, and may be provided only on the inner side surface of the protruding portion 18.

[0072] Alternatively, the side surface 36s of the second insulating layer 36 may be aligned with the inner side surface of the protruding portion 18. Therefore, the entire top surface 18u of the protruding portion 18 may be exposed to the outside on the side surface 36s of the second insulating layer 36. Here, the slit structure 38 may be provided on the inner side surface of the protruding portion 18.

[0073] Fig. 20 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.21 is a diagram showing that according to some embodiments Fig. 20 An enlarged view of an example of portion "I".

[0074] exist Fig. 20 and Fig.21 , the side surface of the lower structure 10 and the side surface of the upper structure 30 may form a stepped structure near the bonding surface between the lower structure 10 and the upper structure 30. The upper structure 30 may protrude outward from the side surface of the lower structure 10. For example, the second insulating layer 36 may protrude outward from the side surface 16s of the first insulating layer 16. The entire top surface 18u of the protruding portion 18 may be in contact with the second insulating layer 36. Therefore, on the side surface 16s of the first insulating layer 16, a portion of the bottom surface 36b of the second insulating layer 36 may be exposed to the outside. The slit structure 38 may be provided in the second insulating layer 36. Some of the slit structures 38 may be arranged on the top surface 18u of the protruding portion 18, and other of the slit structures 38 may be arranged on the inner side surface of the protruding portion 18. Other slit structures 38 may be arranged on the outer side surface 18s of the protruding portion 18. Therefore, the bottom surface of still other slit structures 38 may be exposed to the outside at one side of the lower structure 10 .

[0075] Fig. 22 is a cross-sectional view illustrating an example of a semiconductor package according to some embodiments. Fig.23is a diagram showing that according to some embodiments Fig. 22 An enlarged view of an example of a portion of the FIG.

[0076] exist Fig. 22 and Fig.23 In the embodiment of the present invention, a base substrate 100 may be provided. The base substrate 100 may be a substrate (e.g., a printed circuit board (PCB)) in which no electronic components (e.g., transistors) are provided. The base substrate 100 may include a first base pad 140 and a second base pad 160. The first base pad 140 may be exposed to the outside of the base substrate 100 near the top surface of the base substrate 100. The top surface of the first base pad 140 may be coplanar with the top surface of the base substrate 100. The second base pad 160 may be exposed to the outside of the base substrate 100 near the bottom surface of the base substrate 100. The bottom surface of the second base pad 160 may be coplanar with the bottom surface of the base substrate 100. The first base pad 140 may be electrically connected to the second base pad 160 through an interconnect in the base substrate 100. The first base pad 140 and the second base pad 160 may include at least one of metal materials. For example, the first base pad 140 and the second base pad 160 may be formed of copper (Cu) or include copper (Cu).

[0077] The external terminal 180 may be disposed on the bottom surface of the base substrate 100. The external terminal 180 may be disposed on the second substrate pad 160. The external terminal 180 may be formed of or include an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

[0078] exist Fig. 22 In the embodiment, the base substrate 100 is a printed circuit board, but the base substrate 100 is not limited to this embodiment. In some embodiments, the base substrate 100 may include an integrated circuit disposed therein. For example, the base substrate 100 may be a first semiconductor chip including an electronic component (e.g., a transistor). For example, the base substrate 100 may be a wafer-level die formed of a semiconductor material (e.g., silicon (Si)). The first semiconductor chip 100 may include a first semiconductor substrate, a first circuit layer including an integrated circuit formed on the first semiconductor substrate, a first path vertically penetrating the first semiconductor substrate, a first upper pad disposed on the top surface of the first semiconductor substrate, a first upper protective layer disposed on the top surface of the first semiconductor substrate to surround the first upper pad, a first lower pad disposed on the bottom surface of the first semiconductor substrate, and a first lower protective layer disposed on the bottom surface of the first semiconductor substrate to surround the first lower pad.

[0079] The second semiconductor chip 200 may be stacked on the first semiconductor chip 100. The second semiconductor chip 200 may be of the same kind. For example, the second semiconductor chip 200 may be a memory chip. In some embodiments, four second semiconductor chips 200 are provided, but the number of the second semiconductor chips 200 is not limited to this embodiment. For example, if necessary, the number of the second semiconductor chips 200 may be changed to one of 2, 3, 5 or a higher number. Hereinafter, the structure of the second semiconductor chip 200 will be described in more detail with reference to one of the second semiconductor chips 200.

[0080] The second semiconductor chip 200 may include a second semiconductor substrate 210, a second circuit layer 220, a second via 230, a second upper pad 240, a second upper protective layer 250, a second lower pad 260, and a second lower protective layer 270. The second semiconductor substrate 210 may include a semiconductor material. For example, the second semiconductor substrate 210 may be a single crystal silicon substrate. The bottom surface of the second semiconductor substrate 210 may be the front surface of the second semiconductor substrate 210, and the top surface of the second semiconductor substrate 210 may be the rear surface of the second semiconductor substrate 210. Here, the front surface of the second semiconductor substrate 210 may be defined as a surface of the second semiconductor substrate 210 on which a semiconductor device, interconnection line, or pad is formed or mounted, and the rear surface of the second semiconductor substrate 210 may be defined as a surface opposite to the front surface.

[0081] The second semiconductor chip 200 may include a second circuit layer 220 disposed to face the base substrate 100. The second circuit layer 220 may include a semiconductor device 222 and a device interconnection portion 224.

[0082] The semiconductor device 222 may include one or more transistors TR disposed on the bottom surface of the second semiconductor substrate 210. The semiconductor device 222 may include a memory circuit, a logic circuit, or a passive device.

[0083] The bottom surface of the second semiconductor substrate 210 may be covered with a device interlayer insulating layer 226. The device interlayer insulating layer 226 may be disposed on the bottom surface of the second semiconductor substrate 210 to bury the semiconductor device 222. The device interlayer insulating layer 226 may be formed of, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), or include at least one of them. Alternatively, the device interlayer insulating layer 226 may be formed of at least one of low-k dielectric materials or include at least one of them.

[0084] The device interconnection portion 224 connected to the transistor TR may be disposed in the device interlayer insulating layer 226. The device interconnection portion 224 may include an interconnection pattern for horizontal interconnection and a connection contact for vertical interconnection. A portion of the device interconnection portion 224 may be exposed to the outside of the device interlayer insulating layer 226 through the bottom surface of the device interlayer insulating layer 226. For example, a portion of the device interconnection portion 224 may be the lowest interconnection pattern in the interconnection pattern of the device interconnection portion 224. The interconnection pattern may be formed of, for example, at least one of copper (Cu) or tungsten (W) or include at least one of them.

[0085] The semiconductor device 222 , the device interlayer insulating layer 226 , and the device interconnection portion 224 may constitute a second circuit layer 220 .

[0086] The second via 230 may vertically penetrate the second semiconductor substrate 210 and may be connected to the device interconnection portion 224. The second via 230 may vertically penetrate the device interlayer insulating layer 226 and the second semiconductor substrate 210 and may be exposed to the outside through the top surface of the second semiconductor substrate 210. In some embodiments, the second via 230 may be formed of or include tungsten (W).

[0087] The second lower pad 260 may be disposed on the device interlayer insulating layer 226. The second lower pad 260 may be coupled to the device interconnection portion 224 and the second via 230. The second lower pad 260 may be electrically connected to the semiconductor device 222 through the device interconnection portion 224. The second lower pad 260 may include a metal material. For example, the second lower pad 260 may be formed of or include copper (Cu).

[0088] The second lower protective layer 270 may be disposed on the device interlayer insulating layer 226. For example, the second lower protective layer 270 may be disposed on the bottom surface of the device interlayer insulating layer 226 to surround the second lower pad 260. The second lower pad 260 may be exposed to the outside of the second lower protective layer 270. The bottom surface of the second lower protective layer 270 may be coplanar with the bottom surface of the second lower pad 260. The second lower protective layer 270 may be formed of or include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0089] The second upper pads 240 may be disposed on the top surface of the second semiconductor substrate 210. At least some of the second upper pads 240 may be coupled to the second via 230. The second upper pads 240 may include a metal material. For example, the second upper pads 240 may be formed of or include copper (Cu).

[0090] The second upper protective layer 250 may be disposed on the top surface of the second semiconductor substrate 210. The second upper protective layer 250 on the second semiconductor substrate 210 may surround the second upper pad 240. The second upper pad 240 may be exposed to the outside of the second upper protective layer 250. The top surface of the second upper protective layer 250 may be coplanar with the top surface of the second upper pad 240. The second upper protective layer 250 may be formed of or include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0091] The second upper protective layer 250 may include a protruding portion 252. The protruding portion 252 may be disposed at a height higher than the top surface of the second upper protective layer 250. A side surface of the protruding portion 252 may be exposed outward from the side surface of the second upper protective layer 250. The protruding portion 252 may extend along the side surface of the second semiconductor chip 200. As an example, when viewed in a plan view, the protruding portion 252 may have a closed loop shape extending along the edge of the second semiconductor chip 200.

[0092] The second semiconductor chips 200 may have substantially the same structure, but the uppermost second semiconductor chip among the second semiconductor chips 200 may not include the second via 230, the second upper pad 240, and the second upper protective layer 250. However, the second semiconductor chip 200 is not limited to this embodiment.

[0093] The second semiconductor chips 200 may be sequentially stacked on the base substrate 100. The second semiconductor chips 200 may be stacked sequentially on the base substrate 100. Figures 1 to 21 The lower structure 10 and the upper structure 30 described above may be combined with each other in the same or similar manner. For example, the lower second semiconductor chip in the second semiconductor chip 200 combined with each other may correspond to the second semiconductor chip 200 of FIG. Figures 1 to 21 The lower structure 10 described above, and the upper second semiconductor chip 200 of such a second semiconductor chip may correspond to the reference Figures 1 to 21 Hereinafter, a stack structure of the second semiconductor chips 200 will be described with reference to a pair of second semiconductor chips 200 combined with each other.

[0094] The second upper pad 240 in the lower second semiconductor chip in the second semiconductor chip 200 can be vertically aligned with the second lower pad 260 in the upper second semiconductor chip in the second semiconductor chip 200. The second semiconductor chips 200 can be in contact with each other. At the interface between the second semiconductor chips 200, the second upper pad 240 in the lower second semiconductor chip in the second semiconductor chip 200 can be bonded to the second lower pad 260 in the upper second semiconductor chip in the second semiconductor chip 200. Here, the second upper pad 240 and the second lower pad 260 can form a metal-to-metal hybrid bonding structure. For example, the second upper pad 240 and the second lower pad 260 bonded to each other can have a continuous structure, and therefore, the interface between the second upper pad 240 and the second lower pad 260 may not be visible or observable. For example, the second upper pad 240 and the second lower pad 260 may be formed of the same material, and in this case, there may be no visible or observable interface between the second upper pad 240 and the second lower pad 260. In some embodiments, the second upper pad 240 and the second lower pad 260 may be provided as a single object. For example, the second upper pad 240 and the second lower pad 260 may be combined to form a single object.

[0095] Due to the bonding of the second semiconductor chips 200, the second upper protective layer 250 in the lower one of the second semiconductor chips 200 may contact the second lower protective layer 270 in the upper one of the second semiconductor chips 200. Here, the protrusion portion 252 may be inserted into the second lower protective layer 270.

[0096] The lowermost second semiconductor chip among the second semiconductor chips 200 may be mounted on the base substrate 100. For example, the second lower pads 260 of the lowermost second semiconductor chip among the second semiconductor chips 200 may be directly bonded to the first substrate pads 140 of the base substrate 100, or the lowermost second semiconductor chip among the second semiconductor chips 200 may be bonded to the base substrate 100 using connection terminals (e.g., solder balls) disposed between the first substrate pads 140 and the second lower pads 260.

[0097] The mold layer 300 may be disposed on the base substrate 100. On the top surface of the base substrate 100, the mold layer 300 may surround the second semiconductor chip 200. The mold layer 300 may include an insulating material. For example, the mold layer 300 may include an epoxy mold compound (EMC). In addition, the mold layer 300 may be formed to cover the second semiconductor chip 200.

[0098] Fig.24 is a cross-sectional view showing an example of a semiconductor module according to some embodiments. Fig.24 In the embodiment, the semiconductor module may include a module substrate 910, a chip stack package 930 and a graphics processing unit 940 mounted on the module substrate 910, and an external molding layer 950 covering the chip stack package 930 and the graphics processing unit 940, and in an embodiment, it may be a memory module. The semiconductor module may also include an interposer 920 disposed on the module substrate 910.

[0099] A module substrate 910 may be provided. The module substrate 910 may include a printed circuit board (PCB) with a signal pattern formed on a top surface thereof.

[0100] The module terminal 912 may be disposed under the module substrate 910. The module substrate 910 may include solder balls or solder bumps, and the semiconductor module may be classified into a ball grid array (BGA) type, a fine ball grid array (FBGA) type, or a land grid array (LGA) type depending on the kind and structure of the module substrate 910.

[0101] The interposer 920 may be disposed on the module substrate 910. The interposer 920 may include a first substrate pad 922 and a second substrate pad 924 disposed on the top surface and the bottom surface of the interposer 920 and exposed to the outside of the interposer 920, respectively. The interposer 920 may be configured to provide a redistribution structure for the chip stack package 930 and the graphics processing unit 940. The interposer 920 may be mounted on the module substrate 910 in a flip chip manner. For example, the interposer 920 may be mounted on the module substrate 910 using a substrate terminal 926 disposed on the second substrate pad 924. The substrate terminal 926 may include a solder ball or a solder bump. A first bottom fill layer 928 may be disposed between the module substrate 910 and the interposer 920.

[0102] The chip stack package 930 may be disposed on the interposer 920. The chip stack package 930 may have a Fig. 22 and Fig.23 The semiconductor packages described herein have the same or similar structures.

[0103] The chip stack package 930 may be mounted on the interposer 920. For example, the chip stack package 930 may be coupled to the first substrate pad 922 of the interposer 920 through the base substrate 100 or the external terminal 180 of the first semiconductor chip 100. The second bottom fill layer 938 may be disposed between the chip stack package 930 and the interposer 920. The second bottom fill layer 938 may fill the space between the interposer 920 and the base substrate (or the first semiconductor chip 100), and may surround the base substrate 100 or the external terminal 180 of the first semiconductor chip 100.

[0104] The graphics processing unit 940 may be disposed on the interposer 920. The graphics processing unit 940 may be spaced apart from the chip stack package 930. The thickness of the graphics processing unit 940 may be greater than the thickness of each of the semiconductor chips 100 and 200 of the chip stack package 930. The graphics processing unit 940 may include a logic circuit. For example, the graphics processing unit 940 may be a logic chip. The bump 942 may be disposed on the bottom surface of the graphics processing unit 940. For example, the graphics processing unit 940 may be coupled to the first substrate pad 922 of the interposer 920 through the bump 942. The third bottom fill layer 944 may be disposed between the interposer 920 and the graphics processing unit 940. The third bottom fill layer 944 may fill the space between the interposer 920 and the graphics processing unit 940, and may surround the bump 942.

[0105] The external molding layer 950 may be disposed on the interposer 920. The external molding layer 950 may cover the top surface of the interposer 920. The external molding layer 950 may surround the chip stack package 930 and the graphics processing unit 940. The top surface of the external molding layer 950 may be located at the same height as the top surface of the chip stack package 930. The external molding layer 950 may include an insulating material. For example, the external molding layer 950 may include an epoxy molding compound (EMC).

[0106] Figure 25 to Figure 35 is a cross-sectional view showing an example of a method of manufacturing a semiconductor package according to some embodiments. Fig.25 In the embodiment of the present invention, a first substrate 12 may be provided. The first substrate 12 may be a semiconductor substrate. The first substrate 12 may include a device region DR and a scribe lane region SR located between the device regions DR. The device region DR may be a region in which a semiconductor package is to be formed, and the scribe lane region SR may be a region on which a sawing process for separating the semiconductor packages from each other is to be performed.

[0107] The first circuit layer 14 may be formed on the first substrate 12. The first circuit layer 14 may include a first connection pattern 15 for connecting the first substrate 12 to the first pad 20. The first connection pattern 15 may be formed on the device region DR.

[0108] The first insulating layer 16 may be formed by depositing an insulating material on the first circuit layer 14. The first insulating layer 16 may cover the first circuit layer 14.

[0109] The first pad 20 may be formed on the first circuit layer 14. For example, the formation of the first pad 20 may include patterning the first insulating layer 16 to form an opening exposing the first connection pattern 15, forming a seed / barrier layer to conformally cover the top surface of the first insulating layer 16 and the side and bottom surfaces of the opening, forming a conductive layer through an electroplating process using the seed / barrier layer as a seed, and performing a polishing process on the conductive layer to expose the top surface of the first insulating layer 16. However, the inventive concept is not limited to this example, and the first pad 20 may be formed using other various methods.

[0110] exist Fig.26 In the embodiment of the present invention, a protruding portion 18 may be formed on the first insulating layer 16. For example, the protruding portion 18 may be formed by forming an insulating layer on the first insulating layer 16 and patterning the insulating layer. The protruding portion 18 may be located on the scribe lane region SR. The insulating layer may be formed of the same material as the first insulating layer 16. Therefore, there may be no boundary between the protruding portion 18 and the first insulating layer 16, and hereinafter, the protruding portion 18 may be referred to as a part of the first insulating layer 16. In some embodiments, the protruding portion 18 may be formed by patterning the first insulating layer 16. For example, the protruding portion 18 may be formed by etching the first insulating layer 16 on the device region DR instead of the scribe lane region SR.

[0111] exist Fig. 27 In the embodiment, a second substrate 32 may be provided. The second substrate 32 may be a semiconductor substrate. A second circuit layer 34 may be formed on the second substrate 32. The second circuit layer 34 may include a second connection pattern 35 for connecting the second substrate 32 to the second pad 40.

[0112] The second insulating layer 36 may be formed by depositing an insulating material on the second circuit layer 34. The second insulating layer 36 may cover the second circuit layer 34.

[0113] The second pad 40 may be formed on the second circuit layer 34. For example, the formation of the second pad 40 may include patterning the second insulating layer 36 to form an opening exposing the second connection pattern 35, forming a seed / barrier layer to conformally cover the top surface of the second insulating layer 36 and the side and bottom surfaces of the opening, forming a conductive layer through an electroplating process using the seed / barrier layer as a seed, and performing a polishing process on the conductive layer to expose the top surface of the second insulating layer 36. However, the second pad 40 is not limited to this embodiment, and various methods may be used to form the second pad 40.

[0114] exist Fig.28 In the embodiment, the second substrate 32 may be disposed on the first substrate 12. For example, the second substrate 32 may be disposed on the first substrate 12 such that the first pads 20 and the second pads 40 are vertically aligned with each other.

[0115] Therefore, the distance between the first substrate 12 and the second substrate 32 may be reduced in such a manner that the first insulating layer 16 and the second insulating layer 36 contact each other. The top surface of the first insulating layer 16 may contact the bottom surface of the second insulating layer 36. The top surface of the first pad 20 may contact the bottom surface of the second pad 40. Here, the protrusion 18 may be inserted into the second insulating layer 36.

[0116] exist Fig.29 In Fig.28 The resulting structure is subjected to heat treatment. Due to the heat treatment process, the first pad 20 and the second pad 40 can be combined with each other. The combination of the first pad 20 and the second pad 40 can be achieved in a natural way. For example, the first pad 20 and the second pad 40 can be formed of the same material (e.g., copper (Cu)), and in this case, the first pad 20 and the second pad 40 can be combined with each other by a metal-to-metal hybrid bonding process, which is caused by surface activation at the interface between the first pad 20 and the second pad 40 that are in contact with each other. Therefore, the first pad 20 and the second pad 40 can be combined to form a single object, and there may be no visible or observable interface between the first pad 20 and the second pad 40.

[0117] exist Figure 30 to Figure 35 In Fig.29 A singulation process is performed on the resultant structure to form semiconductor packages separated from each other. Hereinafter, the singulation process will be described in more detail.

[0118] exist Fig.30 In the embodiment of the present invention, cracks may be formed in the first substrate 12. Cracks may be formed in the scribe lane region SR. For example, the first substrate 12 may be irradiated with a laser beam. The irradiation of the laser beam may cause cracks in the first substrate 12 or in the bottom surface of the first substrate 12.

[0119] Next, the crack in the first substrate 12 may extend in a specific direction. When the crack extends, the cracked portion may extend in a specific direction in the structure. For example, the crack in the first substrate 12 may extend along the direction defined by Fig.30 The first extension path RT1 may be a path extending from the inner portion of the first substrate 12 in a vertical direction through the first circuit layer 14, the first insulating layer 16, and the protruding portion 18 of the first insulating layer 16 to the top surface of the protruding portion 18. The crack may be extended in a natural manner, or may be extended by a crack in the first substrate 12 or the protruding portion 18. Fig.30 This causes stress to be applied to the entire structure.

[0120] exist Fig.31In the embodiment, the crack may cut the first circuit layer 14, the first insulating layer 16, and the protruding portion 18 of the first insulating layer 16, and as a result, a cut-off section SS corresponding to the first expansion path RT1 may be formed.

[0121] However, cracks can continue to grow. For example, cracks can extend along Fig.31 The second expansion path RT2 depicted by the arrows is extended. The second expansion path RT2 may be a path extending from the top surface of the protruding portion 18 (e.g., from the end of the cut-off section SS) along the vertical direction through the second insulating layer 36, the second circuit layer 34, and the second substrate 32 to the top surface of the second substrate 32. The second expansion path RT2 may be vertically aligned with the first expansion path RT1. For example, the first expansion path RT1 and the second expansion path RT2 may be a portion of a substantially straight line or a substantially flat plane parallel to the vertical direction (e.g., perpendicular to the top surface of the first substrate 12). The expansion of the crack may be achieved in a natural manner, or may be achieved by cutting the second substrate 32 or the second circuit layer 34 in the second substrate 32. Fig.31 This causes stress to be applied to the entire structure.

[0122] Due to the vertical extension of the cracks passing through the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32, the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32 may be cut. Therefore, the semiconductor packages respectively located on the device region DR may be separated from each other. For example, the semiconductor package may have a structure in which the side surface of the first insulating layer 16 and the side surface of the second insulating layer 36 are coplanar with each other, as shown in FIG. Figure 1 Described.

[0123] Alternatively, the semiconductor package may be provided in such a manner that the side surface of the first insulating layer 16 is not coplanar with the side surface of the second insulating layer 36 .

[0124] exist Fig.32 middle, Fig.30 The crack in the resulting structure may extend from the end of the cut section SS along the interface between the first insulating layer 16 and the second insulating layer 36. For example, the crack may extend along the interface between the first insulating layer 16 and the second insulating layer 36. Fig.32 The third extension path RT3 depicted by the arrows extends. The third extension path RT3 may be parallel to the top surface of the protruding portion 18.

[0125] exist Fig.33 In the case of cracks, the crack can continue to grow. For example, the crack can extend along the Fig.33The fourth extension path RT4 is extended along the arrow of . The fourth extension path RT4 may be a path extending from the top surface of the protruding portion 18 through the second insulating layer 36, the second circuit layer 34, and the second substrate 32 to the top surface of the second substrate 32 in a vertical direction. The crack may extend along the third extension path RT3 between the extension along the first extension path RT1 and the extension along the fourth extension path RT4, and the third extension path is a horizontal path. Therefore, the fourth extension path RT4 may be horizontally displaced relative to the first extension path RT1.

[0126] Due to the vertical extension of the cracks passing through the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32, the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32 can be cut. Therefore, the semiconductor packages respectively located on the device region DR can be separated from each other. For example, for the semiconductor packages located on the device region DR, the semiconductor packages respectively located on the device region DR can be separated from each other. Fig.33 The semiconductor package on the left device region DR of the first insulating layer 16 and the protruding portion 18 may have a shape protruding outward from the side surface of the second insulating layer 36, as shown in FIG. Figure 6 or Figure 8 Described.

[0127] Alternatively, the semiconductor package may be provided in such a manner that the side surface of the first insulating layer 16 is not coplanar with the side surface of the second insulating layer 36 .

[0128] exist Fig.34 middle, Fig.30 The cracks in the resulting structure may extend along the interface between the first insulating layer 16 and the second insulating layer 36. For example, the cracks may extend along the interface formed by Fig.34 The fifth extension path RT5 depicted by the arrows extends. The fifth extension path RT5 may be parallel to the top surface of the protruding portion 18. Here, the direction of the fifth extension path RT5 may be anti-parallel to the third extension path RT3.

[0129] exist Fig.35 In the case of cracks, the crack can continue to grow. For example, the crack can extend along the Fig.35 The sixth extension path RT6 depicted by the arrow of . The sixth extension path RT6 may be a path extending from the top surface of the protruding portion 18 through the second insulating layer 36, the second circuit layer 34, and the second substrate 32 to the top surface of the second substrate 32 in a vertical direction. The crack may extend along the fifth extension path RT5 between the extension along the first extension path RT1 and the extension along the sixth extension path RT6, which is a horizontal path. Therefore, the sixth extension path RT6 may be horizontally displaced relative to the first extension path RT1.

[0130] Due to the vertical extension of the cracks passing through the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32, the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32 can be cut. Therefore, the semiconductor packages respectively located on the device region DR can be separated from each other. For example, for the semiconductor packages located on the device region DR, the semiconductor packages respectively located on the device region DR can be separated from each other. Fig.35 The second insulating layer 36 may include a portion protruding outward from the side surface of the first insulating layer 16, as shown in FIG. Fig.10 Described.

[0131] According to some embodiments, at the interface of each layer (e.g., at the interface between the first insulating layer 16 and the second insulating layer 36), the crack may extend along the interface or in the horizontal direction (e.g., along the third extension path RT3 or the fifth extension path RT5). However, since the crack extends along the third extension path RT3 or the fifth extension path RT5 parallel to the top surface of the protruding portion 18, the horizontal crack extension may be constrained to the top surface of the protruding portion 18. That is, the crack may not extend to the area outside the protruding portion 18. Therefore, the crack may be prevented from excessively extending in the horizontal direction, and thereby the first insulating layer 16 and the second insulating layer 36 are prevented from detaching from each other. As a result, process failures (e.g., incomplete cutting problems of the second insulating layer 36, the second circuit layer 34, and the second substrate 32) may be prevented, which may occur when the crack extends only in the horizontal direction rather than in the vertical direction. For example, the failure rate in the process of manufacturing the semiconductor package may be reduced, and the structural stability of the semiconductor package may be improved.

[0132] Figure 36 to Figure 39 is a cross-sectional view showing an example of a method of manufacturing a semiconductor package according to some embodiments. Fig.36 In Fig. 27 A slit structure 38 is formed in the second insulating layer 36 of the resulting structure. For example, a plurality of holes vertically penetrating the second insulating layer 36 may be formed by patterning the second insulating layer 36. The slit structure 38 may be formed by filling the holes with an insulating material, or the holes themselves may be used as the slit structure 38. The slit structure 38 may be located on the scribe lane region SR.

[0133] exist Fig.37 In the reference Fig.28 and Fig.29The process described above. For example, the second substrate 32 may be arranged on the first substrate 12 so that the first insulating layer 16 and the second insulating layer 36 are in contact with each other, and the first pad 20 and the second pad 40 are in contact with each other. Here, the protrusion 18 may be inserted into the second insulating layer 36. At least one of the slit structures 38 may be in contact with the top surface of the protrusion 18. Other slit structures in the slit structures 38 may be in contact with the top surface of the first insulating layer 16. Next, a heat treatment process may be performed to bond the first pad 20 and the second pad 40 to each other.

[0134] exist Fig.38 In the process, a crack may be formed in the first substrate 12. A crack may be formed on the scribe line region SR. The crack in the first substrate 12 may extend in a specific direction. The crack may extend from the inner portion of the first substrate 12 through the first circuit layer 14, the first insulating layer 16, and the protruding portion 18 of the first insulating layer 16 in a vertical direction to the top surface of the protruding portion 18. Due to the extension of the crack, a cut-off section SS may be formed to cut the first circuit layer 14, the first insulating layer 16, and the protruding portion 18 of the first insulating layer 16.

[0135] The crack may extend from the end of the cut section SS along the interface between the first insulating layer 16 and the second insulating layer 36. For example, the crack may extend along the interface between the first insulating layer 16 and the second insulating layer 36. Fig.38 The seventh extension path RT7 depicted by the arrow of is extended. The seventh extension path RT7 may be parallel to the top surface of the protruding portion 18. A terminal point of the seventh extension path RT7 may contact one of the slit structures 38. Therefore, the crack may be allowed to extend along the top surface of the protruding portion 18 until it reaches one of the slit structures 38.

[0136] exist Fig.39 In the case of cracks, the crack can continue to grow. For example, the crack can extend along the Fig.39 The eighth expansion path RT8 depicted by the arrow of . The slit structure 38 can be used to constrain the expansion direction of the crack. The slit structure 38 can change the expansion direction of the crack from the horizontal direction (for example, along the seventh expansion path RT7) to the vertical direction. For example, the slit structure 38 can be used as a guide to allow the crack to expand vertically. The eighth expansion path RT8 can be a path extending from the top surface of the protruding portion 18 through the second insulating layer 36, the second circuit layer 34 and the second substrate 32 to the top surface of the second substrate 32 in a vertical direction. The eighth expansion path RT8 can overlap with one of the slit structures 38. For example, the crack can pass through one of the slit structures 38. The crack can expand along the seventh expansion path RT7 between the expansion along the first expansion path RT1 and the expansion along the eighth expansion path RT8, and the seventh expansion path is a horizontal path. Therefore, the eighth expansion path RT8 can be horizontally displaced relative to the first expansion path RT1.

[0137] Due to the vertical extension of the cracks passing through the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32, the first substrate 12, the first circuit layer 14, the first insulating layer 16, the second insulating layer 36, the second circuit layer 34, and the second substrate 32 may be cut. Therefore, the semiconductor packages respectively located on the device region DR may be separated from each other. For example, the semiconductor package may be manufactured to have a structure with a slit structure 38, as shown in FIG. Fig.14 Described.

[0138] According to some embodiments, a semiconductor package may include a protruding portion disposed in a first insulating layer of a lower structure, and a process failure (e.g., a detachment problem of a second insulating layer from a first insulating layer) may be prevented, which process failure may be caused by horizontal crack propagation in a singulation process performed as part of a manufacturing process of the semiconductor package. Therefore, the first insulating layer and the second insulating layer may be firmly bonded to each other, and the lower structure may be firmly bonded to the upper structure. As a result, a semiconductor package having improved structural stability may be achieved.

[0139] In a method for manufacturing a semiconductor package according to some embodiments, a crack may expand in a horizontal direction along an interface between a first insulating layer and a second insulating layer. The protruding portion may suppress the horizontal expansion of the crack. Therefore, the crack may be prevented from excessively expanding in the horizontal direction, thereby preventing the first insulating layer and the second insulating layer from detaching from each other. As a result, process failures (e.g., incomplete cutting problems of the second insulating layer, the second circuit layer, or the second substrate) may be prevented, which may occur when the crack expands only in the horizontal direction and not vertically. In other words, the failure rate in the process of manufacturing a semiconductor package may be reduced, and the structural stability of the semiconductor package may be improved.

[0140] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of what can be claimed. Certain features described in the present disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features in a combination may be deleted from the combination, and a combination may involve a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor package, comprising: Substructure; as well as a superstructure located on the substructure, The lower structure includes a first semiconductor substrate, a plurality of first pads, and a first insulating layer, wherein the plurality of first pads are located on the first semiconductor substrate, and the first insulating layer is disposed on the first semiconductor substrate and surrounds the plurality of first pads. The upper structure includes a second semiconductor substrate, a plurality of second pads, and a second insulating layer, wherein the plurality of second pads are located on the second semiconductor substrate, and the second insulating layer is disposed on the second semiconductor substrate and surrounds the plurality of second pads. wherein the side surface of the lower structure and the side surface of the upper structure define a stepped structure adjacent to a joining surface between the lower structure and the upper structure, wherein the first insulating layer includes a protruding portion extending to a height higher than a top surface of the first insulating layer and extending into the second insulating layer, wherein the protruding portion contacts the side surface of the lower structure, and Wherein, each first pad of the plurality of first pads and a corresponding second pad of the plurality of second pads contact each other and form a single object having the same material.

2. The semiconductor package according to claim 1, wherein: The width of the protruding portion ranges from 1 μm to 3 μm.

3. The semiconductor package according to claim 1, wherein: The height of the protruding portion ranges from 1 μm to 5 μm.

4. The semiconductor package according to claim 1, in, The lower structure protrudes outward from the side surface of the upper structure, and At least a portion of a top surface of the protruding portion is exposed to the outside adjacent to the side surface of the upper structure.

5. The semiconductor package according to claim 1, in, The upper structure protrudes outward from the side surface of the lower structure, and A portion of the bottom surface of the second insulating layer is exposed to the outside at a side surface adjacent to the protruding portion.

6. The semiconductor package according to claim 1, wherein: A side surface of the protruding portion is exposed to the outside at a location adjacent to the side surface of the lower structure.

7. The semiconductor package according to claim 1, wherein: The protruding portion extends along an edge of the lower structure and has a closed loop shape when viewed in a plan view.

8. The semiconductor package according to claim 1, in, The protruding portion includes a plurality of protruding portions spaced apart from each other in a direction from the side surface of the lower structure toward a central portion of the lower structure, and Wherein, the side surface of the upper structure is arranged on the top surface of one of the plurality of protruding portions.

9. The semiconductor package according to claim 1, in, The upper structure further includes a plurality of slit structures disposed at the second insulating layer, wherein the plurality of slit structures vertically extend through the second insulating layer and are exposed through a bottom surface of the second insulating layer, and Wherein, at least one of the plurality of slit structures contacts a top surface of the protruding portion.

10. The semiconductor package according to claim 9, in, The protruding portion includes a first side surface coplanar with the side surface of the lower structure and a second side surface facing a central portion of the lower structure, and Another slit structure among the plurality of slit structures is disposed on the second side surface of the protruding portion and contacts the top surface of the first insulating layer.

11. The semiconductor package according to claim 9, wherein: When viewed in a plan view, each of the plurality of slit structures extends along an edge of the lower structure and has a closed loop shape.

12. The semiconductor package according to claim 9, wherein: The plurality of slit structures define an empty space filled with air or include an insulating material.

13. The semiconductor package according to claim 1, wherein: The protruding portion has a cross section of a square shape, a rectangular shape, a trapezoidal shape in which a top width is smaller than a bottom width, or a fan-shaped shape with an upwardly convex portion.

14. A semiconductor package, comprising: Substructure; as well as a superstructure located on the substructure, The lower structure includes a first semiconductor substrate, a plurality of first pads, and a first insulating layer, wherein the plurality of first pads are located on the first semiconductor substrate, and the first insulating layer is disposed on the first semiconductor substrate and surrounds the plurality of first pads. The upper structure includes a second semiconductor substrate, a plurality of second pads, a second insulating layer, and a slit structure, wherein the plurality of second pads are located on the second semiconductor substrate, the second insulating layer is disposed on the second semiconductor substrate and surrounds the plurality of second pads, and the slit structure vertically extends through the second insulating layer. wherein the first insulating layer includes a protruding portion extending upward from a top surface of the first insulating layer and extending into the second insulating layer, wherein the first side surface of the protruding portion is exposed to the outside at a position adjacent to the side surface of the lower structure, wherein the slit structure is exposed to the outside at a bottom surface adjacent to the second insulating layer and contacts a top surface of the protruding portion, and Wherein, each first pad of the plurality of first pads and a corresponding second pad of the plurality of second pads contact each other and form a single object having the same material.

15. The semiconductor package according to claim 14, wherein: The side surface of the lower structure and the side surface of the upper structure form a step-like structure adjacent to a bonding surface between the lower structure and the upper structure.

16. The semiconductor package according to claim 15, in, The lower structure protrudes outward from the side surface of the upper structure, and At least a portion of a top surface of the protruding portion is exposed to the outside adjacent to the side surface of the upper structure.

17. The semiconductor package according to claim 15, in, The upper structure protrudes outward from the side surface of the lower structure, and A portion of the bottom surface of the second insulating layer is exposed to the outside at the side surface adjacent to the protruding portion.

18. The semiconductor package according to claim 14, wherein: The width of the protruding portion ranges from 1 μm to 3 μm.

19. The semiconductor package according to claim 14, wherein: The height of the protruding portion ranges from 1 μm to 5 μm.

20. The semiconductor package according to claim 14, wherein The protruding portion extends along an edge of the lower structure and has a closed loop shape when viewed in a plan view.

21. The semiconductor package according to claim 20, wherein: When viewed in a plan view, the slit structure extends along the edge of the lower structure and has a closed loop shape.

22. The semiconductor package according to claim 14, in, The slit structure comprises a plurality of slit structures, wherein some of the plurality of slit structures contact the top surface of the protruding portion, wherein the protruding portion includes a second side surface opposite to the first side surface and facing the central portion of the lower structure, and Wherein, on the second side surface of the protruding portion, other slit structures among the plurality of slit structures contact the top surface of the first insulating layer.

23. The semiconductor package according to claim 14, wherein: Each of the plurality of slit structures defines an empty space filled with air or includes an insulating material.

24. The semiconductor package according to claim 14, wherein: The protruding portion has a cross section of a square shape, a rectangular shape, a trapezoidal shape in which a top width is smaller than a bottom width, or a fan-shaped shape with an upwardly convex portion.

25. A semiconductor package, comprising: substrate; a first semiconductor chip, wherein the first semiconductor chip is disposed on the substrate; a chip stack including a plurality of second semiconductor chips vertically stacked on the substrate and horizontally spaced apart from the first semiconductor chip; as well as a molding layer disposed on the substrate and surrounding the first semiconductor chip and the chip stack, wherein each of the plurality of second semiconductor chip components comprises a semiconductor substrate, an upper pad, an upper insulating layer, a lower pad and a lower insulating layer, wherein the upper pad is arranged on the top surface of the semiconductor substrate, the upper insulating layer is arranged on the top surface of the semiconductor substrate and surrounds the upper pad, the upper insulating layer comprises a protruding portion extending upward from the top surface of the upper insulating layer, the lower pad is arranged on the bottom surface of the semiconductor substrate, and the lower insulating layer is arranged on the bottom surface of the semiconductor substrate and surrounds the lower pad, wherein adjacent second semiconductor chips among the plurality of second semiconductor chips are in contact with each other, wherein, at a contact surface between the plurality of second semiconductor chips, the lower pad and the upper pad contact each other and form a single object having the same material, wherein the protruding portion extends along an edge of each of the plurality of second semiconductor chips and has a closed loop shape when viewed in a plan view, and Wherein, the width of the protruding portion ranges from 1 μm to 3 μm.

26. The semiconductor package according to claim 25, wherein: The protruding portion of the upper insulating layer of a first second semiconductor chip among the plurality of second semiconductor chips extends into the lower insulating layer of a second second semiconductor chip among the plurality of second semiconductor chips.

27. The semiconductor package according to claim 25, wherein: The plurality of second semiconductor chips are disposed to have a step-like structure adjacent to contact surfaces between the plurality of second semiconductor chips.

28. The semiconductor package according to claim 25, wherein: The protruding portion of each of the plurality of second semiconductor chips is exposed to the outside at a side surface adjacent to the second semiconductor chip.

29. The semiconductor package according to claim 25, wherein: The height of the protruding portion ranges from 1 μm to 5 μm.

30. The semiconductor package according to claim 25, wherein The protruding portion has a cross section of a square shape, a rectangular shape, a trapezoidal shape in which a top width is smaller than a bottom width, or a fan-shaped shape with an upwardly convex portion.

31. The semiconductor package according to claim 25, in, Each of the plurality of second semiconductor chips further includes a plurality of slit structures disposed in the lower insulating layer, wherein the plurality of slit structures vertically extend into the second insulating layer and are exposed through the bottom surface of the lower insulating layer, and The plurality of slit structures of each of the plurality of second semiconductor chips are in contact with a top surface of the protruding portion of another second semiconductor chip of the plurality of second semiconductor chips disposed therebelow.

32. The semiconductor package according to claim 31, wherein The plurality of slit structures include empty spaces filled with air or include insulating materials.

33. A method for manufacturing a semiconductor package, the method comprising: forming a lower structure, the lower structure comprising a first semiconductor substrate having a device region and a scribe lane region between the device regions, a first pad disposed on the device region of the first semiconductor substrate, and a first insulating layer disposed on the first semiconductor substrate to surround the first pad; forming a protrusion extending upward from a top surface of the first insulating layer on the first insulating layer in the scribe line area; forming an upper structure, the upper structure comprising a second semiconductor substrate, a second pad disposed on the second semiconductor substrate, and a second insulating layer disposed on the second semiconductor substrate to surround the second pad, the first pad and the second pad comprising the same metal material; Laying the upper structure on the lower structure so that the first pad contacts the second pad and the protruding portion is laid into the second insulating layer; performing a heat treatment process on the lower structure and the upper structure to bond the first pad to the second pad, thereby resulting in a single object; as well as forming a crack in the scribe line region of the first semiconductor substrate, The crack propagates from the first semiconductor substrate to extend through the first insulating layer, the protruding portion, the second insulating layer, and the second semiconductor substrate.

34. The method according to claim 33, in, The crack sequentially propagates along a first propagation path defined as passing through the first semiconductor substrate, the first insulating layer, and the protruding portion, and a second propagation path defined as passing through the second insulating layer and the second semiconductor substrate, and The first extension path and the second extension path are perpendicular to a top surface of the first semiconductor substrate.

35. The method according to claim 34, in, the crack propagates along a third propagation path, the third propagation path being defined parallel to the top surface of the protruding portion, wherein the crack sequentially propagates along the first propagation path, the third propagation path, and the second propagation path, and The first extension path and the second extension path are horizontally displaced from each other.

36. The method of claim 34, wherein: The first expansion path and the second expansion path are vertically aligned with each other.

37. The method according to claim 34, in, The upper structure further includes a plurality of slit structures disposed in the second insulating layer, wherein the plurality of slit structures vertically extend into the second insulating layer, are exposed through the bottom surface of the second insulating layer, and contact the top surface of the protruding portion, and Wherein, the third expansion path is arranged in one of the plurality of slit structures.

Images