Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method thereof and electronic equipment. The chip packaging structure comprises a rewiring layer, a first adapter plate, a second adapter plate, a first connecting structure, a second connecting structure, a first chip, a second chip, a third chip and a fourth chip. Wherein the rewiring layer comprises an interconnection structure, the first adapter plate and the second adapter plate are arranged on the rewiring layer and are electrically connected with the interconnection structure, at least one of the first adapter plate and the second adapter plate is an active adapter plate, one end of each first connecting structure is electrically connected with the first adapter plate, and the other end of each second connecting structure is electrically connected with the second adapter plate. One ends of the plurality of second connection structures are electrically connected with the second adapter plate, the first chip and the second chip are electrically connected with the other ends of the plurality of first connection structures respectively, and the third chip and the fourth chip are electrically connected with the other ends of the plurality of second connection structures respectively. According to the technical scheme, horizontal and three-dimensional integrated interconnection of multiple chips is achieved, and the integration level of the packaging structure is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of artificial intelligence and high-performance computing, high-density interconnection between multiple chips is a problem that needs to be solved. How to achieve horizontal and three-dimensional integrated interconnection and improve the integration of packaging structures is one of the key research directions. Summary of the invention

[0003] The present application proposes a chip packaging structure, including a rewiring layer, a first adapter plate and a second adapter plate, a plurality of first connection structures and a plurality of second connection structures, and a first chip, a second chip, a third chip and a fourth chip. The rewiring layer includes an interconnection structure, the first adapter plate and the second adapter plate are arranged on the rewiring layer and are electrically connected to the interconnection structure respectively, at least one of the first adapter plate and the second adapter plate is an active adapter plate, one end of the plurality of first connection structures is electrically connected to the first adapter plate, one end of the plurality of second connection structures is electrically connected to the second adapter plate, the first chip and the second chip are electrically connected to the other end of the plurality of first connection structures respectively, and the third chip and the fourth chip are electrically connected to the other end of the plurality of second connection structures respectively.

[0004] In some embodiments, the chip packaging structure further includes a third connection structure, a fourth connection structure and a first connection column, the first chip is electrically connected to one end of the third connection structure, and the other end of the third connection structure is electrically connected to the first connection column.

[0005] The third chip is electrically connected to one end of the fourth connection structure, and the other end of the fourth connection structure is electrically connected to the first connection column.

[0006] In some embodiments, the first chip and the third chip are control chips, and the second chip and the fourth chip are memory chips.

[0007] In some embodiments, the first chip is a central processing unit chip, the second chip is a dynamic random access memory chip, the third chip is a graphics processing unit chip, and the fourth chip is a high bandwidth memory chip.

[0008] In some embodiments, the first transfer board and the second transfer board are arranged in parallel with the bottom surface of the rewiring layer. The first chip, the second chip, the third chip and the fourth chip are arranged in parallel with the bottom surface of the rewiring layer.

[0009] In some embodiments, the chip packaging structure further includes a packaging layer, which wraps the first transfer board and the second transfer board.

[0010] In an embodiment of the present application, a first adapter board and a second adapter board are arranged on the rewiring layer, and are electrically connected to the interconnection structure of the rewiring layer respectively, so as to realize the interconnection between the two adapter boards. At least one of the first adapter board and the second adapter board is an active adapter board, which can provide a diversified interconnection network. One end of the multiple first connection structures is electrically connected to the first adapter board, and the other end is electrically connected to the first chip and the second chip respectively, so as to realize the interconnection between the first adapter board and the first chip and the second chip; one end of the multiple second connection structures is electrically connected to the second adapter board, and the other end is electrically connected to the third chip and the fourth chip respectively, so as to realize the interconnection between the second adapter board and the third chip and the fourth chip. The chip packaging structure constructed by multiple interconnection relationships realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and there is no need to re-design the interconnection between multiple chips on the circuit board.

[0011] On the other hand, the present application also provides a method for preparing a chip packaging structure, comprising the following steps S1 to S5:

[0012] Step S1: disposing a first adapter board and a second adapter board on a carrier board, wherein at least one of the first adapter board and the second adapter board is an active adapter board.

[0013] Step S2: forming a plurality of first connection structures and a plurality of second connection structures, wherein one end of the plurality of first connection structures is electrically connected to the first adapter board, and one end of the plurality of second connection structures is electrically connected to the second adapter board.

[0014] Step S3: electrically connecting the first chip and the second chip to the other ends of the plurality of first connection structures, and electrically connecting the third chip and the fourth chip to the other ends of the plurality of second connection structures.

[0015] Step S4: removing the carrier board.

[0016] Step S5: forming a rewiring layer, the rewiring layer is located on a side of the first adapter board away from the first chip and on a side of the second adapter board away from the third chip, the rewiring layer includes an interconnection structure, and the interconnection structure is electrically connected to the first adapter board and the second adapter board.

[0017] In some embodiments, before forming the first adapter plate and the second adapter plate, the preparation method further includes forming a first connecting column on the carrier. In the process of forming the first connecting structure and the second connecting structure, a third connecting structure and a fourth connecting structure are simultaneously formed, wherein one end of the third connecting structure is electrically connected to the first connecting column, and one end of the fourth connecting structure is electrically connected to the first connecting column. In the process of electrically connecting the first chip to the first connecting structure, the first chip is also electrically connected to the other end of the third connecting structure, and in the process of electrically connecting the third chip to the second connecting structure, the third chip is also electrically connected to the other end of the fourth connecting structure.

[0018] In some embodiments, after forming the first adapter board and the second adapter board, and before forming the first connection structure and the second connection structure, the preparation method further includes forming a first packaging layer on the carrier, the first packaging layer exposing the surface of the first adapter board away from the carrier, and exposing the surface of the second adapter board away from the carrier. Before removing the carrier, the preparation method further includes forming a second packaging layer, the second packaging layer encapsulating the first adapter board, the second adapter board, the first chip, the second chip, the third chip, and the fourth chip.

[0019] The chip packaging structure prepared by the above preparation method realizes the horizontal interconnection between the first adapter board and the second adapter board, realizes the interconnection between the first adapter board and the first chip and the second chip, and realizes the interconnection between the second adapter board and the third chip and the fourth chip. That is, the horizontal and three-dimensional integrated interconnection between multiple chips is realized, the integration of the packaging structure is improved, and there is no need to re-design the interconnection between multiple chips on the circuit board.

[0020] In a third aspect, the present application also provides an electronic device, including the chip packaging structure mentioned above, and a circuit board, wherein the chip packaging structure is electrically connected to the circuit board. The chip packaging structure in the electronic device realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and does not need to perform the interconnection design between the multiple chips again on the circuit board.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0023] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0024] Figure 2 A flow chart of a chip packaging structure preparation method provided in an embodiment of the present application;

[0025] Figure 3 to Figure 12 A step diagram of the preparation method provided in the embodiment of the present application;

[0026] Fig.13 An electronic device is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] In the description of the present application, “plurality” means two or more.

[0030] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0031] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0032] At present, chip-on-wafer-on-substrate (CoWoS) technology is a common 2.5D packaging solution for high-computing power chips. During the technology iteration process, the size of the adapter board continues to increase, which will inevitably lead to a decrease in the manufacturing yield of the adapter board and subsequent reliability issues of large-size silicon adapter boards, while increasing the corresponding costs.

[0033] In contrast, the silicon bridge embedded active transfer board provides better electrical, signal and power integrity performance than the silicon intermediate connector solution, with lower cost and no limitation on wafer size. The technology is highly scalable and can be seamlessly integrated into complex chip architectures. The use of high-density interconnect silicon bridges to connect chips makes the interconnect line density an order of magnitude higher than traditional organic flip-chip solder packaging.

[0034] However, the current main silicon bridge technology is to produce high-density wiring and fine-pitch micro-bumps on a silicon substrate, and achieve horizontal interconnection between chips through substrate embedment or fan-out packaging integration, but it is unable to achieve horizontal and three-dimensional integrated interconnection. In addition, the integration of the packaging structure is limited, and usually it is necessary to perform interconnection design again on the system-level circuit board to achieve interconnection with other chips.

[0035] To solve the above problems, the present application proposes a chip packaging structure 100, such as Figure 1 As shown, Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application.

[0036] The chip packaging structure 100 includes a rewiring layer 10, and the rewiring layer 10 includes an interconnection structure 11. The chip packaging structure 100 also includes a first adapter board 12 and a second adapter board 13 disposed on the rewiring layer 10, and the first adapter board 12 and the second adapter board 13 are electrically connected to the interconnection structure 11 respectively, and at least one of the first adapter board 12 and the second adapter board 13 is an active adapter board.

[0037] The chip packaging structure 100 further includes a plurality of first connection structures 14 and a plurality of second connection structures 15, wherein one end of the plurality of first connection structures 14 is electrically connected to the first adapter board 12, and one end of the plurality of second connection structures 15 is electrically connected to the second adapter board 13. The chip packaging structure 100 further includes a first chip 16, a second chip 17, a third chip 18, and a fourth chip 19, wherein the first chip 16 and the second chip 17 are electrically connected to the other ends of the plurality of first connection structures 14, respectively, and the third chip 18 and the fourth chip 19 are electrically connected to the other ends of the plurality of second connection structures 15, respectively.

[0038] In the embodiment of the present application, the first adapter board 12 and the second adapter board 13 are arranged on the rewiring layer 10, and are respectively electrically connected to the interconnection structure 11 of the rewiring layer 10, thereby realizing horizontal interconnection between the two adapter boards. In addition, the rewiring layer 10 also provides a basis for the interconnection between the chip packaging structure 100 and the high-density substrate, which is more flexible.

[0039] In addition, one end of the plurality of first connection structures 14 is electrically connected to the first adapter board 12, and the other end is electrically connected to the first chip 16 and the second chip 17, respectively, thereby realizing the interconnection between the first adapter board 12 and the first chip 16 and the second chip 17. One end of the plurality of second connection structures 15 is electrically connected to the second adapter board 13, and the other end is electrically connected to the third chip 18 and the fourth chip 19, respectively, thereby realizing the interconnection between the second adapter board 13 and the third chip 18 and the fourth chip 19.

[0040] At least one of the first adapter board 12 and the second adapter board 13 is an active adapter board. For example, the first adapter board 12 can be an active adapter board, and the second adapter board 13 can be a passive adapter board, wherein the "passive adapter board" includes a silicon wafer, a through hole (Through Silicon Via, TSV) penetrating the silicon wafer, and a wiring arranged on the silicon wafer, and the "active adapter board" includes not only a silicon wafer, a through hole penetrating the silicon wafer, and a wiring arranged on the silicon wafer, but also includes active devices arranged on the silicon wafer, and the active devices are used to form a functional circuit that meets the design requirements. For another example, the first adapter board 12 can be a passive adapter board, and the second adapter board 13 can be an active adapter board. For another example, the first adapter board 12 and the second adapter board 13 are both active adapter boards.

[0041] Compared with passive silicon bridges, active adapter board interconnection can better optimize signal integrity performance and signal conditioning functions. The chip packaging structure constructed with multiple interconnection relationships can better realize horizontal and vertical high-density interconnection between chips, with strong flexibility, and realize horizontal and three-dimensional integrated interconnection between multiple chips, which improves the integration of the packaging structure and eliminates the need to re-design the interconnection between the multiple chips on the circuit board.

[0042] The adapter boards provided in the embodiment of the present application are not limited to two, but may be three, four, five, etc., and at least one of the multiple adapter boards is an active adapter board. Multiple adapter boards can form an interwoven interconnection network, provide more interconnection points and higher interconnection density, and can easily expand the functions and performance of the system, and in some cases can also improve the fault tolerance of the system.

[0043] The chips provided in the embodiment of the present application are not limited to four, but can also be five, six, seven, etc. Multiple chips are integrated in the chip packaging structure 100, which can improve the integration level and reduce the communication time between chips, without the need to re-design the interconnection between the multiple chips on the circuit board.

[0044] In some embodiments, Figure 1As shown, the chip package structure 100 further includes a third connection structure 20, a fourth connection structure 21 and a first connection pillar 22. The first chip 16 is electrically connected to one end of the third connection structure 20, and the other end of the third connection structure 20 is electrically connected to the first connection pillar 22. The third chip 18 is electrically connected to one end of the fourth connection structure 21, and the other end of the fourth connection structure 21 is electrically connected to the first connection pillar 22.

[0045] Through the third connecting structure 20, the fourth connecting structure 21 and the first connecting column 22, direct interconnection between the first chip 16 and the third chip 18 is achieved, which improves the connection density and integration. Direct communication can be achieved between the first chip 16 and the third chip 18 without going through the adapter board or other channels on the system circuit board, which can reduce the delay of data transmission. In tasks that require a large amount of parallel processing, the computing power of the control chip can be more efficiently utilized.

[0046] In some embodiments, Figure 1 As shown, the first chip 16 and the third chip 18 are control chips, and the second chip 17 and the fourth chip 19 are storage chips.

[0047] Exemplarily, the first chip 16 and the third chip 18 may be high-computing power chips, and by using a bridging technology using two or more adapter boards, a high-density direct interconnection between the high-computing power chip and the storage chip is achieved.

[0048] In some embodiments, Figure 1 As shown, the first chip 16 is a central processing unit chip (CPU), the second chip 17 is a dynamic random access memory chip (DRAM), the third chip 18 is a graphics processing unit chip (GPU), and the fourth chip 19 is a high bandwidth memory chip (HBM).

[0049] The first chip 16 and the second chip 17 are interconnected via the first adapter board 12, and the third chip 18 and the fourth chip 19 are interconnected via the second adapter board 13. The first adapter board 12 or the second adapter board 13 can provide higher bandwidth interconnection and optimize the signal path, so that the data transmission between the central processing unit chip and the dynamic random access memory chip, and between the graphics processing unit chip and the high-bandwidth memory chip is faster, reducing the attenuation and interference of the signal during the transmission process, thereby improving the integrity of the signal.

[0050] In some embodiments, Figure 1As shown, the rewiring layer 10 includes a bottom surface P1 away from the first adapter board 12. The first adapter board 12 and the second adapter board 13 are arranged in a flat pattern in a direction parallel to the bottom surface P1 of the rewiring layer 10, that is, the first adapter board 12 and the second adapter board 13 are not stacked. The first chip 16, the second chip 17, the third chip 18 and the fourth chip 19 are arranged in a flat pattern in a direction parallel to the bottom surface P1 of the rewiring layer 10.

[0051] In some embodiments, Figure 1 As shown, the chip packaging structure further includes a packaging layer 23, which wraps the first adapter board 12 and the second adapter board 13 to ensure the stability of the first chip 16 and the second chip 17 bridged by the first adapter board 12, and the stability of the third chip 18 and the fourth chip 19 bridged by the second adapter board 13. The packaging layer 23 provides physical protection for the internal electronic components to prevent mechanical damage, dust, moisture and other environmental factors from damaging sensitive semiconductor materials. Exemplarily, the packaging layer 23 material includes epoxy molding compound (EMC).

[0052] On the other hand, the present application also provides a method for preparing a chip packaging structure, such as Figure 2 As shown, Figure 2 A flow chart of a chip packaging structure preparation method provided in an embodiment of the present application, Figure 3 to Figure 12 A step diagram of the preparation method provided in the embodiments of the present application.

[0053] Specifically, the preparation method includes the following steps S1 to S5:

[0054] Step S1: Figure 3-4 As shown, the first adapter board 12 and the second adapter board 13 are disposed on the carrier board L01 , and at least one of the first adapter board 12 and the second adapter board 13 is an active adapter board.

[0055] Exemplarily, before step S1, Figure 3 As shown, the preparation method further includes forming a first connecting column 22 on the carrier L01. The carrier L01 includes a temporary carrier L02 and a temporary bonding adhesive L03 coated on the upper surface of the carrier L02. Then, the first connecting column 22 is prepared on the carrier L01 by an electroplating process, and the material of the first connecting column 22 may include copper.

[0056] Afterwards, if Figure 4 As shown, through the patch process, the active adapter board is connected to the carrier board L01 to form a first adapter board 12 and a second adapter board 13. The active adapter board can also be an active silicon bridge.

[0057] Step S2: Figure 5 to Figure 7As shown, a plurality of first connection structures 14 and a plurality of second connection structures 15 are formed, one end of the plurality of first connection structures 14 is electrically connected to the first adapter board 12 , and one end of the plurality of second connection structures 15 is electrically connected to the second adapter board 13 .

[0058] Exemplarily, before step S2, as Figure 5 As shown, the preparation method further includes forming a first packaging layer 24 on the carrier L01. The first packaging layer 24 wraps the first transfer board 12 and the second transfer board 13. The material of the first packaging layer 24 includes epoxy molding compound (EMC), and the process adopts a wafer-level molding process.

[0059] Afterwards, if Figure 6 As shown, grinding, thinning and chemical mechanical polishing are performed to reduce the package volume and achieve surface flatness, so that the first package layer 24 exposes the surface of the first adapter plate 12 away from the carrier L01 and exposes the surface of the second adapter plate 13 away from the carrier L01, and at the same time, exposes the first connecting column 22.

[0060] For example, in some embodiments, Figure 7 As shown, during the process of completing step S2 , the third connection structure 20 and the fourth connection structure 21 are formed simultaneously, wherein one end of the third connection structure 20 is electrically connected to the first connection column 22 , and one end of the fourth connection structure 21 is electrically connected to the first connection column 22 .

[0061] Exemplarily, the process of completing step S2 adopts a micro-bump manufacturing process to form a high-density interconnection structure.

[0062] Step S3: Figure 8-Figure 9 As shown, the first chip 16 and the second chip 17 are electrically connected to the other ends of the plurality of first connection structures 14 , and the third chip 18 and the fourth chip 19 are electrically connected to the other ends of the plurality of second connection structures 15 .

[0063] For example, Figure 8 As shown, in the process of completing step S3, the first chip 16 and the second chip 17 are electrically connected to the other end of the plurality of first connection structures 14, and at the same time, the first chip 16 is also electrically connected to the other end of the third connection structure 20. The third chip 18 and the fourth chip 19 are electrically connected to the other end of the plurality of second connection structures 15, and at the same time, the third chip 18 is also electrically connected to the other end of the fourth connection structure 21.

[0064] Thus, the first chip 16 and the second chip 17 are electrically connected through the first connection structure 14 and the first adapter board 12. The third chip 18 and the fourth chip 19 are electrically connected through the second connection structure 15 and the second adapter board 13. The first chip 16 and the third chip 18 are electrically connected through the third connection structure 20 and the fourth connection structure 21 and the first connection column 22.

[0065] In some embodiments, Fig. 9 As shown, after completing step S3, the bottom filling and molding process is used to perform plastic encapsulation and thinning to form a second encapsulation layer 25. The second encapsulation layer 25 wraps the first chip 16, the second chip 17, the third chip 18 and the fourth chip 19, and covers the surfaces of the first transfer board 12 and the second transfer board 13 exposed by the first encapsulation layer 24. Exemplarily, the second encapsulation layer 25 is made of the same material as the first encapsulation layer 24, including epoxy molding compound (EMC).

[0066] The second packaging layer 25 and the first packaging layer 24 together form the packaging layer 23 of the chip packaging structure.

[0067] The packaging layer 23 wraps the first adapter board 12, the second adapter board 13, the first chip 16, the second chip 17, the third chip 18 and the fourth chip 19 to form a relatively stable packaging structure. At this point, the packaging process is completed.

[0068] Step S4: Fig.10 As shown, the carrier board L01 is removed.

[0069] For example, Fig.10 As shown, the temporary bonding glue L03 is removed by the debonding process, and as the temporary bonding glue L03 is peeled off and removed, the temporary carrier L02 is also removed. After removing the carrier L01, the lower surface of the first adapter board 12 and the second adapter board 13 is exposed, that is, the side away from the first chip 16 and the third chip 18.

[0070] Step S5: Fig.11 As shown, a rewiring layer 10 is formed. The rewiring layer 10 is located on a side of the first adapter board 12 away from the first chip 16 and on a side of the second adapter board 13 away from the third chip 18. The rewiring layer 10 includes an interconnection structure 11, which is electrically connected to the first adapter board 12 and the second adapter board 13.

[0071] For example, Fig.11As shown, a rewiring layer 10 is formed on the lower surface of the first adapter board 12 and the second adapter board 13, that is, the side of the first adapter board 12 and the second adapter board 13 away from the first chip 16, and the electrical connection between the first adapter board 12 and the second adapter board 13 is achieved by utilizing the interconnection structure 11 of the rewiring layer 10.

[0072] In some embodiments, Fig.12 As shown, after completing step S5, a micro-bump manufacturing process is adopted on a side of the rewiring layer 10 away from the first adapter board 12 and the second adapter board 13 to form solder balls 26 for subsequent electrical connection with the circuit board.

[0073] The chip packaging structure prepared according to this preparation method realizes horizontal interconnection between the first adapter board 12 and the second adapter board 13, realizes interconnection between the first adapter board 12 and the first chip 16 and the second chip 17, and realizes interconnection between the second adapter board 13 and the third chip 18 and the fourth chip 19. That is, horizontal and three-dimensional integrated interconnection between multiple chips is realized, the integration of the packaging structure is improved, and there is no need to re-design the interconnection between multiple chips on the circuit board.

[0074] The above preparation method combines the micro-bump manufacturing process with the wafer-level fan-out packaging process, and integrates it into the molding, grinding, thinning and chemical mechanical polishing processes. It does not require a silicon adapter plate, which can reduce packaging costs and improve packaging reliability.

[0075] In a third aspect, the present application also provides an electronic device 200, such as Fig.13 As shown, Fig.13 An electronic device provided in an embodiment of the present application includes the chip packaging structure 100 mentioned above, and a circuit board 201, wherein the chip packaging structure 200 is electrically connected to the circuit board 201. The chip packaging structure 100 in the electronic device 200 realizes horizontal and three-dimensional integrated interconnection between multiple chips, improves the integration of the packaging structure, and does not need to perform interconnection design again on the circuit board 201.

[0076] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: rewiring layers, including interconnect structures; A first adapter plate and a second adapter plate are disposed on the rewiring layer and are electrically connected to the interconnect structure respectively; At least one of the first adapter board and the second adapter board is an active adapter board; A plurality of first connection structures and a plurality of second connection structures, wherein one end of the plurality of first connection structures is electrically connected to the first adapter plate, and one end of the plurality of second connection structures is electrically connected to the second adapter plate; A first chip, a second chip, a third chip and a fourth chip, wherein the first chip and the second chip are electrically connected to the other ends of the plurality of first connection structures respectively, and the third chip and the fourth chip are electrically connected to the other ends of the plurality of second connection structures respectively.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a third connecting structure, a fourth connecting structure and a first connecting column; The first chip is electrically connected to one end of the third connection structure, and the other end of the third connection structure is electrically connected to the first connection column; The third chip is electrically connected to one end of the fourth connection structure, and the other end of the fourth connection structure is electrically connected to the first connection column.

3. The chip packaging structure according to claim 1, characterized in that: The first chip and the third chip are control chips, and the second chip and the fourth chip are storage chips.

4. The chip packaging structure according to claim 3, characterized in that: The first chip is a central processing unit chip, the second chip is a dynamic random access memory chip, the third chip is a graphics processing unit chip, and the fourth chip is a high bandwidth memory chip.

5. The chip packaging structure according to claim 1, characterized in that: The first adapter board and the second adapter board are arranged flatly along a direction parallel to the bottom surface of the rewiring layer; The first chip, the second chip, the third chip and the fourth chip are arranged in a tiled manner along a direction parallel to a bottom surface of the rewiring layer.

6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a packaging layer, and the packaging layer wraps the first adapter board and the second adapter board.

7. A method for preparing a chip packaging structure, characterized in that: include: Disposing a first adapter board and a second adapter board on a carrier board, wherein at least one of the first adapter board and the second adapter board is an active adapter board; forming a plurality of first connection structures and a plurality of second connection structures, wherein one end of the plurality of first connection structures is electrically connected to the first adapter board, and one end of the plurality of second connection structures is electrically connected to the second adapter board; electrically connecting the first chip and the second chip to the other ends of the plurality of first connection structures, and electrically connecting the third chip and the fourth chip to the other ends of the plurality of second connection structures; removing the carrier plate; A rewiring layer is formed, the rewiring layer is located on a side of the first adapter board away from the first chip, and is located on a side of the second adapter board away from the third chip; the rewiring layer includes an interconnection structure, and the interconnection structure is electrically connected to the first adapter board and the second adapter board.

8. The preparation method according to claim 7, characterized in that: Before forming the first adapter plate and the second adapter plate, the preparation method further includes: forming a first connecting column on the carrier; In the process of forming the first connection structure and the second connection structure, a third connection structure and a fourth connection structure are formed simultaneously; one end of the third connection structure is electrically connected to the first connection pillar, and one end of the fourth connection structure is electrically connected to the first connection pillar; In the process of electrically connecting the first chip to the first connection structure, the first chip is also electrically connected to the other end of the third connection structure; in the process of electrically connecting the third chip to the second connection structure, the third chip is also electrically connected to the other end of the fourth connection structure.

9. The preparation method according to claim 7, characterized in that: After forming the first adapter plate and the second adapter plate, and before forming the first connection structure and the second connection structure, the preparation method further includes: forming a first packaging layer on the carrier, wherein the first packaging layer exposes a surface of the first adapter plate away from the carrier, and exposes a surface of the second adapter plate away from the carrier; Before removing the carrier plate, the preparation method further comprises: A second packaging layer is formed, wherein the second packaging layer encapsulates the first adapter board, the second adapter board, the first chip, the second chip, the third chip, and the fourth chip.

10. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 6; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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