Phase interpolator circuit with broadband and high linearity and CDR thereof

Abstract

The invention belongs to the technical field of phase interpolators, and particularly relates to a broadband high-linearity phase interpolator circuit and a CDR thereof. Comprising a quadrant selection module which is used for carrying out coarse tuning on the phase of a clock output by a phase interpolator to realize phase offset of four quadrant intervals; an input signal of the quadrant selection module is a wide-range frequency four-phase clock signal provided by a PLL (Phase Locked Loop), and an output signal of the quadrant selection module is an orthogonal differential clock signal; the amplitude adjusting module is used for adjusting the amplitude VS1 of an output clock of the amplitude adjusting module so as to adjust the voltage conversion rate of the differential clock signal; the core interpolation circuit module is used for carrying out interpolation operation on the input differential clock signal and adjusting tail current through the M + N-bit control bit adjusting signal so as to output the differential clock signal; and the tail current control bit module provides phase weight selection for the core interpolation circuit module. The overall phase interpolator has the advantages of being wide in output clock frequency and high in linearity.

Description

Technical Field

[0001] The present invention belongs to the technical field of phase interpolators, and in particular relates to a phase interpolator circuit with wideband and high linearity and a CDR thereof. Background Art

[0002] As the transmission rate of digital systems continues to increase, higher requirements are placed on the bit error rate. At the receiving end of the serial interface, the jitter of the sampling clock recovered by the CDR determines the bit error rate of the recovered sampled data. Among the various CDR structures, the CDR based on the phase interpolator can achieve better loop stability and can share the PLL with multiple phase clocks, and is widely used.

[0003] The traditional phase interpolator consists of a plurality of equal current source arrays through the tail current source, and the weight control signal controls the flow path of each current source, thereby adjusting the tail current size of the two input signal differential pairs, so that the phase of the output signal is interpolated between the two input signal phases. The relationship between the output signal phase obtained by this interpolation method and the weight control signal is nonlinear, and the linearity of the interpolator is related to the phase difference between the two input signals. The larger the phase difference, the lower the linearity of the interpolator. Summary of the invention

[0004] The purpose of the present invention is to provide a phase interpolator circuit and its CDR with wide frequency and high linearity. Based on the traditional phase interpolator, the overall phase interpolator of the present invention has the characteristics of wide output clock frequency and high linearity.

[0005] In order to solve the above technical problems, the present invention provides a phase interpolator circuit with wideband and high linearity, comprising: A quadrant selection module is used to coarsely adjust the phase of the phase interpolator output clock and realize the phase shift of the four quadrant intervals between 0°~90°, 90°~180°, 180°~270° and 270°~360°; the input signal of the quadrant selection module is the four-phase clock signals CLK0, CLK90, CLK180 and CLK270 with a wide range of frequencies provided by the PLL, and the output signal is the orthogonal differential clock signals CLKQ, CLKQN, CLKI and CLKIN; An amplitude adjustment module adjusts the output clock amplitude VS1 to adjust the voltage conversion rate of the differential clock signals CLKQ, CLKQN, CLKI and CLKIN, thereby improving the linearity of the output clock of the phase interpolator; The core interpolation circuit module uses a CML circuit to perform interpolation operations on the input differential clock signals CLKQ, CLKQN, CLKI and CLKIN, and adjusts the tail current through the M+N-bit control bit adjustment signal to output differential clock signals CLK_OUT and CLK_OUTN; The tail current control bit module provides phase weight selection for the core interpolation circuit module, solves the nonlinearity of the output clock of the core interpolation circuit module caused by the establishment time of the tail current switching during fine adjustment through an M-bit control signal, and realizes fine adjustment of the output phase of the phase interpolator through an N-bit control signal, and the fine adjustment phase accuracy is 90° / N.

[0006] Preferably, the quadrant selection module is composed of a first quadrant selection unit and a second quadrant selection unit, wherein the first quadrant selection unit and the second quadrant selection unit both include: capacitors C1-C4, switches S1-S8, inverters INV1-INV6 and resistors R1-R4; Among them, one end of the capacitor C1 is used as the clock signal input end, the other end of the capacitor C1 is connected to the switch S1, the switch S4 and one end of the resistor R1, the other end of the switch S1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the output end of the inverter INV2 and to one end of the capacitor C3, the switch S7 and the switch S8, the other end of the capacitor C3 is connected to one end of the resistor R3 and the input end of the inverter INV5, the output end of the inverter INV5 is connected to the other end of the resistor R3 and outputs a differential clock signal; One end of the capacitor C2 serves as a clock signal input end, the other end of the capacitor C2 is connected to the switch S2, the switch S3 and one end of the resistor R2, the other end of the switch S2 is connected to the input end of the inverter INV2, the other end of the switch S3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the output end of the inverter INV4 and to one end of the capacitor C4, the switch S5 and the switch S6, the other end of the switch S4 is connected to the input end of the inverter INV4, the other end of the capacitor C4 is connected to one end of the resistor R4 and the input end of the inverter INV6, the output end of the inverter INV6 is connected to the other end of the resistor R4 and outputs a differential clock signal; The other end of the resistor R1 is connected to the other ends of the switch S5 and the switch S8 , and the other end of the resistor R2 is connected to the other ends of the switch S6 and the switch S7 .

[0007] Preferably, it also includes control signals SI, SIN, SQ and SQN provided by the digital module; In the first quadrant selection unit, the control signal SI is used to control switches S1, S3, S6 and S8, and the control signal SIN is used to control switches S2, S4, S5 and S7; In the second quadrant selection unit, the control signal SQ is used to control switches S1, S3, S6 and S8, and the control signal SQN is used to control switches S2, S4, S5 and S7.

[0008] Preferably, inverters INV1-INV4 use the same structure, inverters INV5-INV6 use the same structure, the power supply voltage of inverters INV1-INV6 is provided by amplitude VS1, the low potential is connected to the ground, and the maximum output voltage amplitude range is GND-VS1.

[0009] Preferably, in the first quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK0, one end of the capacitor C2 is used to input the clock signal CLK180, the output end of the inverter INV5 is used to output the differential clock signal CLKI, and the output end of the inverter INV6 is used to output the differential clock signal CLKIN; In the second quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK90, one end of the capacitor C2 is used to input the clock signal CLK270, the output end of the inverter INV5 is used to output the differential clock signal CLKQ, and the output end of the inverter INV6 is used to output the differential clock signal CLKQN.

[0010] Preferably, the amplitude adjustment module uses LDO for amplitude adjustment, specifically including: an operational amplifier AMP1, a driving tube M1 and a feedback resistor R5; the positive input terminal of the operational amplifier AMP1 is connected to the input signal VP1, and the input signal VP1 is a voltage generated by the reference module, the negative input terminal of the operational amplifier AMP1 is connected to the feedback resistor R5 and one end of the current IBIAS1, the other end of the current IBIAS1 is grounded, and the current IBIAS1 is an adjustable current generated by the reference module, the output terminal of the operational amplifier AMP1 is connected to the gate terminal of the driving tube M1, the source terminal of the driving tube M1 is connected to the voltage VDD1, the drain terminal of the driving tube M1 is connected to the other end of the feedback resistor R5 and the amplitude VS1, the amplitude VS1 is the output voltage of the amplitude adjustment module, and serves as the power supply voltage of the quadrant selection module, and VS1=VP1+IBIAS1×R5.

[0011] Preferably, the core interpolation circuit module is a phase interpolation structure of an equal value tail current array, and the unit reference current of the tail current is an adjustable reference current I0, specifically including: The I-channel reference current part and the Q-channel reference current part have the same structure and both include M NMOS tube pairs, each of which is composed of a first NMOS tube and a second NMOS tube; the gate terminals of the first NMOS tube and the second NMOS tube are connected to the reference voltage VREF and input signals; the source terminals of the first NMOS tube and the second NMOS tube are connected and connected to the grounded reference current I0 through a control switch; the drain terminal of the first NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain terminal of the second NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1; The I-path interpolation current part and the Q-path interpolation current part have the same structure, both of which include N NMOS tube pairs, each of which is composed of a third NMOS tube and a fourth NMOS tube; the gate end of the third NMOS tube is connected to the differential clock signal and used as a differential input signal, and the gate end of the fourth NMOS tube is connected to the differential clock signal and used as a differential input signal; the source ends of the third NMOS tube and the fourth NMOS tube are connected and connected to the grounded reference current I0 through the interpolation current switch; the drain end of the third NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain end of the fourth NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1.

[0012] Preferably, the tail current selection function of the I-way reference current part is realized by controlling switches DI0~DIM, and the tail current selection function of the I-way interpolation current part is realized by interpolation current switches AI0~AIN; Similarly, the tail current selection function of the Q-path reference current part is realized by controlling the switches DQ0~DQM, and the tail current selection function of the Q-path interpolation current part is realized by the interpolation current switches AQ0~AQN.

[0013] Preferably, a control signal is provided by a digital module as an input signal of the tail current control bit module, and an output signal of the tail current control bit module is used as a control signal of control switches DI0~DIM, control switches DQ0~DQM, interpolation current switches AI0~AIN and interpolation current switches AQ0~AQN.

[0014] The present invention also provides a CDR of a high-speed SERDES interface, which adopts the phase interpolator circuit with wide bandwidth and high linearity as described above.

[0015] Compared with the prior art, the present invention has the following beneficial effects: Based on the traditional phase interpolator, the overall phase interpolator of the present invention has the characteristics of wide output clock frequency and high linearity. First, the four-phase clock generated by the PLL is roughly adjusted, and the quadrant selection module is used to achieve coarse adjustment of the output clock phase, and the amplitude adjustment module is used to achieve clock amplitude adjustment. Then, the core interpolation circuit module and the tail current adjustment module are used to achieve fine adjustment of the clock phase. Finally, the entire phase interpolator can achieve phase adjustment of 0°~360°, and the phase interpolator in the clock data recovery circuit (CDR) applied to the high-speed SERDES interface has the characteristics of wideband and high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the overall structure of the phase interpolator of the present invention.

[0017] Figure 2 It is a structural schematic diagram of the first quadrant selection unit in the quadrant selection module of the present invention.

[0018] Figure 3 It is a structural schematic diagram of the second quadrant selection unit in the quadrant selection module of the present invention.

[0019] Figure 4 It is a structural schematic diagram of the amplitude adjustment module of the present invention.

[0020] Figure 5 It is a structural schematic diagram of the I-path and Q-path interpolation current parts in the core interpolation circuit module of the present invention.

[0021] Figure 6 It is a specific structural schematic diagram of the I-channel interpolation current part in the core interpolation circuit module of the present invention.

[0022] Figure 7 It is a specific structural schematic diagram of the Q-path interpolation current part in the core interpolation circuit module of the present invention.

[0023] Figure 8 It is a specific structural schematic diagram of the I-channel reference current part in the core interpolation circuit module of the present invention.

[0024] Fig. 9 It is a specific structural schematic diagram of the Q-path reference current part in the core interpolation circuit module of the present invention.

[0025] Fig.10 It is a structural schematic diagram of the tail current control bit module of the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] like Figure 1 As shown, an embodiment of the present invention specifically provides a phase interpolator circuit with wideband and high linearity applied to a clock data recovery circuit (CDR) of a high-speed SERDES interface, including four parts: a quadrant selection module, an amplitude adjustment module, a core interpolation circuit module and a tail current control bit module.

[0028] The quadrant selection module realizes coarse adjustment of the phase of the phase interpolator output clock, and realizes the phase shift of the four quadrant intervals between 0~90°, 90~180°, 180~270° and 270~360°. The input is the four-phase clock signal CLK0, CLK90, CLK180, CLK270 with a wide range of frequencies provided by the PLL, and the output signals are CLKQ, CLKQN, CLKI, and CLKIN, wherein CLKQ and CLKQN have the same clock frequency and opposite phases, and similarly CLKI and CLKIN have the same clock frequency and opposite phases, and the differential clock signal reduces common-mode interference.

[0029] The amplitude adjustment module adjusts the output clock amplitude VS1 of the amplitude adjustment module. By adjusting the amplitude VS1, the voltage conversion rate of the output signals CLKQ, CLKQN, CLKI, and CLKIN is adjusted. A suitable voltage conversion rate can improve the linearity of the output clock of the phase interpolator.

[0030] The tail current control bit module provides phase weight selection for the core interpolation circuit, solves the nonlinearity of the output clock of the core interpolation circuit caused by the establishment time of the tail current switching during fine adjustment through an M-bit control signal, realizes fine adjustment of the output phase of the phase interpolator through an N-bit control signal, and the fine adjustment phase accuracy is 90° / N. Through the combination of M+N-bit control bit adjustment signals, the output clock of the phase interpolator is achieved to simultaneously ensure high linearity and high precision within the full range of the four-quadrant interval.

[0031] The core interpolation circuit uses a CML (Current Mode Logic) circuit to perform interpolation operations on the input orthogonal differential clock signals CLKQ, CLKQN, CLKI, and CLKIN, and adjusts the tail current through the M+N-bit control bit adjustment signal to achieve output differential clock signals CLK_OUT and CLK_OUTN. The differential clock signals CLK_OUT and CLK_OUTN output by the entire phase interpolator have the characteristics of wide frequency, high linearity, and high phase shift accuracy.

[0032] like Figure 2 and Figure 3As shown, the input signals CLK0, CLK90, CLK180, and CLK270 of the quadrant selection module are provided by PLL, and the clock frequency range provided is 1 GHz to 20 GHz. The frequency range of the output clocks CLKI, CLKIN, CLKQ, and CLKQN can also reach 1 GHz to 20 GHz. Circuit structure description: the input signal CLK0 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the switch S1, the switch S4, and one end of the resistor R1, the other end of the switch S1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the capacitor C3, one end of the switch S7 and the switch S8, and the output end of the inverter INV2, the other end of the capacitor C3 is connected to one end of the resistor R3 and the input end of the inverter INV5, the output end of the inverter INV5 is connected to the other end of the resistor R3, and the signal CLKI is output. The input signal CLK180 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the switch S2, the switch S3 and one end of the resistor R2, the other end of the switch S3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the capacitor C4, the switch S5, one end of the switch S6 and the output end of the inverter INV4, the other end of the capacitor C4 is connected to one end of the resistor R4 and the input end of the inverter INV6, the output end of the inverter INV6 is connected to the other end of the resistor R4, and the signal CLKIN is output. One end of the switch S2 is connected to the capacitor C2 and one end of the switch S3, and the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the output end of the inverter INV1, the capacitor C3, the switch S7 and one end of the switch S8. One end of switch S4 is connected to capacitor C2, one end of switch S1 and the input end of inverter INV4, and the output end of inverter INV4 is connected to the output end of inverter INV3, capacitor C4, switch S5 and one end of switch S6. One end of resistor R1 is connected to C1, and the other end is connected to switch S5 and switch S8. One end of resistor R2 is connected to capacitor C2, and the other end is connected to switch S6 and switch S7. The control signal SI provided by the digital module is used to control switches S1, S3, S6 and S8. The control signal SIN is opposite to the control signal SI. SIN is used to control switches S2, S4, S5 and S7. Inverters INV1, INV2, INV3 and INV4 use the same structure. The power supply voltage is provided by VS1, the low potential is connected to the ground terminal, and the maximum output voltage amplitude range is GND~VS1. Inverters INV5 and INV6 use the same structure. The input signal CLK90 and the input signal CLK270 can obtain the output signals CLKQ and CLKQN through the same structure. The difference in structure lies in the control signals SQ and SQN provided by the digital module. The four quadrant selection functions are realized by the control signals SI, SIN, SQ, and SQN provided by the digital module to realize the link selection from the input clock signal to the output clock signal.For example, SI and SQ simultaneously give the same low-level control signal, so that switches S1, S3, S6, and S8 are opened at the same time, and SIN and SQN correspond to the same high-level signal, so that switches S2, S4, S5, and S7 are closed at the same time, so that the clock signal CLK0 can be transmitted to the DC-isolating capacitor C1, and then to the input end of the inverter INV4 through the switch S2. After the driving capability of the signal is changed, it reaches the DC-isolating capacitor C4, and is driven and amplified by INV6 to obtain the output signal CLKIN. The closure of switch S7 realizes the resistor R1 as the feedback resistor of the inverter INV4, thereby realizing the output link from CLK0 to CLKIN. Similarly, the output links from CLK180 to CLKIN, CLK90 to CLKQN, and CKL270 to CLKQ are realized.

[0033] like Figure 4 As shown, the amplitude adjustment module uses LDO for amplitude adjustment, the input signal VP1 is the voltage generated by the reference module, VP1 is connected to the positive input terminal of the operational amplifier AMP1, the negative input terminal VN1 of the operational amplifier AMP1 is connected to one end of the resistor R5 to form feedback, the current IBIAS1 is the adjustable current generated by the reference module, connected to the resistor R5 and the negative input terminal VN1 of the operational amplifier AMP1, the gate terminal of the output driver tube M1 is connected to the output terminal of the operational amplifier, the source terminal of the output driver tube M1 is connected to the voltage VDD1, and the output voltage VS1 of the amplitude adjustment module = VP1 + IBIAS1 × R5. The output voltage VS1 is used as the power supply voltage of the quadrant selection module. Through the structure of the quadrant selection module and the amplitude adjustment module, the function of different swing capabilities of the differential output signals CLKI and CLKIN, CLKQ and CLKQN can be realized, as the input differential signal of the next-level core interpolation circuit. Ideally, the adjusted clock signals CLKI, CLKIN, CLKQ, and CLKQN are similar to triangular waves.

[0034] like Figures 5 to 9As shown, the core interpolation circuit module is a phase interpolation structure of an equivalent tail current array. The unit reference current of the tail current is I0, which is an adjustable reference current. The I-channel control switches DI0~DIM realize the tail current selection function of the I-channel reference current part, and the I-channel interpolation current switches AI0~AIN realize the tail current selection function of the I-channel interpolation current part. Similarly, the Q-channel control switches DQ0~DQM realize the tail current selection function of the Q-channel reference current part, and the Q-channel interpolation current switches AQ0~AQN realize the tail current selection function of the Q-channel interpolation current part. When the equivalent tail current structures DI0~DIM, AI0~AIN, DQ0~DQM, AQ0~AQN switches are closed or opened, the overall tail current value is the same, and the current flowing through the resistors RI and RQ is the same, ensuring the same output swing and improving the linearity of the interpolation output. The input signal of the reference current part of the I path is the reference voltage VREF, which is connected to the gate terminals of the NMOS tubes MDI00, MDI01, MDI10, MDI11…MDIM0, MDIM1. The CLKI in the interpolation current part of the I path is connected to the gate terminals of the NMOS tubes MAI00, MAI10…MAIN0, and the differential input signal CLKIN is connected to the gate terminals of the NMOS tubes MAI01, MAI11…MAIN1. Similarly, the input signal of the reference current part of the Q path is the reference voltage VREF, which is connected to the gate terminals of the NMOS tubes MDQ00, MDQ01, MDQ10, MDQ11…MDQM0, MDQM1. In the current part, CLKQ is connected to the gate terminals of NMOS tubes MAQ00, MAQ10…MAQN0, the differential input signal CLKQN is connected to the gate terminals of NMOS tubes MAQ01, MAQ11…MAQN1, the gate terminals of M+N NMOS tubes MDI00, MDI10…MDIM0 and MAI00, MAI10…MAIN0 and MDQ00, MDQ10…MDQM0 and MAQ00, MAQ10…MAQN0 are connected to one end of resistor RI, and the other end of resistor RI is connected to voltage VDD1, and similarly, M+N NMOS tubes are connected to one end of resistor RQ, and the other end of RQ is connected to voltage VDD1. By controlling the tail current through AI0~AIN and AQ0~AQM, phase adjustment with N-bit accuracy can be achieved, and fine adjustment of 90° / N steps can be achieved in the four-quadrant range of 0~360°. By coordinating the control signals of DI0~DIM, DQ0~DQM and AI0~AIN, AQ0~AQM, the phase change in the four-quadrant range of 0~360° can be made more linear, reducing clock jitter.

[0035] like Fig.10As shown, the input signal of the tail current control bit module is the control signal provided by the digital module to realize the output control signals DI0~DIM, AI0~AIN, DQ0~DQM, AQ0~AQM. The output control signals DI0~DIM are given to the I-way reference current part of the core interpolation circuit module, and the output control signals AI0~AIN are given to the I-way interpolation current part of the core interpolation circuit module. Similarly, the output control signals DQ0~DQM are given to the Q-way reference current part of the core interpolation circuit module, and the output control signals DQ0~DQM are given to the Q-way interpolation current part of the core interpolation circuit module.

[0036] In summary, when the phase interpolator of the present invention is used, the four-phase clocks CLK0, CLK90, CLK180, and CLK270 generated by the PLL are first roughly adjusted, the quadrant selection module is used to realize the selection of the four quadrants, the amplitude adjustment module is used to realize the clock amplitude adjustment, and then the core interpolation circuit module and the tail current adjustment module are used to finally realize the 0-360° adjustment of the clock CLK_OUT phase. The phase interpolator implemented in the clock data recovery circuit (CDR) applied to the high-speed SERDES interface has the characteristics of wideband, high linearity, and low jitter.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A phase interpolator circuit with wideband and high linearity, characterized in that: include: A quadrant selection module is used to coarsely adjust the phase of the phase interpolator output clock and realize the phase shift of the four quadrant intervals between 0°~90°, 90°~180°, 180°~270° and 270°~360°; the input signal of the quadrant selection module is the four-phase clock signals CLK0, CLK90, CLK180 and CLK270 with a wide range of frequencies provided by the PLL, and the output signal is the orthogonal differential clock signals CLKQ, CLKQN, CLKI and CLKIN; An amplitude adjustment module adjusts the output clock amplitude VS1 to adjust the voltage conversion rate of the differential clock signals CLKQ, CLKQN, CLKI and CLKIN, thereby improving the linearity of the output clock of the phase interpolator; The core interpolation circuit module uses a CML circuit to perform interpolation operations on the input differential clock signals CLKQ, CLKQN, CLKI and CLKIN, and adjusts the tail current through the M+N-bit control bit adjustment signal to output differential clock signals CLK_OUT and CLK_OUTN; The tail current control bit module provides phase weight selection for the core interpolation circuit module, solves the nonlinearity of the output clock of the core interpolation circuit module caused by the establishment time of the tail current switching during fine adjustment through an M-bit control signal, and realizes fine adjustment of the output phase of the phase interpolator through an N-bit control signal, and the fine adjustment phase accuracy is 90° / N.

2. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: The quadrant selection module is composed of a first quadrant selection unit and a second quadrant selection unit, wherein the first quadrant selection unit and the second quadrant selection unit both include: capacitors C1-C4, switches S1-S8, inverters INV1-INV6 and resistors R1-R4; Among them, one end of the capacitor C1 is used as the clock signal input end, the other end of the capacitor C1 is connected to the switch S1, the switch S4 and one end of the resistor R1, the other end of the switch S1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the output end of the inverter INV2 and to one end of the capacitor C3, the switch S7 and the switch S8, the other end of the capacitor C3 is connected to one end of the resistor R3 and the input end of the inverter INV5, the output end of the inverter INV5 is connected to the other end of the resistor R3 and outputs a differential clock signal; One end of the capacitor C2 serves as a clock signal input end, the other end of the capacitor C2 is connected to the switch S2, the switch S3 and one end of the resistor R2, the other end of the switch S2 is connected to the input end of the inverter INV2, the other end of the switch S3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the output end of the inverter INV4 and to one end of the capacitor C4, the switch S5 and the switch S6, the other end of the switch S4 is connected to the input end of the inverter INV4, the other end of the capacitor C4 is connected to one end of the resistor R4 and the input end of the inverter INV6, the output end of the inverter INV6 is connected to the other end of the resistor R4 and outputs a differential clock signal; The other end of the resistor R1 is connected to the other ends of the switch S5 and the switch S8 , and the other end of the resistor R2 is connected to the other ends of the switch S6 and the switch S7 .

3. A phase interpolator circuit with wideband and high linearity as claimed in claim 2, characterized in that: Also included are control signals SI, SIN, SQ and SQN provided by the digital module; In the first quadrant selection unit, the control signal SI is used to control switches S1, S3, S6 and S8, and the control signal SIN is used to control switches S2, S4, S5 and S7; In the second quadrant selection unit, the control signal SQ is used to control switches S1, S3, S6 and S8, and the control signal SQN is used to control switches S2, S4, S5 and S7.

4. A phase interpolator circuit with wideband and high linearity as claimed in claim 2, characterized in that: Inverters INV1~INV4 use the same structure, inverters INV5~INV6 use the same structure, the power supply voltage of inverters INV1~INV6 is provided by amplitude VS1, the low potential is connected to the ground, and the maximum output voltage amplitude range is GND~VS1.

5. A phase interpolator circuit with wideband and high linearity as claimed in claim 2, characterized in that: In the first quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK0, one end of the capacitor C2 is used to input the clock signal CLK180, the output end of the inverter INV5 is used to output the differential clock signal CLKI, and the output end of the inverter INV6 is used to output the differential clock signal CLKIN; In the second quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK90, one end of the capacitor C2 is used to input the clock signal CLK270, the output end of the inverter INV5 is used to output the differential clock signal CLKQ, and the output end of the inverter INV6 is used to output the differential clock signal CLKQN.

6. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: The amplitude adjustment module uses LDO for amplitude adjustment, and specifically includes: an operational amplifier AMP1, a driving tube M1 and a feedback resistor R5; the positive input terminal of the operational amplifier AMP1 is connected to the input signal VP1, and the input signal VP1 is a voltage generated by the reference module, the negative input terminal of the operational amplifier AMP1 is connected to the feedback resistor R5 and one end of the current IBIAS1, the other end of the current IBIAS1 is grounded, and the current IBIAS1 is an adjustable current generated by the reference module, the output terminal of the operational amplifier AMP1 is connected to the gate terminal of the driving tube M1, the source terminal of the driving tube M1 is connected to the voltage VDD1, the drain terminal of the driving tube M1 is connected to the other end of the feedback resistor R5 and the amplitude VS1, the amplitude VS1 is the output voltage of the amplitude adjustment module, and is used as the power supply voltage of the quadrant selection module, and VS1=VP1+IBIAS1×R5.

7. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: The core interpolation circuit module is a phase interpolation structure of an equal value tail current array, and the unit reference current of the tail current is an adjustable reference current I0, specifically including: The I-channel reference current part and the Q-channel reference current part have the same structure and both include M NMOS tube pairs, each of which is composed of a first NMOS tube and a second NMOS tube; the gate terminals of the first NMOS tube and the second NMOS tube are connected to the reference voltage VREF and input signals; the source terminals of the first NMOS tube and the second NMOS tube are connected and connected to the grounded reference current I0 through a control switch; the drain terminal of the first NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain terminal of the second NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1; The I-path interpolation current part and the Q-path interpolation current part have the same structure, both of which include N NMOS tube pairs, each of which is composed of a third NMOS tube and a fourth NMOS tube; the gate end of the third NMOS tube is connected to the differential clock signal and used as a differential input signal, and the gate end of the fourth NMOS tube is connected to the differential clock signal and used as a differential input signal; the source ends of the third NMOS tube and the fourth NMOS tube are connected and connected to the grounded reference current I0 through the interpolation current switch; the drain end of the third NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain end of the fourth NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1.

8. A phase interpolator circuit with wideband and high linearity as claimed in claim 7, characterized in that: The tail current selection function of the reference current part of the I channel is realized by controlling the switches DI0~DIM, and the tail current selection function of the interpolation current part of the I channel is realized by the interpolation current switches AI0~AIN; Similarly, the tail current selection function of the Q-path reference current part is realized by controlling the switches DQ0~DQM, and the tail current selection function of the Q-path interpolation current part is realized by the interpolation current switches AQ0~AQN.

9. A phase interpolator circuit with wideband and high linearity as claimed in claim 8, characterized in that: A control signal is provided through a digital module as an input signal of the tail current control bit module, and an output signal of the tail current control bit module is used as a control signal of control switches DI0~DIM, control switches DQ0~DQM, interpolation current switches AI0~AIN and interpolation current switches AQ0~AQN.

10. A CDR for a high-speed SERDES interface, characterized in that: A phase interpolator circuit with wide bandwidth and high linearity as described in any one of claims 1 to 9 is used.

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