Adaptive combination equalization circuit and adaptive circuit, method, device and equipment thereof

Abstract

The present invention discloses an adaptive combination equalization circuit and its adaptive circuit, method, device and equipment, which belong to the field of signal processing and are used for adaptively adjusting the parameters to be adjusted of the combination equalization circuit, solving the problems of poor signal compensation effect and large volume of the adaptive circuit. The first control voltage in the first equalization circuit is first determined by a first integration circuit, the second control voltage of the combination equalization circuit is determined by a second integration circuit, and then the difference between the second control voltage of the combination equalization circuit and the first control voltage is used as the third control voltage of the second equalization circuit, so that the control voltages corresponding to the front-stage equalization circuit and the rear-stage equalization circuit are complementary, and the compensation work for the signal to be compensated can be completed more accurately, and the adaptive control of the combination equalization circuit is realized by using a set of adaptive circuits, which reduces the volume of the adaptive circuit.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and in particular to an adaptive combined equalization circuit and an adaptive circuit, method, device and equipment thereof. Background Art

[0002] The interface link can use an equalizing circuit to improve signal quality and restore the correct signal. However, under high attenuation conditions, a single equalizing circuit is difficult to achieve the expected performance, so a combined equalizing circuit can be used to improve signal quality. In addition, since the characteristics of the transmission channel will change with factors such as temperature, voltage, and spacing, the relevant parameters of the combined equalizing circuit can be adaptively adjusted through an adaptive circuit, so that the combined equalizing circuit can adapt to the changes in the characteristics of the transmission channel and compensate for the signal more accurately. However, the related technology lacks a mature adaptive circuit, which leads to problems such as poor signal compensation effect and large size of the adaptive circuit.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] The purpose of the present invention is to provide an adaptive combined equalizing circuit and its adaptive circuit, method, device and equipment, wherein a first control voltage in a first equalizing circuit (one of a front-stage equalizing circuit and a rear-stage equalizing circuit) is first determined by a first integrating circuit, a second control voltage of the combined equalizing circuit is determined by a second integrating circuit, and then a difference between the second control voltage of the combined equalizing circuit and the first control voltage is used as a third control voltage of a second equalizing circuit (the other of the front-stage equalizing circuit and the rear-stage equalizing circuit), so that the control voltages corresponding to the front-stage equalizing circuit and the rear-stage equalizing circuit are complementary, and the compensation work for the signal to be compensated can be completed more accurately, and adaptive control of the combined equalizing circuit is realized by using a set of adaptive circuits, thereby reducing the volume of the adaptive circuit.

[0005] In order to solve the above technical problems, the present invention provides an adaptive circuit, comprising:

[0006] a first integrating circuit whose output terminal is connected to the control terminal of the first equalizing circuit, and is used to determine a first control voltage of the first equalizing circuit, wherein the control voltage refers to an integrated voltage of a product of a signal difference value of the equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference value refers to a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to a pre-stage equalizing circuit or a post-stage equalizing circuit in the combined equalizing circuit;

[0007] A second integrating circuit, used for determining a second control voltage of the combined equalizing circuit;

[0008] a subtraction circuit whose output terminal is connected to the control terminal of the second balancing circuit, and is used for subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to the control voltage of the second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0009] The first control voltage is used to adjust the parameter to be adjusted of the first equalizing circuit, and the third control voltage is used to adjust the parameter to be adjusted of the second equalizing circuit.

[0010] On the other hand, the first equalizing circuit includes a rear-stage equalizing circuit in the combined equalizing circuit, and the second equalizing circuit includes a front-stage equalizing circuit in the combined equalizing circuit.

[0011] On the other hand, the first integration circuit includes a first subtractor, a first multiplier and a first integrator;

[0012] The input end of the first subtractor is connected to the input end and the output end of the first equalizer circuit respectively, the input end of the first multiplier is connected to the output end of the first subtractor and the output end of the first equalizer circuit respectively, the output end of the first multiplier is connected to the input end of the first integrator, and the output end of the first integrator serves as the output end of the first integrator circuit.

[0013] On the other hand, the second integration circuit includes a second subtractor, a second multiplier and a second integrator;

[0014] The segments of the second subtractor are respectively connected to the input and output of the combined equalization circuit, the input of the second multiplier is respectively connected to the output of the second subtractor and the output of the combined equalization circuit, the output of the second multiplier is connected to the input of the second integrator, and the output of the second integrator serves as the output of the second integration circuit.

[0015] In another aspect, the subtraction circuit includes a third subtractor;

[0016] The input end of the third subtractor is connected to the output end of the first integration circuit and the output end of the second integration circuit respectively.

[0017] On the other hand, the parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels;

[0018] The adaptive circuit further comprises:

[0019] a proportional reduction circuit, used for reducing the first control voltage according to a reduction ratio corresponding to a postscript of a target level, to obtain a sub-control voltage of the postscript of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of postscript levels, and the reduction ratio corresponding to the postscript of the target level refers to: a voltage ratio between a main mark in an input signal of the combined equalizing circuit and the postscript of the target level, the main mark refers to: a main mark at an amplitude point of the input signal of the combined equalizing circuit, and the postscript refers to: a subsequent mark after the amplitude point of the input signal of the combined equalizing circuit;

[0020] The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

[0021] On the other hand, the proportional reduction circuit includes N levels of voltage dividing resistors;

[0022] The voltage-dividing resistors of the 1st to Nth levels are connected end to end in order of levels, the second end of the voltage-dividing resistor of the previous level is connected to the first end of the voltage-dividing resistor of the next level, the first end of the voltage-dividing resistor of the 1st level is connected to the output end of the first integration circuit, the voltage-dividing resistor of the Nth level is grounded, and the first end of the voltage-dividing resistor of the Lth level serves as the output end of the post-label sub-control voltage of the Lth level, L∈[2,N].

[0023] To solve the above technical problems, the present invention further provides an adaptive combined equalization circuit, comprising a pre-stage equalization circuit and a post-stage equalization circuit, and also comprising an adaptive circuit as described above, which is respectively connected to the pre-stage equalization circuit and the post-stage equalization circuit;

[0024] A pre-stage equalization circuit, used for performing a first-stage compensation on a signal to be compensated received through an information channel;

[0025] The post-stage equalization circuit is used to perform second-stage compensation on the signal to be compensated after the first-stage compensation.

[0026] On the other hand, the post-stage equalization circuit includes an external power supply, a resistance circuit, a main mark control voltage source, and a signal processing circuit corresponding to the main mark and each post-mark;

[0027] The output end of the external power supply is connected to the first end of the resistance circuit, the second end of the resistance circuit is respectively connected to the first end of each signal processing circuit, the second end of each signal processing circuit is respectively grounded, the control end of the main mark signal processing circuit is connected to the main mark control voltage source, the control end of the first stage post-mark signal processing circuit is connected to the output end of the first integration circuit, the control ends of the second to N stage post-mark signal processing circuits are respectively connected to the output ends of the corresponding sub-control voltages in the proportional reduction circuit, and the input end of each signal processing circuit is used to receive the to-be-adjusted signal corresponding to the main mark or post-mark to which it belongs;

[0028] The first terminals of the signal processing circuits serve together as the output terminals of the subsequent equalization circuit.

[0029] On the other hand, the signal processing circuit includes a first controllable switch, a second controllable switch and a third controllable switch;

[0030] The drain of the first controllable switch and the drain of the second controllable switch serve together as a first end of a signal processing circuit, the gate of the first controllable switch and the gate of the second controllable switch serve as an input end of the signal processing circuit, the source of the first controllable switch and the source of the second controllable switch are connected to the drain of a third controllable switch, the source of the third controllable switch serves as a second end of the signal processing circuit, and the gate of the third controllable switch serves as a control end of the signal processing circuit;

[0031] The first controllable switch, the second controllable switch and the third controllable switch are all N-type metal oxide semiconductor field effect transistors.

[0032] On the other hand, the pre-stage equalization circuit includes a continuous time linear equalization circuit;

[0033] The continuous time linear equalization circuit includes an external power supply, a load circuit, an on-off control circuit, a source negative feedback circuit and a current control circuit;

[0034] The external power supply is connected to the first end of the load circuit, the second end of the load circuit is connected to the first end of the on-off control circuit and together serves as the output end of the continuous-time linear equalization circuit, the second end of the on-off control circuit is respectively connected to the first end of the source negative feedback circuit and the current control circuit, the second end of the current control circuit is grounded, and the control end of the source negative feedback circuit is connected to the output end of the third control voltage of the adaptive circuit.

[0035] On the other hand, the source negative feedback circuit includes a fourth controllable switch, a fifth controllable switch and a sixth controllable switch;

[0036] The source of the fourth controllable switch is connected to the drain and source of the fifth controllable switch respectively, the drain of the fourth controllable switch is connected to the drain and source of the sixth controllable switch respectively, and the control terminals of the fourth to sixth controllable switches serve together as the control terminals of the source negative feedback circuit;

[0037] Among them, the fourth to sixth controllable switches are all N-type metal oxide semiconductor field effect transistors.

[0038] On the other hand, the load circuit includes a seventh controllable switch, an eighth controllable switch, a first load capacitor and a second load capacitor;

[0039] The source of the seventh controllable switch and the source of the eighth controllable switch serve together as the first end of the load circuit, the gate of the seventh controllable switch and the gate of the eighth controllable switch are both connected to the output end of the third control voltage of the adaptive circuit, the drain of the seventh controllable switch is connected to the first end of the first load capacitor, the drain of the eighth controllable switch is connected to the first end of the second load capacitor, the first end of the first load capacitor and the first end of the second load capacitor serve together as the second end of the load circuit, the second end of the first load capacitor is grounded, and the second end of the second load capacitor is grounded;

[0040] Wherein, the seventh controllable switch and the eighth controllable switch are both P-type metal oxide semiconductor field effect transistors.

[0041] In order to solve the above technical problems, the present invention also provides an adaptive method, comprising:

[0042] Determine a first control voltage of the first equalizing circuit, wherein the control voltage refers to: an integrated voltage of a product of a signal difference value of the equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference value refers to: a difference voltage between an output signal and an input signal of the equalizing circuit to which the control voltage belongs, and the first equalizing circuit refers to: a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit;

[0043] determining a second control voltage of the combined equalization circuit;

[0044] Subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0045] The first control voltage and the third control voltage are respectively sent to the corresponding equalizing circuits, so that the parameter to be adjusted of the first equalizing circuit is adjusted by the first control voltage, and the parameter to be adjusted of the second equalizing circuit is adjusted by the third control voltage.

[0046] On the other hand, the parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels;

[0047] After determining the first control voltage of the first equalizing circuit, the adaptive method further includes:

[0048] The first control voltage is reduced according to the reduction ratio corresponding to the postscript of the target level to obtain a sub-control voltage of the postscript of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of postscript levels, and the reduction ratio corresponding to the postscript of the target level refers to: a voltage ratio between a main mark in the input signal of the combined equalizing circuit and the postscript of the target level, the main mark refers to: a main mark located at an amplitude point of the input signal of the combined equalizing circuit, and the postscript refers to: a subsequent mark located after the amplitude point of the input signal of the combined equalizing circuit;

[0049] The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

[0050] On the other hand, the adaptive method further comprises:

[0051] Determine whether the duration of a signal difference of a target equalizing circuit in the combined equalizing circuit is greater than a preset threshold value exceeds a preset duration, wherein the target equalizing circuit refers to any one of the pre-stage equalizing circuit and the post-stage equalizing circuit;

[0052] If exceeded, the control indicator will indicate an abnormality.

[0053] In order to solve the above technical problems, the present invention further provides an adaptive device, comprising:

[0054] A first determination module is used to determine a first control voltage of a first equalizing circuit, wherein the control voltage refers to: an integrated voltage of a product of a signal difference of an equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference refers to: a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to: a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit;

[0055] A second determining module, used to determine a second control voltage of the combined equalizing circuit;

[0056] A first subtraction module, configured to subtract the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0057] The first sending module is used to send the first control voltage and the third control voltage to the corresponding equalizing circuits respectively, so as to adjust the parameters to be adjusted of the first equalizing circuit by the first control voltage and adjust the parameters to be adjusted of the second equalizing circuit by the third control voltage.

[0058] In order to solve the above technical problems, the present invention further provides an adaptive device, comprising:

[0059] Memory for storing computer programs;

[0060] A processor is used to implement the steps of the above-mentioned adaptive method when executing the computer program.

[0061] In order to solve the above technical problem, the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned adaptive method when executed by a processor.

[0062] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned adaptive method are implemented.

[0063] Technical effect: The present invention provides an adaptive circuit. Considering that the front-stage and rear-stage equalizing circuits in the combined equalizing circuit cooperate to complete the compensation for the signal to be compensated, the present invention can first determine the first control voltage in the first equalizing circuit (one of the front-stage equalizing circuit and the rear-stage equalizing circuit) through a first integration circuit, determine the second control voltage of the combined equalizing circuit through a second integration circuit, and then use the difference between the second control voltage and the first control voltage of the combined equalizing circuit as the third control voltage of the second equalizing circuit (the other of the front-stage equalizing circuit and the rear-stage equalizing circuit), so that the control voltages corresponding to the front-stage equalizing circuit and the rear-stage equalizing circuit are complementary, and the compensation work for the signal to be compensated can be completed more accurately, and the adaptive control of the combined equalizing circuit is realized by using a set of adaptive circuits, thereby reducing the size of the adaptive circuit.

[0064] The present invention also provides an adaptive combined equalization circuit, an adaptive method, an apparatus, a device, a computer program product and a computer-readable storage medium, which have the same beneficial effects as the above adaptive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0066] Figure 1 A schematic diagram of the structure of an adaptive circuit provided by the present invention;

[0067] Figure 2 A connection relationship diagram between an adaptive circuit and a combined equalization circuit provided by the present invention;

[0068] Figure 3 A schematic diagram of the structure of another adaptive circuit provided by the present invention;

[0069] Figure 4 A schematic diagram of the structure of a multiplier-accumulator provided by the present invention;

[0070] Figure 5 A schematic diagram of the structure of a pre-stage equalization circuit provided by the present invention;

[0071] Figure 6 A schematic diagram of the frequency response characteristics of a CTLE provided by the present invention;

[0072] Figure 7 A schematic diagram of a flow chart of an adaptive method provided by the present invention;

[0073] Figure 8 A schematic diagram of the structure of an adaptive device provided by the present invention;

[0074] Fig. 9 A schematic diagram of the structure of an adaptive device provided by the present invention;

[0075] Fig.10 A schematic diagram of the structure of a computer-readable storage medium provided by the present invention. DETAILED DESCRIPTION

[0076] The core of the present invention is to provide an adaptive combined equalizing circuit and its adaptive circuit, method, device and equipment. The first control voltage in the first equalizing circuit (one of the front-stage equalizing circuit and the rear-stage equalizing circuit) is first determined by a first integrating circuit, and the second control voltage of the combined equalizing circuit is determined by a second integrating circuit. Then, the difference between the second control voltage of the combined equalizing circuit and the first control voltage is used as the third control voltage of the second equalizing circuit (the other of the front-stage equalizing circuit and the rear-stage equalizing circuit). The control voltages corresponding to the front-stage equalizing circuit and the rear-stage equalizing circuit are complementary, and the compensation work for the signal to be compensated can be completed more accurately. In addition, the adaptive control of the combined equalizing circuit is realized by using a set of adaptive circuits, and the volume of the adaptive circuit is reduced.

[0077] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0078] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of an adaptive circuit provided by the present invention, the adaptive circuit comprising:

[0079] A first integrating circuit 1 whose output terminal is connected to the control terminal of the first equalizing circuit is used to determine a first control voltage of the first equalizing circuit, wherein the control voltage refers to an integrated voltage of a product of a signal difference of the equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, and a signal difference refers to a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit;

[0080] A second integrating circuit 2, used for determining a second control voltage of the combined equalizing circuit;

[0081] A subtraction circuit 3 whose output terminal is connected to the control terminal of the second balancing circuit, and is used for subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to the control voltage of the second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0082] The first control voltage is used to adjust the parameter to be adjusted of the first equalizing circuit, and the third control voltage is used to adjust the parameter to be adjusted of the second equalizing circuit.

[0083] Specifically, the combined equalization circuit generally includes a pre-stage equalization circuit and a post-stage equalization circuit.

[0084] Specifically, considering the technical problems in the above background technology, and considering that the front-stage and rear-stage equalizing circuits in the combined equalizing circuit themselves are collaboratively used to complete the compensation for the signal to be compensated, the control voltages of the parameters to be adjusted of the front-stage equalizing circuit and the rear-stage equalizing circuit should be complementary in theory, and the increase of one will lead to the decrease of the other. Therefore, the adaptive circuit in the embodiment of the present invention is intended to provide an adaptive circuit that makes the "control voltage of the parameter to be adjusted of the front-stage equalizing circuit" and the "control voltage of the parameter to be adjusted of the rear-stage equalizing circuit" influence each other and are complementary. Therefore, the first integration circuit 1 in the embodiment of the present invention can determine the first control voltage of the first equalizing circuit (one of the front-stage and rear-stage equalizing circuits), and determine the second control voltage of the entire combined equalizing circuit through the second integration circuit 2. Finally, the third control voltage belonging to the second equalizing circuit (the other of the front-stage and rear-stage equalizing circuits) can be obtained by subtracting the first control voltage from the second control voltage, so that the parameter to be adjusted of the first equalizing circuit can be adjusted through the first control voltage, and the parameter to be adjusted of the second equalizing circuit can be adjusted through the third control voltage.

[0085] Specifically, from the definition of the control voltage (the integral voltage of the product of the signal difference of the balancing circuit to which the control voltage belongs and the output signal of the balancing circuit to which the control voltage belongs, and the signal difference refers to the difference voltage between the output signal and the input signal of the balancing circuit to which the control voltage belongs), it can be seen that the control voltage refers to the integral voltage of the product of "the difference voltage between the output signal and the input signal of the balancing circuit to which the control voltage belongs" and "the output signal of the balancing circuit to which the control voltage belongs", and the control voltage is related to both the output signal and the input signal of the balancing circuit to which the control voltage belongs, which is beneficial to improving the compensation effect.

[0086] Among them, since the first control voltage in the embodiment of the present invention is obtained by calculating "the output signal and the input signal of the first balancing circuit", and the third control voltage is obtained by subtracting the first control voltage from the second control voltage, the sum of the third control voltage and the first control voltage is the "second control voltage of the entire balancing circuit", that is, the first control voltage and the third control voltage restrain and complement each other, and when one side increases, the other side will decrease, thereby jointly ensuring the compensation effect of the signal to be compensated at the input end of the combined balancing circuit.

[0087] In addition, in the embodiment of the present invention, each equalizing circuit is not provided with its own adaptive circuit, but a single adaptive circuit can realize adaptive adjustment of the parameters to be adjusted of the front-stage and rear-stage equalizing circuits, which is beneficial to reducing the volume and energy consumption of the adaptive circuit of the combined equalizing circuit.

[0088] Among them, Figure 1 In, V in It is the signal to be compensated which is transmitted through the channel to the input end of the combined equalization circuit. m V is compensated by the pre-stage equalization circuit in , V d is V after compensation by the post-stage equalization circuit m .

[0089] To better illustrate the embodiments of the present invention, please refer to Figure 2 , Figure 2 A connection relationship diagram between an adaptive circuit and a combined equalizing circuit provided by the present invention. Since the first integrating circuit 1 and the second integrating circuit 2 of the adaptive circuit require the input signal and the output signal of the combined equalizing circuit, and also require the output signal of the preceding equalizing circuit, the adaptive circuit can be respectively connected to the input end and the output end of the preceding equalizing circuit, and also to the output end of the succeeding equalizing circuit. The adaptive circuit is also intentionally connected to the preceding equalizing circuit and the succeeding equalizing circuit respectively, so as to provide control voltages therefor.

[0090] The present invention provides an adaptive circuit. Considering that the front-stage and rear-stage equalizing circuits in the combined equalizing circuit cooperate to complete the compensation of the signal to be compensated, the present invention can first determine the first control voltage in the first equalizing circuit (one of the front-stage equalizing circuit and the rear-stage equalizing circuit) through a first integration circuit, determine the second control voltage of the combined equalizing circuit through a second integration circuit, and then use the difference between the second control voltage of the combined equalizing circuit and the first control voltage as the third control voltage of the second equalizing circuit (the other of the front-stage equalizing circuit and the rear-stage equalizing circuit), so that the control voltages corresponding to the front-stage equalizing circuit and the rear-stage equalizing circuit complement each other, and can more accurately complete the compensation work for the signal to be compensated, and use a set of adaptive circuits to realize adaptive control of the combined equalizing circuit, thereby reducing the volume of the adaptive circuit.

[0091] Based on the above embodiments:

[0092] As an optional embodiment, the first equalizing circuit includes a post-stage equalizing circuit in the combined equalizing circuit, and the second equalizing circuit includes a pre-stage equalizing circuit in the combined equalizing circuit.

[0093] Specifically, considering that the output signal of the subsequent equalizing circuit is better compensated, the control voltage of the subsequent equalizing circuit is used as a reference, that is, the control voltage of the subsequent equalizing circuit is subtracted from the second control voltage to obtain the third control voltage, which is beneficial to improving the adjustment effect of the entire adaptive circuit on the combined equalizing circuit. Therefore, the first equalizing circuit in the embodiment of the present invention includes the subsequent equalizing circuit in the combined equalizing circuit, and the second equalizing circuit includes the previous equalizing circuit in the combined equalizing circuit.

[0094] Of course, the first equalizing circuit may also be a pre-equalizing circuit, which is not limited in the embodiment of the present invention.

[0095] As an optional embodiment, the first integration circuit 1 includes a first subtractor, a first multiplier and a first integrator;

[0096] The input end of the first subtractor is connected to the input end and the output end of the first equalizer circuit respectively, the input end of the first multiplier is connected to the output end of the first subtractor and the output end of the first equalizer circuit respectively, the output end of the first multiplier is connected to the input end of the first integrator, and the output end of the first integrator serves as the output end of the first integration circuit 1.

[0097] To better illustrate the embodiments of the present invention, please refer to Figure 3 , Figure 3 A schematic diagram of another adaptive circuit provided by the present invention is shown in FIG. Figure 3 The application premise is that the first equalization circuit is a post-equalization circuit, so Vd Subtract V m Get V dfe_e , and then through the first multiplier (CF1) to V dfe_e With V d The first control voltage V is obtained by multiplying the multiplier output by the first integrator. b1 , while in the upper row of links, V is first subtracted by the second subtractor (i.e. JF2). d Subtract V in Get V total_e , and then through the second multiplier (CF2) to V total_e With V d The second control voltage V is obtained by integrating the output of the second multiplier through the second integrator. total Finally, the third subtractor (ie JF3) is used to convert V total Subtract V b1 Then the third control voltage V c1 .

[0098] Specifically, the first integration circuit 1 in the embodiment of the present invention has the advantages of simple structure, small size and low cost.

[0099] Of course, in addition to this specific architecture, the first integration circuit 1 may also be in other forms, which is not limited in the embodiment of the present invention.

[0100] As an optional embodiment, the second integration circuit 2 includes a second subtractor, a second multiplier and a second integrator;

[0101] The segments of the second subtractor are respectively connected to the input and output of the combined equalizer circuit, the input of the second multiplier is respectively connected to the output of the second subtractor and the output of the combined equalizer circuit, the output of the second multiplier is connected to the input of the second integrator, and the output of the second integrator serves as the output of the second integrator circuit 2.

[0102] Specifically, the second integration circuit 2 in the embodiment of the present invention has the advantages of simple structure, small size and low cost.

[0103] Of course, in addition to this specific architecture, the second integration circuit 2 may also be in other forms, which is not limited in the embodiment of the present invention.

[0104] As an optional embodiment, the subtraction circuit 3 includes a third subtractor;

[0105] The input end of the third subtractor is connected to the output end of the first integration circuit 1 and the output end of the second integration circuit 2 respectively.

[0106] Specifically, the subtraction circuit 3 in the embodiment of the present invention has the advantages of simple structure, small size and low cost.

[0107] Of course, in addition to this specific form, the subtraction circuit 3 may also be in other forms, which is not limited in the embodiment of the present invention.

[0108] As an optional embodiment, the parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels;

[0109] The adaptive circuit also includes:

[0110] A proportional reduction circuit is used to reduce the first control voltage according to the reduction ratio corresponding to the post-mark of the target level to obtain a sub-control voltage of the post-mark of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of post-mark levels, and the reduction ratio corresponding to the post-mark of the target level refers to: a voltage ratio between a main mark in the input signal of the combined equalization circuit and the post-mark of the target level, the main mark refers to: a main mark located at an amplitude point of the input signal of the combined equalization circuit, and the post-mark refers to: a subsequent mark located after the amplitude point of the input signal of the combined equalization circuit;

[0111] The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

[0112] Specifically, considering that many post-stage equalization circuits are specifically used to process the signal tailing generated by the signal to be compensated after channel transmission, the processing of the signal tailing usually starts from the signal peak and makes a mark every preset period, thereby making multiple marks. The first mark located at the signal peak is usually called the main mark (main mark), and the subsequent marks starting from the second one are called post-marks. The post-marks after the main mark are successively called the first-level post-mark, the second-level post-mark...the N-th-level post-mark.

[0113] Among them, in an equalizing circuit with a tap coefficient as a parameter to be adjusted, the tap coefficient of the first-level post-marker can be adjusted by a first control voltage, and in order to adjust the tap coefficients of the 2nd to Nth level post-markers in the equalizing circuit, it is necessary to provide a control voltage for the taps of the 2nd to Nth level post-markers so as to adjust the tap coefficients of the 2nd to Nth level post-markers, and considering that in the signal to be compensated, there is a voltage proportional relationship between the main mark and the post-marks of each level, and the proportional relationship is consistent with the proportional relationship between the corresponding tap coefficients (theoretical values), therefore, the proportional reduction circuit in the embodiment of the present invention can reduce the first control voltage according to the reduction ratio corresponding to the post-marker of the target level, and obtain the sub-control voltage of the post-marker of the target level, so that the control voltage of the tap coefficient of each level of the post-marker can be obtained efficiently and accurately.

[0114] As an optional embodiment, the proportional reduction circuit includes N levels of voltage dividing resistors;

[0115] The voltage-dividing resistors of the 1st to Nth levels are connected end to end in order of level, the second end of the voltage-dividing resistor of the previous level is connected to the first end of the voltage-dividing resistor of the next level, the first end of the voltage-dividing resistor of the 1st level is connected to the output end of the first integration circuit 1, the voltage-dividing resistor of the Nth level is grounded, and the first end of the voltage-dividing resistor of the Lth level serves as the output end of the post-label sub-control voltage of the Lth level, L∈[2,N].

[0116] Specifically, the voltage divider resistor has the advantages of simple structure, small size and low cost.

[0117] Of course, in addition to this specific form, the scale-down circuit may also be of other types, which is not limited in the embodiment of the present invention.

[0118] The present invention also provides an adaptive combined equalization circuit, comprising a pre-stage equalization circuit and a post-stage equalization circuit, and also comprising an adaptive circuit as in the above-mentioned embodiment, which is respectively connected to the pre-stage equalization circuit and the post-stage equalization circuit;

[0119] A pre-stage equalization circuit, used for performing a first-stage compensation on a signal to be compensated received through an information channel;

[0120] The post-stage equalization circuit is used to perform second-stage compensation on the signal to be compensated after the first-stage compensation.

[0121] Specifically, the adaptive circuit and the combined equalization circuit are connected together to form an adaptive combined equalization circuit. For the introduction of the adaptive combined equalization circuit in the embodiment of the present invention, please refer to the aforementioned embodiment of the adaptive circuit, and the embodiment of the present invention will not be repeated here.

[0122] As an optional embodiment, the post-stage equalization circuit includes an external power supply, a resistance circuit, a main mark control voltage source, and a signal processing circuit corresponding to the main mark and each post-mark;

[0123] The output end of the external power supply is connected to the first end of the resistance circuit, the second end of the resistance circuit is respectively connected to the first end of each signal processing circuit, the second end of each signal processing circuit is respectively grounded, the control end of the signal processing circuit of the main mark is connected to the main mark control voltage source, the control end of the signal processing circuit of the first stage post mark is connected to the output end of the first integration circuit 1, the control ends of the signal processing circuits of the second to N stages post mark are respectively connected to the output ends of the corresponding sub-control voltages in the proportional reduction circuit, and the input end of each signal processing circuit is used to receive the to-be-adjusted signal corresponding to the main mark or post mark to which it belongs;

[0124] The first terminals of the signal processing circuits serve together as the output terminals of the subsequent equalization circuit.

[0125] Specifically, the post-stage equalization circuit in the embodiment of the present invention has a simple structure and can adjust the tap coefficients of the post-mark taps of each stage in the form of an adding circuit.

[0126] Of course, in addition to this specific structure, the post-stage equalization circuit can also be in other specific forms, which is not limited in the embodiment of the present invention.

[0127] The circuit in the embodiment of the present invention is actually a circuit related to tap coefficient control in a DFE (Decision Feedback Equalizer).

[0128] As an optional embodiment, the signal processing circuit includes a first controllable switch, a second controllable switch and a third controllable switch;

[0129] The drain of the first controllable switch and the drain of the second controllable switch serve together as the first end of the signal processing circuit, the gate of the first controllable switch and the gate of the second controllable switch serve as the input end of the signal processing circuit, the source of the first controllable switch and the source of the second controllable switch are connected to the drain of the third controllable switch, the source of the third controllable switch serves as the second end of the signal processing circuit, and the gate of the third controllable switch serves as the control end of the signal processing circuit;

[0130] The first controllable switch, the second controllable switch and the third controllable switch are all N-type metal oxide semiconductor field effect transistors.

[0131] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figure 4 , Figure 4 This is a structural schematic diagram of a multiplier-accumulator provided by the present invention, VDD is an external power supply, two resistors R constitute a resistor circuit, and the three columns below are respectively a signal processing circuit corresponding to the main mark, a signal processing circuit corresponding to the first-level post-mark, and a signal processing circuit corresponding to the second-level post-mark. Each signal processing circuit is composed of three thyristors, with a simple structure and low cost.

[0132] in, Figure 4 V b is the main control voltage output by the main control voltage source, V b2 is the control voltage after the second stage, V m_p and V m_n The input signal V m The forward and reverse signals, V 1_p and V 1_n are the positive and negative signals of the input signal V1, V 2_p and V 2_n are the positive and negative signals of the input signal V2 respectively. mis the input signal of the equalizer DFE, V1 is the output signal of the first-stage shaping circuit after the decision device of the equalizer DFE, and V2 is the output signal of the second-stage shaping circuit after the decision device. , V on With V op As an input signal of the decision maker in the DFE, the structure of the DFE equalization circuit may include a multiplier-accumulator, a decision maker, and a two-stage shaping circuit.

[0133] Specifically, Figure 4 The signal processing circuit corresponding to the main mark in the b The tap coefficient of the main control is "V m Multiply to get a product, the first level of the corresponding signal processing circuit can be "V b1 The tap coefficient of the first stage post-control is multiplied by V1 to obtain a product, and the signal processing circuit corresponding to the second stage post-control can be "controlled by V b2 The tap coefficient of the second stage of control is multiplied by V2, and then the three products are superimposed through two resistors R, so as to achieve the input signal V m partial compensation.

[0134] As an optional embodiment, the pre-stage equalization circuit includes a continuous time linear equalization circuit;

[0135] The continuous time linear equalization circuit includes an external power supply, a load circuit, an on-off control circuit, a source negative feedback circuit and a current control circuit;

[0136] An external power supply is connected to a first end of a load circuit, a second end of the load circuit is connected to a first end of an on-off control circuit and together serve as an output end of a continuous-time linear equalization circuit, a second end of the on-off control circuit is respectively connected to a first end of a source negative feedback circuit and a current control circuit, a second end of the current control circuit is grounded, and a control end of the source negative feedback circuit is connected to an output end of a third control voltage of the adaptive circuit.

[0137] Specifically, the continuous time linear equalization circuit is CTLE (Continuous Time Linear Equalization). CTLE can compensate for the high-frequency attenuation of the channel, improve the performance of the eye diagram at the receiving end, and increase the bandwidth of the signal. The continuous time linear equalization circuit in the embodiment of the present invention has the advantages of simple structure and low cost.

[0138] Of course, in addition to CTLE, the pre-stage equalization circuit may also be of other types, which is not limited in the embodiment of the present invention.

[0139] As an optional embodiment, the source negative feedback circuit includes a fourth controllable switch, a fifth controllable switch and a sixth controllable switch;

[0140] The source of the fourth controllable switch is connected to the drain and source of the fifth controllable switch respectively, the drain of the fourth controllable switch is connected to the drain and source of the sixth controllable switch respectively, and the control terminals of the fourth to sixth controllable switches serve together as the control terminals of the source negative feedback circuit;

[0141] Among them, the fourth to sixth controllable switches are all N-type metal oxide semiconductor field effect transistors.

[0142] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figure 5 , Figure 5 The schematic diagram of the structure of a pre-stage equalization circuit provided by the present invention is a CTLE equalization circuit, the external power supply is VDD, and the load circuit includes two resistors R L And two capacitors C L The on-off control circuit includes a first transistor M1 and a second transistor M2, and the current control circuit includes a third transistor M3 and a fourth transistor M4, wherein M1 to M4 are all N-type MOS (Metal-Oxide-SemiconductorField-Effect Transistor) tubes.

[0143] Specifically, the source negative feedback circuit can be composed of fourth to sixth controllable switches, and the fourth controllable switch is Figure 5 R S , the fifth controllable switch is Figure 5 C S , the sixth controllable switch is also Figure 5 C S The capacitance and resistance of the source negative feedback circuit can be adjusted by the third control voltage, and the fourth controllable switch can work in the linear region to obtain a variable resistance. C1 When controlling the source negative feedback circuit, the gate-source voltage V gs The larger the value, the smaller the on-resistance. When there is no bias, the MOS tube in the source negative feedback circuit is in the on state. As an active device, the source negative feedback circuit in the embodiment of the present invention can not only be controlled by the third control voltage, that is, adapt to the change of the third control voltage to change the resistance and capacitance, which is beneficial to improving the compensation accuracy of CTLE, but also helps to make the source negative feedback circuit more miniaturized.

[0144] Of course, in addition to this specific structure, the source negative feedback circuit can also be in other forms, which is not limited in the embodiment of the present invention.

[0145] As an optional embodiment, the load circuit includes a seventh controllable switch, an eighth controllable switch, a first load capacitor and a second load capacitor;

[0146] The source of the seventh controllable switch and the source of the eighth controllable switch serve together as the first end of the load circuit, the gate of the seventh controllable switch and the gate of the eighth controllable switch are both connected to the output end of the third control voltage of the adaptive circuit, the drain of the seventh controllable switch is connected to the first end of the first load capacitor, the drain of the eighth controllable switch is connected to the first end of the second load capacitor, the first end of the first load capacitor and the first end of the second load capacitor serve together as the second end of the load circuit, the second end of the first load capacitor is grounded, and the second end of the second load capacitor is grounded;

[0147] Wherein, the seventh controllable switch and the eighth controllable switch are both P-type metal oxide semiconductor field effect transistors.

[0148] Specifically, the resistor R in the load circuit of the CTLE balancing circuit in the embodiment of the present invention is L It can be composed of a P-channel MOS tube, and the PMOS in the load circuit can be controlled by a third control voltage to change the resistance value, which can further improve the compensation accuracy of the CTLE.

[0149] Of course, in addition to this specific structure, the CTLE equalization circuit may also be in other forms, which is not limited in the embodiment of the present invention.

[0150] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figure 6 , Figure 6 This is a schematic diagram of the frequency response characteristics of a CTLE provided by the present invention. The CTLE equalizer can provide a zero point before all poles, which is equivalent to a high-pass filter. The CTLE equalization circuit can amplify the high-frequency gain of the signal to compensate for the attenuation of the channel. Its transfer function is:

[0151] ;

[0152] Where H(s) is the transfer function of the CTLE equalizer circuit, s is the complex variable in the Laplace transform, and g m is the transconductance (the inverse of the resistance) of the MOS transistors M1 and M2. From the transfer function, we can see that the circuit contains a zero point w z , two extreme points w p1 With w p2 , the low-frequency gain of the CTLE equalizer circuit is A1, and the peak gain is A2, where:

[0153] ;

[0154] ;

[0155] ;

[0156] ;

[0157] ;

[0158] Specifically, from the above formula, we know that the gain (low-frequency gain and peak gain), zero point and pole of the CTLE equalizer circuit are related to the resistor R L , source negative feedback capacitor CS and resistor R S In this regard, the embodiments of the present invention utilize an adaptive circuit to achieve adaptive changes in resistance and capacitance (in the source negative feedback circuit and the load circuit).

[0159] Specifically, when the difference of CTLE (that is, the difference voltage of the output signal of the CTLE equalization circuit minus the input signal) is large, it means that the compensation effect of CTLE is poor. The compensation effect can be improved by changing the compensation gain, that is, increasing (peak gain) A2 and reducing (low-frequency gain) A1. The increase of A2 can be achieved by increasing the load resistor R L According to the on-resistance of the PMOS tube, when the difference voltage is positive, V c1 Increase, load resistance R L |V gs | decreases, the on-resistance increases, that is, the load resistance R L increases; on the contrary, the load resistance R L When the CTLE gain changes, the zero and pole will also change, such as Figure 6 As shown. c1 Control source negative feedback circuit and load circuit, and when the difference is positive, V c1 Increase, source-drain voltage V gs The larger the on-resistance, the smaller the on-resistance, that is, R S decreases, then the zero point and the first pole w p1 Increases and moves to the right. The source-drain voltage of the P-channel MOS tube |V gs | decreases, the on-resistance increases, that is, the load resistance R L increases, the second pole w p2 To decrease, move to the left.

[0160] Among them, Figure 6 In the figure, the dotted line is the frequency response characteristic curve of the CTLE equalizer circuit before the compensation gain, and the solid line is the frequency response characteristic curve of the CTLE equalizer circuit after the compensation gain. Correspondingly, A'2 is the peak gain after the compensation gain, and w' z is the zero point after gain compensation, w' p1 is the first pole after the compensation gain, w' p2 It is the second pole after the compensation gain.

[0161] Specifically, the adaptive circuit in the embodiment of the present invention can support different transmission rates under the chiplet link, and is fully applicable to various interconnection interfaces such as C2C (Chip-to-Chip) and D2D (Die-to-Die).

[0162] Please refer to Figure 7 , Figure 7 A schematic flow chart of an adaptive method provided by the present invention, the adaptive method comprising:

[0163] S101: determining a first control voltage of a first equalizing circuit, wherein the control voltage refers to: an integrated voltage of a product of a signal difference value of an equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference value refers to: a difference voltage between an output signal and an input signal of the equalizing circuit to which the control voltage belongs, and the first equalizing circuit refers to: a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit;

[0164] S102: Determine a second control voltage of the combined equalization circuit;

[0165] S103: subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0166] S104: Send the first control voltage and the third control voltage to the corresponding equalizing circuits respectively, so as to adjust the parameter to be adjusted of the first equalizing circuit by the first control voltage, and adjust the parameter to be adjusted of the second equalizing circuit by the third control voltage.

[0167] As an optional embodiment, the parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels;

[0168] After determining the first control voltage of the first equalizing circuit, the adaptive method further includes:

[0169] The first control voltage is reduced according to the reduction ratio corresponding to the post-mark of the target level to obtain a sub-control voltage of the post-mark of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of post-mark levels, and the reduction ratio corresponding to the post-mark of the target level refers to: a voltage ratio between a main mark in the input signal of the combined equalizing circuit and the post-mark of the target level, the main mark refers to: a main mark located at an amplitude point of the input signal of the combined equalizing circuit, and the post-mark refers to: a subsequent mark located after the amplitude point of the input signal of the combined equalizing circuit;

[0170] The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

[0171] As an optional embodiment, the adaptive method further includes:

[0172] Determine whether the duration of a signal difference of a target equalizing circuit in the combined equalizing circuit is greater than a preset threshold value exceeds a preset duration, wherein the target equalizing circuit refers to any one of the pre-stage equalizing circuit and the post-stage equalizing circuit;

[0173] If exceeded, the control indicator will indicate an abnormality.

[0174] Specifically, considering that under normal circumstances, whether it is the front-stage equalizing circuit or the rear-stage equalizing circuit in the combined equalizing circuit, the signal difference will be adjusted to a reasonable range within a certain period of time. If the signal difference is outside the reasonable range for a long time, it may indicate that a related component has failed. Therefore, in the embodiment of the present invention, it is possible to actively determine whether the duration for which the signal difference of the target equalizing circuit in the combined equalizing circuit is greater than a preset threshold exceeds a preset duration. If so, the indicator can be controlled to indicate an abnormality so that the staff can promptly discover the abnormality and perform maintenance.

[0175] Specifically, the preset threshold and the preset time can be set independently, and the embodiment of the present invention does not limit this.

[0176] The prompter may be of various types, such as a voice announcer, etc., which is not limited in the embodiment of the present invention.

[0177] For an introduction to the adaptive method provided in the embodiment of the present invention, please refer to the aforementioned embodiment of the adaptive circuit, and the embodiment of the present invention will not be described in detail here.

[0178] Please refer to Figure 8 , Figure 8 A schematic diagram of a flow chart of an adaptive device provided by the present invention, the adaptive device comprising:

[0179] A first determination module 81 is used to determine a first control voltage of a first equalizing circuit, wherein the control voltage refers to an integral voltage of a product of a signal difference of an equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference refers to a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit;

[0180] A second determining module 82, configured to determine a second control voltage of the combined equalizing circuit;

[0181] A first subtraction module 83, configured to subtract the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit;

[0182] The first sending module 84 is used to send the first control voltage and the third control voltage to the corresponding equalizing circuits respectively, so as to adjust the parameters to be adjusted of the first equalizing circuit by the first control voltage and adjust the parameters to be adjusted of the second equalizing circuit by the third control voltage.

[0183] As an optional embodiment, the parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels;

[0184] Adaptive devices also include:

[0185] A proportional reduction module, used for reducing the first control voltage according to the reduction ratio corresponding to the post-mark of the target level, to obtain a sub-control voltage of the post-mark of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of post-mark levels, and the reduction ratio corresponding to the post-mark of the target level refers to: a voltage ratio between a main mark in the input signal of the combined equalizing circuit and the post-mark of the target level, the main mark refers to: a main mark located at an amplitude point of the input signal of the combined equalizing circuit, and the post-mark refers to: a subsequent mark located after the amplitude point of the input signal of the combined equalizing circuit;

[0186] The second sending module is used to transmit the sub-control voltage of each post-marker to the post-stage equalization circuit, so as to adjust the tap coefficient of the corresponding post-marker through the self-control voltage of each post-marker.

[0187] As an optional embodiment, the adaptive device further includes:

[0188] A first judgment module is used to judge whether the duration of the signal difference of the target equalizing circuit in the combined equalizing circuit is greater than the preset threshold value exceeds the preset duration, and if so, trigger the control module, wherein the target equalizing circuit refers to any one of the pre-stage equalizing circuit and the post-stage equalizing circuit;

[0189] The control module is used to control the indicator to indicate abnormality.

[0190] For an introduction to the adaptive device provided in the embodiment of the present invention, please refer to the embodiment of the adaptive method described above, and the embodiment of the present invention will not be described in detail here.

[0191] Please refer to Fig. 9 , Fig. 9 A schematic diagram of a process flow of an adaptive device provided by the present invention, the adaptive device comprising:

[0192] A memory 91, used for storing computer programs;

[0193] The processor 92 is used to implement the steps of the adaptive method in the above-mentioned embodiment when executing the computer program.

[0194] For an introduction to the adaptive device provided in the embodiment of the present invention, please refer to the embodiment of the adaptive method described above, and the embodiment of the present invention will not be described in detail here.

[0195] The present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the adaptive method in the above-mentioned embodiment when executed by a processor.

[0196] For an introduction to the computer program product provided by the embodiment of the present invention, please refer to the aforementioned embodiment of the adaptive method, and the embodiment of the present invention will not be described in detail here.

[0197] Please refer to Fig.10 , Fig.10 This is a flow chart of a computer-readable storage medium provided by the present invention. A computer program 102 is stored on the computer-readable storage medium 101. When the computer program 102 is executed by the processor 101, the steps of the adaptive method in the above-mentioned embodiment are implemented.

[0198] For an introduction to the computer-readable storage medium provided in an embodiment of the present invention, please refer to the aforementioned embodiment of the adaptive method, and the embodiment of the present invention will not be described in detail here.

[0199] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the element.

[0200] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adaptive circuit, characterized in that: include: a first integrating circuit whose output terminal is connected to the control terminal of the first equalizing circuit, and is used to determine a first control voltage of the first equalizing circuit, wherein the control voltage refers to an integrated voltage of a product of a signal difference value of the equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference value refers to a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to a pre-stage equalizing circuit or a post-stage equalizing circuit in the combined equalizing circuit; A second integrating circuit, used for determining a second control voltage of the combined equalizing circuit; a subtraction circuit whose output terminal is connected to the control terminal of the second balancing circuit, and is used for subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to the control voltage of the second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit; The first control voltage is used to adjust the parameter to be adjusted of the first equalizing circuit, and the third control voltage is used to adjust the parameter to be adjusted of the second equalizing circuit.

2. The adaptive circuit according to claim 1, characterized in that: The first equalizing circuit includes a rear-stage equalizing circuit in the combined equalizing circuit, and the second equalizing circuit includes a front-stage equalizing circuit in the combined equalizing circuit.

3. The adaptive circuit according to claim 2, characterized in that: The first integration circuit includes a first subtractor, a first multiplier and a first integrator; The input end of the first subtractor is connected to the input end and the output end of the first equalizer circuit respectively, the input end of the first multiplier is connected to the output end of the first subtractor and the output end of the first equalizer circuit respectively, the output end of the first multiplier is connected to the input end of the first integrator, and the output end of the first integrator serves as the output end of the first integrator circuit.

4. The adaptive circuit according to claim 3, characterized in that: The second integration circuit includes a second subtractor, a second multiplier and a second integrator; The segments of the second subtractor are respectively connected to the input and output of the combined equalization circuit, the input of the second multiplier is respectively connected to the output of the second subtractor and the output of the combined equalization circuit, the output of the second multiplier is connected to the input of the second integrator, and the output of the second integrator serves as the output of the second integration circuit.

5. The adaptive circuit according to claim 4, characterized in that: The subtraction circuit includes a third subtractor; The input end of the third subtractor is connected to the output end of the first integration circuit and the output end of the second integration circuit respectively.

6. The adaptive circuit according to claim 2, characterized in that: The parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels; The adaptive circuit further comprises: a proportional reduction circuit, used for reducing the first control voltage according to a reduction ratio corresponding to a postscript of a target level, to obtain a sub-control voltage of the postscript of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of postscript levels, and the reduction ratio corresponding to the postscript of the target level refers to: a voltage ratio between a main mark in an input signal of the combined equalizing circuit and the postscript of the target level, the main mark refers to: a main mark at an amplitude point of the input signal of the combined equalizing circuit, and the postscript refers to: a subsequent mark after the amplitude point of the input signal of the combined equalizing circuit; The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

7. The adaptive circuit according to claim 6, characterized in that: The proportional reduction circuit includes N levels of voltage-dividing resistors; The voltage-dividing resistors of the 1st to Nth levels are connected end to end in order of levels, the second end of the voltage-dividing resistor of the previous level is connected to the first end of the voltage-dividing resistor of the next level, the first end of the voltage-dividing resistor of the 1st level is connected to the output end of the first integration circuit, the voltage-dividing resistor of the Nth level is grounded, and the first end of the voltage-dividing resistor of the Lth level serves as the output end of the post-label sub-control voltage of the Lth level, L∈[2,N].

8. An adaptive combined equalization circuit, characterized in that: The device comprises a pre-stage equalizing circuit and a post-stage equalizing circuit, and further comprises an adaptive circuit as claimed in any one of claims 1 to 7 connected to the pre-stage equalizing circuit and the post-stage equalizing circuit respectively; A pre-stage equalization circuit, used for performing a first-stage compensation on a signal to be compensated received through an information channel; The post-stage equalization circuit is used to perform second-stage compensation on the signal to be compensated after the first-stage compensation.

9. The adaptive combined equalization circuit according to claim 8, characterized in that: The post-stage equalization circuit includes an external power supply, a resistance circuit, a main mark control voltage source, and a signal processing circuit corresponding to the main mark and each post-mark; The output end of the external power supply is connected to the first end of the resistance circuit, the second end of the resistance circuit is respectively connected to the first end of each signal processing circuit, the second end of each signal processing circuit is respectively grounded, the control end of the main mark signal processing circuit is connected to the main mark control voltage source, the control end of the first stage post-mark signal processing circuit is connected to the output end of the first integration circuit, the control ends of the second to N stage post-mark signal processing circuits are respectively connected to the output ends of the corresponding sub-control voltages in the proportional reduction circuit, and the input end of each signal processing circuit is used to receive the to-be-adjusted signal corresponding to the main mark or post-mark to which it belongs; The first terminals of the signal processing circuits serve together as the output terminals of the subsequent equalization circuit.

10. The adaptive combined equalization circuit according to claim 9, characterized in that: The signal processing circuit includes a first controllable switch, a second controllable switch and a third controllable switch; The drain of the first controllable switch and the drain of the second controllable switch serve together as a first end of a signal processing circuit, the gate of the first controllable switch and the gate of the second controllable switch serve as an input end of the signal processing circuit, the source of the first controllable switch and the source of the second controllable switch are connected to the drain of a third controllable switch, the source of the third controllable switch serves as a second end of the signal processing circuit, and the gate of the third controllable switch serves as a control end of the signal processing circuit; The first controllable switch, the second controllable switch and the third controllable switch are all N-type metal oxide semiconductor field effect transistors.

11. The adaptive combined equalization circuit according to claim 8, characterized in that: The pre-stage equalization circuit includes a continuous time linear equalization circuit; The continuous time linear equalization circuit includes an external power supply, a load circuit, an on-off control circuit, a source negative feedback circuit and a current control circuit; The external power supply is connected to the first end of the load circuit, the second end of the load circuit is connected to the first end of the on-off control circuit and together serves as the output end of the continuous-time linear equalization circuit, the second end of the on-off control circuit is respectively connected to the first end of the source negative feedback circuit and the current control circuit, the second end of the current control circuit is grounded, and the control end of the source negative feedback circuit is connected to the output end of the third control voltage of the adaptive circuit.

12. The adaptive combined equalization circuit according to claim 11, characterized in that: The source negative feedback circuit includes a fourth controllable switch, a fifth controllable switch and a sixth controllable switch; The source of the fourth controllable switch is connected to the drain and source of the fifth controllable switch respectively, the drain of the fourth controllable switch is connected to the drain and source of the sixth controllable switch respectively, and the control terminals of the fourth to sixth controllable switches serve together as the control terminals of the source negative feedback circuit; Among them, the fourth to sixth controllable switches are all N-type metal oxide semiconductor field effect transistors.

13. The adaptive combined equalization circuit according to claim 12, characterized in that: The load circuit includes a seventh controllable switch, an eighth controllable switch, a first load capacitor and a second load capacitor; The source of the seventh controllable switch and the source of the eighth controllable switch serve together as the first end of the load circuit, the gate of the seventh controllable switch and the gate of the eighth controllable switch are both connected to the output end of the third control voltage of the adaptive circuit, the drain of the seventh controllable switch is connected to the first end of the first load capacitor, the drain of the eighth controllable switch is connected to the first end of the second load capacitor, the first end of the first load capacitor and the first end of the second load capacitor serve together as the second end of the load circuit, the second end of the first load capacitor is grounded, and the second end of the second load capacitor is grounded; Wherein, the seventh controllable switch and the eighth controllable switch are both P-type metal oxide semiconductor field effect transistors.

14. An adaptive method, characterized in that include: Determine a first control voltage of the first equalizing circuit, wherein the control voltage refers to: an integrated voltage of a product of a signal difference value of the equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference value refers to: a difference voltage between an output signal and an input signal of the equalizing circuit to which the control voltage belongs, and the first equalizing circuit refers to: a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit; determining a second control voltage of the combined equalization circuit; Subtracting the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit; The first control voltage and the third control voltage are respectively sent to the corresponding equalizing circuits, so that the parameter to be adjusted of the first equalizing circuit is adjusted by the first control voltage, and the parameter to be adjusted of the second equalizing circuit is adjusted by the third control voltage.

15. The adaptive method according to claim 14, characterized in that: The parameters to be adjusted of the post-stage equalization circuit include tap coefficients of multiple post-stage labels; After determining the first control voltage of the first equalizing circuit, the adaptive method further includes: The first control voltage is reduced according to the reduction ratio corresponding to the postscript of the target level to obtain a sub-control voltage of the postscript of the target level, wherein the target level includes any positive integer from 2 to N, N is the total number of postscript levels, and the reduction ratio corresponding to the postscript of the target level refers to: a voltage ratio between a main mark in the input signal of the combined equalizing circuit and the postscript of the target level, the main mark refers to: a main mark located at an amplitude point of the input signal of the combined equalizing circuit, and the postscript refers to: a subsequent mark located after the amplitude point of the input signal of the combined equalizing circuit; The sub-control voltage of each post-marker is transmitted to the post-stage equalization circuit, so that the tap coefficient of the corresponding post-marker can be adjusted through the self-control voltage of each post-marker.

16. The adaptive method according to claim 14, characterized in that: The adaptive method further comprises: Determine whether the duration of a signal difference of a target equalizing circuit in the combined equalizing circuit is greater than a preset threshold value exceeds a preset duration, wherein the target equalizing circuit refers to any one of the pre-stage equalizing circuit and the post-stage equalizing circuit; If exceeded, the control indicator will indicate an abnormality.

17. An adaptive device, characterized in that: include: A first determination module is used to determine a first control voltage of a first equalizing circuit, wherein the control voltage refers to: an integrated voltage of a product of a signal difference of an equalizing circuit to which the control voltage belongs and an output signal of the equalizing circuit to which the control voltage belongs, the signal difference refers to: a difference voltage between an output signal of the equalizing circuit to which the control voltage belongs and an input signal, and the first equalizing circuit refers to: a pre-stage equalizing circuit or a post-stage equalizing circuit in a combined equalizing circuit; A second determining module, used to determine a second control voltage of the combined equalizing circuit; A first subtraction module, configured to subtract the first control voltage from the second control voltage to obtain a third control voltage, wherein the third control voltage refers to a control voltage of a second balancing circuit, and the second balancing circuit refers to another balancing circuit in the combined balancing circuit except the first balancing circuit; The first sending module is used to send the first control voltage and the third control voltage to the corresponding equalizing circuits respectively, so as to adjust the parameters to be adjusted of the first equalizing circuit by the first control voltage and adjust the parameters to be adjusted of the second equalizing circuit by the third control voltage.

18. An adaptive device, characterized in that include: Memory for storing computer programs; A processor, configured to implement the steps of the adaptive method according to any one of claims 14 to 16 when executing the computer program.

19. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the adaptive method according to any one of claims 14 to 16 are implemented.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the adaptive method according to any one of claims 14 to 16 are implemented.

Images