A parity delay chain and decoding method thereof
By adopting a parity delay chain structure in the delay chain and using the parity level decomposition sampling results, the problems of uneven delay and decoding difficulties caused by single-stage inverters are solved, and higher measurement accuracy and stable performance are achieved.
Patent Information
- Application Number
- CN202411841380.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-08
AI Technical Summary
When the existing delay chain uses a single-stage inverter as the delay unit, there are problems such as uneven overall chain delay and difficult decoding of sampling results.
Using a parity delay chain structure, the measurement signal is sampled through multiple cascaded delay units and flip-flops. The processing unit decomposes the entire chain sampling results according to the parity level of the delay unit to obtain odd chain and even chain sampling results, thereby replacing the continuous opposite output of multiple single-stage inverters as continuous same outputs, avoiding uneven delays.
The delay uniformity of the delay chain is achieved, the difficulty of decoding the sampling results is reduced, and the measurement accuracy and performance are improved.
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Figure CN119788077A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of high-precision time measurement, and in particular to an odd-even delay chain and a decoding method thereof. Background Art
[0002] High-precision time interval measurement is widely used in the back-end readout of nuclear resonance scattering experiments in high-energy physics, and its performance directly affects the result analysis and energy spectrum drawing of nuclear resonance scattering experiments. In addition, by accurately measuring the flight time of photons using the time of flight (ToF) method, accurate position information can be calculated. Therefore, in addition to the field of high-energy physics, high-precision time measurement solutions are also widely used in fluorescence imaging, space exploration, astronomical observation, positron emission tomography, laser ranging, autonomous driving, aerospace, radar positioning, three-dimensional imaging, and fluid flow measurement.
[0003] High-precision time interval measurement is mainly achieved through two platforms: FPGA (Field Programmable Gate Array) and Application Specific Integrated Circuit (ASIC). The main implementation schemes include direct counting method, clock phase division method and interpolation delay chain method. The time intervals that can be resolved by the FPGA platform are mainly concentrated in the range of more than 100 picoseconds. In the ASIC platform, the resolution of time intervals has reached the level of less than 100 picoseconds. In recent years, from the increase in demand for high-energy physics experiments to the development of autonomous driving technology and the popularization of smart water meters, high-precision and high-resolution time measurement has become particularly important. In the ToF method, the higher the time resolution, the more accurate the location information can be. Therefore, high-precision time interval measurement urgently needs to achieve higher time resolution.
[0004] The resolution of the interpolation delay chain method is determined by the delay time and process of the delay unit. The delay unit used in the traditional method is a buffer, which is composed of two inverters, whose input and output are in phase and the delay is average. However, the delay is usually large, resulting in low resolution. The traditional method often increases the number of interpolation units to improve the resolution, but the more devices in the design, the larger the area and the higher the cost.
[0005] The existing method uses a single-stage inverter as a delay unit to improve the resolution. However, the input and output of the single-stage inverter are inverted, resulting in opposite outputs of adjacent single-stage inverters. The entire chain will have uneven delays, which will not only affect the measurement accuracy and performance, but also increase the difficulty of decoding the sampling results. Summary of the invention
[0006] Based on the above technical problems, the present invention provides an odd-even delay chain, which solves the problems of uneven delay of the entire chain and difficulty in decoding sampling results when the existing delay chain uses a single-stage inverter as a delay unit.
[0007] In a first aspect, the present invention provides an odd-even delay chain, comprising:
[0008] A plurality of cascaded delay units, used for receiving a measurement signal and performing delay processing on the time between the measurement signal and an edge of a sampling clock, wherein the number of the delay units is an even number;
[0009] A plurality of triggers, whose input ends are respectively connected to the output ends of the plurality of delay units, are used to sample the outputs of the plurality of delay units to obtain a whole chain sampling result;
[0010] The processing unit is connected to the output ends of multiple triggers, and is used to decompose the whole chain sampling results according to the odd and even levels of the delay unit to obtain odd chain sampling results and even chain sampling results, and output the whole chain sampling results, odd number sampling results and even chain sampling results.
[0011] Preferably, the delay unit is an inverter, and its output end is in phase opposition with its input end.
[0012] Preferably, the number of the plurality of delay units is obtained by the clock cycle and the delay time length of the inverter, as shown below:
[0013] M=T clk / T d ;
[0014] Where M is the number of inverters, T clk is the clock period, T d is the delay length of a single inverter.
[0015] Preferably, the trigger is a D trigger, the data range of the whole chain sampling result is [0~(M-1)], the data range of the odd chain sampling result and the even chain sampling result is [0~(m-1)], the odd chain sampling results include [0,1…m-2,m-1], and the even chain sampling results include [0,2…(m-2)*2,(m-1)*2], where M=2m.
[0016] In a second aspect, the present invention further provides a decoding method for decoding an odd-even delay chain, comprising:
[0017] Back-label the odd-chain sampling results and the even-chain sampling results to a whole chain;
[0018] Threshold expansion is performed on the levels of two adjacent sampling data in the odd chain sampling results and the even chain sampling results to obtain two adjacent intervals and take the intersection to obtain the jump point on the entire chain, where the jump point is the boundary between 0 and 1;
[0019] The level at which the transition point on the entire chain is located is taken as the decoding result.
[0020] Preferably, it also includes:
[0021] Perform the inversion operation on the odd chain sampling result;
[0022] The number of 1s in the odd-chain sampling result or the even-chain sampling result after the inversion operation is counted, and the level where the statistical result is located is used as the decoding result, which ranges from [0 to (m-1)].
[0023] Preferably, it also includes:
[0024] Perform beat processing on the whole chain sampling results to obtain the beat results;
[0025] The whole chain sampling result and the beat result are XOR processed to obtain the processing result, and the level where the 01 boundary in the processing result is located is used as the decoding result, which ranges from [0 to (M-1)].
[0026] Compared with the prior art, at least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:
[0027] The present invention proposes an odd-even delay chain, in which multiple single-stage delay units are sampled through multiple triggers. The processing unit decomposes the sampling results of the entire chain according to the odd and even levels of the delay units to obtain odd chain sampling results and even chain sampling results. The continuously opposite outputs of the existing multiple single-stage inverters are replaced with continuously identical outputs, and the bidirectional output is changed into a unidirectional output. The entire chain will not have uneven delays, and the measurement accuracy and performance will not be affected.
[0028] In terms of decoding, since the odd-even delay chain has replaced the continuous opposite outputs of the existing multiple single-stage inverters with continuous identical outputs, changing the bidirectional output to a unidirectional output, the present invention reverse-labels the odd chain sampling results and the even chain sampling results back to the whole chain, and searches for the jump point from the whole chain, thereby reducing the difficulty of decoding. The present invention maintains the uniformity of each level of delay, ensures the stability of performance, and reduces the difficulty of decoding. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 This is the principle diagram of the interpolation delay chain method;
[0031] Figure 2 It is a schematic diagram of the basic structure of the delay chain;
[0032] Figure 3 It is a schematic diagram of the basic structure of the odd-even delay chain of the present invention;
[0033] Figure 4 It is a schematic diagram of the physical implementation of the basic structure of the odd-even delay chain of the present invention;
[0034] Figure 5 This is a sampling result diagram of mode 1 of the present invention;
[0035] Figure 6 This is a sampling result diagram of mode 2 of the present invention;
[0036] Figure 7 It is a schematic diagram of the odd chain and even chain back-labeling of the present invention. DETAILED DESCRIPTION
[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] The interpolation delay chain method expresses the time interval ΔT between the start signal and the stop signal to be measured in the form of "coarse count" + "fine count". Coarse count means that time is measured in clock cycles. When the time interval is less than one cycle, coarse count cannot be quantified, and the measurement result of the time interval less than one clock cycle will be expressed by fine count. By combining coarse and fine quantization, high-precision time measurement can be achieved.
[0039] Interpolation delay chain method Figure 1 As shown, the interpolation delay chain divides a clock cycle into M delay units for interpolation, wherein the first fine counting result t 1 is the interval between the start signal and the sampling clock edge, and the second fine counting result t 2is the interval between the stop signal and the sampling clock edge, and the coarse count result is T. T d is the delay of the first-level interpolation delay unit, T clk is the clock cycle, and N is the number of clock cycles. The first detailed counting result t 1 and the second detailed counting result t 2 It is represented by the number of interpolated delay units in the corresponding interval. 1 , N 1 t 1 Interpolation T d For the second detailed counting result t 2 , N 2 t 2 Interpolation T d ΔT is the time interval of the signal to be measured. The time interval calculation formula is shown in formula (1).
[0040] ΔT=t 1 +Tt 2 =(N 1 -N 2 )×T d +N×T clk (1).
[0041] The trigger samples the output of each level of the delay chain, and then decodes the sampling results to find the jump level. The total delay time accumulated to this level is the fine quantization result, which is t 1 and t 2 . Reference Figure 2 The most commonly used delay unit is a buffer composed of two inverters. The input and output of the buffer are in phase, and there is only a delay between the two. The signal is input into the delay chain, and a working clock is provided for multiple triggers to obtain the sampling result of the entire chain. The sampling result with the buffer as the delay unit is in the format of a standard thermometer code. The present invention uses an inverter as the basic delay unit to construct a delay chain.
[0042] Based on the above, refer to Figure 3 The present invention provides an odd-even delay chain, comprising a plurality of cascaded delay units, a plurality of triggers and a processing unit.
[0043] A plurality of cascaded delay units form a delay chain, which is used to receive a measurement signal and perform delay processing on the time between the measurement signal and the edge of a sampling clock. The input ends of the plurality of triggers are respectively connected to the output ends of the plurality of delay units, which are used to sample the outputs of the plurality of delay units to obtain a whole chain sampling result SumD, where Sum is a summation symbol and D represents a D flip-flop (Data flip-flop). The processing unit is connected to the output ends of the plurality of triggers, which is used to decompose the whole chain sampling result according to the odd and even levels of the delay units to obtain an odd chain sampling result SumD_Odd and an even chain sampling result SumD_Even, and output the whole chain sampling result SumD, the odd sampling result SumD_Odd and the even chain sampling result SumD_Even.
[0044] When an even number of inverters are cascaded, the logic level of the output signal of the last stage and the input signal of the first stage will not change, and there will only be a time-accumulated delay. The present invention inserts a certain number of inverters in one clock cycle, and the number of inverters is calculated as shown in formula (2):
[0045] M=T clk / T d (2);
[0046] Where M represents the number of inverters, T clk Represents the clock period, T d Represents the delay length of a single-stage inverter.
[0047] Furthermore, in the application process, affected by environmental changes, the delay of the inverter will change within a certain range, so the number of inverters finally used in the present invention retains a certain margin on the number calculated by formula (2), and finally forms an inverter chain. The output of each delay unit of the delay chain is sampled by a D trigger. The inverter chain and the trigger finally form a complete odd-even delay chain.
[0048] The fine counting of the present invention is composed of at least two odd-even delay chains, corresponding to the time interval measurement of one start signal and one stop signal. The odd-even delay chain is formed by cascading inverters as delay units, and the output of each delay unit is sampled through a trigger.
[0049] Furthermore, the physical implementation layout of the delay chain is as follows Figure 4 shown.
[0050] Based on the above-mentioned odd-even delay chain, the present invention further proposes a decoding method, including three decoding modes corresponding to different precisions and resolutions.
[0051] Mode 1: This mode corresponds to the whole chain sampling result SumD. Two chains can correspond to the input of 1 start signal and 1 stop signal. Since the input signal propagates in the inverter chain, the output signal ZN of each stage of the inverter will be flipped, so the sampling result flips between "0" and "1". The sampling results of each level of trigger are output. At the edge of the sampling clock, if the sampling results of two adjacent levels are consistent, it means that the jump level occurs at the lower level of the two adjacent levels. The accumulated time when the signal propagates to this level of inverter is equal to the time difference between the signal and the clock edge. When the sampling results of two adjacent levels are different, it means that the jump has not occurred, and the accumulated time is not equal to the time difference. Such as "0101...011010...01" or "0101...010010...01", where "...11..." and "...00..." are regarded as jump points. For example Figure 5 As shown, the K-1 level is the jump level. For this structure, the XOR method is used to decode the result of the trigger output. The whole chain sampling result SumD is processed by tapping (the signal is stored and delayed by one clock cycle), and the SumD and the SumD after tapping are XORed. The logic of the XOR operation is that if the two operands are the same, the result is "0", and if they are different, the result is "1". Therefore, the result after the XOR calculation is "0" before the jump level and "1" after the jump level. The level at the junction of "01" is the result of K-1. After the signal to be measured enters the delay chain, there are M possible "fine count" decoding results, ranging from [0 to (M-1)], corresponding to ultra-high resolution measurement.
[0052] Mode 2: This mode corresponds to the odd sampling result SumD_Odd and the even chain sampling result SumD_Even, and its range is [0~(m-1)], M=2m, such as Figure 6 As shown. According to the delay chain structure, the data of the odd and even levels are inverted. By inverting the odd level, the same decoding method can be used for the two sets of data. At this time, the sampling result is to sample the output of each two-stage inverter, so the sampling result is consistent before and after the jump occurs. The result flips after the jump occurs, such as "11...1100...00" is a typical thermometer code structure, and "...10..." is the jump point. The sampling result is for example Figure 6As shown, the sampling result of the sampling point in the even chain part is "11...100...00", and the transition level is P. The sampling result of the odd chain part is "00...011...11", and the transition level is P-1. For this structure, the result of the trigger output is decoded by thermometer code, that is, the number of "1" is counted. The number of "1" corresponds to the level where the transition levels P and P-1 are located. After the signal to be measured enters the delay chain, the odd chain sampling result and the even chain sampling result each have m possible "fine counting" decoding results, ranging from [0 to (m-1)]. The odd chain and the even chain are regarded as two independent chains, distributed on m levels. The odd and even delay chain results obtained at this time correspond to high resolution, and the two chains differ by 1 level. When measuring, any one chain is taken as the reference benchmark.
[0053] Mode 3: This mode is based on mode 2 and is extended from the decoding method. The odd sampling result SumD_Odd and the even chain sampling result SumD_Even are reversed back to a whole chain, and then the threshold is expanded by ±1 to obtain two groups of "fine counting" intervals with an interval length of 2. The intersection of the two intervals is taken, and the jump point on the whole chain [0~M-1] is locked. The odd chain and even chain are reversed as follows Figure 7 As shown. The even-numbered levels [0,1…m-2,m-1] correspond to [0,2…(m-2)*2,(m-1)*2], and the odd-numbered levels [0,1…m-1,m] correspond to [1,3…(m-2)*2+1,(m-1)*2+1]. The odd-even back-labeled chain is distributed on the [0~M-1] level. The "fine counting" result at this time corresponds to ultra-high resolution.
[0054] Adjust the decoding algorithm by selecting the mode. Mode 1: Single chain overall output calculation, corresponding to ultra-high resolution measurement. Mode 2: Single chain odd-even output, odd chain and even chain are calculated separately, corresponding to high resolution measurement. Mode 3: Odd chain and even chain are combined and output, corresponding to ultra-high resolution measurement. The resolution of mode 1 and mode 3 is of the same order of magnitude, but the processing method of the delay chain sampling result is different. Mode 1 uses XOR decoding, and mode 2 and mode 3 use thermometer code decoding.
[0055] Resolution describes the fineness of the quantization scale, LSB (Least Significant Bit) is used to describe the minimum range of the full-scale input range, and differential nonlinearity (DNL) reflects the nonlinear changes in the local details of the range. Under the design of this invention, the high resolution corresponds to LSB = t. The ultra-high resolution corresponds to DNL is around ±1LSB. The LSB of ultra-high resolution depends on the inherent delay of the delay unit under different processes, but the resolution can be improved to 1 / 2 of the delay of the commonly used delay unit (buffer) through the odd chain and even chain methods, that is, the resolution is improved while the number of delay units remains unchanged. This invention controls the area and cost while improving the resolution, which not only reduces the difficulty of decoding, but also maintains the uniformity of each level of delay, ensuring stable performance. Different time measurement requirements are matched through a variety of measurement modes. The present invention is not limited to a specific process and working clock cycle.
[0056] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0057] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. An even-odd delay chain, characterized in that: include: A plurality of cascaded delay units, used for receiving a measurement signal and performing delay processing on the time between the measurement signal and an edge of a sampling clock, wherein the number of the delay units is an even number; A plurality of triggers, whose input ends are respectively connected to the output ends of the plurality of delay units, are used to sample the outputs of the plurality of delay units to obtain a whole chain sampling result; The processing unit is connected to the output ends of multiple triggers, and is used to decompose the whole chain sampling results according to the odd and even levels of the delay unit to obtain odd chain sampling results and even chain sampling results, and output the whole chain sampling results, odd number sampling results and even chain sampling results.
2. An odd-even delay chain as claimed in claim 1, characterized in that: The delay unit is an inverter, and its output end is in phase opposition with its input end.
3. An odd-even delay chain as claimed in claim 2, characterized in that: The number of multiple delay units is obtained by the clock cycle and the delay time of the inverter, as shown below: M=T clk / T d ; Where M is the number of inverters, T clk is the clock period, T d is the delay length of a single inverter.
4. An odd-even delay chain as claimed in claim 3, characterized in that: The trigger is a D trigger, the data range of the whole chain sampling result is [0~(M-1)], the data range of the odd chain sampling result and the even chain sampling result is [0~(m-1)], the odd chain sampling result includes [0,1…m-2,m-1], and the even chain sampling result includes [0,2…(m-2)*2,(m-1)*2], where M=2m.
5. A decoding method for decoding the odd-even delay chain according to any one of claims 1 to 4, characterized in that: include: Back-label the odd-chain sampling results and the even-chain sampling results to a whole chain; Threshold expansion is performed on the levels of two adjacent sampling data in the odd chain sampling results and the even chain sampling results to obtain two adjacent intervals and take the intersection to obtain the jump point on the entire chain, where the jump point is the boundary between 0 and 1; The level at which the transition point on the entire chain is located is taken as the decoding result.
6. A decoding method as claimed in claim 5, characterized in that: Also includes: Perform the inversion operation on the odd chain sampling result; The number of 1s in the odd-chain sampling result or the even-chain sampling result after the inversion operation is counted, and the level where the statistical result is located is used as the decoding result, which ranges from [0 to (m-1)].
7. A decoding method as claimed in claim 5, characterized in that: Also includes: Perform beat processing on the whole chain sampling results to obtain the beat results; The whole chain sampling result and the beat result are XOR processed to obtain the processing result, and the level where the 01 boundary in the processing result is located is used as the decoding result, which ranges from [0 to (M-1)].