MEMS chip testing system, method, device and medium

Abstract

The present disclosure provides a MEMS chip testing system, method, device and medium. The MEMS chip testing system includes a master control terminal and a test unit. The test unit includes a centralized control terminal and multiple measurement and control terminals. The centralized control terminal is connected to the master control terminal. The multiple measurement and control terminals and the centralized control terminal are mutually connected through a backplane bus. A CAN bus is arranged on the backplane bus. The centralized control terminal is used to parse a configuration file sent by the master control terminal for testing the MEMS chip to obtain a target test table. The target test table includes multiple test entries. The centralized control terminal is used to broadcast a clock synchronization instruction through the CAN bus when the multiple measurement and control terminals are respectively in a ready state, and control the multiple measurement and control terminals to execute the corresponding test entries when the multiple measurement and control terminals respectively receive the clock synchronization instruction.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of MEMS testing technology, and more specifically, to a MEMS chip testing system, method, device and medium. Background Art

[0002] In the implementation of micro-electro-mechanical systems (MEMS) chip test systems, more attention is often paid to the execution synchronization of the test process than to real-time performance. However, when testing MEMS chips, existing MEMS chip test systems not only have problems such as high latency and insufficient synchronization accuracy, but also require expensive embedded hardware to implement. Summary of the invention

[0003] An objective of the embodiments of the present disclosure is to provide a new technical solution for a MEMS chip testing system.

[0004] According to a first aspect of an embodiment of the present disclosure, a MEMS chip testing system is provided, comprising:

[0005] Master control terminal;

[0006] A test unit, wherein the test unit comprises a centralized control terminal and a plurality of measurement and control terminals, the centralized control terminal is connected to the master control terminal, the plurality of measurement and control terminals and the centralized control terminal are connected to each other via a backplane bus, and a CAN bus is arranged on the backplane bus;

[0007] The centralized control terminal is used to parse the configuration file sent by the master control terminal for testing the MEMS chip to obtain a target test table; wherein the target test table includes a plurality of test entries; and

[0008] When the multiple measurement and control terminals are respectively in a ready state, a clock synchronization instruction is broadcasted through the CAN bus, and when the multiple measurement and control terminals respectively receive the clock synchronization instruction, the multiple measurement and control terminals are controlled to execute the corresponding test items.

[0009] Optionally, the centralized control terminal is further used to broadcast a preparation instruction via the CAN bus;

[0010] The multiple measurement and control terminals are used to execute initialization operations corresponding to the measurement and control terminals when the preparation instructions are received respectively.

[0011] Optionally, the multiple measurement and control terminals are used to send feedback instructions corresponding to the measurement and control terminals being in a ready state to the centralized control terminal through the CAN bus respectively when the operations corresponding to the measurement and control terminals are respectively initialized and completed;

[0012] The centralized control end is further used to determine whether the corresponding measurement and control end is in a ready state when receiving the feedback instructions respectively sent by the multiple measurement and control ends.

[0013] Optionally, the backplane bus further includes an IO bus, the preparation instruction carries a signal type, and the signal type includes one of the following: an IO signal broadcasted through the IO bus and a CAN signal broadcasted through the CAN bus,

[0014] When the multiple measurement and control terminals are used to send feedback instructions corresponding to the measurement and control terminals being in a ready state to the centralized control terminal respectively through the CAN bus, the instruction type of the clock synchronization instruction to be waited for is determined according to the signal type carried in the ready instruction.

[0015] Optionally, the centralized control end is also used to use the IO signal broadcast through the IO bus as the clock synchronization instruction, or use the CAN signal broadcast through the CAN bus as the clock synchronization instruction when receiving the feedback instructions sent respectively by the multiple measurement and control ends.

[0016] Optionally, the backplane bus further includes a clock bus.

[0017] The centralized control end is further used to synchronize the clocks corresponding to the multiple measurement and control ends respectively through the clock bus when receiving the feedback instructions respectively sent by the multiple measurement and control ends.

[0018] Optionally, the clock synchronization instruction is set as the instruction with the highest arbitration priority in the arbitration mechanism of the CAN bus.

[0019] According to a second aspect of an embodiment of the present disclosure, a MEMS chip testing method is provided, which is applied to the MEMS chip testing system described in the first aspect above, wherein the MEMS chip testing system includes a master control terminal and a testing unit, wherein the testing unit includes a centralized control terminal and a plurality of measurement and control terminals, wherein the master control terminal is connected to the master control terminal, wherein the plurality of measurement and control terminals and the centralized control terminal are connected to each other via a backplane bus, wherein a CAN bus is arranged on the backplane bus, wherein the method includes:

[0020] The centralized control end parses the configuration file for testing the MEMS chip sent by the master control end to obtain a target test table; wherein the target test table includes a plurality of test entries;

[0021] When the multiple measurement and control terminals are respectively in a ready state, the centralized control terminal broadcasts a clock synchronization instruction through the CAN bus, and when the multiple measurement and control terminals respectively receive the clock synchronization instruction, the multiple measurement and control terminals are controlled to execute the corresponding test items.

[0022] According to a third aspect of an embodiment of the present disclosure, a MEMS chip testing device is provided, which is applied to the MEMS chip testing system described in the first aspect above, wherein the MEMS chip testing system comprises a master control terminal and a testing unit, wherein the testing unit comprises a centralized control terminal and a plurality of measurement and control terminals, wherein the master control terminal is connected to the master control terminal, wherein the plurality of measurement and control terminals and the centralized control terminal are connected to each other via a backplane bus, wherein a CAN bus is arranged on the backplane bus, wherein the device comprises:

[0023] An acquisition module, configured to parse the configuration file for testing the MEMS chip sent by the central control terminal through the centralized control terminal to obtain a target test table; wherein the target test table includes a plurality of test entries;

[0024] The control module is used to broadcast a clock synchronization instruction through the CAN bus through the centralized control terminal when the multiple measurement and control terminals are respectively in a ready state, and control the multiple measurement and control terminals to execute the corresponding test items when the multiple measurement and control terminals respectively receive the clock synchronization instructions.

[0025] According to a fourth aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the MEMS chip testing method described in the second aspect above is executed.

[0026] One beneficial effect of the embodiment of the present disclosure is that the MEMS chip test system provided by the present disclosure includes a master control terminal and a test unit, the test unit includes a centralized control terminal and multiple measurement and control terminals, the centralized control terminal is connected to the master control terminal, and the centralized control terminal and the multiple measurement and control terminals are connected to each other through a backplane bus, and a CAN bus is arranged on the backplane bus. The centralized control terminal can parse the configuration file sent by the master control terminal for testing the MEMS chip to obtain a target test table, which includes multiple test items, and the centralized control terminal can broadcast clock synchronization instructions through the CAN bus when multiple measurement and control terminals are in a ready state, and control multiple measurement and control terminals to respectively execute corresponding test items when multiple measurement and control terminals respectively receive the clock synchronization instructions. In other words, the MEMS chip test system provided by the embodiment of the present disclosure constructs a high-speed backplane bus with high cost performance in hardware, and is based on the CAN bus broadcast communication method in software, which effectively reduces transmission delay and improves synchronization accuracy.

[0027] Other features and advantages of the present specification will become apparent from the following detailed description of exemplary embodiments of the present specification with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the specification and, together with the description, serve to explain the principles of the specification.

[0029] Figure 1 is one of the hardware configuration diagrams of the MEMS chip testing system according to an embodiment of the present disclosure;

[0030] Figure 2 This is the second hardware configuration diagram of the MEMS chip testing system according to the embodiment of the present disclosure;

[0031] Figure 3 is a schematic diagram of interaction between a master control terminal, a centralized control terminal, and a measurement and control terminal according to an embodiment of the present disclosure;

[0032] Figure 4 is a flow chart of a MEMS chip testing method according to an embodiment of the present disclosure;

[0033] Figure 5 Schematic diagram of the hardware configuration of the MEMS chip testing device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the embodiments of the present disclosure.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0036] The technologies, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the technologies, methods and equipment should be considered as part of the specification.

[0037] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0038] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0039] <Hardware Configuration>

[0040] See also Figure 1 , which is a hardware structure diagram of a MEMS chip testing system provided by an embodiment of the present disclosure. Figure 1As shown, the MEMS chip testing system 1 includes a master control terminal 11 and a testing unit 12 .

[0041] The MEMS chip testing system 1 generally includes a plurality of testing units 12. Figure 2 The MEMS chip test system 1 includes, for example but not limited to, a test unit 12-1, a test unit 12-2, ..., a test unit 12-m, where m is the number of test units. This embodiment does not limit the number of test units included in the MEMS chip test system 1, which can be specifically set according to the number of tooling for the MEMS chip, and this embodiment does not limit this. The following description will be made by taking one of the test units 12 as an example.

[0042] Among them, multiple test units 12 can perform the same test function. For example, the MEMS chip includes three fixtures, so three test units 12 can be set in the MEMS chip test system 1, among which one test unit 12 can be responsible for testing the fixture 1 of the MEMS chip, one test unit 12 can be responsible for testing the fixture 2 of the MEMS chip, and one test unit 12 can be responsible for testing the fixture 3 of the MEMS chip.

[0043] The master control terminal 11 can convert the user-level test items into configuration files that can be used to test the MEMS chip, and send the configuration files to the test unit 12 through the switch.

[0044] The test unit 12 may be referred to as a test chassis. Figure 1 The test unit 12 may include a centralized control terminal 121 and a plurality of measurement and control terminals, namely, a measurement and control terminal 122-1, a measurement and control terminal 122-2, ..., a measurement and control terminal 122-n, where n is the number of measurement and control terminals in the test unit 12, and n is greater than 1. The centralized control terminal 121 is connected to the master control terminal 11, and the plurality of measurement and control terminals and the centralized control terminal 121 are connected to each other via a backplane bus 13, and a CAN bus (not shown in the figure) is arranged on the backplane bus 13.

[0045] It should be noted that it is possible to construct a test unit in a small range with a single centralized control terminal as a unit, thereby limiting the load rate of CAN and ensuring that the communication rate of the high-speed CAN bus is 1Mbps.

[0046] Generally, the types of the multiple measurement and control terminals in the same test unit 12 may be the same or different. The numbers of the multiple measurement and control terminals included in different test units 12 may be the same or different.

[0047] Reference Figure 2Taking the test unit 12-1 as an example, the test unit 12-1 includes a centralized control terminal 121a and three measurement and control terminals, namely, measurement and control terminals 122a-1, 122a-2, and 122a-3. Among them, the measurement and control terminals 122a-1, 122a-2, 122a-3, and the centralized control terminal 121a are interconnected through the backplane bus 13-1, support hot plugging and do not limit the insertion position, and at least a CAN bus is arranged on the backplane bus 13-1. In addition, the types of the measurement and control terminals 122a-1, 122a-2, and 122a-3 can be different, among which the measurement and control terminal 122a-1 is a working current acquisition terminal, the measurement and control terminal 122a-2 is a working voltage acquisition card, and the measurement and control terminal 122a-3 is an audio acquisition terminal.

[0048] Reference Figure 1 The centralized control terminal 121 is used to parse the configuration file for testing the MEMS chip sent by the master control terminal 11 to obtain a target test table; wherein the target test table includes multiple test items. The centralized control terminal 121 is used to broadcast a clock synchronization instruction through the CAN bus when the multiple measurement and control terminals are in a ready state, and control the multiple measurement and control terminals to execute the corresponding test items when the multiple measurement and control terminals receive the clock synchronization instruction.

[0049] The target test table may include multiple test items, and each test item has an attribute called "relative to the execution time of the previous test item" to express the collaborative relationship between the test items. The control and monitoring of the test table level are performed at the centralized control terminal 121, and the execution and management of the test item level are performed at the test control terminal.

[0050] Reference Figure 1 The centralized control terminal 121 is also used to broadcast a preparation instruction through the CAN bus. The multiple measurement and control terminals are used to perform the operation of initializing the corresponding measurement and control terminals when the preparation instructions are received respectively; and when the operations of initializing the corresponding measurement and control terminals are completed, feedback instructions that the corresponding measurement and control terminals are in a ready state are sent to the centralized control terminal 121 through the CAN bus. The centralized control terminal 121 is also used to determine that the corresponding measurement and control terminal is in a ready state when receiving the feedback instructions sent by the multiple measurement and control terminals respectively.

[0051] The operation of initializing the corresponding measurement and control terminal includes, for example but not limited to, initializing the device status and resetting the working timer.

[0052] by Figure 2 As an example, refer to the test unit 12-1 shown in FIG. Figure 2 and Figure 3, the master control terminal 11 sends the configuration file for testing the MEMS chip to the centralized control terminal 121a. The centralized control terminal 121a parses the configuration file to obtain a target test table, which includes multiple test entries. The centralized control terminal 121a broadcasts the preparation instruction through the CAN bus, and after the measurement and control terminals 122a-1, 122a-2, and 122a-3 receive the preparation instruction, they respectively perform the operation of initializing the corresponding measurement and control terminals.

[0053] When the measurement and control terminals 122a-1, 122a-2, and 122a-3 respectively complete the operations of initializing the corresponding measurement and control terminals, they respectively send feedback instructions to the centralized control terminal 121a indicating that the corresponding measurement and control terminals are in a ready state. When the centralized control terminal 121a receives the feedback instructions respectively sent by the measurement and control terminals 122a-1, 122a-2, and 122a-3, it determines that the measurement and control terminals 122a-1, 122a-2, and 122a-3 are all in a ready state, and broadcasts the clock synchronization instruction through the CAN bus. When the measurement and control terminals 122a-1, 122a-2, and 122a-3 respectively receive the clock synchronization instruction, they execute the corresponding test items in the target test table parsed by the centralized control terminal 121a. This embodiment does not elaborate on how the measurement and control terminals 122a-1, 122a-2, and 122a-3 execute the test items.

[0054] According to the embodiment of the present disclosure, the MEMS chip test system provided therein includes a master control terminal and a test unit, the test unit includes a centralized control terminal and multiple measurement and control terminals, the centralized control terminal is connected to the master control terminal, and the centralized control terminal and the multiple measurement and control terminals are connected to each other through a backplane bus, and a CAN bus is arranged on the backplane bus. The centralized control terminal can parse the configuration file sent by the master control terminal for testing the MEMS chip to obtain a target test table, which includes multiple test items, and the centralized control terminal can broadcast clock synchronization instructions through the CAN bus when multiple measurement and control terminals are in a ready state, and control multiple measurement and control terminals to respectively execute corresponding test items when multiple measurement and control terminals respectively receive the clock synchronization instructions. In other words, the MEMS chip test system provided by the embodiment of the present disclosure constructs a high-speed backplane bus with high cost performance in hardware, and is based on the CAN bus broadcast communication method in software, which effectively reduces transmission delay and improves synchronization accuracy.

[0055] This embodiment can significantly improve the synchronization of the MEMS chip test system by reasonably designing the synchronization process and utilizing the characteristics of the backplane CAN bus, and is suitable for various application scenarios requiring high synchronization accuracy.

[0056] In one embodiment, the backplane bus 13 also includes an IO bus (not shown). It should be noted that due to the high cost of the IO bus, a relatively small number of IO buses are usually arranged on the backplane bus 13 to cope with a few scenarios with extreme synchronization requirements.

[0057] Reference Figure 1 , the backplane bus also includes an IO bus, the preparation instruction carries a signal type, and the signal type includes one of the following: an IO signal broadcast through the IO bus and a CAN signal broadcast through the CAN bus.

[0058] When the multiple measurement and control terminals are used to send feedback instructions corresponding to the measurement and control terminals being in a ready state to the centralized control terminal 121 through the CAN bus, the instruction type of the clock synchronization instruction to be waited for is determined according to the signal type carried in the ready instruction.

[0059] The centralized control terminal 121 is also used to use the IO signal broadcast through the IO bus as the clock synchronization instruction, or use the CAN signal broadcast through the CAN bus as the clock synchronization instruction when receiving the feedback instructions respectively sent by the multiple measurement and control terminals.

[0060] Example 1, with Figure 2 Taking the test unit 12-1 shown as an example, the main control terminal 11 sends the configuration file for testing the MEMS chip to the centralized control terminal 121a. The centralized control terminal 121a parses the configuration file to obtain the target test table, which includes multiple test entries. The centralized control terminal 121a broadcasts the preparation instruction through the CAN bus. The signal type carried in the preparation instruction is the clock synchronization instruction, which is the IO signal broadcast through the IO bus.

[0061] After receiving the preparation instruction, the measurement and control terminals 122a-1, 122a-2 and 122ca-3 perform the operation of initializing the corresponding measurement and control terminals. When the measurement and control terminals 122a-1, 122a-2 and 122a-3 respectively complete the operation of initializing the corresponding measurement and control terminals, they respectively send feedback instructions to the centralized control terminal 121a indicating that the corresponding measurement and control terminals are in a ready state, and wait for the clock synchronization instruction whose instruction type is an IO signal.

[0062] When receiving the feedback instructions sent by the measurement and control terminals 122a-1, 122a-2 and 122a-3, the centralized control terminal 121a determines that the measurement and control terminals 122a-1, 122a-2 and 122a-3 are all in a ready state, and broadcasts the IO signal as a clock synchronization instruction through the IO bus. When receiving the clock synchronization instruction, the measurement and control terminals 122a-1, 122a-2 and 122a-3 respectively execute the corresponding test items.

[0063] Example 2, with Figure 2 Taking the test unit 12-1 shown as an example, the main control terminal 11 sends the configuration file for testing the MEMS chip to the centralized control terminal 121a. The centralized control terminal 121a parses the configuration file to obtain the target test table, which includes multiple test entries. The centralized control terminal 121a broadcasts the preparation instruction through the CAN bus. The signal type carried in the preparation instruction is the clock synchronization instruction, which is a CAN signal broadcast through the CAN bus.

[0064] After receiving the preparation instruction, the measurement and control terminals 122a-1, 122a-2 and 122a-3 perform the operation of initializing the corresponding measurement and control terminals. When the measurement and control terminals 122a-1, 122a-2 and 122a-3 respectively complete the operation of initializing the corresponding measurement and control terminals, they respectively send feedback instructions to the centralized control terminal 121a indicating that the corresponding measurement and control terminals are in a ready state, and wait for the clock synchronization signal of the instruction type being a CAN signal.

[0065] When receiving the feedback instructions sent by the measurement and control terminals 122a-1, 122a-2 and 122a-3, the centralized control terminal 121a determines that the measurement and control terminals 122a-1, 122a-2 and 122a-3 are all in a ready state, and broadcasts the CAN signal as a clock synchronization signal through the CAN bus. When receiving the clock synchronization signal, the measurement and control terminals 122a-1, 122a-2 and 122a-3 respectively execute the corresponding test items.

[0066] According to this embodiment, the centralized control end in the test unit is the protocol master node, and the measurement and control end is the slave node. The master node is responsible for time management and the generation, release and monitoring of synchronization instruction sequences. The synchronization process based on CAN or IO is designed to be carried out in three steps: preparation, ready confirmation, and clock synchronization, to ensure that all measurement and control ends have enough preparation time, and then start working more accurately at the corresponding time, thereby enhancing the reliability and consistency of the MEMS chip test system.

[0067] In one embodiment, the backplane bus 13 further includes a clock bus (not shown in the figure), which can provide time synchronization between multiple measurement and control terminals in the same test unit.

[0068] Reference Figure 1 The centralized control terminal 121 is used to synchronize the clocks corresponding to the multiple measurement and control terminals respectively through the clock bus when receiving the feedback instructions respectively sent by the multiple measurement and control terminals.

[0069] Example 3, with Figure 2 Taking the test unit 12-1 shown as an example, the main control terminal 11 sends the configuration file for testing the MEMS chip to the centralized control terminal 121a. The centralized control terminal 121a parses the configuration file to obtain the target test table, which includes multiple test entries. The centralized control terminal 121a broadcasts the preparation instruction through the CAN bus. After receiving the preparation instruction, the measurement and control terminal 122a-1, the measurement and control terminal 122a-2 and the measurement and control terminal 122a-3 respectively perform the operation of initializing the corresponding measurement and control terminal.

[0070] When the measurement and control terminals 122a-1, 122a-2, and 122a-3 respectively complete the operations of initializing the corresponding measurement and control terminals, they respectively send feedback instructions to the centralized control terminal 121a indicating that the corresponding measurement and control terminals are in a ready state. When the centralized control terminal 121a receives the feedback instructions respectively sent by the measurement and control terminals 122a-1, 122a-2, and 122a-3, it first performs clock synchronization through the clock bus, and then broadcasts the clock synchronization instruction through the CAN bus, so as to ensure the clock consistency during the execution of each measurement and control terminal.

[0071] In one embodiment, the clock synchronization instruction is set as the instruction with the highest arbitration priority in the arbitration mechanism of the CAN bus.

[0072] In this embodiment, the arbitration mechanism of the CAN bus is fully utilized, and the arbitration priority of the clock synchronization instruction is set to be the highest, so as to ensure that the centralized control terminal can broadcast the clock synchronization instruction with the highest priority.

[0073] <Method Example>

[0074] Please see Figure 4 , which is a flow chart of a MEMS chip testing method provided by an embodiment of the present application. The method can be applied to a MEMS chip testing system, the MEMS chip testing system includes a master control terminal and a testing unit, the testing unit includes a centralized control terminal and multiple measurement and control terminals, the master control terminal is connected to the master control terminal, the multiple measurement and control terminals and the centralized control terminal are connected to each other through a backplane bus, and a CAN bus is arranged on the backplane bus.

[0075] like Figure 4 As shown, the MEMS chip testing method may include steps S4100 to S4200, which are described in detail below.

[0076] Step S4100: The centralized control terminal parses a configuration file for testing the MEMS chip sent by the master control terminal to obtain a target test table.

[0077] The target test table includes multiple test entries.

[0078] Step S4200, when the multiple measurement and control terminals are respectively in a ready state, the centralized control terminal broadcasts a clock synchronization instruction through the CAN bus, and when the multiple measurement and control terminals respectively receive the clock synchronization instruction, controls the multiple measurement and control terminals to respectively execute the corresponding test items.

[0079] According to this embodiment, the MEMS chip test system includes a main control terminal and a test unit, the test unit includes a centralized control terminal and multiple measurement and control terminals, the centralized control terminal is connected to the main control terminal, and the centralized control terminal and the multiple measurement and control terminals are connected to each other through a backplane bus, and a CAN bus is arranged on the backplane bus. The centralized control terminal can parse the configuration file sent by the main control terminal for testing the MEMS chip to obtain a target test table, which includes multiple test items, and the centralized control terminal can broadcast clock synchronization instructions through the CAN bus when multiple measurement and control terminals are in a ready state, and control multiple measurement and control terminals to respectively execute corresponding test items when multiple measurement and control terminals receive the clock synchronization instructions respectively. In other words, the MEMS chip test system provided by the embodiment of the present disclosure constructs a high-speed backplane bus with high cost performance in hardware, and is based on the CAN bus broadcast communication method in software, which effectively reduces transmission delay and improves synchronization accuracy.

[0080] <Device Example>

[0081] Figure 5 It is a structural schematic diagram of a MEMS chip testing device according to an embodiment. The device can be applied to a MEMS chip testing system. The MEMS chip testing system includes a master control terminal and a testing unit. The testing unit includes a centralized control terminal and multiple measurement and control terminals. The master control terminal is connected to the master control terminal. The multiple measurement and control terminals and the centralized control terminal are interconnected through a backplane bus. A CAN bus is arranged on the backplane bus.

[0082] like Figure 5 As shown, the MEMS chip testing device 500 includes an acquisition module 510 and a control module 520 .

[0083] The acquisition module 510 is used to parse the configuration file for testing the MEMS chip sent by the central control terminal through the centralized control terminal to obtain a target test table; wherein the target test table includes a plurality of test entries;

[0084] The control module 520 is used to broadcast a clock synchronization instruction through the CAN bus through the centralized control end when the multiple measurement and control ends are respectively in a ready state, and control the multiple measurement and control ends to respectively execute the corresponding test items when the multiple measurement and control ends respectively receive the clock synchronization instructions.

[0085] According to this embodiment, the MEMS chip test system includes a main control terminal and a test unit, the test unit includes a centralized control terminal and multiple measurement and control terminals, the centralized control terminal is connected to the main control terminal, and the centralized control terminal and the multiple measurement and control terminals are connected to each other through a backplane bus, and a CAN bus is arranged on the backplane bus. The centralized control terminal can parse the configuration file sent by the main control terminal for testing the MEMS chip to obtain a target test table, which includes multiple test items, and the centralized control terminal can broadcast clock synchronization instructions through the CAN bus when multiple measurement and control terminals are in a ready state, and control multiple measurement and control terminals to respectively execute corresponding test items when multiple measurement and control terminals receive the clock synchronization instructions respectively. In other words, the MEMS chip test system provided by the embodiment of the present disclosure constructs a high-speed backplane bus with high cost performance in hardware, and is based on the CAN bus broadcast communication method in software, which effectively reduces transmission delay and improves synchronization accuracy.

[0086] <Computer Readable Storage Medium>

[0087] The embodiment of the present disclosure further provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the MEMS chip testing method provided by the embodiment of the present disclosure is executed.

[0088] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0089] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0090] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0091] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0092] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0093] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0094] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0095] The flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of an instruction, and the module, a program segment or a part of an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of the boxes in the block diagram and / or the flowchart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0096] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present disclosure is defined by the appended claims.

Claims

1. A MEMS chip testing system, characterized in that: include: Master control terminal; A test unit, wherein the test unit comprises a centralized control terminal and a plurality of measurement and control terminals, the centralized control terminal is connected to the master control terminal, the plurality of measurement and control terminals and the centralized control terminal are connected to each other via a backplane bus, and a CAN bus is arranged on the backplane bus; The centralized control terminal is used to parse the configuration file sent by the master control terminal for testing the MEMS chip to obtain a target test table; wherein the target test table includes a plurality of test entries; and When the multiple measurement and control terminals are respectively in a ready state, a clock synchronization instruction is broadcasted through the CAN bus, and when the multiple measurement and control terminals respectively receive the clock synchronization instruction, the multiple measurement and control terminals are controlled to respectively execute the corresponding test items.

2. The MEMS chip testing system according to claim 1, characterized in that: The centralized control terminal is also used to broadcast a preparation instruction via the CAN bus; The multiple measurement and control terminals are used to execute initialization operations corresponding to the measurement and control terminals when the preparation instructions are received respectively.

3. The MEMS chip testing system according to claim 2, characterized in that: The multiple measurement and control terminals are used to send feedback instructions corresponding to the measurement and control terminals in a ready state to the centralized control terminal through the CAN bus when the operations corresponding to the measurement and control terminals are respectively initialized and completed; The centralized control end is further used to determine whether the corresponding measurement and control end is in a ready state when receiving the feedback instructions respectively sent by the multiple measurement and control ends.

4. The MEMS chip testing system according to claim 3, characterized in that: The backplane bus also includes an IO bus, the preparation instruction carries a signal type, and the signal type includes one of the following: an IO signal broadcasted through the IO bus and a CAN signal broadcasted through the CAN bus, When the multiple measurement and control terminals are used to send feedback instructions corresponding to the measurement and control terminals being in a ready state to the centralized control terminal through the CAN bus, the instruction type of the clock synchronization instruction to be waited for is determined according to the signal type carried in the ready instruction.

5. The MEMS chip testing system according to claim 4, characterized in that: The centralized control end is also used to use the IO signal broadcast through the IO bus as the clock synchronization instruction, or use the CAN signal broadcast through the CAN bus as the clock synchronization instruction when receiving the feedback instructions respectively sent by the multiple measurement and control ends.

6. The MEMS chip testing system according to claim 3, characterized in that: The backplane bus also includes a clock bus. The centralized control end is further used to synchronize the clocks corresponding to the multiple measurement and control ends respectively through the clock bus when receiving the feedback instructions respectively sent by the multiple measurement and control ends.

7. The MEMS chip testing system according to claim 1, characterized in that: The clock synchronization instruction is set as the instruction with the highest arbitration priority in the arbitration mechanism of the CAN bus.

8. A MEMS chip testing method, characterized in that: The MEMS chip testing system applied to any one of claims 1 to 7, the MEMS chip testing system comprising a master control terminal and a test unit, the test unit comprising a centralized control terminal and a plurality of measurement and control terminals, the master control terminal being connected to the master control terminal, the plurality of measurement and control terminals and the centralized control terminal being connected to each other via a backplane bus, a CAN bus being arranged on the backplane bus, the method comprising: The centralized control end parses the configuration file for testing the MEMS chip sent by the master control end to obtain a target test table; wherein the target test table includes a plurality of test entries; When the multiple measurement and control terminals are respectively in a ready state, the centralized control terminal broadcasts a clock synchronization instruction through the CAN bus, and when the multiple measurement and control terminals respectively receive the clock synchronization instruction, the multiple measurement and control terminals are controlled to respectively execute the corresponding test items.

9. A MEMS chip testing device, characterized in that: The MEMS chip testing system applied to any one of claims 1 to 7, the MEMS chip testing system comprising a master control terminal and a test unit, the test unit comprising a centralized control terminal and a plurality of measurement and control terminals, the master control terminal is connected to the master control terminal, the plurality of measurement and control terminals and the centralized control terminal are connected to each other via a backplane bus, a CAN bus is arranged on the backplane bus, and the device comprises: An acquisition module, configured to parse the configuration file for testing the MEMS chip sent by the central control terminal through the centralized control terminal to obtain a target test table; wherein the target test table includes a plurality of test entries; The control module is used to broadcast a clock synchronization instruction through the CAN bus through the centralized control terminal when the multiple measurement and control terminals are respectively in a ready state, and control the multiple measurement and control terminals to respectively execute the corresponding test items when the multiple measurement and control terminals respectively receive the clock synchronization instructions. 10 . A computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions are executed by a processor to execute the MEMS chip testing method according to claim 8 .

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