High-voltage-resistant field plate terminal plane gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a high-voltage-resistant field plate terminal plane gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type region, a first N-type region, a second N-type region, a P-type well region and an N-type source region; re-forming a barrier layer, etching and depositing to form a gate dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a source metal layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a field plate metal layer is formed; according to the preparation method, the terminal voltage endurance capability of the device is improved on the basis that the conduction characteristic of the device is not influenced.

Description

Technical Field

[0001] The invention relates to a high-voltage-withstand field plate terminal planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different emphases, but the overall requirements are higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability, etc.), and lower body diode conduction loss. In addition, on the basis that the device thickness meets the device voltage resistance, the problem of insufficient voltage resistance often occurs at the device terminal. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a high-voltage-withstand field plate terminal planar gate silicon carbide VDMOS and a preparation method thereof, by setting a field plate metal layer, a P-type region, a first N-type region and a second N-type region, the terminal voltage-withstand capability of the device is improved without affecting the conduction characteristics of the device.

[0004] In a first aspect, the present invention provides a method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a P-type region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first N-type region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a second N-type region; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a source metal layer; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 11: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a field plate metal layer; remove the barrier layer to complete the preparation.

[0005] In a second aspect, the present invention provides a high-voltage field plate terminal planar gate silicon carbide VDMOS, which is prepared by the preparation method of a high-voltage field plate terminal planar gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are: 1. The present invention constructs a structure of a P-type well region, a P-type region, a first N-type region, and a second N-type region. The doping concentration of the P-type region and the first N-type region is low, and the electric field strength is low. When the drain is subjected to a high voltage, the electric field concentrated at the corner of the P-type well region diffuses to the left and right sides, so that the electric field strength gradually decreases, forming a slowly varying electric field, avoiding breakdown due to electric field concentration, and improving the terminal withstand voltage capability; Second, the present invention constructs a field plate metal layer, which is connected to the source metal layer. When the drain is subjected to a large voltage, the field plate metal layer is at a low voltage relative to the drain, and a positive charge is formed under the field plate metal layer, which expands the electric field at the edge of the P-type well region, thereby reducing the electric field strength at the edge of the P-type well region, thereby improving the terminal withstand voltage capability of the device; 3. The present invention sets an insulating dielectric layer to improve the voltage resistance of the field plate metal layer, avoid the formation of a breakdown channel between the drain metal layer and the source metal layer in the second N-type region and the P-type region due to the drain voltage, and improve the reliability of the device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of the high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention is shown.

[0009] Figure 2 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0011] Figure 4This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0012] Figure 5 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0013] Figure 6 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0014] Figure 7 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0015] Figure 8 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0016] Fig. 9 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0017] Fig.10 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 9 .

[0018] Fig.11 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 10 .

[0019] Fig.12 This is a cross-sectional view of the process of a high-voltage field plate terminal planar gate silicon carbide VDMOS of the present invention Figure 10 one. DETAILED DESCRIPTION

[0020] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0023] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0024] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a high-voltage field plate terminal planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: forming a barrier layer 113 on the drift layer 102, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a P-type region 104; Step 3, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a first N-type region 105; Step 4, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a second N-type region 106; Step 5, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation into the drift layer 102 to form a P-type well region 103; Step 6: remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, and perform ion implantation into the P-type well region 103 to form an N-type source region 1031; Step 7, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing to form a gate dielectric layer 108; Step 8, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal, and forming a gate metal layer 110; Step 9, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal, and forming a source metal layer 111; Step 10, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and depositing to form an insulating dielectric layer 107; Step 11, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a field plate metal layer 109; remove the barrier layer 113, and complete the preparation.

[0026] In this embodiment, preferably, the width of the first N-type region 105 , the width of the P-type region 104 , and the width of the second N-type region 106 are all equal.

[0027] In this embodiment, preferably, the thickness of the field plate metal layer 109 is smaller than the thickness of the source metal layer 111 .

[0028] In this embodiment, preferably, the doping concentration of the first N-type region 105 is less than the doping concentration of the drift layer 102 .

[0029] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the second N-type region 106 .

[0030] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101; A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a protrusion 1021 is provided on the drift layer 102; A P-type well region 103, wherein the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the P-type well region 103 is connected to the outer side of the protrusion 1021; an N-type source region 1031 is disposed on the P-type well region 103; A P-type region 104, wherein a lower side of the P-type region 104 is connected to an upper side of the drift layer 102, and an inner side of the P-type region 104 is connected to an outer side of the P-type well region 103; A first N-type region 105 , wherein a lower side of the first N-type region 105 is connected to an upper side of the drift layer 102 , and an inner side of the first N-type region 105 is connected to an outer side of the P-type region 104 ; A second N-type region 106 , wherein a lower side of the second N-type region 106 is connected to an upper side of the drift layer 102 , and an inner side of the second N-type region 106 is connected to an outer side of the first N-type region 105 ; An insulating dielectric layer 107 , wherein a lower side of the insulating dielectric layer 107 is connected to the first N-type region 105 , the second N-type region 106 , and the P-type region 104 ; A gate dielectric layer 108, wherein the lower side of the gate dielectric layer 108 is connected to the upper side of the protrusion 1021, the upper side of the P-type well region 103, and the upper side of the N-type source region 1031; A field plate metal layer 109, wherein the lower side of the field plate metal layer 109 is connected to the upper side of the insulating dielectric layer 107; A gate metal layer 110 , wherein the lower side of the gate metal layer 110 is connected to the gate dielectric layer 108 ; A source metal layer 111 , wherein the source metal layer 111 is respectively connected to the P-type well region 103 , the N-type source region 1031 , the P-type region 104 and the field plate metal layer 109 ; and a drain metal layer 112 , wherein the drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101 .

[0031] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 6-10e16cm-3 , the doping concentration of the P-type well region 103 is 6-10e17cm -3 , the doping concentration of the P-type region 104 is 6-10e16cm -3 , the doping concentration of the first N-type region 105 is 1-5e16cm -3 , the doping concentration of the second N-type region 106 is 1-5e17cm -3 The insulating dielectric layer 107 and the gate dielectric layer 108 may be made of silicon dioxide, and the doping concentration of the N-type source region 1031 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 112, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the P-type region 104, the first N-type region 105, and the second N-type region 106 are to form a P-type well region 103-P-type region 104-first N-type region 105-second N-type region 106 structure at the terminal, thereby realizing the transition from the P-type well region 103 to low doping, so that when the device drain is subjected to a high voltage, the electric field is not concentrated at the edge of the P-type well 103, thereby realizing a gradual reduction transition of the electric field, thereby improving the reliability of the terminal; the insulating dielectric layer 10 7 and the field plate metal layer 109 are for when the drain of the device is connected to a high voltage, the field plate metal layer 109 is at a low level relative to the drain, and a P-type region 104 is formed under the insulating dielectric layer 107, so as to realize the expansion of the positive charge region to the edge on the basis of the P-type well region 103-P-type region 104 structure existing in the device structure itself; the field plate metal layer 109 is connected to the source metal layer 111, and when the body diode of the device is freewheeling, the field plate metal layer 109-insulating dielectric layer 107 structure of the device does not affect the body diode characteristics, thereby ensuring the freewheeling capability of the body diode of the device; the doping concentration of the N-type source region 1031 is for reducing the source contact resistance of the device and reducing the on-resistance of the device; The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form a low-resistance ohmic contact with the drain metal layer 112 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50-100 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device; the width of the P-type well region 103 of the device is 30% of the width of the drift layer 102, and the widths of the P-type region 104, the first N-type region 105 and the second N-type region 106 are all equal, which are all the widths of the drift layer 102. 5% of the width, which is a compromise between ensuring the low resistance characteristics of the device and the withstand voltage terminal of the device, so as to achieve both high withstand voltage and low resistance characteristics of the device; the thickness of the P-type well region 103 is 300nm, the thickness of the N-type source region 1031 is 200nm, the thickness of the P-type region 104, the first N-type region 105 and the second N-type region 106 are all 500nm, and the thickness of the insulating dielectric layer 107 is 200nm, which is to ensure that when the drain is subjected to a large voltage, there will be no breakdown problem from the drain to the field plate metal; The present invention constructs a P-type well region 103-P-type region 104-first N-type region 105-second N-type region 106 structure in the device. The P-type region 104 and the first N-type region 105 have low doping concentrations and low electric field strengths. When the drain of the device is subjected to a high voltage, the electric field concentrated at the corner of the P-type well 103 is diffused to the left and right sides, so that the electric field strength is gradually reduced to form a slowly varying electric field, thereby avoiding breakdown caused by electric field concentration and improving the terminal withstand voltage value; constructs a field plate metal layer 109, the field plate metal layer 109 is connected to the source metal layer 111, and the drain is When subjected to a large voltage, the field plate metal layer 109 is at a low voltage relative to the drain, and a positive charge will be formed under the field plate metal layer 109, thereby expanding the electric field at the edge of the P-type well region 103, thereby reducing the electric field strength at the edge of the P-type well region 103, and improving the terminal voltage resistance of the device; the thickness of the insulating dielectric layer 107 of the device is 200nm, which is to improve the voltage resistance of the field plate metal layer 109, avoid the formation of a breakdown channel between the drain metal layer 112 and the source metal layer 111 due to the drain voltage in the second N-type region 106 and the P-type region 104, and improve the reliability of the device structure.

[0032] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a P-type region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first N-type region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a second N-type region; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a source metal layer; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 11: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a field plate metal layer; remove the barrier layer to complete the preparation.

2. The method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the first N-type region, the width of the P-type region, and the width of the second N-type region are all equal.

3. The method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the field plate metal layer is smaller than the thickness of the source metal layer.

4. The method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first N-type region is lower than the doping concentration of the drift layer.

5. The method for preparing a high withstand voltage field plate terminal planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the drift layer is lower than the doping concentration of the second N-type region.

6. A high withstand voltage field plate terminal planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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