Low-resistance separation trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

Description

Technical Field

[0001] The invention relates to a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements for devices in different fields have different emphases, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability, etc.), and lower body diode conduction loss. In view of the increasing demand for high-frequency applications of silicon carbide VDMOS in module power supplies, the problem that the switching loss and body diode loss of VDMOS account for an increasing proportion of device power consumption, a solution is urgently needed. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a low-resistance separated trench gate silicon carbide VDMOS and a preparation method thereof, wherein a first gate metal layer, a second gate metal layer and a Schottky body diode are constructed inside the device to reduce the driving loss and body diode loss of the device.

[0004] In a first aspect, the present invention provides a method for preparing a low-resistance separated trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a low resistance region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the low resistance area to form a first groove and a second groove, and depositing to form a first insulating dielectric layer and a second insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first insulating dielectric layer and the second insulating dielectric layer to form a first trench and a second trench, depositing metal to form a first gate metal layer and a second gate metal layer respectively; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the low resistance area to form a third groove, depositing metal, and forming a first source metal layer; Step 9, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the P-type source region and the N-type source region, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

[0005] In a second aspect, the present invention provides a low-resistance separation trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a low-resistance separation trench gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are: 1. The present invention reduces the gate structure size of the device and reduces the gate-drain capacitance between the gate and the drain by providing the first gate metal and the second gate metal layer, thereby reducing the switching capacitance of the device and improving the switching speed of the device; Second, the first source metal layer is constructed in the middle of the device, thereby constructing a Schottky diode inside the device, which can reduce the conduction loss of the body diode of the device. At the same time, under the condition of lower source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed; 3. A heavily doped P-type source region is constructed outside the P-type well region of the device. The P-type source region has two functions. The first is to form a space charge region between the P-type source region and the drift layer. Due to the high doping concentration of the P-type source region, the space charge region mainly diffuses to the drift layer, and forms a space charge region on the first gate metal layer and the second gate metal layer of the device close to the P-type well region, thereby improving the device's drain-to-source and gate withstand voltage capability; the second is to form an ohmic contact with the second source metal layer, and perform auxiliary freewheeling when the Schottky diode freewheeling cannot meet the current demand, thereby improving the device's current capability; Fourth, the low resistance region is distributed directly below the first gate metal layer and the second gate metal layer, which can achieve electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of a low-resistance separated trench gate silicon carbide VDMOS of the present invention is shown.

[0009] Figure 2 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0011] Figure 4 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0012] Figure 5 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0013] Figure 6 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0017] Fig.10 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0018] Fig.11 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0019] Fig.12 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 10 one.

[0020] Fig.13 A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 10 two.

[0021] Fig.14A cross-sectional view of the process of a low-resistance separated trench gate silicon carbide VDMOS of the present invention Figure 10 three. DETAILED DESCRIPTION

[0022] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0024] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0025] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0026] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0027] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing a low-resistance separated trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 113; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: forming a barrier layer 114 on the drift layer 102, etching the barrier layer 114 to form a through hole, and performing ion implantation into the drift layer 102 to form a P-type source region 105; Step 3, removing the original barrier layer 114, re-forming the barrier layer 114, etching the barrier layer 114 to form a through hole, and performing ion implantation into the drift layer 102 to form a low resistance region 106; Step 4: remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a through hole, and perform ion implantation into the drift layer 102 to form a P-type well region 103; Step 5, removing the original barrier layer 114, re-forming the barrier layer 114, etching the barrier layer 114 to form a through hole, and performing ion implantation into the P-type well region 103 to form an N-type source region 104; Step 6, removing the original barrier layer 114, re-forming the barrier layer 114, etching the barrier layer 114 to form a through hole, etching the low resistance region 106 to form a first groove 115 and a second groove 116, and depositing to form a first insulating dielectric layer 107 and a second insulating dielectric layer 108; Step 7, removing the original barrier layer 114, re-forming the barrier layer 114, etching the barrier layer 114 to form a through hole, etching the first insulating dielectric layer 107 and the second insulating dielectric layer 108 to form a first trench 1071 and a second trench 1081, and depositing metal to form a first gate metal layer 109 and a second gate metal layer 110 respectively; Step 8, removing the original barrier layer 114, re-forming the barrier layer 114, etching the barrier layer 114 to form a through hole, etching the low resistance region 106 to form a third groove 117, depositing metal, and forming a first source metal layer 111; Step 9, remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a through hole, etch the P-type source region 105 and the N-type source region 104, deposit metal to form a second source metal layer 112, remove the barrier layer 114, and complete the preparation.

[0028] In this embodiment, preferably, the silicon carbide substrate 101 , the drift layer 102 and the low resistance region 106 are all N-type.

[0029] In this embodiment, preferably, the doping concentration of the low resistance region 106 is greater than the doping concentration of the drift layer 102 .

[0030] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the drift layer 102 ; the doping concentration of the P-type source region 105 is greater than the doping concentration of the N-type source region 104 ; and the doping concentration of the P-type source region 105 is greater than the doping concentration of the P-type well region 103 .

[0031] In this embodiment, preferably, the thickness of the left wall of the first insulating dielectric layer 107 is smaller than the thickness of the right wall.

[0032] In this embodiment, preferably, the thickness of the left wall of the second insulating dielectric layer 108 is greater than the thickness of the right wall.

[0033] like Figure 1 As shown, the VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101; A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, a protrusion 1021 is provided on the drift layer 102, and a groove 10211 is provided on the protrusion 1021; A P-type well region 103, wherein the lower side of the P-type well region 103 is connected to the upper side of the protrusion 1021; An N-type source region 104, wherein the lower side of the N-type source region 104 is connected to the upper side of the P-type well region 103; A P-type source region 105, wherein the P-type source region 105 is connected to the upper side of the drift layer 102; the inner side of the P-type source region 105 is connected to the outer side of the protrusion 1021, the outer side of the P-type well region 103 and the outer side of the N-type source region 104; A low resistance region 106, wherein the low resistance region 106 is disposed in the groove 10211; A first insulating dielectric layer 107, wherein the lower portion of the first insulating dielectric layer 107 is disposed in the groove 10211, and the lower side of the first insulating dielectric layer 107 is connected to the upper side of the low resistance region 106, and one side of the first insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104; a first trench 1071 is disposed in the first insulating dielectric layer 107; A second insulating dielectric layer 108, wherein the lower portion of the second insulating dielectric layer 108 is disposed in the groove 10211, and the lower side of the second insulating dielectric layer 108 is connected to the upper side of the low resistance region 106, and one side of the second insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104; a second trench 1081 is disposed in the second insulating dielectric layer 108; A first gate metal layer 109, wherein the first gate metal layer 109 is disposed in the first trench 1071; A second gate metal layer 110, wherein the second gate metal layer 110 is disposed in the second trench 1081; A first source metal layer 111, wherein the lower portion of the first source metal layer 111 is disposed in the groove 10211, and the lower side of the first source metal layer 111 is connected to the upper side of the low resistance region 106, and the side of the first source metal layer 111 is respectively connected to the other side of the first insulating dielectric layer 107 and the other side of the second insulating dielectric layer 108; A second source metal layer 112, wherein the second source metal layer 112 is respectively connected to the P-type source region 105 and the N-type source region 104; and a drain metal layer 113 , wherein the drain metal layer 113 is connected to the lower side of the silicon carbide substrate 101 .

[0034] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 6-10e16cm -3 , the doping concentration of the N-type low resistance region 106 is 6-10e17cm -3 , the doping concentration of the P-type well region 103 is 6-10e16cm -3 , the doping concentration of the P-type source region 105 is 1-5e19cm -3 The materials of the first insulating dielectric layer 107 and the second insulating dielectric layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 104 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 113, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the P-type well region 103 is to achieve the withstand voltage of the pn junction of the device when the drain of the device is subjected to a high voltage; the doping concentration of the P-type source region 105 is to form a space charge region mainly diffused toward the N-type drift layer 102 with the N-type drift layer 102, so as to protect the device P-type well 103, the first gate metal layer 109 and the second gate metal layer 110 from being subjected to a large voltage at the drain; at the same time The P-type source region 105 also needs to achieve ohmic contact with the second source metal layer 112, so as to complete the supplement of the device current capacity under the condition that the device parasitic Schottky body diode is insufficient to continue the current, thereby improving the device current capacity; the doping concentration of the N-type low resistance region 106 is to form a Schottky contact with the first source metal 111, reduce the body diode conduction voltage drop of the device and ensure reverse withstand voltage; the N-type low resistance region 106 also needs to achieve electric field shielding of the device gate and drain, thereby reducing the gate-drain capacitance of the device and improving the switching speed of the device; the doping concentration of the N-type source region 104 is to reduce the source contact resistance of the device and reduce the on-resistance of the device; The thickness of the N-type silicon carbide substrate 101 is 1 μm, which is to form a low-resistance ohmic contact with the drain metal layer 113 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50-100 μm, which is adjusted within the above range according to the different requirements for the device's withstand voltage characteristics; the thickness of the second source metal layer 112 is 300 nm, the thickness of the first source metal layer 111 is 700 nm, the thickness of the P-type source region 105 is 600 nm, and the width is 500 nm; the N-type source region 1 04 has a thickness of 100nm, the P-type well region 103 has a thickness of 200nm, the N-type low resistance region 106 has a thickness of 200nm and a width of 3μm, the bottom thickness of the first insulating dielectric layer is 100nm and a width of 1μm, the sidewall width close to the P-type well region 103 is 50nm, and the sidewall width away from the P-type well region 103 is 100nm, the first gate metal layer 109 and the second gate metal layer 110 are both 600nm thick and 850nm wide; In this embodiment, the first gate metal layer 109 and the second gate metal layer 110 are arranged separately, thereby reducing the gate structure size of the device, reducing the gate-drain capacitance between the gate and the drain of the device, thereby reducing the switching capacitance of the device and improving the switching speed of the device; the N-type low resistance region 106 of the device is located directly below the first gate metal layer 109 and the second gate metal layer 110, which can achieve electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device.

[0035] A first source metal layer 111 is constructed, thereby constructing a Schottky diode inside the device, reducing the conduction loss of the body diode of the device. At the same time, under the condition of lower source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed. A heavily doped P-type source region 105 is constructed outside the P-type well region 103 of the device. The P-type source region 105 has two functions: first, the P-type source region 105 and the N-type drift layer 102 form a space charge region. Since the doping concentration of the P-type source region 105 is high, the space charge region mainly diffuses to the N-type drift layer 102, and forms a space charge region on the first gate metal layer 109 and the second gate metal layer 110 of the device near the P-type well region 103, so as to improve the device's drain-to-source and gate withstand voltage capabilities. Second, an ohmic contact is formed with the second source metal layer 112, and auxiliary freewheeling is performed when the Schottky body diode freewheeling cannot meet the current demand, thereby improving the current capability of the device.

[0036] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low-resistance separated trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a low resistance region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the low resistance area to form a first groove and a second groove, and depositing to form a first insulating dielectric layer and a second insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first insulating dielectric layer and the second insulating dielectric layer to form a first trench and a second trench, depositing metal to form a first gate metal layer and a second gate metal layer respectively; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the low resistance area to form a third groove, depositing metal, and forming a first source metal layer; Step 9, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the P-type source region and the N-type source region, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer and low resistance region are all N-type.

3. The method for preparing a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the low resistance region is greater than the doping concentration of the drift layer.

4. The method for preparing a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the drift layer; the doping concentration of the P-type source region is greater than the doping concentration of the N-type source region; the doping concentration of the P-type source region is greater than the doping concentration of the P-type well region.

5. The method for preparing a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the left wall of the first insulating medium layer is smaller than the thickness of the right wall.

6. The method for preparing a low-resistance separated trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the left wall of the second insulating medium layer is greater than the thickness of the right wall.

7. A low-resistance separated trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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