A semi-superjunction laterally isolated planar-gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS and a manufacturing method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing to obtain a first drift region; forming a first source region by ion implantation; depositing to form a first insulating dielectric layer; epitaxially growing to form a second drift region, where the drift layer includes the first drift region and the second drift region; forming a second source region by ion implantation, and the P-type source region includes the first source region and the second source region; depositing to form a second insulating dielectric layer, and the insulating dielectric region includes the first insulating dielectric layer and the second insulating dielectric layer; reforming a barrier layer, etching, and forming a column region, a P-type well region, a protrusion portion, and an N-type source region by ion implantation; reforming a barrier layer, etching, and depositing to form a gate dielectric layer; reforming a barrier layer, etching, and depositing metal to form a gate metal layer and a source metal layer; effectively improving the breakdown voltage capability of the device and reducing the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS and a manufacturing method thereof. Background Art

[0002] As a high-performance power semiconductor device, silicon carbide (SiC) VDMOS has been widely used in fields such as electric vehicles, aerospace, and power conversion due to its high breakdown voltage, low on-resistance, fast switching speed, and high reliability. However, traditional SiC VDMOS devices still face some technical bottlenecks in the design and manufacturing processes, mainly including the following points:

[0003] Contradiction between breakdown voltage and on-resistance: To improve the breakdown voltage of the device, the thickness of the drift region usually needs to be increased, but this will lead to a significant increase in on-resistance, thereby reducing the device efficiency.

[0004] Insufficient optimization of the terminal structure: In high-voltage applications, the terminal structure of the device needs to withstand a large electric field stress, and it is difficult for traditional designs to effectively optimize the terminal structure to improve the breakdown voltage.

[0005] Lateral diffusion problem: Under high-voltage conditions, the lateral diffusion of the pn junction of the device may lead to an increase in leakage current, affecting the stability and reliability of the device. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS and a manufacturing method thereof, which constructs a semi-superjunction structure and a lateral isolation structure inside the device, can effectively improve the breakdown voltage of the device under fixed thickness and area conditions, reduce the on-resistance of the device, and the insulating dielectric region can effectively improve the reliability and breakdown voltage.

[0007] In a first aspect, the present invention provides a manufacturing method of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS, including the following steps:

[0008] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the silicon carbide substrate to obtain a first drift region;

[0009] Step 2: Form a blocking layer above the first drift region, etch the blocking layer to form a through hole, and perform ion implantation on the first drift region to form a first source region;

[0010] Step 3: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, etch the first drift region to the upper side of the silicon carbide substrate, and deposit to form a first insulating dielectric layer;

[0011] Step 4: Remove the blocking layer and epitaxially grow to form a second drift region. The drift layer includes a first drift region and a second drift region;

[0012] Step 5: Form a blocking layer above the second drift region, etch the blocking layer to form a through hole, and perform ion implantation to form a second source region. The P-type source region includes a first source region and a second source region;

[0013] Step 6: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the second drift region to the upper side of the first insulating dielectric layer, and deposit to form a second insulating dielectric layer. The insulating dielectric region includes a first insulating dielectric layer and a second insulating dielectric layer;

[0014] Step 7: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the drift layer to form a column region;

[0015] Step 8: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region and a protrusion;

[0016] Step 9: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region;

[0017] Step 10: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a gate dielectric layer;

[0018] Step 11: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal, and form a gate metal layer;

[0019] Step 12: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal, form a source metal layer, and remove the blocking layer to complete the preparation.

[0020] In a second aspect, the present invention provides a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS, which is prepared by using the preparation method of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS described in the first aspect.

[0021] The advantages of the present invention are as follows:

[0022] First, the present invention realizes the semi-superjunction device structure of the device by constructing a column region in the device, thereby improving the breakdown voltage of the device, reducing the on-resistance of the device, and at the same time reducing the process difficulty;

[0023] Second, the present invention constructs an insulating dielectric region, i.e., a side isolation structure, which can isolate the diffusion region of the device during the pn lateral diffusion process when the drain of the device is subjected to a high voltage, thereby improving the withstand voltage capability of the device and optimizing the terminal structure of the device through the withstand voltage of the insulating dielectric region;

[0024] 3. The present invention solves the contradiction between increasing the withstand voltage of the device and reducing the on-resistance by designing the semi-super junction structure and the side isolation structure of the device, thereby effectively improving the performance of the device;

[0025] Fourth, the present invention adopts a two-step deposition and etching process, thereby solving the problem of difficult control of the accuracy of the deep etching process in the process of preparing the insulating dielectric area and optimizing the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0027] Figure 1 The schematic diagram of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS of the present invention is shown.

[0028] Figure 2 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 1 .

[0029] Figure 3 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 2 .

[0030] Figure 4 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 3 .

[0031] Figure 5 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 4 .

[0032] Figure 6 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 5 .

[0033] Figure 7 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 6 .

[0034] Figure 8 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 7 .

[0035] Figure 9Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 8 。

[0036] Figure 10 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 9 。

[0037] Figure 11 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 。

[0038] Figure 12 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 I.

[0039] Figure 13 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 II.

[0040] Figure 14 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 III.

[0041] Figure 15 Process cross-section of a semi-superjunction laterally isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 IV. Detailed implementation manners

[0042] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0045] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0046] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0047] As Figures 1 to 15 shown, an embodiment of the present application provides a method for preparing a semi-superjunction lateral isolation planar gate silicon carbide VDMOS, including the following steps:

[0048] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form the drain metal layer 9; epitaxially grow on the silicon carbide substrate 1 to obtain the first drift region 23;

[0049] Step 2: Form a barrier layer a above the first drift region 23, etch the barrier layer a to form a through hole, and perform ion implantation into the first drift region 23 to form the first source region 51;

[0050] Step 3: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, etch the first drift region 23 to the upper side of the silicon carbide substrate 1, and deposit to form the first insulating dielectric layer 41;

[0051] Step 4: Remove the barrier layer a, epitaxially grow to form the second drift region 24, and the drift layer 2 includes the first drift region 23 and the second drift region 24;

[0052] Step 5: Form a barrier layer a above the second drift region 24, etch the barrier layer a to form a through hole, and perform ion implantation to form the second source region 52. The P-type source region 5 includes the first source region 51 and the second source region 52; the graphic structures of the first source region 51 and the second source region 52 are the same, and the same photolithography mask can be used for two lithography processes, reducing the device process cost;

[0053] Step 6: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, etch the second drift region 24 to the upper side of the first insulating dielectric layer 41, and deposit to form the second insulating dielectric layer 42. The insulating dielectric region 4 includes the first insulating dielectric layer 41 and the second insulating dielectric layer 42; the graphic structures of the first insulating dielectric layer 41 and the second insulating dielectric layer 42 are the same, and the same photolithography mask can be used for two lithography processes, reducing the device process cost;

[0054] Step 7: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the drift layer 2 to form the column region 21;

[0055] Step 8: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the drift layer 2 to form the P-type well region 3 and the protrusion 22;

[0056] Step 9: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the P-type well region 3 to form the N-type source region 31;

[0057] Step 10: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and deposit to form the gate dielectric layer 6;

[0058] Step 11: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and deposit metal to form the gate metal layer 7;

[0059] Step 12: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form the source metal layer 8, and remove the barrier layer a to complete the preparation.

[0060] In this embodiment, preferably, the silicon carbide substrate 1 and the drift layer 2 are both of N type, and the column region 21 is of P type.

[0061] In this embodiment, preferably, the thickness of the column region 21 is 40%-60% of the thickness of the drift layer 2.

[0062] In this embodiment, preferably, the doping concentration of the column region 21 is greater than the doping concentration of the drift layer 2.

[0063] In this embodiment, preferably, the doping concentration of the P-type source region 5 is greater than the doping concentration of the drift layer 2.

[0064] In this embodiment, preferably, the width of the insulating dielectric region 4 is 2-5 μm.

[0065] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0066] A silicon carbide substrate 1,

[0067] A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a column region 21 and a protrusion 22 are provided in the drift layer 2;

[0068] A P-type well region 3, the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the column region 21, and the inner side of the P-type well region 3 is connected to the outer side of the protrusion 22; an N-type source region 31 is provided in the P-type well region 3;

[0069] An insulating dielectric region 4, the lower side of the insulating dielectric region 4 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the insulating dielectric region 4 is connected to the outer side of the drift layer 2 and the outer side of the P-type well region 3;

[0070] A P-type source region 5, the lower side of the P-type source region 5 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the P-type source region 5 is connected to the outer side of the insulating dielectric region 4;

[0071] A gate dielectric layer 6, the lower side of the gate dielectric layer 6 is connected to the upper side of the protrusion 22 and the upper side of the P-type well region 3;

[0072] A gate metal layer 7, the lower side of the gate metal layer 7 is connected to the upper side of the gate dielectric layer 6;

[0073] The source metal layer 8, and the source metal layer 8 is respectively connected to the P-type source region 5, the insulating dielectric region 4, the P-type well region 3, and the N-type source region 31;

[0074] And, the drain metal layer 9, and the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1.

[0075] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 1 - 5e17 cm -3 , the doping concentration of the P-type source region 5 is 1 - 5e18 cm -3 , the insulating dielectric region 4 can be one or a composite of silicon dioxide and silicon nitride, the doping concentration of the P-type column region 21 is 6 - 12e17 cm -3 , the doping concentration of the P-type well region is 5 - 8e17 cm -3 , the gate dielectric layer 6 can be silicon dioxide, the doping concentration of the N-type source region 31 is 2 - 8e18 cm -3 ;

[0076] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, and at the same time ensure the construction of a pn junction with the P-type source region 5 to achieve the reverse breakdown voltage of the device and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse breakdown voltage and the on-resistance of the device, and the insulating dielectric region 4 is to achieve the lateral truncation of the electric field in the device terminal region to the left and right sides, improving the device breakdown voltage; the P-type column region 21 and the N-type drift layer 2 form a semi-superjunction structure of the device, realizing the comprehensive longitudinal and lateral breakdown voltage of the pn junction of the device, improving the breakdown voltage ability of the device while reducing the on-resistance of the device; the P-type well region 3 is the basis for constructing the gate switching structure of the device, and the doping concentration of the N-type source region 31 is to reduce the contact resistance of the source metal layer 8 of the device, thereby reducing the on-resistance of the device;

[0077] The thickness of the N-type silicon carbide substrate 1 of the device is 5 μm, which is for forming a pn junction breakdown voltage structure with the P-type source region 5 to ensure the breakdown voltage capacity of this region; the thickness of the N-type drift layer 2 is 50 - 100 μm (including the thickness of the protruding portion 22), and it is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the P-type pillar region 21 is 40 - 60% of the thickness of the N-type drift layer 2 to achieve longitudinal breakdown voltage at the bottom of the device and a combination of transverse and longitudinal breakdown voltage at the top while reducing the process difficulty; the width of the insulating dielectric region 4 is 2 - 5 μm. This is because under the condition that the etching depth is about 50 μm, the etching depth-to-width ratio process is difficult, so the margin is increased from the device structure design to improve the device yield; the width of the P-type source region 5 is 2 - 10 μm, the thickness of the contact region between the top of the P-type well region 3 and the source metal layer 8 is 500 nm, the thickness of the N-type source region 31 is 200 nm, and the width of the N-type source region 31 is 10% of the width of the drain metal layer 9; the thickness of the source metal layer 8 is 200 nm, and the thickness of the gate metal layer 7 is 150 nm;

[0078] In addition to achieving the isolation of the device terminal, the insulating dielectric region 4 also realizes the isolation of the P-type source region 5, the N-type drift layer 2, and the P-type well region 3, which can overcome the problem of mutual diffusion and improve the stability and reliability of the device;

[0079] In this embodiment, a semi-superjunction device structure of the device is realized by constructing a P-type pillar region 21 in the device, thereby improving the breakdown voltage capacity of the device, reducing the on-resistance of the device, and reducing the process difficulty at the same time. Insulating dielectric regions, that is, side isolation structures, are constructed on the left and right sides of the device. This structure can achieve the isolation of the diffusion region of the device during the pn lateral diffusion process when the drain of the device bears a high voltage. By the breakdown voltage of the insulating dielectric region 4, the breakdown voltage capacity of the device is improved, and the terminal structure of the device is optimized. Through the design of the semi-superjunction structure and the side isolation structure of the device, the contradiction between the improvement of the breakdown voltage and the reduction of the on-resistance of the device is solved, and the performance of the device is effectively improved.

[0080] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative only and not used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.

Claims

1. A method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to obtain a first drift region; Step 2, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and performing ion implantation into the first drift region to form a first source region; Step 3, removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first drift region to the upper side of the silicon carbide substrate, and depositing to form a first insulating dielectric layer; Step 4, removing the barrier layer of step 3, and forming a second drift region by epitaxial growth, wherein the drift layer includes the first drift region and the second drift region; Step 5, forming a barrier layer above the second drift region, etching the barrier layer to form a through hole, and implanting ions to form a second source region, wherein the P-type source region includes a first source region and a second source region; Step 6, removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift region to the upper side of the first insulating dielectric layer, and depositing to form a second insulating dielectric layer, wherein the insulating dielectric region includes the first insulating dielectric layer and the second insulating dielectric layer; Step 7, removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a pillar region; Step 8, removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type well region and a protruding portion; Step 9, removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 10, removing the barrier layer of step 9, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 11, removing the barrier layer of step 10, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 12, removing the barrier layer of step 11, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal to form a source metal layer, removing the barrier layer, and completing the preparation; The lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a column area and a protrusion are provided in the drift layer; the lower side of the P-type well area is connected to the upper side of the drift layer and the upper side of the column area, and the inner side of the P-type well area is connected to the outer side of the protrusion; an N-type source area is provided in the P-type well area; the lower side of the insulating dielectric area is connected to the upper side of the silicon carbide substrate, and the inner side of the insulating dielectric area is connected to the outer side of the drift layer and the outer side of the P-type well area; the lower side of the P-type source area is connected to the upper side of the silicon carbide substrate, and the inner side of the P-type source area is connected to the outer side of the insulating dielectric area; the lower side of the gate dielectric layer is connected to the upper side of the protrusion and the upper side of the P-type well area; the lower side of the gate metal layer is connected to the upper side of the gate dielectric layer; the source metal layer is respectively connected to the P-type source area, the insulating dielectric area, the P-type well area and the N-type source area; the drain metal layer is connected to the lower side of the silicon carbide substrate.

2. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate and the drift layer are both N-type, and the column region is P-type.

3. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the column region is 40-60% of the thickness of the drift layer.

4. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the column region is greater than the doping concentration of the drift layer.

5. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the drift layer.

6. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the insulating dielectric region is 2-5 μm.

7. A semi-superjunction side-isolated planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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