A power device and its application and manufacturing method

Abstract

The present invention discloses a power device and its application and manufacturing method, wherein the power device comprises: a substrate; a channel layer, arranged on the substrate; a barrier layer, arranged on the channel layer; a first gallium nitride layer, arranged on the barrier layer and covering the barrier layer; a second gallium nitride layer, arranged on the first gallium nitride layer; a third gallium nitride layer, arranged on the second gallium nitride layer; a first drain, arranged on the third gallium nitride layer; a first source, arranged on the third gallium nitride layer, and a concave portion is formed between the first source and the first drain; and a first gate, arranged on the barrier layer, and the first gate covers the concave portion, and the first source and the first drain are close to the top of the concave portion; wherein the second gallium nitride layer and the third gallium nitride layer are located between the source and the drain and the barrier layer. The power device provided by the present invention can improve the quality of integrated power devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a power device and an application and manufacturing method thereof. Background Art

[0002] As a wide bandgap semiconductor, gallium nitride has the characteristics of high breakdown electric field, high electron saturation velocity and mobility, so gallium nitride-based power devices can be used for the preparation of a new generation of high-power converters. The current gallium nitride-based power devices are lateral heterojunction AlGaN / GaN high electron mobility transistor devices. Due to the low hole mobility in gallium nitride, it is difficult to achieve high P-type doping in the material, and the lack of monolithic complementary P-type field effect transistors (Field Effect Transistor, FET), it is difficult to form integrated high-performance logic circuits and reverse amplifier stages. Summary of the invention

[0003] The object of the present invention is to provide a power device and its application and manufacturing method. Through the power device and its application and manufacturing method provided by the present invention, a monolithic integrated device with a field effect transistor is provided.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides a power device, which at least comprises:

[0006] The power device includes a first device, and the first device includes:

[0007] substrate;

[0008] A channel layer is disposed on the substrate;

[0009] A barrier layer, disposed on the channel layer;

[0010] A first gallium nitride layer is disposed on the barrier layer and covers the barrier layer;

[0011] A second gallium nitride layer, disposed on the first gallium nitride layer;

[0012] A third gallium nitride layer, disposed on the second gallium nitride layer;

[0013] A first drain electrode is disposed on the third gallium nitride layer;

[0014] a first source electrode, disposed on the third gallium nitride layer, with a recess formed between the first source electrode and the first drain electrode; and

[0015] A first gate is disposed on the barrier layer, and the first gate covers the concave portion, and the first source and the first drain are close to the top of the concave portion;

[0016] The second gallium nitride layer and the third gallium nitride layer are located between the source electrode, the drain electrode and the barrier layer.

[0017] Optionally, the power device further includes a buffer layer formed on the substrate, and the buffer layer is an aluminum nitride buffer layer.

[0018] Optionally, the first gallium nitride layer is an unintentionally doped gallium nitride layer.

[0019] Optionally, the second gallium nitride layer is a doped P-type gallium nitride layer, and the doping concentration is 1e19cm-3-2e19cm-3.

[0020] Optionally, the third gallium nitride layer is a heavily doped P-type gallium nitride layer and has a doping concentration of 5e19cm-3-6e19cm-3.

[0021] Optionally, the power device further includes an oxide layer, wherein the oxide layer is disposed between the gate and the first gallium nitride layer, and the oxide layer covers the recess and the bottom of the source and the drain.

[0022] Optionally, the gate includes a nickel metal layer and a gold metal layer disposed on the nickel metal layer.

[0023] Optionally, the power device further includes a second device, and the second device and the first device are isolated by an isolation trench, and the isolation trench passes through the multi-layer gallium nitride layer and the barrier layer and extends into the channel layer.

[0024] Optionally, the second device includes:

[0025] A mesa structure is disposed on the barrier layer, and the mesa structure includes the first gallium nitride layer, the second gallium nitride layer and the third gallium nitride layer disposed in sequence;

[0026] A second source electrode is disposed on the channel layer and located on one side of the mesa structure;

[0027] a second drain electrode, disposed on the channel layer and located on the other side of the mesa structure; and

[0028] The second grid is arranged on the mesa structure.

[0029] The present invention also provides a method for manufacturing a power device, comprising:

[0030] providing a substrate;

[0031] forming a channel layer on the substrate;

[0032] forming a barrier layer on the channel layer;

[0033] forming a first gallium nitride layer, a second gallium nitride layer and a third gallium nitride layer in sequence on the barrier layer;

[0034] etching the third gallium nitride layer and the second gallium nitride layer to form a concave portion;

[0035] forming a first source electrode and a first drain electrode on the third gallium nitride layer at both sides of the concave portion; and

[0036] A first gate is formed in the concave portion, and the first source and the first drain are formed near a top of the concave portion.

[0037] The present invention also provides an electronic device, comprising the power device described above

[0038] As described above, the present invention provides a power device and its application and manufacturing method, which uses a GaN / AlGaN heterojunction structure to generate a two-dimensional hole gas, so that the P-type gallium nitride has a lower hole mobility. Since the hole has a higher effective mass, the source-drain spacing can be reduced to compensate for the lack of hole mobility, thereby improving the quality of the integrated power device. In addition, the heavily doped gallium nitride layer can form a good ohmic contact with the electrode, and the undoped gallium nitride layer can separate the P-type gallium nitride layer and the barrier layer, further improving the hole mobility here.

[0039] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0041] Figures 1 to 6 A diagram of the manufacturing process of a semiconductor device.

[0042] Figures 7 to 11 A diagram of the manufacturing process of a P-type field effect transistor.

[0043] Fig.12 It is a schematic diagram of the structure of a monolithically integrated semiconductor device having a P-type field effect transistor.

[0044] Figures 13 to 24Schematic diagram of the structure of monolithically integrated metal-oxide semiconductor field-effect transistor and high electron mobility transistor.

[0045] Fig.25 for Fig.24 Equivalent circuit diagram of .

[0046] Fig.26 It is a half-bridge circuit diagram.

[0047] Fig. 27 This is the equivalent circuit diagram of a half-bridge circuit without an isolation slot.

[0048] Fig.28 This is the equivalent circuit diagram of a half-bridge circuit with an isolation slot.

[0049] Figures 29 to 36 A diagram showing the manufacturing process of a half-bridge circuit with an isolation groove.

[0050] Fig.37 It is a semiconductor epitaxial structure.

[0051] Fig.38 Flowchart for cleaning GaN epitaxy.

[0052] Fig.39 Flowchart for cleaning GaN epitaxial after etching.

[0053] Fig.40 A diagram of an apparatus for processing semiconductor structures using supercritical gases. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] See also Figures 1 to 36 As shown, the semiconductor device or monolithically integrated semiconductor device provided by the present invention includes a substrate 100, an epitaxial structure arranged on the substrate 100, and a source 107, a drain 108 and a gate 109 arranged on the epitaxial structure. The epitaxial structure includes a heterostructure formed by gallium nitride and aluminum gallium nitride (GaN / AlGaN). In the present application, the semiconductor device is, for example, a semiconductor power device.

[0056] See also Figure 1As shown, in one embodiment of the present invention, the substrate 100 may be a silicon substrate, such as silicon (Si) or silicon carbide (SiC). In other embodiments, the substrate 100 may also be sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), gallium nitride (GaN) or other semiconductor substrate materials. After the substrate 100 is formed, a buffer layer 101 may be formed between the substrate 100 and the epitaxial structure by chemical vapor deposition or metal organic chemical vapor deposition to improve the lattice matching between the substrate 100 and the epitaxial structure, and the material of the buffer layer 101 may be, for example, one or more of gallium nitride, aluminum gallium nitride or aluminum nitride. In the present embodiment, the buffer layer 101 may be, for example, an aluminum nitride buffer layer, and the thickness of the buffer layer 101 may be, for example, 1-4um, specifically, for example, 1um.

[0057] See also Figure 1 As shown, in one embodiment of the present invention, the epitaxial structure includes a channel layer 102 disposed on a buffer layer 101, and a barrier layer 103 disposed on the channel layer 102. The channel layer 102 is disposed on the buffer layer 101, and for example, 3-6 um gallium nitride can be grown on the buffer layer 101 to form the channel layer 102. In this embodiment, the thickness of the channel layer 102 is, for example, 4 um. The barrier layer 103 is formed on the channel layer 102, and the barrier layer 103 is, for example, an aluminum gallium nitride layer, and the material of the barrier layer 103 is, for example, Al 0.23 Ga 0.77 N. The thickness of the barrier layer 103 is, for example, 20-30 nm, specifically, for example, 25 nm. In this embodiment, a gate opening 1041 is also provided on the barrier layer 103 to deposit the gate 109. In this embodiment, the channel layer 102 and the barrier layer 103 can be prepared by chemical vapor deposition or metal organic chemical vapor deposition.

[0058] See also Figures 1 to 37 As shown, in one embodiment of the present invention, for the epitaxial structure with gallium nitride / aluminum gallium nitride (GaN / AlGaN) provided by the present invention, and the semiconductor device made of the epitaxial structure. During the manufacturing process, multiple cleanings are required to improve the surface roughness and epitaxial defects, thereby ensuring the stability of the metal contact resistance and the reliability of the GaN device. First, after forming the channel layer 102 made of gallium nitride, the silicon-based gallium nitride epitaxial wafer can be cleaned, and the silicon-based gallium nitride epitaxial wafer can be cleaned multiple times with deionized water to remove large particles attached to the surface of gallium nitride. Specifically, for example, the gallium nitride epitaxial wafer can be cleaned with deionized water twice.

[0059] See also Figures 1 to 38As shown, in one embodiment of the present invention, after forming the aluminum gallium nitride barrier layer 103 and before growing a gate dielectric layer such as silicon nitride, the surface of the barrier layer 103 is cleaned to eliminate interface defects on the AlGaN / SiNx surface. First, RCA cleaning is performed, specifically, for example, steps S10-S15 are performed, and for example, 2% hydrofluoric acid (HF) can be used for cleaning for 100 seconds, and then ultrapure water can be used for cleaning for 600 seconds, and then the first solution SC1 can be used for cleaning for 600 seconds. The first solution SC1 is, for example, a mixture of water (H2O), hydrogen peroxide (H2O2) and ammonia (NH4OH) in a certain proportion, and the proportion of each component in the first solution is, for example, H2O:H2O2:NH4OH=5:1:1. After cleaning with the first solution SC1, ultrapure water is used for cleaning for 600 seconds, and then the second solution SC2 is used for cleaning for 600 seconds. The second solution SC2 is, for example, a solution formed by mixing water (H2O), hydrogen peroxide (H2O2) and hydrochloric acid (HCl) in a certain proportion, and the proportion of each component in the second solution SC2 is, for example, H2O:H2O2:HCl=6:1:1. The first solution SC1 and the second solution SC2 can remove surface ions and organic contamination, and improve the roughness of the surface of the epitaxial structure. After cleaning with the second solution SC2, ultrapure water can be used for cleaning, for example, for 600 seconds. After RCA cleaning, for example, steps S16-S18 are performed, and for example, 2% hydrofluoric acid (HF) is used for cleaning, for example, for 100 seconds, and then ultrapure water is used for cleaning, for example, for 600 seconds, and then dried. Cleaning with hydrofluoric acid (HF) solution again can ensure that the surface of the gallium nitride epitaxial surface will not have residual oxides due to the hydrogen peroxide (H2O2) solution.

[0060] See also Figures 1 to 39 As shown, in one embodiment of the present invention, in this embodiment, after etching the channel layer 102 and the barrier layer 103, for example, after forming a gate opening, a source opening or a drain opening, the etched area may be cleaned. Fig.39 As shown in step S20 to step S25, for example, isopropyl alcohol (IPA) may be used to clean for 600 seconds, and then ultrapure water may be used to clean for 600 seconds. Then, propanol (ACE) may be used to clean for 600 seconds, and then ultrapure water may be used to clean for 600 seconds. Finally, 2% hydrofluoric acid (HF) may be used to clean for 100 seconds, and then ultrapure water may be used to clean for 600 seconds, and then the surface may be dried.

[0061] See also Figures 2 to 3As shown, in one embodiment of the present invention, a gate dielectric layer may also be provided in the semiconductor device to reduce the threshold voltage hysteresis phenomenon. Specifically, in the present embodiment, the gate dielectric layer includes a passivation layer 105 and an oxide layer 106 provided on the barrier layer 103, and the passivation layer 105 is, for example, an aluminum nitride layer provided on the barrier layer 103. In the present embodiment, the passivation layer 105 is, for example, deposited and formed by plasma enhanced atomic layer deposition (PEALD). The oxide layer 106 is, for example, an aluminum oxide layer provided on the aluminum nitride layer, and is, for example, deposited and formed by atomic layer deposition (ALD), and the passivation layer 105 and the oxide layer 106 cover the barrier layer 103 and the gate opening 1041 on the barrier layer 103. Among them, the thickness of the passivation layer 105 is, for example, 1-5nm, and specifically, for example, it may be 2nm. The thickness of the oxide layer 106 is, for example, 5-10nm, and specifically, for example, 8nm. After the oxide layer 106 is formed, the passivation layer 105 and the oxide layer 106 are annealed in an N2 environment at a temperature of, for example, 300-500° C. to improve the quality of the gate dielectric layer.

[0062] See also Figures 2 to 6 As shown, since the AlN material of the passivation layer 105 has a higher bandgap width and higher thermal conductivity efficiency, the blocking ability of the gate dielectric to the leakage current and the interface quality with gallium nitride can be improved. When the bandgap width and the conduction band offset are large, the electrons can be suppressed from passing through the dielectric layer, reducing the gate leakage. Since aluminum nitride and gallium nitride have good lattice matching and thermal conductivity characteristics, the aluminum nitride in the passivation layer 105 is in direct contact with gallium nitride, which can improve the interface quality. At the same time, in this embodiment, aluminum nitride and aluminum oxide are used as gate insulating dielectrics, and the aluminum nitride layer made by PEALD can reduce the interface defects between the oxide layer 106 and gallium nitride, reduce the leakage current of the gate 109, and improve the stability and reliability of the gate 109, so that the semiconductor device has a lower threshold voltage hysteresis. It can avoid the phenomenon of threshold voltage hysteresis caused by the deep energy level traps at the interface between the oxide layer 106 and the barrier layer 103 capturing channel electrons under a large forward gate voltage, thereby improving the stability of the threshold voltage.

[0063] See also Figure 1 , Figures 5 and 6As shown, after forming the passivation layer 105 and the oxide layer 106, the source 107, the gate 109 and the drain 108 are formed respectively. The source 107 and the drain 108 are located on both sides of the gate opening 1041 and are in contact with the barrier layer 103. The gate 109 is located in the interface and is in contact with the oxide layer 106. In this embodiment, the passivation layer 105 and the oxide layer 106 can be etched on both sides to the barrier layer 103, and metal Ti / Al / Ni / Au is deposited on the barrier layer 103 on both sides of the passivation layer 105 and the oxide layer 106 to form the source 107 and the drain 108. Among them, Ti / Al / Ni / Au in this application means that the gate 103 includes a titanium metal layer, an aluminum metal layer arranged on the titanium metal layer, a nickel metal layer arranged on the aluminum metal layer, and a gold metal layer arranged on the nickel metal layer. And the subsequent same writing has the same interpretation as in this embodiment, and no further description will be made in the subsequent. After the source 107 and the drain 108 are formed, they may be annealed in a nitrogen (N2) environment at a temperature of, for example, 750-850° C. to improve the quality of the source 107 and the drain 108. Figure 5 As shown, the source 107 and the drain 108 can be at the same height as the oxide layer 106. Figure 6 As shown, the source 107 and the drain 108 are higher than the oxide layer 106. After the source 107 and the drain 108 are formed, metal Ni / Au is deposited on the oxide layer 106 in the gate opening 1041 and on the oxide layer 106 on both sides of the gate opening 1041 to form a gate 109, and the cross-section of the gate 109 can be symmetrically "T"-shaped. In this embodiment, the distance between the source 107 and the gate 109 is, for example, 2-3um, and specifically, 2.5um. The distance between the gate 109 and the drain 108 is, for example, 14-15um, and specifically, 14.5um. The width of the gate 109 is, for example, 3-4um, and specifically, 3um. The source 107 and the drain 108 can be at the same height as the gate dielectric layer, or can be higher than the gate dielectric layer and at the same height as the gate 109. Since the barrier layer 103 at the bottom of the gate 109 in this embodiment is completely etched, the threshold voltage is no longer sensitive to the etching depth. Since the electric field inside the gallium nitride is very weak when the device is close to being turned off, the threshold voltage hysteresis phenomenon can be further reduced.

[0064] See also Figures 7 to 12As shown, in one embodiment of the present application, the present disclosure provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device is a monolithically integrated semiconductor device, and the semiconductor device includes a first device and a second device. The first device is a P-type field effect transistor, and the second device is an N-type field effect transistor. The first device includes an epitaxial structure and a first source 1071, a first drain 1081, an oxide layer 106 on the first source 1071 and the first drain 1081, and a first gate 1091 on the oxide layer 106. The second device includes an epitaxial structure and a second source 1072, a second drain 1082, and a second gate 1092 formed thereon. In this embodiment, the epitaxial structure includes a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, and a plurality of gallium nitride layers. The buffer layer 101 is formed on the substrate 100, the channel layer 102 is formed on the buffer layer 101, and the barrier layer 103 is formed on the channel layer 102. In this embodiment, for example, three gallium nitride layers are included.

[0065] See also Figure 7 As shown, in this embodiment, the substrate 100 is, for example, a silicon substrate. A layer of aluminum nitride film is sputtered on the substrate 100 to form a buffer layer 101. After the aluminum nitride layer is formed, the formed buffer layer 101 may be subjected to a high temperature annealing process to improve the quality of the buffer layer 101. The buffer layer 101 is disposed between the substrate 100 and the channel layer 102 to prevent silicon in the substrate 100 from reacting with gallium in the channel layer 102.

[0066] Please refer to Figure 7 As shown, in this embodiment, the channel layer 102 is a gallium nitride layer, and gallium nitride can be grown on the buffer layer 101 by chemical vapor deposition or metal organic chemical vapor deposition. First, in a reaction chamber of a gallium nitride growing device, one or more of helium, argon, nitrogen and hydrogen are introduced into the reaction chamber, and then the temperature of the reaction chamber is increased to a preset temperature, wherein the preset temperature is the growth temperature of the gallium nitride layer, and under this condition, a gallium nitride layer of a preset thickness, i.e., the channel layer 102, is grown.

[0067] Please refer to Figure 7As shown, in this embodiment, the epitaxial structure provides a source of hole carriers, which come from the unintentionally doped gallium nitride on the top, and the two-dimensional hole gas induced by polarization at the interface of the aluminum gallium nitride heterostructure. For example, a low-temperature chemical vapor deposition method such as plasma enhanced chemical vapor deposition (PECVD) can be used to form a barrier layer 103 on the channel layer 102. A first gallium nitride layer 141, a second gallium nitride layer 142, and a third gallium nitride layer 143 are sequentially formed on the barrier layer 103. Among them, the first gallium nitride layer 141 is an unintentionally doped gallium nitride layer, which is used to separate the P-type gallium nitride layer and the barrier layer, and can increase the mobility of holes, and the thickness of the first gallium nitride layer 141 can be, for example, 15-25nm, specifically, for example, 20nm. The second gallium nitride layer 142 is a doped P-type gallium nitride layer. The third gallium nitride layer 143 is a heavily doped P-type gallium nitride layer, which can form a good ohmic contact with the top electrode. In this embodiment, the doping source of P-doping is magnesium (Mg). Magnesium has a higher activation energy as an acceptor doping, and thus has a lower hole mobility in the P-type gallium nitride material. The doping concentration of magnesium ions in the second gallium nitride layer 142 is, for example, 1e19 cm -3 -2e19cm -3 The doping concentration of magnesium ions in the third gallium nitride layer 143 is, for example, 5e19 cm -3 -6e19cm -3 The heterostructure of gallium nitride and aluminum gallium nitride can generate two-dimensional hole gas. In this embodiment, a negative two-dimensional electron gas layer is generated in the barrier layer 103 and near the channel layer 102 , and a positive two-dimensional electron gas layer is generated in the first gallium nitride layer 141 and near the channel layer 102 .

[0068] See also Figure 8 As shown, in this embodiment, after the epitaxial structure is formed, metal Ni / Au / Ni is deposited on the epitaxial structure on one side of the epitaxial structure by electron beam evaporation to form a first source 1071 and a first drain 1081. Specifically, the first source 1071 and the first drain 1081 are arranged on the third gallium nitride layer 143, and there is a certain preset distance between the first source 1071 and the first drain 1081 to form a recess 144. The first source 1071 and the first drain 1081 include multiple metal layers. In this embodiment, the first source 1071 and the first drain 1081 include, for example, a first metal layer, a second metal layer and a third metal layer arranged in sequence, and the first metal layer is, for example, a Ni metal layer, the second metal layer is, for example, an Au metal layer, and the third metal layer is a Ni metal layer.

[0069] See also Fig. 9As shown, in this embodiment, after forming the first source 1071 and the first drain 1081, an etching technique such as inductively coupled plasma (ICP) or reactive ion etching (RIE) can be used to remove the P-type gallium nitride layer at the bottom of the recess 144. Specifically, the removed P-type gallium nitride layer includes the third gallium nitride layer 143 and the second gallium nitride layer 142 at the bottom of the recess 144. At this time, the bottom of the recess 144 stays on the surface of the first gallium nitride layer 141.

[0070] See also Fig.10 As shown, in some embodiments, chlorine gas (Cl2) or boron chloride (BCl3) is used to perform mesa etching on the epitaxial structure, and an isolation groove 146 is formed on the side of the first source 1071 away from the recess 144, and on the side of the first drain 1081 away from the recess 144. The isolation groove 146 can be used to separate adjacent semiconductor devices, and the isolation groove 146 passes through the electrode, the third gallium nitride layer 143, the second gallium nitride layer 142, the first gallium nitride layer 141, the barrier layer 103 and a portion of the channel layer 102, and has a certain preset distance from the buffer layer 101.

[0071] See also Fig.11 As shown, in this embodiment, after forming the isolation groove 146, aluminum oxide is deposited on the bottom wall and side wall of the recess 144, and above the first source 1071 and the first drain 1081 by, for example, atomic layer deposition technology (ALD) to form an oxide layer 106. Ni / Au is deposited on the oxide layer 106 as the first gate 1091 to form the first device. The first gate 1091 covers part of the oxide layer 106, including the oxide layer 106 on the bottom wall and side wall of the recess 144, and the oxide layer 106 on the first source 1071 and the first drain 1081 near the side of the recess, and the part of the oxide layer 106 above the first source 1071 and the first drain 1081 away from the recess 144 is not covered. The first gate 1091 includes multiple metal layers, and in this embodiment, for example, includes a nickel metal layer 1101 and an Au metal layer 1102 disposed on the Ni metal layer 1101.

[0072] See also Fig.12As shown, in other embodiments, the second device can be formed simultaneously when the first device is formed to form a monolithically integrated semiconductor device. In this embodiment, the epitaxial structure of the first device and the second device is the same, and the second device is isolated from the first device by an isolation groove 146. Specifically, when the first device is manufactured and the mesa etching is performed, the epitaxial structure can be etched twice in the area where the second device is formed. Among them, during the first etching process, the mesa etching is performed around the second gate 1092 and centered on the position where the second gate 1092 is located. The formed mesa structure 145 has a first preset distance H1 from the second gate 1092, and during the first etching, the third gallium nitride layer 143, the second gallium nitride layer 142, and the first gallium nitride layer 141 to the barrier layer 103 outside the second gate 1092 are etched away. After the first etching is completed, the second etching is performed. The second etching is centered on the mesa structure 145 formed by the first etching, and is performed on both sides of the mesa structure 145 formed by the first etching, and at a first preset distance H2 (H2>H1) from the second gate 1092 to the isolation groove 146. Etching is performed again toward one side of the substrate, and the barrier layer 103 is etched away to the channel layer 102, and a step is formed with the mesa structure 145 formed by the first etching. In this embodiment, steps are formed on both sides of the mesa structure 145 formed by the first etching. After the second etching is completed, Ni / Au is deposited on the mesa structure 145 formed for the first time, and at the center of the mesa structure 145 as the second gate 1092. Ti / AL / Ni / Au is deposited on two symmetrical steps to form a second source 1072 and a second drain 1082. In this embodiment, the formation order of the second gate 1092, the second source 1072 and the second drain 1082 and the specific deposition process are not limited. For example, the second source 1072 and the second drain 1082 may be formed after the first source 1071 and the first drain 1081 are formed, and the second gate 1092 may be formed after the first gate 1091 is formed.

[0073] See also Figures 13 to 25 As shown, in another embodiment of the present invention, a monolithically integrated semiconductor device is also provided, the semiconductor device comprising a first device and a second device, forming a power switch system. In this embodiment, the first device is, for example, a metal-oxide semiconductor field effect transistor (MOSFET), which is a silicon-based control device, and the second device is, for example, a high electron mobility transistor (HEMT), which is a power device. In this embodiment, when the two devices are located on different substrates 100, the switch of the system is susceptible to parasitic capacitance. The present application integrates the silicon-based control device and the gallium nitride power device, which can effectively suppress junction parasitics.

[0074] See also Fig.13As shown, in this embodiment, a silicon substrate 100 is first provided, and the substrate 100 is etched to form a boss 1003, and both sides of the boss 1003 are platforms with a height lower than the boss 1003. The boss 1003 is used to form a first device, for example, defined as a first region 1001, and the platform on one side of the boss 1003 is used to form a second device and an isolation structure, for example, defined as a second region 1002.

[0075] See also Fig.13 As shown, in this embodiment, after etching the substrate 100, an isolation layer 147 is deposited on the substrate 100. The material of the isolation layer 147 is, for example, silicon oxide (SiO2). The thickness of the isolation layer 147 on the first region 1001 is less than the thickness of the isolation layer 147 on the second region 1002. In this embodiment, the thickness of the isolation layer 147 on the first region 1001 is, for example, 18-30nm, specifically, for example, 20nm, which is used to form the gate dielectric layer of the first device. The height of the isolation layer 147 on the second region 1002 is greater than the height of the isolation layer 147 on the first region 1001, and the thickness of the isolation layer 147 on the second region 1002 is, for example, 1.0-1.5um, which is used to form an isolation structure between the first device and the second device.

[0076] See also Fig.13 As shown, in this embodiment, after forming the isolation layer 147, a polysilicon layer 148 is deposited on the isolation layer 147, and a mask layer 149 is deposited on the polysilicon layer. The material of the mask layer 149 is, for example, silicon oxide (SiO2), and the thickness of the mask layer 149 is, for example, 1-1.8um, specifically, for example, 1.5um. The polysilicon layer 148 is used to form the gate of the first device. The isolation layer 147 serves as a mask for epitaxial growth in the second device.

[0077] See also Figures 14 to 17As shown, in this embodiment, after forming the polysilicon layer 148 and the mask layer 149, silicon nitride (SiN3) is deposited on the mask layer 149 to form a protective layer 150, and the protective layer 150 is used as a mask to form a recess 151 in the second region 1002, and after forming the recess 151, the protective layer 150 is removed, for example, by using phosphoric acid (H3PO4). In this embodiment, after forming the protective layer 150, etching is performed on the protective layer 150 in the second region 1002 toward the side of the substrate 100, for example, by dry etching, to sequentially etch away the protective layer 150, the mask layer 149, the polysilicon layer 148, the isolation layer 147 and the substrate 100 of a preset thickness to form the recess 151. The recess 151 is formed at a preset distance from the boss 1003 to retain the isolation layer 147 between the recess 151 and the boss 1003. The isolation layer 147 between the recess 151 and the boss 1003 can form a trench isolation structure between the first device and the second device. After the recess 151 is formed, the surface of the etched area can be smoothed to ensure the quality of the formed second device.

[0078] See also Fig.18 As shown, in this embodiment, after the recess 151 is formed, the isolation layer 147 is used as a mask to sequentially form a channel layer 102, a barrier layer 103 and a gate dielectric layer 152 of the second device in the recess 151. For example, a layer of gallium nitride is deposited in the recess 151 by a metal organic chemical vapor deposition (MOCVD) method to form the channel layer 102, and the channel layer 102 is at the same height as the surface of the substrate 100 in the second region 1002. After the channel layer 102 is formed, for example, a layer of aluminum gallium nitride is deposited on the surface of the channel layer 102 by a MOCVD method to form a barrier layer 103, and the barrier layer 103 is at the same height as the isolation layer 147. After the barrier layer 103 is formed, a layer of silicon nitride (SiN) is deposited on the barrier layer 103 as the gate dielectric layer 152 of the second device. The thickness of the gate dielectric layer 152 is, for example, 20-30 nm. After the gate dielectric layer 152 is formed, the isolation layer 147 is removed.

[0079] See also Fig.19As shown, in this embodiment, after removing the isolation layer 147, the polysilicon layer 148 is etched to form a first gate 1091. The substrate 100 on both sides of the first gate 1091 is doped to form a source region and a drain region 156 of the first device. Among them, the first gate 1091 is arranged on the boss 1003 and is located on the side away from the second device. The source region in this embodiment is arranged in the boss 1003 and is located on the side of the first gate 1091 relative to the second device. The source region provided in this embodiment includes a P-type lightly doped region 155, a P-type heavily doped region 153 and an N-type heavily doped region 154 arranged on the P-type lightly doped region 155. The P-type heavily doped region 153 and the N-type heavily doped region 154 are flush with the interface of the boss 1003, and the depths of the P-type heavily doped region 153 and the N-type heavily doped region 154 are arranged side by side, the N-type heavily doped region 154 is adjacent to the first gate 1091, and the P-type heavily doped region 153 is located on the side of the N-type heavily doped region 154 relative to the first gate 1091. The doping depth of the P-type lightly doped region 155 is greater than the doping depths of the P-type heavily doped region 153 and the N-type heavily doped region 154, and the P-type lightly doped region 155 covers the P-type heavily doped region 153 and the N-type heavily doped region 154. The P-type lightly doped region 155 extends horizontally to below the first gate 1091 and partially overlaps with the first gate 1091. The drain region 156 provided in this embodiment includes an N-type heavily doped region, the drain region 156 is arranged between the first gate 1091 and the second device, and the drain region 156 has a preset distance from the first gate 1091. The doping depth of the drain region 156 is greater than the doping depths of the P-type heavily doped region 153 and the N-type heavily doped region 154 in the source region, and less than the doping depth of the P-type lightly doped region 155 in the source region. In this embodiment, the P-type doping source is, for example, boron ions or boron fluoride ions (BF2), and the N-type doping source is, for example, phosphorus ions.

[0080] See also Fig.19 As shown, in this embodiment, after forming the first gate 1091, the source region and the drain region 156, a passivation layer 157 is formed on the first gate 1091, the isolation layer 147 and the isolation structure between the first device and the second device. For example, a layer of silicon oxide (SiO2) can be deposited using a plasma enhanced chemical vapor deposition (PECVD) method to form the passivation layer 157. In some embodiments, after forming the passivation layer 157, annealing can be performed to activate the dopant.

[0081] See also Figures 19 to 21As shown, in this embodiment, after the passivation layer 157 is formed, an opening 158 is formed on the side of the second region 1002 close to the first device and the side away from the first device. For example, the gate dielectric layer 152 and the barrier layer 103 of the second device where the opening 158 is required are etched away, so that the opening 158 is in contact with the channel layer 102. After the opening 158 is formed, metal Ti / Al / Ni / Au is deposited in the two openings 158 to form a second source 1072 and a second drain 1082 of the second device. Among them, the one close to the first device is, for example, the second source 1072 of the second device, and the one away from the first device is the second drain 1082 of the second device.

[0082] See also Figure 22 to Figure 23 As shown, in this embodiment, after forming the second source electrode 1072 and the second drain electrode 1082, an opening 159 connecting the source region and the drain region 156 is respectively opened on the passivation layer 157 and located on both sides of the first gate 1091, and the opening 159 penetrates the passivation layer 157 and the isolation layer 147. Metal aluminum is deposited in the opening 159 to form the first source electrode 1071 and the first drain electrode 1081. The first source electrode 1071 contacts the source region, and the first drain electrode 1081 contacts the drain region.

[0083] See also Figure 24 to Figure 25 As shown in FIG. 1 , in this embodiment, after forming the first source 1071 and the first drain 1081, metal Ni / Au is deposited on the gate dielectric layer 152 to form a second gate 1092. The second gate 1092 is close to the drain side of the second device. That is, the manufacturing of the first device and the second device is completed. After the manufacturing of the first device and the second device is completed, at least one metal layer can be formed on the first device and the second device to connect the first device and the second device to form a Fig.25 The power switch system shown in FIG. The number of metal layers is not limited and can be Fig.25 The first device and the second device are electrically connected as shown.

[0084] See also Figure 26 to Figure 36 As shown, in another embodiment of the present invention, a monolithic integrated semiconductor device is also provided, the semiconductor device comprising a first device and a second device, forming a half-bridge circuit. Wherein, the first device and the second device are both high electron mobility transistors (HEMT), and one high electron mobility transistor is connected to a high level, and the other high electron mobility transistor is connected to a low level. The semiconductor device provided in this embodiment can prevent the back gate effect from occurring when the half-bridge circuit is working, and suppress the generation of parasitic inductance.

[0085] See also Fig.29As shown, in this embodiment, a substrate is provided, and the substrate includes silicon layers with different polarities, and a buried layer 160 disposed in the silicon layer. Specifically, the substrate includes a first silicon layer 1004, a buried layer 160 disposed on the first silicon layer 1004, and a second silicon layer 1005 disposed on the buried layer 160. Among them, the first silicon layer 1004 is polar silicon Si (100), and the thickness of the first silicon layer 1004 is, for example, 1-1.1 mm, and specifically, for example, 1 mm. The buried layer 160 is disposed on the first silicon layer 1004, and the material of the buried layer 160 is, for example, silicon oxide (SiO2), and the thickness of the buried layer 160 is, for example, 1-1.1 um, and specifically, for example, 1 um. The second silicon layer 1005 is disposed on the buried layer 160, and the second silicon layer 1005 is non-polar silicon Si (111), and the thickness of the second silicon layer 1005 is, for example, 1.5-1.6 um, and specifically, for example, 1.5 um. After forming the substrate, the substrate may be cleaned.

[0086] See also Fig.29 As shown, in this embodiment, the buffer layer 161 is arranged on gallium nitride, and the material of the buffer layer 161 is, for example, gallium nitride, and the thickness of the buffer layer 161 is, for example, 4000-4500nm, and specifically, for example, 4200nm. The channel layer 102 is arranged on the buffer layer 161, and the material of the channel layer 102 is, for example, gallium nitride. The thickness of the channel layer 102 is, for example, 400-450nm, and specifically, for example, 420nm. A barrier layer 103 is arranged on the channel layer 102, and the material of the barrier layer 103 is, for example, aluminum gallium nitride. The thickness of the barrier layer 103 is, for example, 20-25nm, and specifically, for example, 24.7nm. A cap layer 162 may also be arranged on the barrier layer 103, and the material of the cap layer 162 is, for example, gallium nitride. The thickness of the cap layer 162 is, for example, 3-5nm, and specifically, for example, 3.2nm.

[0087] See also Fig.30 As shown, in this embodiment, after forming the cap layer 162, an isolation groove 163 is etched on the epitaxial layer. The isolation groove 163 extends into the substrate and passes through the second silicon layer 1005 and a portion of the buried layer 160 to isolate the first device from the second device. For example, Cl2 or BCl3 can be used, and inductively coupled plasma (ICP) can be used to etch the cap layer 162, the barrier layer 103, the channel layer 102, the buffer layer 161, the second silicon layer 1005, and the buried layer 160 of a preset thickness, and stop in the buried layer 160, thereby forming the isolation groove 163. In this embodiment, the isolation groove 163 is arranged between the first device and the second device, and the isolation groove 163 extends to the buried layer 160 in the substrate, which can effectively isolate the substrate of the first device from the second device, prevent the back gate effect, and suppress the generation of parasitic inductance.

[0088] See also Figure 31 to Figure 32As shown, in this embodiment, after the isolation groove 163 is formed, a gate opening is formed by etching on both sides of the isolation groove 163. In the subsequent step, metal is deposited in the gate opening to form a gate. In this embodiment, the cap layer 162 at the gate position and the barrier layer 103 of a preset thickness can be dry-etched to form a gate opening. The barrier layer 103 with a thickness of 2-3nm can be retained at the bottom of the gate to form an enhanced device. In this embodiment, the gate opening includes, for example, a first gate opening 165 located on one side of the isolation groove 163 and a second gate opening 164 located on the other side of the isolation groove 163. And the first gate opening 165 on one side of the isolation groove 163 is far away from the isolation groove 163, and the second gate opening 164 on the other side of the isolation groove 163 is close to the isolation groove 163. After the gate opening is formed, a passivation layer 166 is formed on the isolation groove 163, the gate opening and the cap layer 162. For example, a low pressure chemical vapor deposition (LPCVD) method may be used to deposit a layer of silicon nitride (Si 3 N 4 ) on the isolation trench 163 and the cap layer 162 to form the passivation layer 166 .

[0089] See also Figure 33 to Figure 34 As shown, in this embodiment, after forming the passivation layer 166, tetraethyl silicate (PETEOS) is deposited on the passivation layer 166 as a protective layer 167. The protective layer 167 fills the gate opening and is laid flat on the passivation layer 166. After forming the protective layer 167, a source opening and a drain opening are formed on both sides of the isolation groove 163 and on both sides of the gate opening by using reactive ion etching (RIE) and inductively coupled plasma (ICP) etching. For example, a first source opening 168 and a first drain opening 169 are formed on one side of the isolation groove 163 and on both sides of the first gate opening 165. The first source opening 168 is located on the side of the first gate opening 165 away from the isolation groove 163, the first drain opening 169 is located between the first gate opening 165 and the isolation groove 163, and the distance between the first source opening 168 and the first gate opening 165 is much smaller than the distance between the first drain opening 169 and the first gate opening 165. On the other side of the isolation groove 163 and on both sides of the second gate opening 164, a second source opening 170 and a second drain opening 171 are formed respectively. The second drain opening 171 is located on the side of the second gate opening 164 away from the isolation groove 163, the second source opening 170 is located between the second gate opening 164 and the isolation groove 163, and the distance between the second source opening 170 and the second gate opening 164 is much smaller than the distance between the second drain opening 171 and the second gate opening 164.

[0090] See also Figure 35 to Figure 36As shown, in this embodiment, after forming the electrode openings, magnetron sputtering Ti / Al / Ti / TiN multilayer metal is performed in the source openings and drain openings, and source and drain patterning stripping is performed, and rapid thermal annealing is performed. Metal is deposited in and above the first source opening 168 to form a first source 1071, metal is deposited in and above the first drain opening 169 to form a first drain 1081, metal is deposited in and above the second source opening 170 to form a second source 1072, and metal is deposited in and above the second drain opening 171 to form a second drain 1082. After forming the source and drain, for example, the protective layer 167 in the first gate opening 165 and the second gate opening 164 is removed by reactive ion etching (RIE), and TiN / Ti / Al multilayer metal is magnetron sputtered in the first gate opening 165 and the second gate opening 164, and then gate patterning and stripping are performed to form the first gate 1091 and the second gate 1092, thereby forming the first device and the second device. In this embodiment, the first source 1071, the first gate 1091, the first drain 1081, the second source 1072, the second gate 1092 and the second drain 1082 are all higher than the openings where they are located, and extend to both sides of the openings to form electrodes of a T-shaped structure. The use of the passivation layer 166 and the T-shaped electrode can further improve the withstand voltage of the enhancement-mode GaN HEMT device and achieve monolithic integration of a half-bridge circuit with good performance.

[0091] See also Fig.37 As shown, in other embodiments, in order to avoid the substrate bias effect of the integrated device, in addition to setting an oxide buried layer in the substrate. The present application can also provide an epitaxial structure with a superlattice buffer layer to avoid the substrate bias effect of the integrated device, and the buffer layer 101 with a superlattice structure 1013 can reduce the on-resistance and suppress current collapse, so as to reduce resistance, optimize the high-quality buffer layer, and increase the breakdown voltage.

[0092] For details, please refer to Fig.37As shown, in this embodiment, the substrate 100 is, for example, a silicon substrate, the buffer layer 101 is disposed on the substrate 100, and the buffer layer 101 includes an aluminum nitride layer 1011, an aluminum gallium nitride layer 1012 disposed on the aluminum nitride layer 1011, and a superlattice structure 1013 disposed on the aluminum gallium nitride layer 1012. The thickness of the aluminum nitride layer 1011 is, for example, 100-120 nm, specifically, for example, 110 nm, 115 nm, or 120 nm. The aluminum gallium nitride layer 1012 is disposed on the aluminum nitride layer 1011, and the thickness of the aluminum gallium nitride layer 1012 is, for example, 250-320 nm, specifically, for example, 300 nm. The superlattice structure 1013 is disposed on the aluminum gallium nitride layer 1012, and the superlattice structure 1013 is, for example, an aluminum nitride layer and a gallium nitride layer that are repeatedly stacked. The thickness of the superlattice structure 1013 is, for example, 2400-2600nm, and specifically, for example, 2500nm. The present embodiment does not limit the thickness of the aluminum nitride layer and the gallium nitride layer in the superlattice structure 1013. According to the process, the thickness of the aluminum nitride layer and the gallium nitride layer in the superlattice structure 1013 can be made smaller. A channel layer 102 is provided on the superlattice structure 1013. In the present embodiment, the channel layer 102 is, for example, a gallium nitride layer of 1.2-1.8um, and the specific thickness of the channel layer 102 is, for example, 1.5um. A barrier layer 103 is provided on the channel layer 102. In the present embodiment, the thickness of the barrier layer 103 is, for example, 20-30nm, and specifically, for example, 25nm. The epitaxial structure provided in the present embodiment can be used to form a plurality of electrodes to form a semiconductor device. The epitaxial structure provided in this embodiment uses the semiconductor device described in this application. The buffer layer 101 having the superlattice structure 1013 in the epitaxial structure has a vertical isolation effect and can optimize the performance of the semiconductor device. The buffer layer 101 having the superlattice structure 1013 can improve the voltage blocking capability, and the vertical isolation also significantly reduces the substrate bias effect. In addition, the vertical substrate leakage current is well suppressed under a higher positive substrate bias voltage.

[0093] See also Figures 1 to 37 In the semiconductor device shown, when aluminum gallium nitride is deposited on the gallium nitride channel layer to form a barrier layer, an AlGaN / GaN heterostructure can be formed. The interface of the AlGaN / GaN heterostructure can produce a high-mobility two-dimensional electron gas (2DEG) for manufacturing a power switch transistor with extremely low on-state resistance. After the AlGaN / GaN heterostructure is formed, the AlGaN / GaN heterostructure can be treated with supercritical CO2 to improve the AlGaN / GaN heterojunction interface to exhibit a lower defect state density and gate leakage current.

[0094] See also Fig.40As shown, in this embodiment, for example, gaseous CO2 is transported from a gas cylinder 12 to a high-pressure pump 11 at a pressure of, for example, 3000 pounds per square inch (psi) to complete the phase transition from gas to supercritical fluid. The AlGaN / GaN heterostructure is placed in a reaction chamber 10, and carbon dioxide and H2O in a supercritical state are introduced into the reaction chamber 10, and treated at, for example, 150°C for, for example, 3 hours. During the reaction, due to the large activation energy and chemically stable double bond structure of CO2, it does not participate in the reaction during the supercritical CO2 treatment process, and defects are mainly repaired by supplementing dangling bonds, so that the interface defect state density is reduced. In this embodiment, H2O is decomposed into H + and OH - , and when a negative bias is applied, the H + Since supercritical CO2 has strong solubility and penetration, the H + will enter the sample through supercritical CO2. Under supercritical conditions, H + It can fill the Ga vacancy. + After the defects are repaired, the vacancies caused by the lattice mismatch between AlGaN and GaN can be repaired, thereby repairing the AlGaN / GaN interface, thereby improving the problem of low defect state density and gate leakage current at the AlGaN / GaN heterojunction interface.

[0095] See also Figures 19 to 24 In the semiconductor device shown, when silicon nitride (SiNx) is deposited on an AlGaN / GaN heterostructure, after the silicon nitride is deposited, there is a lattice mismatch between GaN and SiNx, with multiple dangling bonds and multiple N vacancies. As a result, the electrons of the gate and the two-dimensional electron gas in the channel are easily captured by interface state defects, and the interface state defects directly below the gate will cause the threshold voltage to be unstable, and the interface state defects in the gate-drain region will deplete the channel electrons and cause the dynamic resistance to increase. In this embodiment, the AlGaN / GaN heterostructure provided with a silicon nitride layer can be treated with supercritical CO2 to improve the interface defects of SiNx / GaN.

[0096] See also Fig.40 As shown, in this embodiment, for example, gaseous CO2 is transported from a gas cylinder 12 to a high-pressure pump 11 at a pressure of, for example, 3000 pounds per square inch (psi), to complete a phase transition from a gas state to a supercritical fluid. An AlGaN / GaN heterostructure provided with a silicon nitride layer is placed in a reaction chamber 10, and carbon dioxide and H2O in a supercritical state are introduced into the reaction chamber 10, mixed with, for example, 1 g of Mg3N2 in the reaction chamber 10, and treated at, for example, 120°C for, for example, 1 hour.

[0097] See also Fig.40As shown, in this embodiment, during the reaction, due to the large activation energy of CO2 and the stable chemical properties of the double bond structure, it does not participate in the reaction during the supercritical CO2 treatment process. In this embodiment, Mg3N2 and H2O react as follows:

[0098] Mg3N2+H2O→Mg(OH)2+NH3.

[0099] Please refer to Fig.40 As shown in the figure, due to the strong solubility and penetration of supercritical CO2, the NH3 generated by the reaction will enter the SiNx / GaN interface through the supercritical CO2, and when the NH3 molecules dissolve in the supercritical CO2, the supercritical NH3 combines with the excess dangling bonds and N vacancies to form NH2 - The deamination reaction will occur on the adjacent NH2 - The reactions are as follows:

[0100] NH2 - +NH2 - +NH2 - →N3+3H2.

[0101] During the supercritical fluid treatment process, the amination and deamination reactions are carried out dynamically in the reaction chamber 10, and eventually complete Si-N bonds and Ga-N bonds are formed at the SiNx / GaN interface and inside the dielectric layer, and N vacancies are filled, thereby improving the traps at the SiNx / GaN interface. Through supercritical CO2 treatment, the number of traps at the SiNx / GaN interface is reduced, thereby avoiding device reliability problems caused by gate electrons or two-dimensional electron gas being trapped, and improving the quality of the formed semiconductor device.

[0102] See also Figures 1 to 40 As shown, the epitaxial structure provided in the present invention and the semiconductor device formed by the epitaxial structure can be applied to various semiconductor structures, electronic components or electronic devices, such as switching elements, power elements, radio frequency elements, light-emitting diodes, micro light-emitting diodes, display panels, mobile phones, watches, laptop computers, drop-type devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.

[0103] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power device, characterized in that: The power device includes a first device, and the first device includes: substrate; A channel layer is disposed on the substrate; A barrier layer, disposed on the channel layer; A first gallium nitride layer is disposed on the barrier layer and covers the barrier layer; A second gallium nitride layer, disposed on the first gallium nitride layer; A third gallium nitride layer, disposed on the second gallium nitride layer; A first drain electrode is disposed on the third gallium nitride layer; a first source electrode, disposed on the third gallium nitride layer, with a recess formed between the first source electrode and the first drain electrode; and A first gate is disposed on the barrier layer, and the first gate covers the concave portion, and the first source and the first drain are close to the top of the concave portion; The second gallium nitride layer and the third gallium nitride layer are located between the first source electrode, the first drain electrode and the barrier layer, the first gallium nitride layer is an unintentionally doped gallium nitride layer, the second gallium nitride layer is a doped P-type gallium nitride layer, and the third gallium nitride layer is a heavily doped P-type gallium nitride layer.

2. The power device according to claim 1, characterized in that: It also includes a buffer layer formed on the substrate, and the buffer layer is an aluminum nitride buffer layer.

3. The power device according to claim 1, characterized in that: The second gallium nitride layer is a doped P-type gallium nitride layer, and the doping concentration is 1e19cm -3 -2e19cm -3 .

4. The power device according to claim 1, characterized in that: The third gallium nitride layer is a heavily doped P-type gallium nitride layer with a doping concentration of 5e19cm -3 -6e19cm -3 .

5. The power device according to claim 1, characterized in that: The power device further includes an oxide layer, which is disposed between the first gate and the first gallium nitride layer, and covers the recess and tops of the first source and the first drain.

6. The power device according to claim 1, characterized in that: The power device further includes a second device, and the second device is isolated from the first device by an isolation trench, and the isolation trench passes through the third gallium nitride layer, the second gallium nitride layer, the first gallium nitride layer and the barrier layer, and extends into the channel layer.

7. The power device according to claim 6, characterized in that: The second device comprises: A mesa structure is disposed on the barrier layer, and the mesa structure includes the first gallium nitride layer, the second gallium nitride layer and the third gallium nitride layer disposed in sequence; A second source electrode is disposed on the channel layer and located on one side of the mesa structure; a second drain electrode, disposed on the channel layer and located on the other side of the mesa structure; and The second grid is arranged on the mesa structure.

8. A method for manufacturing a power device, characterized in that: include: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a first gallium nitride layer, a second gallium nitride layer and a third gallium nitride layer in sequence on the barrier layer; etching the third gallium nitride layer and the second gallium nitride layer to form a concave portion; forming a first source electrode and a first drain electrode on the third gallium nitride layer at both sides of the concave portion; and forming a first gate in the concave portion and at a top of the first source electrode and the first drain electrode close to the concave portion; The first gallium nitride layer is an unintentionally doped gallium nitride layer, the second gallium nitride layer is a doped P-type gallium nitride layer, and the third gallium nitride layer is a heavily doped P-type gallium nitride layer.

9. An electronic device, characterized in that: Comprising the power device as claimed in claim 1.

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