A semiconductor device and a manufacturing method thereof

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology. It simplifies the manufacturing process of at least five types of gate-around transistors with different absolute threshold voltage values, reducing the manufacturing difficulty of semiconductor devices. The semiconductor device includes a semiconductor substrate and at least five types of gate-around transistors disposed on the semiconductor substrate. Different types of gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate. In the different types of gate-around transistors, at least a portion of the nanostructures in different channel regions are made of different materials, and the portions of the nanostructures with different materials in the different channel regions are staggered along the thickness direction of the semiconductor substrate. In the at least five types of gate-around transistors, the nanostructures in different channel regions belonging to at least two types of gate-around transistors are made of the same material, and the portions of the nanostructures with the same material in the different channel regions are aligned along the thickness direction of the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gate-around transistors (GMT-A) include gate stacks formed not only on the top and sidewalls of the channel, but also on the bottom of the channel. Therefore, compared with planar transistors and fin field-effect transistors, GMT-A has advantages such as higher gate control capability.

[0003] However, when a semiconductor device includes at least two types of gate ring transistors formed on a semiconductor substrate, and the absolute values ​​of the threshold voltages of the at least two types of gate ring transistors are different, the manufacturing process of these two types of gate ring transistors using existing manufacturing methods is complex and demanding, resulting in greater difficulty in manufacturing semiconductor devices. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which simplifies the manufacturing process of at least five types of gate-around transistors with different absolute threshold voltage values ​​and reduces the manufacturing difficulty of semiconductor devices.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: a semiconductor substrate and at least five types of gate-around transistors disposed on the semiconductor substrate. The different types of gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate. In the different types of gate-around transistors, at least a portion of the nanostructures included in different channel regions are made of different materials, and the portions of the nanostructures with different materials in the different channel regions are staggered along the thickness direction of the semiconductor substrate. In the at least five types of gate-around transistors, the nanostructures included in different channel regions belonging to at least two types of gate-around transistors are made of the same material, and the portions of the nanostructures with the same material in the different channel regions are aligned along the thickness direction of the semiconductor substrate.

[0006] When the above technical solution is adopted, in the semiconductor device provided by the present invention, the nanostructures included in different channel regions of different types of gate ring transistors are made of at least some different materials, and the nanostructures with at least some different materials may have different conductivity characteristics. Therefore, by using at least some different semiconductor materials to manufacture the nanostructures included in different types of gate ring transistors, it is beneficial to make the channel regions of different types of gate ring transistors have different conduction characteristics, thereby making different types of gate ring transistors have threshold voltages with different absolute values ​​to meet the corresponding operating requirements.

[0007] Furthermore, the different material portions of the nanostructures included in different channel regions are staggered along the thickness direction of the semiconductor substrate. Moreover, in at least five types of gate-around transistors, the nanostructures in different channel regions belonging to at least two types of gate-around transistors share the same material, and the portions of the nanostructures in different channel regions that share the same material are aligned along the thickness direction of the semiconductor substrate. Based on this, when manufacturing the semiconductor device provided by this invention, the above-mentioned at least five types of gate-around transistors can be manufactured by forming at least three semiconductor layers of different materials that are alternately stacked on the semiconductor substrate, with each of the at least three alternately stacked semiconductor layers serving as a channel layer / sacrificial layer. Furthermore, by simply selecting different semiconductor layers and combining adjacent different semiconductor layers in the channel regions of some types of gate-around transistors, the aforementioned channel regions with different conductivity characteristics can be obtained, thereby enabling different types of gate-around transistors to have threshold voltages of different absolute values. Simultaneously, the complex deposition-etching-deposition process is eliminated from forming gate stack structures with different thicknesses and / or materials to obtain different types of gate-around transistors with different threshold voltages, simplifying the semiconductor device manufacturing process.

[0008] In one example, in at least two types of gate-around transistors, the nanostructures comprising the channel region have at least two materials, and the portions of the nanostructures made of different materials have the same thickness.

[0009] In one example, the nanostructure of the gate-around transistor comprises Si. 1-x Ge x , 0≤x≤1. In different types of gate-ring transistors, the germanium content in at least a portion of the nanostructures included in different channel regions varies.

[0010] In one example, in different types of gate ring transistors, the germanium content in at least a portion of the nanostructures included in the different channel regions differs by at least 20%.

[0011] In one example, among at least five types of gate-around transistors, the different channel regions belonging to at least two types of gate-around transistors include nanostructures with different thicknesses.

[0012] In one example, portions of the channel regions of different types of gate ring transistors made of the same material are integrally formed.

[0013] In one example, different types of ring gate transistors include gate stack structures made of the same material.

[0014] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: first, providing a semiconductor substrate; next, forming at least five types of gate-around transistors (GMT-AOTs) on the semiconductor substrate. The different types of GMT-AOTs are spaced apart along a direction parallel to the surface of the semiconductor substrate. In the different types of GMT-AOTs, at least a portion of the nanostructures in different channel regions are made of different materials, and the portions of the nanostructures with different materials in the different channel regions are staggered along the thickness direction of the semiconductor substrate. In the at least five types of GMT-AOTs, portions of the nanostructures in different channel regions belonging to at least two types of GMT-AOTs are made of the same material, and the portions of the nanostructures with the same material in the different channel regions are aligned along the thickness direction of the semiconductor substrate.

[0015] In one example, at least five types of gate-around transistors are formed on a semiconductor substrate, including: forming at least five types of fin structures that are spaced apart and have the same structure on the semiconductor substrate. Each type of fin structure includes at least three semiconductor layers of different materials that are alternately stacked along the thickness direction of the semiconductor substrate. Next, a first mask structure is formed transversely on each type of fin structure. Next, the portion of each type of fin structure exposed outside the first mask structure is processed to form the source and drain regions included in each type of gate-around transistor. Next, at least a portion of the first mask structure is removed. Next, a portion of the semiconductor layers in one type of fin structure is selectively removed so that the remaining semiconductor layers in this type of fin structure form the channel region included in the corresponding type of gate-around transistor; and this step is repeated until the channel regions included in all types of gate-around transistors are formed. Next, a gate stack structure is formed around the periphery of the channel regions included in each type of gate-around transistor.

[0016] In one example, the nanostructure includes a ring-gate transistor located in the bottom portion of the semiconductor layer as the target type of ring-gate transistor. Furthermore, before forming a gate stack structure surrounding the channel region included in each type of ring-gate transistor after removing at least a portion of the first mask structure, the method of manufacturing the semiconductor device further includes selectively removing a portion of the thickness of the semiconductor substrate located below the target type of ring-gate transistor.

[0017] In one example, forming at least five types of fin-like structures that are spaced apart and have the same structure on a semiconductor substrate includes: forming at least three semiconductor layers of different materials that are alternately stacked along the thickness direction of the semiconductor substrate. Next, at least the at least three alternately stacked semiconductor layers are selectively etched to form at least five types of fin-like structures.

[0018] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0020] Figure 1 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 1 ;

[0021] Figure 2 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 2 ;

[0022] Figure 3 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0023] Figure 4 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0024] Figure 5 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0025] Figure 6 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0026] Figure 7 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0027] Figure 8 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 8 ;

[0028] Figure 9 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 9 ;

[0029] Figure 10 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 ;

[0030] Figure 11 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 one;

[0031] Figure 12 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 two;

[0032] Figure 13 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 three;

[0033] Figure 14 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 Four;

[0034] Figure 15 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 five;

[0035] Figure 16 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 six;

[0036] Figure 17 A longitudinal sectional view of the semiconductor device during the manufacturing process provided in this embodiment of the invention. Figure 10 seven.

[0037] Reference numerals: 11 is a semiconductor substrate, 12 is a gate-around transistor, 13 is a channel region, 14 is a nanostructure, 15 is a source region, 16 is a drain region, 17 is a gate stack structure, 18 is a shallow trench isolation structure, 19 is a gate sidewall, 20 is an interlayer dielectric layer, 21 is a fin structure, 22 is a semiconductor layer, 23 is a first mask structure, 24 is a second mask structure, 25 is a third mask structure, and 26 is a target gate-around transistor. Detailed Implementation

[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0039] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0043] A gate-around transistor (GMT) comprises gate stacks formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared to planar transistors and fin field-effect transistors, GMTs offer advantages such as higher gate control capability. Based on this, when different transistors within a semiconductor device utilize GMTs, the device's performance can be improved.

[0044] Secondly, in the actual manufacturing process of semiconductor devices, multiple "deposition-etching-deposition" processes are typically employed to form gate stack structures of different thicknesses and / or materials on the channels of different types of transistors within the semiconductor device. This allows different transistors to correspond to different threshold voltage control parameters, enabling the regulation of the threshold voltage of different transistors within the semiconductor device. With the development of semiconductor technology, integrated circuits with higher performance and more powerful functions require greater component density, and the size and space of each component, the space between components, and the space within each component itself also need to be further reduced. For gate-to-ring transistors, the space between two adjacent nanostructures in the channel and between the nanostructures and the semiconductor substrate is relatively small. Forming gate stack structures of different thicknesses and / or materials within this small space is challenging, leading to reduced yield and performance of semiconductor devices.

[0045] To address the aforementioned technical problems, those skilled in the art have developed a space-saving dipole threshold voltage control technique to regulate the threshold voltage of different transistors in semiconductor devices. Specifically, taking a gate-ring transistor as an example, after forming the corresponding channels for the gate-ring transistor in different types of regions, a gate dielectric layer is formed on the outer periphery of the channels in each type of region. Next, a dipole layer of appropriate thickness and material is formed on the gate dielectric layer, and an annealing process is used to push key elements in the dipole layer (e.g., lanthanum in a lanthanum oxide dipole layer) to the interface, resulting in different threshold voltage control parameters for different types of regions. Finally, the remaining dipole layer is removed. This achieves threshold voltage regulation of different gate-ring transistors without reducing the gate formation space, thus not affecting subsequent gate filling.

[0046] However, the aforementioned dipole threshold modulation technique involves significant process complexity and high technical requirements, leading to substantial difficulties in manufacturing semiconductor devices. Furthermore, the annealing process in dipole threshold modulation, which pushes key elements in the dipole layer to the interface, presents certain compatibility issues. For example, when the channel material of a gate-around transistor is germanium-silicon or germanium, the annealing process alters the carrier transport performance within the channel, thereby degrading the conductivity of the gate-around transistor.

[0047] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, at least a portion of the nanostructures in different channel regions of different types of gate-around transistors are made of different materials, thereby enabling different types of gate-around transistors to have threshold voltages of varying absolute values. Furthermore, the portions of the nanostructures in the different channel regions are staggered along the thickness direction of the semiconductor substrate. Moreover, in at least five types of gate-around transistors, at least two types of gate-around transistors have nanostructures in different channel regions made of the same material, and these identical portions are aligned along the thickness direction of the semiconductor substrate, simplifying the semiconductor device manufacturing process.

[0048] Specifically, in a first aspect, embodiments of the present invention provide a semiconductor device. For example... Figure 17 As shown, the semiconductor device includes a semiconductor substrate 11 and at least five types of gate-around transistors 12 disposed on the semiconductor substrate 11. Different types of gate-around transistors 12 are spaced apart along a direction parallel to the surface of the semiconductor substrate 11. Among the different types of gate-around transistors 12, at least a portion of the nanostructures 14 included in different channel regions 13 are made of different materials, and the portions of the nanostructures 14 in the different channel regions 13 are staggered along the thickness direction of the semiconductor substrate 11. Among the at least five types of gate-around transistors 12, portions of the nanostructures 14 included in different channel regions 13 belonging to at least two types of gate-around transistors 12 are made of the same material, and the portions of the nanostructures 14 in the different channel regions 13 are aligned along the thickness direction of the semiconductor substrate 11.

[0049] When the above technical solution is adopted, such as Figure 17 As shown, in the semiconductor devices provided by the embodiments of the present invention, in different types of gate ring transistors 12, the nanostructures 14 included in different channel regions 13 are made of at least a portion of different materials, and the nanostructures 14 with at least a portion of different materials may have different conductivity characteristics. Therefore, by using at least a portion of different semiconductor materials to manufacture the nanostructures 14 included in different types of gate ring transistors 12, it is advantageous to make the channel regions 13 of different types of gate ring transistors 12 have different conduction characteristics, thereby enabling different types of gate ring transistors 12 to have threshold voltages with different absolute values ​​to meet the corresponding operating requirements. In addition, the portions of the nanostructures 14 included in different channel regions 13 that are made of different materials are staggered along the thickness direction of the semiconductor substrate 11. Furthermore, in at least five types of gate ring transistors 12, the portions of the nanostructures 14 included in different channel regions 13 of at least two types of gate ring transistors 12 are made of the same material, and the portions of the nanostructures 14 included in different channel regions 13 that are made of the same material are aligned along the thickness direction of the semiconductor substrate 11. Based on this, as Figures 1 to 17As shown, when manufacturing the semiconductor device provided in this embodiment of the invention, at least three semiconductor layers 22 of different materials are formed and alternately stacked on a semiconductor substrate 11, and the at least three semiconductor layers 22 of alternately stacked are channel layers / sacrificial layers to each other, so as to manufacture the above-mentioned at least five types of gate ring transistors 12. Moreover, by simply selecting different semiconductor layers 22 and combining adjacent different semiconductor layers 22 in the channel regions 13 of some types of gate ring transistors 12, the above-mentioned channel regions 13 with different conductivity characteristics can be obtained, thereby realizing that different types of gate ring transistors 12 have threshold voltages with different absolute values. At the same time, it is not necessary to use the complex deposition-etching-deposition method to form gate stack structures 17 with different thicknesses and / or materials to obtain different types of gate ring transistors 12 with different absolute values, thus simplifying the semiconductor device manufacturing process.

[0050] In practical applications, the specific structure of the aforementioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in this embodiment of the invention can be a silicon, germanium-silicon, germanium, or other semiconductor substrate without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate with some structure formed. For example, when the semiconductor device provided in this embodiment of the invention is a device in the second or higher layer of an integrated circuit, the semiconductor substrate includes semiconductor structures located below at least five types of gate-ring transistors, etc.

[0051] For the aforementioned at least five types of gate-around transistors, the embodiments of the present invention do not specifically limit the number of gate-around transistors disposed on the semiconductor substrate, the number of gate-around transistors included in each type, the threshold voltage magnitude, or the distribution among different gate-around transistors; these can be set according to actual needs. Specifically, the semiconductor device provided by the embodiments of the present invention may include only five types of gate-around transistors, or it may include six, eight, ten, etc., types of gate-around transistors. Within the same type of gate-around transistor, there may be only one gate-around transistor, or there may be multiple gate-around transistors.

[0052] From a structural perspective, such as Figure 17As shown, each type of gate-around transistor 12 includes a source region 15, a drain region 16, a channel region 13, and a gate stack structure 17. In the same gate-around transistor 12, the source region 15 and the drain region 16 are spaced apart. The channel region 13 is located between the source region 15 and the drain region 16, and contacts both the source region 15 and the drain region 16. The channel region 13 may include only one layer of nanostructure 14, or it may include multiple layers of nanostructure 14 spaced apart along the thickness direction of the semiconductor substrate 11. Each nanostructure 14 has a gap with the semiconductor substrate 11. The gate stack structure 17 surrounds the outer periphery of each nanostructure 14 layer. The gate stack structure 17 may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the outer periphery of each nanostructure 14 layer included in the channel region 13 and covers the corresponding gate formation region portion of the semiconductor substrate 11. The gate is located on the gate dielectric layer.

[0053] In terms of materials, the source and drain regions can be made of any semiconductor material such as silicon, germanium-silicon, or germanium. In the gate stack structure, the gate dielectric layer can be made of insulating materials such as HfO2, ZrO2, TiO2, or Al2O3, while the gate material can be made of conductive materials such as TiN, TaN, or TiSiN.

[0054] As for the material of the channel region of each type of gate ring transistor, it can be determined according to the threshold voltage requirements of each type of gate ring transistor in the actual application scenario, as long as at least part of the nanostructures included in the different channel regions of different types of gate ring transistors are different.

[0055] Specifically, such as Figure 17 As shown, among different types of gate-ring transistors 12, some gate-ring transistors 12 may have a single-layer nanostructure 14 in the channel region 13, while others may have a stacked structure comprising at least two semiconductor layers 22 disposed along the thickness direction of the semiconductor substrate 11. Within the same nanostructure 14, the materials of different semiconductor layers 22 are different.

[0056] For example, the nanostructures included in the gate-around transistor are made of Si. 1-x Ge x When 0 ≤ x ≤ 1, the germanium content in at least a portion of the nanostructures in different channel regions of different types of gate-ring transistors varies. The difference in germanium content in at least a portion of the nanostructures in different channel regions of different types of gate-ring transistors can be determined based on the threshold voltage requirements of different types of gate-ring transistors in practical applications, and is not specifically limited here.

[0057] For example, in different types of gate ring transistors, the germanium content in at least a portion of the nanostructures included in different channel regions can differ by at least 20%.

[0058] For example: Figure 17 As shown, five types of gate-around transistors 12 can be disposed on the semiconductor substrate 11. Among them, the channel region 13 of three types of gate-around transistors 12 includes a single-layer nanostructure 14. The channel region 13 of two types of gate-around transistors 12 includes a double-layer nanostructure 14. Specifically, the material of the nanostructure 14 included in the channel region 13 of the first type of gate-around transistor can include Si, and the material of the nanostructure 14 included in the channel region 13 of the second type of gate-around transistor can also include Si. 0.75 Ge 0.25 The material of the nanostructure 14 included in the channel region 13 of the third type of gate-around transistor may include Si. 0.5 Ge 0.5 The channel region 13 of the fourth type of gate-around transistor includes a nanostructure 14 whose material may include Si and Si. 0.5 Ge 0.5 The material of the nanostructure 14 included in the channel region 13 of the fifth type of gate-around transistor may include Si. 0.75 Ge 0.25 and Si 0.5 Ge 0.5 In the above scenario, the nanostructures 14 of the first to third types of gate-around transistors are staggered, and the Si material portion of the nanostructure 14 of the fourth type of gate-around transistor is staggered with the nanostructures 14 of the second, third, and fifth types of gate-around transistors, respectively, and aligned with the nanostructure 14 of the first type of gate-around transistor. The Si material portion of the nanostructure 14 of the fourth type of gate-around transistor... 0.5 Ge 0.5 The materials in the nanostructure 14 of the first and second type ring gate transistors, and the nanostructure 14 of the fifth type ring gate transistor, are respectively made of Si. 0.5 Ge 0.5 The Si in the nanostructure 14 of the fifth type of gate ring transistor is partially interleaved and aligned with the nanostructure 14 included in the third type of gate ring transistor. Similarly, the Si in the nanostructure 14 of the fifth type of gate ring transistor is partially interleaved and aligned with the nanostructure 14 included in the fifth type of gate ring transistor. 0.5 Ge 0.5 The materials are respectively related to the nanostructure 14 included in the first and second types of gate ring transistors, and the material Si in the nanostructure 14 included in the fifth type of gate ring transistor. 0.75 Ge 0.25 The portion is staggered and aligned with the nanostructure 14 included in the third type of gate ring transistor. The Si in the nanostructure 14 included in the fourth type of gate ring transistor... 0.75 Ge 0.25 The material portions are staggered with the nanostructures 14 included in the first, third, and fifth type ring gate transistors, respectively, and aligned with the nanostructures 14 included in the second type ring gate transistor.

[0059] In at least two types of gate-around transistors, where the channel region comprises nanostructures using at least two materials, the thicknesses of the different material portions of the nanostructures can be the same or different. Furthermore, in at least five types of gate-around transistors, the thicknesses of the nanostructures comprising different channel regions belonging to at least two types of gate-around transistors can be the same or different. The thickness of the portions of the same material, as well as the number and distribution of the portions of different materials within the nanostructures of each type of gate-around transistor, can be determined based on the threshold voltage requirements of the gate-around transistor in the actual application scenario, and are not specifically limited here.

[0060] In addition, in practical applications, the parts of the channel region containing the same material in different types of gate ring transistors can be integrally formed, which further simplifies the manufacturing process of semiconductor devices and helps to control the manufacturing cost of semiconductor devices.

[0061] It should be noted that, as Figures 10 to 17 As shown, a gate-ring transistor 12 comprising a partial semiconductor layer 22 at the bottom layer of the nanostructure 14 is defined as a target type of gate-ring transistor 26. The partial semiconductor layer 22 at the bottom layer is determined relative to the semiconductor device manufacturing process and the specific structure of the nanostructure 14 included in other types of gate-ring transistors 12. For example: Figures 10 to 17 As shown, in the first type of gate ring transistor and the fourth type of gate ring transistor, the nanostructure 14 includes a portion of the semiconductor layer 22 located at the bottom layer. Therefore, the first type of gate ring transistor and the fourth type of gate ring transistor are target type gate ring transistors. In this case, the thickness of the portion of the semiconductor substrate 11 located below the target type gate ring transistor is less than the thickness of the portion located below the other type of gate ring transistor 12, so that the gate stack structure 17 can surround the outer periphery of the nanostructure 14 located at the bottom layer in the first type of gate ring transistor and the fourth type of gate ring transistor.

[0062] Secondly, such as Figure 17 As shown, the gate stack structure 17 included in different types of ring gate transistors 12 is made of the same material to further simplify the manufacturing process of semiconductor devices and reduce the manufacturing difficulty of semiconductor devices.

[0063] In some cases, such as Figure 17 As shown, the gate-ring transistor 12 may further include a gate sidewall 19. The gate sidewall 19 is disposed on both sides of the gate stack structure 17 along the length direction to isolate the gate stack structure 17 from other conductive structures and ensure that the semiconductor device has stable electrical characteristics.

[0064] In some cases, such as Figures 3 to 17As shown, the semiconductor device provided by the present invention may further include a shallow trench isolation structure 18 and / or an interlayer dielectric layer 20. The shallow trench isolation structure 18 is located on the semiconductor substrate 11 and is used to isolate different active regions of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 18 can be set according to actual conditions. The interlayer dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 17, used to protect the source region 15 and drain region 16 from etching and cleaning operations when at least a portion of the first mask structure 23 and the corresponding semiconductor layer 22 are removed.

[0065] The material of at least one of the above-mentioned gate sidewall, shallow trench isolation structure and interlayer dielectric layer can be insulating materials such as SiN, Si3N4, SiO2 or SiCO.

[0066] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 17 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps: First, a semiconductor substrate 11 is provided. Next, at least five types of gate-around transistors 12 are formed on the semiconductor substrate 11. Different types of gate-around transistors 12 are spaced apart along a direction parallel to the surface of the semiconductor substrate 11. Among the different types of gate-around transistors 12, at least a portion of the nanostructures 14 included in different channel regions 13 are made of different materials, and the portions of the nanostructures 14 with different materials in the different channel regions 13 are staggered along the thickness direction of the semiconductor substrate 11. Among the at least five types of gate-around transistors 12, portions of the nanostructures 14 included in different channel regions 13 belonging to at least two types of gate-around transistors 12 are made of the same material, and the portions of the nanostructures 14 with the same material in the different channel regions 13 are aligned along the thickness direction of the semiconductor substrate 11.

[0067] It should be noted that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as that of the semiconductor device provided in the first aspect. Therefore, the information on the structure and materials of various gate ring transistors in the second aspect can be referred to the information on the structure and materials of various gate ring transistors in the first aspect above. In addition, the beneficial effects of the second aspect and its various implementations in the present invention can also be referred to the beneficial effect analysis in the first aspect and its various implementations, and will not be repeated here.

[0068] For example, forming at least five types of gate-around transistors on a semiconductor substrate may include the following steps:

[0069] like Figure 1 and Figure 2As shown, at least five types of fin structures 21 with the same structure and spaced apart are formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, each type of fin structure 21 includes at least three semiconductor layers 22 that are alternately stacked and made of different materials.

[0070] Specifically, each of the aforementioned semiconductor layers can be used to fabricate at least a portion of the corresponding nanostructure in the corresponding type of gate-ring transistor. In this case, the material, number of layers, and positional relationship between semiconductor layers of different materials in the fin structure can be determined based on the materials of different parts of the nanostructure and the relative positional relationship between parts of different materials along the thickness direction of the semiconductor substrate. Alternatively, only a portion of the semiconductor layers in the fin structure can be used to fabricate at least a portion of the corresponding nanostructure in the corresponding type of gate-ring transistor, and some semiconductor layers can be used to form at least a portion of the gaps between adjacent nanostructures in the same channel region. In this case, the material of the semiconductor layer corresponding to the gap can be any semiconductor material different from the nanostructure material, and the thickness of the semiconductor layer corresponding to the gap can be determined based on the thickness of the gate stack structure, without specific limitations here.

[0071] For example: Figures 1 to 17 As shown, in the case where the manufactured semiconductor device includes five types of gate ring transistors 12, if each semiconductor layer 22 is used to manufacture at least a portion of the corresponding nanostructure 14 in the corresponding type of gate ring transistor 12, then the fin structure 21 may include only three semiconductor layers 22 of different materials.

[0072] For example, if the manufactured semiconductor device includes five types of gate ring transistors, and only a portion of the semiconductor layers are used to manufacture at least a portion of the corresponding nanostructure in the corresponding type of gate ring transistor, then the fin structure may include at least four semiconductor layers.

[0073] In the actual manufacturing process, such as Figure 1 As shown, at least three semiconductor layers 22, made of different materials and alternately stacked along the thickness direction of the semiconductor substrate 11, can be formed on the semiconductor substrate 11 using processes such as epitaxy. Next, as... Figure 2 As shown, photolithography and etching processes can be used to selectively etch at least three alternately stacked semiconductor layers 22 to form at least five types of fin structures 21. Specifically, in the case where the manufactured semiconductor device does not include a shallow trench isolation structure, only the at least three alternately stacked semiconductor layers need to be selectively etched, and the remaining at least three semiconductor layers after selective etching form fin structures. Alternatively, as... Figure 2As shown, when the manufactured semiconductor device also includes a shallow trench isolation structure 18, at least three semiconductor layers 22 and a portion of the semiconductor substrate 11 need to be selectively etched to form fins; then, as... Figure 2 As shown, a shallow trench isolation structure 18 is formed on a semiconductor substrate 11 using processes such as deposition and etching. The top height of the shallow trench isolation structure 18 is lower than the bottom height of the underlying semiconductor layer 22, and the portion of the fins exposed outside the shallow trench isolation structure 18 is a fin-like structure 21.

[0074] Next, as Figure 3 As shown, a first mask structure 23 is formed across each type of fin structure 21.

[0075] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, photolithography and etching processes are used to selectively etch the mask material to form the first mask structure described above. The material of the first mask structure can be set according to actual needs, as long as it can provide mask protection in the subsequent process.

[0076] For example, the first mask structure described above may include a sacrificial gate. The material of the sacrificial gate may include a material that is easily removable, such as polysilicon. Secondly, the first mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include a material such as silicon oxide. Additionally, the first mask structure may also include a sacrificial gate and gate sidewalls located at least on both sides of the sacrificial gate along its length. The material of the gate sidewalls can be referred to the preceding text and will not be repeated here. Furthermore, the first mask structure may simultaneously include the aforementioned gate oxide layer, sacrificial gate, and gate sidewalls.

[0077] Next, as Figures 4 to 7 As shown, the portion of each type of fin structure 21 exposed outside the first mask structure 23 is processed to form the source region 15 and drain region 16 included in each type of ring gate transistor 12.

[0078] In actual manufacturing, processes such as ion implantation can be used to directly dope the portion of each type of fin structure exposed outside the first mask structure to form the source and drain regions of the corresponding gate-ring transistor. Alternatively, wet etching or dry etching can be used to selectively remove the portion of the fin structure exposed outside the first mask structure; then, epitaxial growth can be used to form the source and drain regions of the gate-ring transistor on both sides of the remaining fin structure.

[0079] It should be noted that when the materials, conductivity types, and doping of the source and drain regions of different types of gate-ring transistors are the same, the above operations can be performed simultaneously on different types of fin structures. This allows for the simultaneous formation of the source and drain regions of different types of gate-ring transistors, thereby improving the manufacturing efficiency and reducing the manufacturing cost of semiconductor devices. Alternatively, as... Figure 6 and Figure 7 As shown, under the protection of the corresponding second mask structure 24 (photoresist mask or silicon nitride mask, etc.), the above-described process can be performed on a type of fin structure first to form the source region 15 and drain region 16 included in that type of gate ring transistor. Then, the previously formed second mask structure 24 is removed, and a new second mask structure 24 is formed covering the corresponding fin structure and the previously formed source region 15 and drain region 16. The previous step is repeated until the source region 15 and drain region 16 included in all types of gate ring transistors are formed.

[0080] Next, as Figure 8 As shown, an interlayer dielectric layer 20 covering the semiconductor substrate 11 can be formed using processes such as deposition and chemical mechanical polishing. The top of this interlayer dielectric layer 20 is flush with the top of the first mask structure 23. The material of the interlayer dielectric layer 20 can be referred to the previous text and will not be repeated here.

[0081] Next, as Figure 9 As shown, at least part of the first mask structure is removed using dry etching or wet etching processes.

[0082] Specifically, whether or not the entire first mask structure needs to be removed depends on its specific structure. For example, if the first mask structure only includes the gate oxide layer and the sacrificial gate, then the entire first mask structure needs to be removed. As another example, if the first mask structure includes the sacrificial gate and the gate sidewall, then only the sacrificial gate needs to be removed, meaning only a portion of the first mask structure needs to be removed.

[0083] Next, as Figures 10 to 16 As shown, a portion of the semiconductor layer in a type of fin structure is selectively removed so that the remaining semiconductor layer in this type of fin structure forms the channel region 13 included in the corresponding ring gate transistor 12; and this step is repeated until the channel region 13 included in all ring gate transistors 12 is formed.

[0084] In the actual manufacturing process, the fin-like structure to be processed is defined as the target type fin-like structure. Based on this, such as Figures 10 to 16As shown, a third mask structure 25 (photolithography mask or silicon nitride mask, etc.) can be formed over the remaining fin-like structures other than the target fin-like structure using processes such as deposition and etching. Then, based on the material of the nanostructure 14 included in the corresponding gate-ring transistor formed by the target fin-like structure, a portion of the semiconductor layer in one type of fin structure (i.e., the target fin-like structure) is selectively removed using dry etching or wet etching processes. (The semiconductor layer to be removed is a semiconductor layer different from the nanostructure material included in the corresponding gate-ring transistor), thereby allowing the remaining semiconductor layer in this type of fin structure to form the channel region 13 included in the corresponding gate-ring transistor. Then, the previously formed third mask structure is removed. The above operation is repeated until the channel regions 13 included in all gate-ring transistors are formed.

[0085] It should be noted that, as Figure 11 and Figure 14 As shown, if a portion of the nanostructure 14 in a gate ring transistor 12 includes a portion of the semiconductor layer 22 located at the bottom layer, and the gate ring transistor 12 with the nanostructure 14 including the portion of the semiconductor layer 22 located at the bottom layer is defined as the target type gate ring transistor 26, then after removing at least a portion of the first mask structure, before forming the gate stack structure 17 surrounding the channel region 13 included in each type of gate ring transistor 12, it is necessary to selectively remove a portion of the semiconductor substrate 11 located below the target type gate ring transistor 26 using a dry etching or wet etching process under the protection of the corresponding third mask structure 25, so as to release the nanostructure 14 located at the bottom layer.

[0086] Next, as Figure 17 As shown, a gate stack structure 17 can be formed around the channel region 13 included in each type of gate ring transistor 12 using processes such as atomic layer deposition. The material of this gate stack structure 17 can be referred to the previous text and will not be repeated here.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0088] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, and at least five types of gate ring transistors disposed on the semiconductor substrate; the different types of gate ring transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate; Among the different types of gate ring transistors, at least a portion of the nanostructures included in different channel regions are made of different materials, and the portions of the nanostructures included in different channel regions that are made of different materials are staggered along the thickness direction of the semiconductor substrate; among the at least five types of gate ring transistors, the portions of the nanostructures included in different channel regions belonging to at least two types of gate ring transistors are made of the same material, and the portions of the nanostructures included in different channel regions that are made of the same material are aligned along the thickness direction of the semiconductor substrate; In at least five types of gate ring transistors, the surface height of the semiconductor substrate is different in the region where at least two types of gate ring transistors are located.

2. The semiconductor device according to claim 1, characterized in that, In at least two types of gate-ring transistors, the nanostructure comprising the channel region has at least two materials, and the portions of the nanostructure made of different materials have the same thickness.

3. The semiconductor device according to claim 1, characterized in that, The nanostructure of the gate-ring transistor includes Si. 1-x Ge x , 0≤x≤1; In different types of gate ring transistors, the germanium content in at least a portion of the nanostructures included in different channel regions varies.

4. The semiconductor device according to claim 3, characterized in that, In the different types of gate ring transistors, the germanium content in at least a portion of the nanostructures included in the different channel regions differs by at least 20%.

5. The semiconductor device according to claim 1, characterized in that, Of the at least five types of gate ring transistors, the nanostructures in different channel regions belonging to at least two types of gate ring transistors have different thicknesses.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The portions of the channel regions of different types of gate-around transistors that are made of the same material are integrally formed; And / or, the gate stack structures of different classes of ring gate transistors are made of the same material.

7. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; At least five types of gate-around transistors are formed on the semiconductor substrate; different types of gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate; wherein, in different types of gate-around transistors, at least a portion of the nanostructures included in different channel regions are made of different materials, and the portions of the nanostructures included in different channel regions that are made of different materials are staggered along the thickness direction of the semiconductor substrate; in the at least five types of gate-around transistors, the portions of the nanostructures included in different channel regions belonging to at least two types of gate-around transistors are made of the same material, and the portions of the nanostructures included in different channel regions that are made of the same material are aligned along the thickness direction of the semiconductor substrate; In at least five types of gate ring transistors, the surface height of the semiconductor substrate is different in the region where at least two types of gate ring transistors are located.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The formation of at least five types of gate-around transistors on the semiconductor substrate includes: At least five types of fin structures with the same structure and spaced apart are formed on the semiconductor substrate; each type of fin structure includes at least three semiconductor layers of different materials that are alternately stacked along the thickness direction of the semiconductor substrate. A first mask structure is formed transversely on each type of fin-like structure; The portion of each type of fin structure exposed outside the first mask structure is processed to form the source and drain regions included in each type of ring gate transistor; Remove at least a portion of the first mask structure; Selectively remove a portion of the semiconductor layer in one type of fin structure, so that the remaining semiconductor layer in this type of fin structure forms the channel region included in the corresponding type of gate ring transistor; and repeat this step until the channel regions included in all types of gate ring transistors are formed; A gate stack structure is formed around the outer periphery of the channel region included in each type of ring gate transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The nanostructure includes a ring-gate transistor located in the bottom portion of the semiconductor layer, which is a target type ring-gate transistor; After removing at least a portion of the first mask structure, and before forming the gate stack structure surrounding the outer periphery of the channel region included in each type of the gate ring transistor, the method of manufacturing the semiconductor device further includes selectively removing a portion of the thickness of the semiconductor substrate located below the target type of gate ring transistor.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of at least five types of fin-like structures that are spaced apart and have the same structure on the semiconductor substrate includes: At least three semiconductor layers of different materials are formed on the semiconductor substrate and are alternately stacked along the thickness direction of the semiconductor substrate; At least three semiconductor layers that are alternately stacked are selectively etched to form the at least five types of fin structures.

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