Selective transfer of thermal management die

Abstract

An embodiment discloses an electronic device including an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

Description

Background Art

[0001] In semiconductor manufacturing, layers are transferred from one substrate to another using layer transfer techniques, which are usually performed at the wafer level. These techniques require the entire layer to be transferred intact, regardless of whether the entire layer is needed. Therefore, any unwanted portions of the transferred layer must be etched away after the transfer, which increases cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figures 1A-1I An exemplary process flow for selective layer transfer using selective release technology is shown.

[0003] Figure 2A-2I An exemplary process flow for selective layer transfer using blanket laser exposure is shown.

[0004] Figures 3A-3I An exemplary process flow for selective layer transfer from a singulated donor substrate is shown.

[0005] Figures 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown.

[0006] Figures 5A-5F An exemplary process flow for forming an integrated circuit package using selective transfer of a passive interposer is shown.

[0007] Figure 6A-6B An example of selective layer transfer between wafers is shown.

[0008] Figure 7 A flow chart for performing a selective layer transfer is shown.

[0009] Figures 8A-8C An exemplary process flow for selective layer transfer using selective release techniques for a thermal management die is shown.

[0010] Fig. 9 A package including a thermal management die selectively transferred to a single base die is shown.

[0011] Fig.10 A package including a thermal management die selectively transferred to a exploded base die is shown.

[0012] Fig.11 A package including a structural layer over a thermal management die that is selectively transferred to a single base die is shown.

[0013] Fig.12 A package including a structural layer over a thermal management die that is selectively transferred to a decomposed base die is shown.

[0014] Figures 13A-13D An exemplary base die topography for selective transfer of a thermal management die is shown.

[0015] Fig.14 A flow chart for selective transfer of thermal management dies is shown.

[0016] Fig.15 Another flow chart for selective transfer of thermal management dies is shown.

[0017] Fig.16 Shown are top views of wafers and dies that may be included in a microelectronic assembly.

[0018] Fig.17 A cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly is shown.

[0019] Figures 18A-18D Perspective views of exemplary planar, FinFET, gate-around, and stacked gate-around transistors are shown.

[0020] Fig.19 A cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly is shown.

[0021] Fig. 20 A block diagram of an exemplary electrical device that may include a microelectronic assembly is shown. DETAILED DESCRIPTION

[0022] Selective layer transfer

[0023] In semiconductor manufacturing, a layer is transferred from one substrate to another using a layer transfer technique, which is usually performed at a wafer level. Layer transfer is used for a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material fabrication, III-V semiconductors on complementary metal oxide semiconductors (CMOS), and traditional CMOS applications, such as metal-insulator-metal (MIM) devices and thin devices and / or interconnect layer transfers. Current layer transfer techniques are limited to complete layer transfers, but when a complete layer is not required, doing so may affect cost and performance. For example, blanket layer transfer techniques (e.g., ion cutting and laser debonding layer transfers) require the entire transfer of a complete layer. Therefore, any unwanted areas of the transferred layer must be etched away after the transfer, which results in increased cost and process complexity.

[0024] Alternatively, specific dies or chiplets may be transferred using pick and place techniques. For example, a chiplet generally refers to an integrated circuit (IC) containing a well-defined subset of functions that is designed to be combined with other chiplets to form a single IC package. In order to transfer a chiplet (e.g., for MIM chiplet integration in a system on a chip (SoC)), a chiplet device is fabricated on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into chiplets, and the chiplets are then individually attached to a receptor substrate (e.g., a SoC wafer or package) using a pick and place machine. This significantly increases cost because additional processing is required to singulate the wafer and individually attach the corresponding chiplet dies. For example, chiplets are generally manufactured on relatively thick substrates so that they can be manipulated without being damaged during the singulation and attachment steps, and after the attachment step, additional processing is performed to thin the chiplets and / or remove the carrier substrate, which further increases cost and process complexity. Specifically, chiplets are typically fabricated on substrates that are over 700 micrometers (μm or micron) thick to provide structural and mechanical stability during fabrication, and can be thinned to approximately 20-100 μm by backside grinding after the singulation / attachment step. However, grinding typically results in planing along the edges of the chiplet die. Furthermore, it can be difficult to thin chiplets beyond 20 μm without creating defects. Similarly, chiplets are typically singulated with die areas on the order of millimeters, as the thickness of the die is often limited for chips less than 1 square millimeter (mm2). 2 ) makes picking and placing components very difficult for small chips.

[0025] Integrated circuits can also be manufactured in a monolithic manner, where all IC components and interconnections are fabricated sequentially on the same underlying substrate or wafer. However, monolithic ICs have various limitations, including design restrictions due to incompatible processes, lack of flexibility, and low yields.

[0026] Accordingly, the present disclosure proposes selective layer transfer techniques for selectively transferring portions of layers between substrates together with devices and systems formed using the portions. For example, one or more of the described techniques enable selected areas on a donor substrate to be transferred to a receptor substrate, which enables the donor substrate to be reused multiple times while also addressing the limitations described above for blanket layer transfer and pick-and-place techniques. Specifically, the described solutions (e.g., one or more of the embodiments described herein) use selective release techniques on a donor substrate (e.g., a wafer, panel, or die) in combination with a patterned bonding template on a receptor substrate (e.g., a wafer, panel, or die), thereby allowing selected areas of a layer on a donor substrate to be transferred to a receptor substrate. For the purposes of the present disclosure, the term layer may sometimes be used to refer to a single layer of a single material or a multilayer of one or more materials. For example, a selective transfer layer may be formed on a substrate, and the layer may be a single material layer, or may be a stack of layers that together form a layer of IC components (e.g., a die, interconnect, bridge, capacitor, and / or other semiconductor devices). Layers may also include stacked wafers, e.g., wafer-to-wafer bonded and stacked logic and / or memory wafers. As an example, a donor wafer may include a layer of IC components (e.g., IC dies), and selective layer transfer may be used to selectively transfer a specific subset of these IC components to a recipient wafer simultaneously.

[0027] The described solution provides various advantages. For example, the described solution enables transfer of selected areas of a donor wafer (as opposed to an entire layer), which enables the donor wafer to be reused for multiple products, thereby amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) across multiple wafers. This solution also eliminates the need to etch away excess areas required for a full layer transfer, and as a result, the selectively transferred areas may not have tapered edges resulting from etching, or may have a reverse tapered shape due to etching performed for singulation prior to transfer, unlike the areas etched after the full layer transfer.

[0028] Furthermore, in various examples, IC component layers may be selectively transferred at any suitable level of granularity, including complete IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, and the like.

[0029] This solution also enables the selective transfer of areas with ultra-thin layers without the added handling and yield loss caused by the handling difficulties of the chiplet pick and place method (e.g., singulation, attaching each chiplet individually, post-attachment thinning of the chiplets). This helps to reduce the Z height of the product (e.g., for form factor, thermal and / or power delivery reasons) as well as the overall process complexity. For example, very thin IC dies or chiplets can be formed on any substrate and selectively transferred directly from the substrate. Therefore, selective transfer of these dies not only eliminates the need for post-attachment thinning, but also enables these dies to be much thinner than dies subjected to singulation, pick and place attachment, and subsequent thinning thereafter. In some cases, for example, the described solution can enable the transfer of dies having thicknesses ranging from 100 nanometers (nm) to 5μm or more. Furthermore, since post-attachment thinning is not required, the selectively transferred die can have no or minimal gouging on the die edges since no grinding is performed, unlike thinning the chiplets after attachment.

[0030] Similarly, the described solution supports the selective transfer of very small areas (e.g., very small dies or chiplets) on a donor substrate, which is very challenging using pick and place techniques. In some cases, for example, the described solution can enable selective transfer of very small areas (e.g., very small dies or chiplets) on a donor substrate, which is very challenging using pick and place techniques. 2 Transfer of a die (or other IC component) with an area of ​​100 μm 2 (10μmx10μm), 10000μm 2 (100μmx100μm), 810000μm 2 The transfer of dies (or other IC components) of an area of ​​(900 μm x 900 μm) or the like is possible, and there is no limit on the maximum size of the area that can be selectively transferred.

[0031] This solution also supports the selective transfer of dies with non-standard shapes and designs that are difficult to manipulate using pick and place machines, for example, dies with atypical shapes, arbitrary shapes, irregular shapes, or non-convex shapes (e.g., L-shape, U-shape, shapes with sharp angles), dies with high aspect ratios (e.g., 8:1 or higher aspect ratios), dies with holes, and the like.

[0032] Furthermore, this solution has very low topography and supports high surface cleanliness and planarization (eg, using chemical mechanical polishing (CMP) processes), which makes it compatible with hybrid and fusion bonding processes. Additional advantages are described throughout this disclosure and are apparent from the description below.

[0033] Accordingly, this solution enables the manufacture of complex IC packages and products by selectively transferring certain components (e.g., active circuitry such as IC dies, passive circuitry) rather than incorporating these components using conventional processes such as: (i) entire layer transfer and etching away excess area; (ii) pick and place assembly of individual IC components; and / or (iii) monolithic IC fabrication.

[0034] Figures 1A-1I An exemplary process flow for selective layer transfer using a selective release technique is shown. In the illustrated example, a layer of integrated circuit (IC) components is selectively transferred from a donor substrate 100 to an acceptor substrate 110, as further described below.

[0035] exist Figure 1A , a release layer 102 is formed on a carrier substrate, referred to as a donor substrate 100. The release layer 102 is a temporary bonding and debonding layer for selectively transferring the layer 104. In some embodiments, the release layer 102 may include one or more layers and / or one or more materials capable of providing adhesion to the donor substrate 100 and / or absorbing energy from a laser (e.g., a laser beam), for example, (one or more) lossy dielectric and / or thin metal layers that provide adhesion and absorb / reflect infrared (IR) light, (one or more) organic polymer layers (e.g., polyimide) that provide adhesion and absorb visible or ultraviolet (UV) light, and / or (one or more) patterned dielectric layers with anchors to provide residual adhesion (e.g., after ablation of a metal layer by an IR laser).

[0036] The layer 104 to be selectively transferred is formed on the release layer 102 on the donor substrate 100, for example, by directly fabricating the layer 104 (e.g., on the release layer 102) or blanket transferring the layer 104. The selectively transferred layer 104 may include one or more material layers, for example, a single material layer or a stack of layers that together form a layer of IC components (e.g., a complete IC die, a chiplet, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor devices). In some embodiments, for example, the selectively transferred layer 104 may be a pre-fabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies that is blanket transferred to the release layer 102 on the donor substrate 100.

[0037] exist Figure 1BIn the process, the selective transfer layer 104 is sliced ​​over the donor substrate 100 (without cutting through the donor substrate 100) using a technique such as etching, reactive ion etching (RIE), plasma dicing, mechanical sawing, etc., thereby partially singulating the IC components 106 in the layer 104. In some embodiments, the release layer 102 may also be singulated (e.g., sliced ​​or etched) together with the transfer layer 104.

[0038] exist Figure 1C In the embodiment of the present invention, a release layer 112 is optionally formed over another carrier substrate, referred to as an acceptor substrate 110. For example, if the selectively transferred IC component 106 is to be subsequently debonded from the acceptor substrate 110 after transfer, the release layer 112 may be formed over the acceptor substrate 110. Otherwise, if the selectively transferred IC component 106 is to remain on the acceptor substrate 110 after transfer, the release layer 112 on the acceptor substrate 110 may be omitted.

[0039] Next, a bonding template including bonding features 114 is formed on a surface of acceptor substrate 110 (e.g., over release layer 112, if included). The bonding template includes a pattern of bonding features 114 or bonding areas that enable specific areas on donor substrate 100 to be selectively transferred to acceptor substrate 110. For example, the locations of bonding features 114 or bonding areas on acceptor substrate 110 correspond to areas or IC components 106 on donor substrate 100 that are to be transferred to acceptor substrate 110.

[0040] In some embodiments, for example, the bonding features 114 may include "island" or "mesa" features that are similar in size to the target area to be transferred from the donor substrate 100. For example, each island or mesa feature may be an elevated structure on the surface of the acceptor substrate 110 that occupies an area (e.g., shape / surface area) similar to the corresponding IC component 106 on the donor substrate 100. In other embodiments, the bonding features 114 are replaced by lithographic or additively manufactured surface treatments that enhance adhesion in the target area of ​​the acceptor substrate 110 (e.g., the area where the bonding features 114 are shown) and prevent adhesion in other areas, including but not limited to surface topography changes, use of materials with high and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, etc.

[0041] In various embodiments, these bonding features 114 may be composed of a dielectric material, a conductive material (e.g., a metal), or both, depending on the desired electrical connection between the bonded IC component 106 and the receptor substrate 110. For example, the bonding features 114 may be a blanket dielectric structure without electrical contacts, or, where an electrical connection through the bonding interface is desired, the bonding features 114 may be a dielectric structure with electrical contacts therethrough.

[0042] exist Figure 1D In the process, the donor substrate 100 and the acceptor substrate 110 are brought into contact with each other, wherein their top surfaces are aligned face-to-face so that the target IC components 106 on the donor substrate 100 are aligned with the corresponding bonding features 114 on the acceptor substrate 110 .

[0043] exist Figure 1E In some embodiments, the donor substrate 100 and the acceptor substrate 110 are partially bonded together. For example, an area of ​​the acceptor substrate 110 having a protruding surface feature or "mesa" is bonded to a corresponding area on the donor substrate 100 having a target IC component 106, while other areas of the donor substrate 100 and the acceptor substrate 110 remain unbonded. In some embodiments, this is controlled, for example, by the height of the bonding protrusions (e.g., bonding features 114) to prevent undesirable contact between areas that will not be transferred. As mentioned above, this can also be controlled by surface treatment of different areas, thereby allowing good bonding in the target area (e.g., the area showing the bonding features 114) and preventing or reducing bonding in other areas.

[0044] exist Figure 1F In the present invention, the IC components 106 bonded to the acceptor substrate 110 are selectively debonded from the donor substrate 100 using a selective release technique, such as IR debonding, selective visible or ultraviolet (UV) laser exposure, etc. For example, a laser (e.g., an IR or UV laser) can be used to selectively remove or ablate the regions 103 of the release layer 102 where the IC components 106 are bonded to the donor substrate 100, thereby forming gaps or voids in the release layer 102 and allowing the IC components 106 to be released from the donor substrate 100.

[0045] exist Figure 1G , the donor substrate 100 and the acceptor substrate 110 are mechanically separated from each other. At this point, the IC components 106 that were selectively bonded to the acceptor substrate 110 (e.g., by the bonding features 114) and debonded from the donor substrate 100 remain on the acceptor substrate 110 and are separated from the donor substrate 100. All other IC components 106 that were not bonded to the acceptor substrate 110 remain on the donor substrate 100.

[0046] exist Figure 1H , the receptor substrate 110 is now ready for continued processing, such as dielectric fill 116 around the transferred IC components 106, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment to a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 112), and / or any other processing required for the finished product (e.g., an IC package).

[0047] exist Fig. 1I , and then the donor substrate 100 is reused to transfer the remaining IC components 106 (e.g., the remaining areas of the selectively transferred layer 104) to a new acceptor substrate 110'. The donor substrate 100 can be reused in this manner until all IC components 106 or the entire layer 104 are selectively transferred to any number of acceptor substrates 110.

[0048] It should be appreciated that the illustrated process flow for selective layer transfer is presented as an example only, and many other process variations are possible. For example, the donor substrate 100 and the acceptor substrate 110 can be wafers, panels, IC packages, chiplets, dies, or any combination thereof (e.g., for transfer from a wafer to a panel, from a chiplet to a wafer, etc.). In addition, each substrate 100, 110 can be composed of a variety of materials, including but not limited to inorganic materials such as silicon, silicon on insulator (SOI), quartz, glass, and / or III-V materials, organic materials such as IR or UV transparent epoxies, etc.

[0049] The materials used in the release layers 102, 112 may vary depending on the type of release or debonding technique used. For example, for infrared (IR) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing and / or reflecting infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing UV light (e.g., a wide range of organic polymers, including but not limited to polyimide). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)), which may be used to buffer laser ablation and thermal energy, control film interference or adhesion, and / or provide residual adhesion after weakening, removing and / or ablating other materials and / or layers in the release layers 102, 112 by laser.

[0050] The number of layers 104 on the donor substrate 100, the arrangement / structure of the layers 104, the materials in each layer 104, and the types of IC components 106 formed in the layers 104 may vary.

[0051] The bonding areas or bonding features 114 on the acceptor substrate 110 may be formed using any suitable surface treatment or other technique to control the bonding level in different areas, including but not limited to surface topography variations (e.g., terraces, depressions), use of high and / or low bonding materials, treatments using hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation treatments, etc. In addition, the bonding features 114 or bonding areas on the acceptor substrate 110 may vary in size, shape, height, topography, pattern, and material. For example, inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and / or silicon carbonitride (SiCN), organic dielectrics such as photoresists and adhesives, conductive materials such as metals, and combinations thereof may be used to form the bonding features 114.

[0052] The donor substrate 100 and the acceptor substrate 110 may be (partially) bonded using any suitable bonding technique, including but not limited to hybrid bonding, fusion bonding, and adhesive bonding. The donor substrate 100 and the acceptor substrate 110 may be debonded or released using any suitable debonding technique, including but not limited to IR and UV laser debonding. In addition, there may be an additional cleaning step so that the donor substrate 100 is reused after each selective layer transfer to the acceptor substrate 110.

[0053] In addition, in some embodiments, additional bonding and / or alignment features at the wafer level and / or the die level may be included (e.g., on the donor die, donor wafer, acceptor wafer, and / or the final product). For example, the donor and / or acceptor wafer may include a ridge or cross structure to facilitate bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across the wafer and / or through the center of the wafer, or a plurality of orthogonal ridges forming a cross pattern. Alignment features for wafers, small dies, and / or die arrays may also be included to facilitate bonding with proper alignment. In addition, multiple dies may be connected by small (e.g., dielectric) bridges to help them bond together and transfer together. For example, if some of the dies connected by the bridge are successfully bonded to the acceptor, the bridge may also help other bonding. Thus, these inter-die bridges may exist on the donor before transfer, and may exist on the acceptor and the final product after transfer.

[0054] Furthermore, in some cases, the debonding process may cause some unique damage or delamination near the edge and / or on the back side of the die, which does not affect the process performance but may indicate the use of this solution.

[0055] Figure 2A-2I An exemplary process flow for selective layer transfer using blanket laser exposure is shown. In the illustrated example, a layer 204 of integrated circuit (IC) components 206 is selectively transferred from a donor substrate 200 to a receptor substrate 210. However, prior to the transfer, the entire release layer 202 on the donor substrate 200 is mechanically weakened (e.g., using IR lasers, visible light lasers, UV lasers, chemical etching, and / or thermal techniques), which can also be referred to as a partial release. In this way, after the target IC component 206 on the donor 200 is bonded to the receptor 210, the target IC component can be completely released from the donor 200 by mechanically separating the donor 200 from the receptor 210. In some cases, this is similar to Figures 1A-1ICompared to the bonding / selective release / debonding process of the present invention, a simplified and faster bonding / debonding process can be obtained. Other variations of the process will be described in connection with other figures of this article. Alternatively, instead of using blanket laser exposure, the corresponding materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the bond with the donor 200 is weaker than the bond with the receptor 210 that is subsequently formed.

[0056] exist Figure 2A In the process, a release layer 202 is formed on a donor substrate 200. A layer 204 to be selectively transferred is formed on the release layer 202, for example, by directly fabricating the layer 204 (e.g., on the release layer 202) or blanket transferring the layer 204. In some embodiments, the selectively transferred layer 204 can be a layer of IC components (e.g., IC dies, chiplets, interconnects, bridges, capacitors, transistors, and / or other semiconductor devices).

[0057] exist Figure 2B In the embodiment of the present invention, the selectively transferred layer 204 is sliced ​​over the donor substrate 200 (without cutting through the entire donor substrate 200 ) to partially singulate the IC components 206 in the layer 204 .

[0058] exist Figure 2C In the embodiment of the present invention, a blanket laser exposure is performed on the donor release layer 202, thereby weakening the entire release layer 202 before transfer. In some embodiments, for example, the blanket laser exposure can be performed using laser (e.g., IR or UV laser exposure), chemical and / or thermal techniques. In this way, the weakened release layer 202 has a lower bonding energy, which results in partial release of the IC component 206 bonded to the layer 202.

[0059] exist Figure 2D In the embodiment, a release layer 212 is optionally formed over the acceptor substrate 210. For example, if the selectively transferred IC component 206 is to be subsequently debonded from the acceptor substrate 210 after transfer, the release layer 212 may be formed over the acceptor 210; otherwise, the release layer 212 on the acceptor 210 may be omitted.

[0060] Next, a bonding template 214 is formed on the surface of the acceptor substrate 210 (e.g., over the release layer 212 (if included)). The bonding template 214 includes a pattern of bonding features or bonding areas (e.g., mesas) that enable specific areas on the donor substrate 200 to be selectively transferred to the acceptor substrate 210. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 210 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments and / or surface activation techniques, etc.

[0061] exist Figure 2E In the process, the donor substrate 200 and the acceptor substrate 210 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 206 on the donor 200 are aligned with corresponding bonding features of the bonding template 214 on the acceptor 210 .

[0062] exist Figure 2F In the embodiment, a donor substrate 200 and an acceptor substrate 210 are partially bonded together, wherein a region of the donor 200 having a target IC component 206 is bonded to a region of the acceptor 210 having a bonding mesa of a bonding template 214 .

[0063] exist Figure 2G , the donor substrate 200 and the acceptor substrate 210 are mechanically separated from each other. At this point, the IC components 206 that were selectively bonded (e.g., by the bonding mesas of the bonding template 214) to the acceptor 210 remain on the acceptor 210 and are debonded / separated from the donor 200 due to the blanket weakening of the donor release layer 202. All other IC components 206 that were not bonded to the acceptor 210 remain on the donor 200.

[0064] Alternatively, in some embodiments, as an implementation Figure 2C As an alternative to (or in addition to) blanket laser exposure in the embodiment of the present invention, the respective materials used in the donor release layer 202 and the receptor bonding template 214 can be selected so that the target IC component 206 will have a stronger bond with the receptor 210 than with the donor 200. In this way, when the donor 200 and the receptor 210 are mechanically separated, the target IC component 206 will be debonded from the donor 200 and remain on the receptor 210 due to the difference in bonding strength.

[0065] exist Figure 2H, the receptor substrate 210 is ready for continued processing, such as dielectric fill 216 around the transferred IC components 206, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment to a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 212), and / or any other processing required for the finished product (e.g., an IC package).

[0066] exist Fig.2I , and then the donor substrate 200 is reused to transfer the remaining IC components 206 (e.g., the remaining areas of the selectively transferred layer 204) to a new acceptor substrate 210'. The donor substrate 200 can be reused in this manner until all IC components 206 or the entire layer 204 are selectively transferred to any number of acceptor substrates 210.

[0067] Figure 2A-2I The components indicated by reference numerals in the figure may be Figures 1A-1I Furthermore, it should be appreciated that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to the process variations described throughout this disclosure.

[0068] Figures 3A-3I An exemplary process flow for performing a selective layer transfer from a singulated donor substrate 300 is shown. In some cases, for example, if the percentage of integrated circuit (IC) components 306 transferred for each selective layer transfer is relatively small, it may be easier and more cost-effective to slice the donor substrate 300 and perform the transfer from singulated donor dies 301 containing a smaller subset of the IC components 306 from the original donor substrate 300. Accordingly, in the illustrated example, a donor substrate 300 having a layer 304 of IC components 306 is sliced, and the resulting layer of IC components 306 on the singulated donor dies 301 is selectively transferred to an acceptor substrate 310. In this way, the transfer is performed at the donor die level rather than at the wafer or panel level.

[0069] exist Figure 3A In the embodiment of the present invention, a release layer 302 is formed over a donor substrate 300. A layer 304 to be selectively transferred is formed over the release layer 302, for example, by directly fabricating the layer 304 or blanket transferring the layer 304. In some embodiments, the selectively transferred layer 304 may be a layer of IC components (e.g., IC dies, chiplets, interconnects, bridges, capacitors, transistors, and / or other semiconductor devices).

[0070] exist Figure 3BIn the embodiment of the present invention, the selective transfer layer 304 is sliced ​​over the donor substrate 300 (without cutting through the donor substrate 300), thereby partially singulating the IC components 306 in the layer 304. In some embodiments, the release layer 302 can also be singulated (e.g., sliced ​​or etched) together with the transfer layer including the IC components 306.

[0071] exist Figure 3C , a donor substrate 300 is diced into singulated donor dies 301, each of which contains a subset of IC components 306 from the original donor substrate 300. For example, each donor die 301 may include one or more IC components 306 from a layer 304 on the original donor substrate 300.

[0072] exist Figure 3D In the process, blanket laser exposure (as shown) or selective laser release is performed on the donor release layer 302 to weaken the entire release layer 302 before transfer (for example, using IR / UV laser exposure or thermal technology), thereby partially releasing the IC component 306 from the donor tube die 301.

[0073] exist Figure 3E , optionally, a release layer 312 is formed over the acceptor substrate 310 (e.g., in the case where the selectively transferred IC component 306 is subsequently debonded from the acceptor substrate 310 after transfer). Next, a bonding template 314 is formed on the surface of the acceptor substrate 310 (e.g., over the release layer 312 (if included)). The bonding template 314 includes a pattern of bonding features or bonding areas (e.g., mesas) that enable specific areas of the donor substrate 301 to be selectively transferred to the acceptor substrate 310. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 310 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among others.

[0074] exist Figure 3F In the embodiment of the present invention, a bonding head 320 is used to pick up one of the donor dies 301 and place it face down on an acceptor substrate 310 so that a target IC component 306 on the donor die 301 is aligned with a corresponding bonding mesa of a bonding template 314 on the acceptor substrate 310. Thereafter, the donor die 301 and the acceptor substrate 310 are partially bonded together (e.g., die-to-wafer bonding), wherein the target IC component 306 is bonded to the acceptor bonding mesa 314.

[0075] exist Figure 3GIn the process, the bond head 320 is lifted and the donor die 301 is mechanically separated from the acceptor substrate 310. At this point, the IC components 306 that were selectively bonded (e.g., by the bonding mesas of the bonding template 314) to the acceptor 310 remain on the acceptor 310 and are debonded / separated (e.g., die-to-wafer debonding) from the donor die 301 due to the blanket weakening of the donor release layer 302. All other IC components 306 that were not bonded to the acceptor substrate 310 remain on the donor die 301.

[0076] Alternatively, in some embodiments, as an implementation Figure 3D Alternatively (or in addition) to the blanket laser exposure in FIG. 1 , the target IC component 306 (eg, contact Figure 1F Alternatively, the donor release layer 302 and the acceptor bonding template 314 may be formed of materials with different bonding strengths so that the target IC component 306 will have a stronger bond with the acceptor substrate 310 than with the donor die 301.

[0077] exist Figure 3H and Fig. 3I In the embodiment, the bonding head 320 steps and repeats the operation. For example, the bonding head 320 moves to a new position and repeats the steps of Figure 3F and Figure 3G The process of selectively transferring another group of IC components 306 from the donor die 301 to other areas of the acceptor substrate 310 is performed.

[0078] The process may be repeated in this manner until all IC components 306 on the donor die 301 have been transferred. At this point, the bond head 320 may pick up another donor die 301 and continue transferring IC components 306 from the new donor die 301 to the same or a different receptor substrate 310.

[0079] After all transfers to receptor substrate 310 are complete, receptor 310 can be ready for continued processing, such as dielectric fill around transferred IC components 306, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment to a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 312), and / or any other processing required for a finished product (e.g., an IC package).

[0080] Figures 3A-3I The components indicated by reference numerals in the figure may be Figures 1A-1IFurthermore, it should be appreciated that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to the process variations described throughout this disclosure.

[0081] Figures 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown. In the illustrated example, integrated circuit (IC) components 414, 434 from multiple donor substrates 410, 430 are selectively transferred to an acceptor substrate 450 using intermediate carrier substrates 420, 440. In some embodiments, the respective donors 410, 430 may have different types of IC components 414, 434, for example, different types of IC dies or chiplets. In this way, multiple types of IC components (e.g., different types of dies or chiplets) may be transferred to the same acceptor substrate 450 using selective layer transfer. Although the illustrated example depicts selective transfers made from two types of donor substrates 410, 430 (e.g., having two types of IC components 414, 434), any number of donor substrates having any type of IC dies or other components are possible (including different die sizes).

[0082] exist Figure 4A , a layer of IC components 414 is selectively transferred from a first donor substrate 410 to an intermediate carrier substrate 420 (e.g., using any of the selective transfer processes described herein throughout). For example, a release layer 412 is formed over the donor substrate 410. Thereafter, the layer 414 to be selectively transferred is formed over the release layer 412 (e.g., by directly fabricating the layer 414 or blanket transferring the layer 414 from a wafer to the donor carrier 410), and the layer 414 is sliced ​​into partially singulated IC components 414. Separately, a release layer 422 is formed over the intermediate carrier / receiver substrate 420, and a bonding template 424 is formed on a surface of the intermediate carrier 420 (e.g., over the release layer 422). Thereafter, the donor 410 and the intermediate carrier 420 are partially bonded together (e.g., where the target IC component 414 on the donor 410 is bonded to a bonding feature or bonding area 424 on the intermediate carrier 420). Thereafter, the donor 410 and the intermediate carrier 420 are debonded and separated from each other using any of the techniques described throughout this disclosure (e.g., selective release, blanket laser exposure, etc.). Thus, the target IC component 414 is debonded / separated from the donor 410 and remains on the intermediate carrier 420.

[0083] exist Figure 4B, another layer of IC components 434 is selectively transferred from a second donor substrate 430 to another intermediate carrier substrate 440 (e.g., using any of the selective transfer processes described herein throughout). For example, a release layer 432 is formed over the donor substrate 430. Thereafter, the layer 434 to be selectively transferred is formed over the release layer 432 (e.g., by directly fabricating the layer 434 or blanket transferring the layer 434 from a wafer to the donor carrier 430), and the layer 434 is sliced ​​into partially singulated IC components 434. Separately, a release layer 442 is formed over the intermediate carrier / receiver substrate 440, and a bonding template 444 is formed on the surface of the intermediate carrier 440 (e.g., above the release layer 442). Thereafter, the donor 430 and the intermediate carrier 440 are partially bonded together (e.g., where the target IC component 434 on the donor 430 is bonded to a bonding feature or bonding area 444 on the intermediate carrier 440). Thereafter, the donor 430 and the intermediate carrier 440 are debonded and separated from each other using any of the techniques described herein (e.g., selective release, blanket laser exposure, etc.). Thus, the target IC component 434 is debonded / separated from the donor 430 and remains on the intermediate carrier 440.

[0084] exist Figure 4C , IC components 414, 434 located on both intermediate carriers 420, 440 are selectively transferred to an acceptor substrate 450 (e.g., using any of the selective transfer processes described herein throughout). For example, a release layer 452 is formed over the acceptor substrate 450 (e.g., in the case where the selectively transferred IC components 414, 434 are subsequently debonded from the acceptor substrate 450 after transfer). Thereafter, a bonding layer 454 (e.g., having bonding areas or bonding features) is formed on the surface of the acceptor substrate 450 (e.g., above the release layer 452 (if included)). Next, the IC component 414 located on the first intermediate carrier 420 is selectively transferred to the acceptor substrate 450 (e.g., using any of the selective transfer processes described herein throughout). Finally, the IC component 434 located on the second intermediate carrier 440 is selectively transferred to the acceptor substrate 450 (e.g., using any of the selective transfer processes described herein throughout).

[0085] Additional processing is then performed on the receptor substrate 450, such as cleaning steps (e.g., removing residual bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment to a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 452), and / or any other processing required for the finished product (e.g., an IC package).

[0086] It should be appreciated that the illustrated process flow for selective layer transfer is presented by way of example only, and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0087] Figures 5A-5F An exemplary process flow for forming an integrated circuit (IC) package 500 with a selectively transferred passive interposer 506 is shown. Selective transfer can be used for a variety of applications, including transfer of active components (e.g., IC die, transistors, diodes) and passive components (e.g., interconnects, metal-insulator-metal (MIM) chiplets, resistors, capacitors, inductors, transformers). In the illustrated example, the process flow is used to form an IC package 500 with a selectively transferred low-cost passive interposer 506. For example, an interposer 506 with a high-density die-to-die (D2D) link 508 is built on a donor wafer 502 and then selectively transferred to a recipient wafer 512, which enables multiple reuse of the same donor wafer 502 and amortizes the cost of the interconnect device across multiple recipient wafers 512. In some embodiments, other components of the IC package 500, such as IC die 518a-b, can also be selectively transferred. Selective transfer can also be used for other applications including, but not limited to, transfer of photonic / optical components, and localized transfer of III-V semiconductors for radio frequency (RF) devices and high power devices.

[0088] exist Figure 5A In the embodiment of the present invention, a repeating D2D interconnect pattern 506 is established on a release layer 504 of a donor substrate 502, and the resulting D2D interconnect is partially singulated (eg, sliced ​​to but not through the donor substrate 502). The D2D interconnect 506 includes high-density interconnect links 508 separated by dielectric layers 510.

[0089] exist Figure 5BIn the embodiment of the present invention, a transfer template 516 for selective transfer is established on a release layer 514 of an acceptor / carrier substrate 512. The transfer template 516 includes dielectric bonding protrusions 516, called mesas, located on the surface of the acceptor substrate 512. However, in various embodiments, any suitable surface treatment or other technique can be used to control the adhesion level on different areas of the acceptor substrate 512 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to surface topography changes (e.g., mesas, depressions), use of materials with high and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, etc. In addition, in various embodiments, any number of build-up layers can be formed on the acceptor substrate 512 before forming the templated connection base or mesas 516 for selective transfer.

[0090] The D2D interconnect 506 is selectively transferred from the donor 502 to the receptor 512 (e.g., using any of the selective transfer processes described throughout this disclosure) using the bonding surface of the transfer template 516. For example, the donor 502 and the receptor 512 are aligned face-to-face, stacked, and then bonded together such that one of the D2D interconnects 506 on the donor 502 is bonded to the bonding surface of the transfer template 516 on the receptor 512.

[0091] exist Figure 5C In the process, the D2D interconnect 506 bonded to the acceptor mesa of the transfer template 516 is debonded and / or released from the donor release layer 504 using any of the techniques described herein (e.g., selective release, blanket laser exposure, formation of bonds with intensity differentials), and the donor 502 and the acceptor 512 are mechanically separated. Thus, the transferred D2D interconnect 506 is separated from the donor 502 and remains on the acceptor 512.

[0092] exist Figure 5D In the process, additional processing is performed to form the remaining interconnects, including dielectric (e.g., oxide) fill 510 and planarization, interconnect 508 patterning / metallization (e.g., forming through dielectric vias (TDVs), top metal contacts (e.g., hybrid bond pads), dielectric layers, etc.), etc.

[0093] It should be noted that, since the D2D interposer 506 is selectively transferred while the surrounding dielectric layer 510 is directly formed on the receptor 512, there is a seam 511 between the transferred D2D interposer 506 and the surrounding layer 510, as shown in FIG. Figure 5D In general, this type of seam or transition can exist around any type of selectively transferred component since these components are not formed simultaneously with the surrounding layers.

[0094] exist Figure 5E In the embodiment, multiple IC dies 518a-b are attached to the top metal pad 508 (e.g., by hybrid bonding), the area around the dies 518a-b is filled with a dielectric material 510 (e.g., oxide) and planarized, and a structural substrate 520 (e.g., a structural silicon wafer) is attached.

[0095] Dies 518a-b may be attached using standard assembly techniques (eg, pick and place) or using the selective transfer techniques described herein (eg, similar to the transferred D2D interconnect 506).

[0096] If pick and place assembly is used to attach the dies 518a-b, the dies 518a-b are typically formed on a thick substrate for handling purposes and then thinned after attachment.

[0097] However, if the die 518a-b is selectively transferred, the die 518a-b can be formed on a very thin substrate and transferred directly from the substrate. Therefore, the selective transfer of the die 518a-b not only eliminates the need for post-attachment thinning, but also enables the die 518a-b to be much thinner than the die subjected to pick-and-place attachment and subsequent thinning. In addition, if the die 518a-b is selectively transferred, there can be a seam 511 between the die 518a-b and the portion of the layer 510 surrounding the die 518a-b, which is similar to the seam 511 shown around the transferred D2D interconnect 506, as described above. In addition, because the die 518a-b is selectively transferred, they can be different types of dies, which can be formed on separate substrate material sheets (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of the IC device 500.

[0098] exist Fig. 5F In the embodiment of the present invention, receptor 512 is debonded and released from release layer 514 (eg, using any of the techniques described herein, such as IR or UV laser ablation).

[0099] At this point, IC package 500 may be complete, or alternatively, additional processing may be performed. For example, if processing is performed at the wafer or panel level, the resulting IC package 500 on structural substrate 520 may be singulated.

[0100] Figure 6A-6B An example of selective layer transfer between a donor wafer 600 and an acceptor wafer 610 is shown. Specifically, Fig. 6A 6 shows wafers 600, 610 before transfer, and Figure 6BThe wafers 600, 610 are shown after transfer. In the illustrated example, non-contiguous regions of the donor wafer 600 are selectively transferred to non-contiguous locations on the acceptor wafer 610. However, in other embodiments, the target region on the donor 600 and the destination region on the acceptor 610 may be partially contiguous or completely contiguous.

[0101] like Fig. 6A As shown in , before transfer, a donor wafer 600 includes a layer of integrated circuit (IC) components 602 (e.g., dies, chiplets, interconnects, capacitors, transistors, etc.), which components may be partially singulated (e.g., sliced ​​down to but not through the underlying wafer 600). A receptor wafer 610 includes bonding areas 612 (also referred to as bonding templates) patterned into non-adjacent locations on the surface, where the target IC components 602 from the donor 600 are to be transferred. In some embodiments, for example, the bonding areas 612 may be raised structures or protrusions (referred to as "mesas") patterned on the surface of the receptor 612. Furthermore, in some embodiments, the bonding areas 612 on the receptor 610 may have a similar footprint as the target IC components 602 on the donor 600. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion levels on different areas of the receptor substrate 610 (e.g., to form adhesion areas and non-adhesion areas for selective transfer), including but not limited to surface topography changes (e.g., terraces, depressions), use of materials with high and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, etc.

[0102] like Figure 6B As shown in FIG. 6 , after transfer, the target IC components 602 are transferred from the donor wafer 600 to the acceptor wafer 610. Thus, the donor wafer 600 includes the empty areas 603 where the transferred IC components 602 were located, while the acceptor wafer 610 includes the transferred IC components 602 located where the bonding areas 612 were patterned. Specifically, the individual IC components 602 from the donor wafer 600 are now bonded to the individual bonding areas 612 on the acceptor wafer 610.

[0103] Although the illustrated examples depict selective transfer between two wafers, selective transfer may be performed between panels or other substrates of any shape or size, including substrates having non-matching shapes and sizes.

[0104] Figure 7A flowchart 700 for performing a selective layer transfer is shown. In view of the present disclosure, it should be recognized that the illustrated process flow is only an exemplary method for performing a selective layer transfer. In addition, the steps of the illustrated process flow can be performed using any suitable semiconductor manufacturing technology. For example, film deposition (e.g., depositing a layer, filling a portion of a layer (e.g., a removed portion), and filling a via opening) can be performed using any suitable deposition technology, including (e.g.,) chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD). In addition, patterning and removal, such as interconnect patterning, forming via openings, and shaping, can be performed using any suitable technology (e.g., lithography-based patterning / masking and / or etching).

[0105] The flowchart begins at block 702, receiving a first substrate having a layer of integrated circuit (IC) components, which may be referred to as a donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer located on the base substrate, and a layer of (partially singulated) IC components located on the release layer.

[0106] In some embodiments, the donor substrate can be formed by receiving a base substrate, forming a release layer over the base substrate, forming an IC component layer over the release layer (e.g., by fabricating or transferring the IC component layer over the release layer), and partially singulating the IC component layer (e.g., by cutting through the IC component layer but not through the base substrate).

[0107] In various embodiments, the IC component layer may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuitry or components.

[0108] The base substrate can be composed of one or more materials including elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H) and / or III-V group elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including but not limited to silicon (Si), silicon dioxide (silica or SiO2), silicon on insulator (SOI), quartz, glass, III-V group materials (e.g., gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)) and epoxy resin / resin (e.g., IR or UV transparent resin).

[0109] The release layer may include one or more layers of varying materials, depending on the type of release or debonding technique used. For example, for IR laser debonding, the release layer may include one or more layers of material capable of absorbing and / or reflecting infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of material capable of absorbing ultraviolet (UV) electromagnetic radiation (e.g., an organic polymer, such as polyimide). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric material to buffer laser ablation and thermal energy, control film interference or adhesion, and / or provide residual adhesion after weakening, removing and / or ablating other materials and / or layers in the release layer by laser (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)). Thus, in some embodiments, the release layer(s) may be composed of one or more materials including elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H) and carbon (C), including but not limited to any of the materials mentioned above.

[0110] Thereafter, the flow chart proceeds to block 704 to receive a second substrate having one or more bonding areas, which may be referred to as an acceptor substrate. In some embodiments, the acceptor substrate may include a base substrate patterned with one or more bonding areas on a surface (e.g., a layer of raised bonding features or "mesas" above the base substrate). The acceptor substrate may also optionally include a release layer located above the base substrate (e.g., to enable the base substrate to be subsequently debonded after transfer) and / or one or more additional build layers and / or IC components.

[0111] In some embodiments, the acceptor substrate may be formed by receiving a base substrate, optionally forming a release layer over the base substrate, optionally forming additional build-up layers and / or IC components over the base substrate (e.g., over the optional release layer, if included), and forming bonding areas (e.g., bonding structures) on the surface of the acceptor substrate (e.g., over the previously mentioned layers, if included). In some embodiments, the base substrate and the optional release layer of the acceptor may be composed of any of the materials mentioned above for the release layer of the base substrate and the donor, respectively.

[0112] In some embodiments, the bonding area can include a mesa structure having a footprint similar to that of a corresponding IC component to be transferred from the donor (although in some cases, the mesa can be slightly larger or smaller than the IC component to accommodate alignment and manufacturing tolerances). The mesa structure can be composed of varying materials, depending on the type of bonding and / or whether an electrical connection is required across the bonding interface for the subsequently bonded IC component (e.g., dielectric material, metal, or both). For example, the mesa structure can include a blanket dielectric structure without conductive contacts (e.g., for dielectric-to-dielectric bonding), a dielectric structure with conductive contacts (e.g., for mixed dielectric and metal bonding), and / or a conductive contact by itself (e.g., for metal-to-metal bonding). Thus, in some embodiments, the mesa structure may be composed of one or more materials including elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including but not limited to inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4) and / or silicon carbonitride (SiCN), organic dielectrics such as photoresists and adhesives, and / or conductive materials such as metals and alloys (e.g., any of the aforementioned metal elements and / or their compounds / alloys).

[0113] However, in various embodiments, any suitable technique(s) may be used to control the level of adhesion on different regions of the acceptor substrate. For example, a variety of surface treatments (e.g., photolithography or additive manufacturing) may be used to enhance and / or reduce adhesion in selected regions of the acceptor substrate, including but not limited to modifying the surface topography (e.g., elevated regions versus recessed regions, smooth regions versus rough regions), use of materials with high and / or low adhesion (e.g., forming a layer with adhesive and non-adhesive materials in selected regions), treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques (e.g., plasma or wet activation), etc.

[0114] For example, the surface topography of the receptor substrate can be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form regions with different adhesion levels, such as raised (e.g., adhesive) regions and recessed (e.g., non-adhesive) regions, smooth (e.g., adhesive) regions and rough (e.g., non-adhesive) regions, and so on.

[0115] As another example, the surface of the acceptor substrate can be patterned with a material having high and / or low adhesion in selected areas. For example, a layer patterned to have different areas of adhesive material and non-adhesive material can be formed on the acceptor substrate. In some embodiments, the adhesive material can include silicon dioxide (SiO2) or silicon carbonitride (SiCN) to promote strong oxide fusion bonding, silicon carbide (SiC) to provide lower thermal contact resistance compared to SiO2 or SiCN, and / or a metal to form an electrical connection. In addition, in some embodiments, the non-adhesive material can include silicon nitride (Si3N4) to form a weak bond or no bond.

[0116] As another example, treatment with a hydrophobic material and / or a self-assembled monolayer (SAM) can be used to enhance and / or weaken adhesion in selected areas of a receptor substrate (e.g., using a SAM treatment to create a monolayer with high and / or low adhesion in selected areas). In some embodiments, the hydrophobic material can include a SAM material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecanethiol), a phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM-based materials or films can also be used. In some embodiments, the hydrophobic material can include a thin polymer film, such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized film, etc.). In other embodiments, other hydrophobic materials can be used.

[0117] As another example, surface activation techniques including, but not limited to, plasma or wet activation may be used to enhance and / or weaken adhesion in selected areas of the receptor substrate.

[0118] Thereafter, the flow chart proceeds to block 706 to partially bond the donor substrate to the acceptor substrate (e.g., face-to-face) such that one or more target IC components on the donor substrate are selectively bonded to one or more bonding regions on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including but not limited to hybrid bonding, fusion bonding, and / or adhesive bonding.

[0119] Afterwards, the flow chart proceeds to block 708 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. In this way, when the donor substrate is separated from the acceptor substrate, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0120] In some embodiments, the donor substrate and the acceptor substrate may be debonded / separated from each other by at least partially releasing the target IC component from the release layer of the donor substrate and then mechanically separating the donor substrate from the acceptor substrate. For example, in some embodiments, the target IC component may be completely released from the donor substrate by selectively debonding the target IC component from the donor release layer using a laser (e.g., an IR or UV laser), or alternatively, the target IC component may be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After the target IC component is completely or partially released from the donor, the donor substrate and the acceptor substrate are mechanically separated, and after separation, the target IC component remains bonded to the acceptor and is no longer located on the donor.

[0121] Alternatively or in addition, the donor release layer and the receptor bonding structure can be formed of corresponding materials having completely different bonding strengths, so that the target IC component can have a stronger bond with the receptor than with the donor, thereby causing the target IC component to debond from the donor and remain on the receptor when the donor and receptor are mechanically separated.

[0122] The flow chart then proceeds to block 710 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., by selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, debonding a receptor base substrate (e.g., by an optional receptor release layer), and / or any other processing required for the completed product (e.g., IC package, device, system).

[0123] The finished product may include a variety of components and circuit systems (some of which may be selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memories), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, optical fibers), and / or radio frequency (RF) or high voltage components (e.g., high voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW) / bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, III-V devices / chiplets, passive RF devices such as interconnects, antennas, and inductors).

[0124] Furthermore, in some embodiments, the resulting IC package or product may be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0125] At this point, the flow chart can be completed. However, in some embodiments, the flow chart can restart and / or can repeat certain blocks. For example, in some embodiments, the flow chart can restart at block 702 and continue to perform selective transfer.

[0126] Bonding thermal management die using wafer-level selective transfer

[0127] As power and / or power density in semiconductor chips increase, it becomes increasingly critical to use high thermal conductivity materials to perform localized thermal management near hot spots. Many solutions use passive silicon for thermal management. However, in the case where modeling of future higher power density products shows that thermal bottlenecks are approaching, the use of silicon alone is rapidly becoming insufficient for thermal management. Other materials (e.g., diamond, silicon carbide, etc.) for providing thermal management may be expensive and / or may not be able to achieve blanket wafer-to-wafer bonding in standard wafer sizes (e.g., 300mm). Die-to-wafer bonding of higher thermal conductivity materials is within the scope of consideration. However, bonding of higher conductivity materials using a die-to-wafer solution may suffer from cost and throughput challenges because each of these dies needs to be bonded individually (which reduces throughput and increases assembly process costs) and in many cases surface preparation needs to be performed before bonding (performing individually on each die may be very expensive).

[0128] Various embodiments of the present disclosure utilize selective wafer-level transfer to co-process and bond thermal management dies to an active wafer or wafer stack (wherein a wafer stack may include multiple wafers or portions thereof bonded together in a stacked configuration). One or more embodiments may provide faster and / or more cost-effective bonding of thermal management dies, the ability to surface process all thermal management dies at the wafer level in a single step prior to bonding (thereby achieving more efficient and / or less expensive processing), an improved ability to bond thermal management dies to target areas (e.g., near hot spots) while reducing waste, and / or the ability to utilize thermal management dies having non-rectilinear polygonal shapes (e.g., any suitable convex or concave polygon, circular, etc.) to more closely match the shape and improve areal spreading through etch-based singulation of the thermal management dies.

[0129] Figures 8A-8C An exemplary process flow for selective layer transfer using selective release techniques for a thermal management die is shown. Figures 8A-8CA donor substrate 802 having a thermal management die 806 formed thereon and various acceptor substrates 804A-C that receive different die from the donor substrate are shown. The donor substrate 802 and acceptor substrate 804 can have any of the characteristics of other donor substrates and acceptor substrates described herein. In some examples, the donor substrate 802 can be a source wafer (on which the thermal management die 806 is formed directly) or a carrier wafer (where the thermal management die 806 is formed on a source wafer and then transferred to a carrier wafer, such as to modify the spacing between the die to be compatible with a selective transfer process or acceptor wafer spacing). In some embodiments, the acceptor substrate 804 is a wafer or a wafer stack (e.g., multiple wafers bonded together).

[0130] In various embodiments, wafer-level selective transfer can be used to enable the thermal management die 806 to be bonded from the donor substrate 802 to selected locations on multiple acceptor substrates (e.g., 804A-804C) such as an active wafer or a wafer stack using a wafer-to-wafer bonding scheme. The spacing between two adjacent thermal management dies 806 on the acceptor substrate can be different from the spacing on the donor substrate 802 (e.g., in the illustrated embodiment, the spacing between adjacent thermal management dies placed on the bonding structure 808 of the acceptor substrate 804A is wider than the spacing between adjacent thermal management dies on the donor substrate 802 before any thermal management die is transferred from the donor substrate 802) and can be determined by the thermal requirements on the acceptor substrate (e.g., hot spot locations).

[0131] One or more of the approaches described herein allow starting with a donor substrate fully populated with thermal management dies 806, performing surface preparation steps on all dies 806 during the same process step (e.g., simultaneously), and then bonding some of these dies to a first acceptor substrate (e.g., 804A), other of these dies to a second acceptor substrate (e.g., 804B), and so on, using a single bonding step for each acceptor substrate. This results in significant cost savings over approaches that perform die-to-wafer bonding for thermal management dies individually.

[0132] Fig. 9 A package 900 is shown that includes one or more thermal management dies 902 that have been selectively transferred to a single base die 904. The package 900 also includes a package substrate 906 attached to the base die 904 and another die 910 attached to the base die 904 (e.g., by solder bumps or hybrid bonding). The base die 904 may correspond to a receptor substrate as described herein that receives one or more thermal management dies 902 from a donor substrate during a selective transfer process. The package 900 may also include one or more other dies 910 (e.g., active electrical dies or dummy structural dies).

[0133] The thermal management die 902 may include at least one material having a thermal conductivity that is higher than the thermal conductivity of the primary material of the base die 904 (e.g., silicon). In other words, the die 902 may include a significant amount of material other than silicon. For example, the thermal management die 902 may include one or more of diamond, silicon carbide, aluminum nitride, graphene, boron arsenide, copper, aluminum, silver, or gold. In various embodiments, the thermal management die 902 may substantially or primarily include one or more of these materials or other materials having a thermal conductivity that is higher than the thermal conductivity of the primary material of the base die. Furthermore, in contrast to the die 904, in some examples, the die 902 may not include an integrated circuit system, such as a transistor.

[0134] Although not shown, when the package 900 is implemented within a computing system, a heat sink (e.g., an integrated heat sink including a metal plate) can be placed on top of the package to contact (e.g., directly contact) the thermal management die. The thermal management die 1102 can conduct heat from the base die 1104 toward the heat sink.

[0135] The base die 904 can be coupled (e.g., bonded) to one or more other die 910 having a primary material (e.g., silicon) having a lower thermal conductivity than the thermal management die 902. The thermal management die 902 can be placed over a hot spot area of ​​the base die 904, while the die 910 is placed over other areas of the base die 904 that are expected to be cooler than the hot spot area. The other die 910 can be coupled to the base die 904 in any suitable manner, for example, by selective transfer (as described herein) or by any suitable die-to-die, die-to-wafer, or wafer-to-wafer bonding technique. In some embodiments, the other die(s) 910 are not coupled to the base die 904 by the bonding structure 908, and the thermal management die 902 is placed on top of the bonding structure 908.

[0136] The bonding structure 908 may include one or more layers of inorganic materials (e.g., compounds containing any combination of silicon, oxygen, nitrogen and / or carbon), metals (e.g., copper, silver, gold, titanium, tin, nickel, indium, or a combination thereof), and / or organic materials (e.g., epoxy or silicone). In some embodiments, one or more layers may include a high conductivity filler (e.g., including diamond, silicon carbide, aluminum nitride, boron arsenide, silicon nitride, aluminum oxide, boron nitride, magnesium oxide, beryllium oxide, copper, aluminum, silver, gold, graphene, silicon, or a combination thereof). For example, a bonding structure having one or more primary materials (e.g., organic materials) that do not have high thermal conductivity may include small filler particles having high thermal conductivity. In some embodiments, the filler particles may be spherical or hemispherical or may be long fibers. In one example, the bonding structure 908 may include an epoxy resin interspersed with small thermally conductive filler particles.

[0137] In various embodiments, the bonding structure 908 may include a combination of the above materials. For example, the bonding structure 908 may include a hybrid bonding layer including a metal (e.g., copper) pad (e.g., having a substantially square cross-section in the xy plane) or a slot (e.g., having a substantially rectangular cross-section in the xy plane) located within an inorganic dielectric material (e.g., an oxide). In some embodiments, the bonding structure 908 may include a portion that exhibits high in-plane (e.g., in the xy plane) thermal conductivity and may be anchored at one or more of its edges by a vertical (e.g., in the z-direction) thermally conductive structure (e.g., a plug).

[0138] In some examples, one or more of the bonding structures 908 and / or the thermal management die 902 may include p-type and n-type materials (e.g., semiconductors) to implement a thermoelectric cooler in response to a voltage applied to the n-type and p-type materials, with one side (e.g., the bottom side closest to the base die 904) acting as a "cool" end and the other side (e.g., the top side) acting as a "hot" end, thereby generating a current flowing between the n-type and p-type materials, which achieves cooling of the cool end. In various embodiments, the bonding structure 908 may include an electrical interconnect to couple a voltage to the p-type and n-type materials of the bonding structure 908 or the thermal management die 902's thermoelectric cooler.

[0139] In one example, the bonding structure 908 or the thermal management die 902 may include a p-type Bi2Te3 / Sb2Te3 superlattice and an n-type delta-doped Bi2Te 3_x Se x alloys, which can be interconnected and placed in close proximity to each other.

[0140] The package 900 also includes a gap filling material 912 formed on the base die 904, which fills the area between the thermal management die 902 and the other die 910. The gap filling material 912 can include one or more inorganic materials (e.g., compounds containing any combination of silicon, oxygen, nitrogen, or carbon), one or more metals (e.g., copper, silver, gold, titanium, tin, nickel, indium, or a combination thereof), one or more organic materials (e.g., epoxy molding compound with or without inorganic fillers), or a combination thereof. In some examples, when the gap filling material 912 is a metal or metal alloy, a thin dielectric liner can be first deposited on the sidewalls of the die and any electrical interconnects between the dies to avoid electrical shorts.

[0141] Fig.10A package 1000 is shown including a thermal management die 1002 that is selectively transferred to a decomposed base die 1004. In this embodiment, multiple base dies are coupled to a package substrate 1006. A lower gap fill layer 1012 including a gap fill material may fill the gap(s) between the base dies 1004. One or more through dielectric vias (TDVs) 1014 may also be formed in the lower gap fill layer 1012 to connect the package substrate to an upper layer where one or more other dies 1010 (e.g., active electrical dies or dummy structural dies) are present.

[0142] One or more other dies 1010 may be interspersed between and / or around the selectively transferred thermal management dies 1002. These other dies 1010 and the thermal management dies 1002 are also interspersed in an upper gap fill layer 1016, which may include the same or different material as the lower gap fill layer 1012 (in the depicted embodiment, both the top gap fill layer and the base gap fill layer are shown as the same gap fill material). The gap fill material of the lower gap fill layer 1012 and / or the upper gap fill layer 1016 may include one or more inorganic materials (e.g., compounds containing any combination of silicon, oxygen, nitrogen, or carbon), one or more metals (e.g., copper, silver, gold, titanium, tin, nickel, indium, or combinations thereof), one or more organic materials (e.g., epoxy molding compound with or without inorganic fillers), or combinations thereof.

[0143] The thermal management die 1002 and other die 1010 may be coupled to (e.g., bonded to) the base die 1004 and / or the TDV 1014 in any suitable manner. For example, the bonding interface may include solder, a hybrid bonding layer (e.g., a metal pad such as a copper pad in an inorganic dielectric), a fusion bonding layer (e.g., only an inorganic dielectric), a diffusion bonding layer, or an n-type or p-type interconnect (e.g., to facilitate interconnection of a bonding structure 1008, a thermoelectric cooler or an energy harvester in the thermal management die 1002 or other die 1010), or other suitable materials.

[0144] In various embodiments, the footprint of the thermal management die 1002 or other die 1010 may be entirely within the footprint of the base die. Fig.10), a portion of the footprint of the thermal management die 1002 or other die 1010 is located within the footprint (multiple) of one or more base die 1004, while another portion is not located within the footprint of one or more base die 1004. For example, a corresponding portion of the thermal management die 1002 is located above the corresponding base die 1004, while the other portion extends beyond the footprint of the corresponding base die 1004. As another example, a first portion of the other die 1010 is located within the footprint of one of the base die 1004, while a second portion of the other die 1010 is located within the footprint of another base die 1004, and a third portion of the other die 1010 is not located within the footprint of any base die 1004.

[0145] Fig.11 A package 1100 is shown including a structural layer 1114 over a thermal management die 1102 selectively coupled to a single base die 1104, and Fig.12 The package 1200 is shown including a structural layer 1214 over a thermal management die 1202 that is selectively coupled to a decomposed base die 1204. The structural layer 1114 may also be over one or more other dies 1110, and the structural layer 1214 may also be over one or more other dies 1210. Fig.11 and Fig.12 The embodiments can be used with Fig. 9 and Fig.10 The embodiment is similar to that of , except that structural layers 1114 and 1214 are added.

[0146] The structural layer may protect the rest of the die assembly during processing or handling, serve mechanical purposes (e.g., to reduce die warpage), and / or serve thermal purposes (e.g., to improve heat dissipation from the die in the underlying layer). In some embodiments, the use of a structural layer may enable the thermal management die to be very thin (e.g., having a thickness between 10 microns and 500 microns).

[0147] In various embodiments, the footprint of the structural layer includes the entire footprint of the die composite (including the total footprint of the thermal management die(s), other die(s), and base die(s). In some embodiments, the footprint of the structural layer includes at least the total footprint of the thermal management die(s) and other die(s).

[0148] The structural layer 1114 or 1214 may include any suitable material (e.g., silicon), any of the materials described above for the thermal management die, or other suitable materials. In some embodiments, the structural layer may be deposited directly on top of the underlying layer, for example, by additive manufacturing, such as cold spraying, plating, or other deposition methods. In other embodiments, the structural layer may be fabricated separately and then bonded to the underlying layer using solder, a hybrid bonding layer (e.g., a metal pad in an inorganic dielectric), a fused bonding layer (e.g., an inorganic dielectric), an organic layer (e.g., an epoxy or silicone adhesive together with thermally conductive metal or inorganic filler particles), or other suitable materials.

[0149] Figures 13A-13D An exemplary base die topography for selective transfer of a thermal management die is shown. Figure 9-12 The described morphology is used in the described packaging.

[0150] Fig.13A A base die 1300 is shown along with other dies 1302 coupled to the base die 1300 and a thermal management die 1304 selectively transferred to the base die 1300. In this embodiment, the top of the base die 1300 is relatively flat, and the other dies 1302 can be singulated and then transferred to the base die 1300 using any suitable method (e.g., die-to-wafer bonding). In the depicted embodiment, the other dies 1302 are not placed on the bonding structure 1306, but are bonded to the base die 1300 using a different method. The thermal management die 1304 is selectively transferred to the base die 1300 and placed atop the bonding structure 1306. In other embodiments, one or more of the other dies 1302 can also be selectively transferred to the base die.

[0151] Fig. 13B A base die 1310 is shown where portions of the die have been removed (e.g., by etching) and the thermal management die 1304 has been selectively transferred into the resulting cavity. The thermal management die is placed on the bonding structure 1306. The portion of the base die 1310 next to the thermal management die (adjacent to the formed cavity) may be, for example, dummy silicon (e.g., for structural purposes) or may have active circuitry or other suitable components.

[0152] Fig. 13CShown are a base die 1320 and other die 1314 formed from a wafer bonded to the wafer 1300 including the base die. In a first stage 1322, the wafer 1312 is bonded to the wafer including the base die 1320. In a second stage 1324, portions of the wafer are removed (e.g., by etching) to form the other die 1314 and a cavity in which the bonding structure 1306 can be formed and the thermal management die 1304 can be selectively transferred.

[0153] Fig.13D A base die 1330 is shown with a selectively transferred thermal management die 1304 located on a bonding structure 1306 and a thermally conductive fill material 1316. Thus, instead of placing other dies located near the edge of the thermal management die 1304 on the base die 1330, this area can be occupied by the thermally conductive fill material 1316. In various embodiments, the thermally conductive fill material 1316 can be placed using high throughput additive manufacturing (HTAM). The fill material 1316 can include any suitable material, such as one or more metals (e.g., copper, silver, gold, aluminum), silicon, diamond, silicon carbide, aluminum nitride, graphene, boron arsenide, or other high thermal conductivity materials.

[0154] Fig.14 A flow chart 1400 for selective transfer of a thermal management die is shown. In view of this disclosure it should be appreciated that the illustrated process flow is only one exemplary method for performing a selective layer transfer. Furthermore, the steps of the illustrated process flow may be performed using any suitable semiconductor fabrication technology.

[0155] At 1402, a wafer including a plurality of thermal management dies is attached to a carrier wafer. The wafer including the thermal management dies may not be singulated when attached. In some examples, the carrier wafer does not have the same size (e.g., diameter) as the wafer to which the thermal management dies will be selectively transferred, and / or the same size as the wafer including the thermal management dies. In various examples, the carrier wafer includes a silicon or glass wafer having an organic or inorganic adhesive layer for attachment to the wafer including the thermal management dies.

[0156] At 1404, the wafer with the thermal management die is singulated on a carrier wafer. In some embodiments, the wafer can be singulated mechanically (e.g., using a blade) to create thermal management dies having a rectilinear (e.g., rectangular or square) shape. In other embodiments, singulation can be performed using photolithography techniques (e.g., by adding a patterned mask layer and applying an etching material or using plasma slicing). Using photolithography techniques, singulation can be used to generate thermal management dies having any suitable shape, including any polygonal (e.g., non-rectilinear), circular, or other suitable shapes. Such shapes can be used to optimize area thermal expansion and / or direct heat dissipation from sensitive devices.

[0157] At 1406, surface treatment is performed on the exposed side of the thermal management die. Such treatment may be performed on multiple thermal management dies of a singulated wafer simultaneously. The surface treatment may include, for example, one or more of metallization (e.g., applying a thin metal layer for bonding the thermal management die to a base die), surface cleaning (e.g., using pressurized water or solvents to remove particles or residues to achieve a clean surface with controlled topography), plasma activation (e.g., a treatment such as nitrogen that activates a surface to increase the likelihood that the surface will bond to another surface), or other steps that are optimally performed at the wafer level.

[0158] At 1408, the thermal management die is selectively transferred to a plurality of acceptor wafers (e.g., using any suitable technique described herein). At 1410, additional processing is performed on the acceptor wafers. For example, other dies may be attached to the acceptor wafers, gap fill material may be deposited onto the acceptor wafers, or other suitable steps may be performed (e.g., as described herein in connection with the thermal management die). Figure 7 or additional processing steps described elsewhere herein).

[0159] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may restart and / or certain blocks may be repeated. In view of the present disclosure, it should be recognized that the illustrated process flow is only one exemplary method for performing a selective layer transfer of a thermal management die. Furthermore, the steps of the illustrated process flow may be performed using any suitable semiconductor fabrication technology (e.g., those described herein or other suitable technology).

[0160] Fig.15 Another flow chart 1500 for selective transfer of a thermal management die is shown. In view of this disclosure it should be appreciated that the illustrated process flow is only one exemplary method for performing a selective layer transfer. Furthermore, the steps of the illustrated process flow may be performed using any suitable semiconductor fabrication technology.

[0161] The singulated thermal management die is attached to a carrier wafer at 1502. In various examples, the carrier wafer includes a silicon or glass wafer with an organic or inorganic adhesive layer for attachment to the thermal management die.

[0162] At 1504, surface treatment is performed on the exposed side of the thermal management die. At 1506, the thermal management die is selectively transferred to a plurality of acceptor wafers (e.g., using any suitable technique described herein). At 1508, additional processing is performed on the acceptor wafers. These operations may be related to the above Fig.14 The operations described are similar.

[0163] At this point, the flowchart may be complete. However, in some embodiments, the flowchart may restart and / or certain blocks may be repeated. In view of the present disclosure, it should be recognized that the illustrated process flow is only one exemplary method for performing a selective layer transfer of a thermal management die. Furthermore, the steps of the illustrated process flow may be performed using any suitable semiconductor fabrication technology (e.g., those described herein or other suitable technology).

[0164] Exemplary Embodiments

[0165] Fig.16 1 is a top view of wafer 1600 and die 1602, wherein each die may include a die selectively transferred from a donor wafer, or a die integrated into a system with such a die disclosed herein. Wafer 1600 may be composed of semiconductor material and may include one or more die 1602 having integrated circuit structures formed on a surface of wafer 1600. Each die 1602 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the fabrication of the semiconductor product is completed, wafer 1600 may undergo a singulation process in which the die 1602 are separated from each other to provide discrete "chips" of an integrated circuit product. Die 1602 may include one or more transistors, supporting circuitry for routing electrical signals to transistors, passive components (e.g., signal traces, transistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1600 or die 1602 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1602. For example, a memory array formed by multiple memory devices may be connected to a processor unit (e.g., Fig. 20The processor unit 2002) or other logic units configured to store information in a memory device or execute instructions stored in a memory array are formed on the same die 1602. In some embodiments, various microelectronic assemblies among the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly technology, in which some dies are attached to a wafer 1600 including other dies, and then the wafer 1600 is singulated.

[0166] Fig.17 1 is a cross-sectional side view of an integrated circuit device 1700 that may be included in an IC component (e.g., a die) as disclosed herein, which is selectively transferred from a donor wafer or circuitry incorporating such an IC component. One or more of the integrated circuit devices 1700 may be included in one or more dies 1602 ( Fig.16 ). The integrated circuit device 1700 may be formed on a die substrate 1702 (eg, Fig.16 1600) and may include on a die (e.g., Fig.16 The die substrate 1702 may be a semiconductor substrate composed of a semiconductor material system, for example, the semiconductor material system includes an n-type or p-type material system (or a combination of the two). For example, the die substrate 1702 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1702 may be formed using alternative materials (which may or may not be combined with silicon), including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1702. Although several examples of materials that may form the die substrate 1702 are described herein, any material that may serve as the basis for the integrated circuit device 1700 may be used. The die substrate 1702 may be a singulated die (for example, Fig.16 of a die 1602) or a wafer (e.g., Fig.16 portion of wafer 1600).

[0167] The integrated circuit device 1700 may include one or more device layers 1704 disposed on a die substrate 1702. The device layer 1704 may include features of one or more transistors 1740 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1702. The transistor 1740 may include, for example, one or more source and / or drain (S / D) regions 1720, a gate 1722 that controls the flow of current between the S / D regions 1720, and one or more S / D contacts 1724 that route electrical signals to / from the S / D regions 1720. The transistor 1740 may include additional features not shown for clarity, such as device isolation regions and gate contacts, etc. The transistor 1740 is not limited to Fig.17 The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and gate-wrap-around or all-around transistors such as nanoribbon transistors, nanosheet transistors, or nanowire transistors.

[0168] Figures 18A-18D is a simplified perspective view of an exemplary planar transistor, a FinFET transistor, a gate-all-around transistor, and a stacked gate-all-around transistor. Figures 18A-18D The transistor is shown formed on a substrate 1816 having a surface 1808. Isolation regions 1814 isolate the source and drain regions of the transistor from other transistors and from a bulk region 1818 of the substrate 1816.

[0169] Fig.18A is a perspective view of an exemplary planar transistor 1800 including a gate 1802 that controls current flow between a source region 1804 and a drain region 1806. Transistor 1800 is planar because source region 1804 and drain region 1806 are planar relative to substrate surface 1808.

[0170] Fig.18B is a perspective view of an exemplary FinFET transistor 1820 including a gate 1822 that controls current flow between a source region 1824 and a drain region 1826. Transistor 1820 is non-planar because source region 1824 and drain region 1826 include a "fin" that extends upward from substrate surface 1828. Because gate 1822 surrounds three sides of the semiconductor fin extending from source region 1824 to drain region 1826, transistor 1820 can be considered a tri-gate transistor. Fig.18B One S / D fin is shown extending through the gate 1822 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0171] Fig. 18C is a perspective view of a gate all around (GAA) transistor 1840 including a gate 1842 that controls current flow between a source region 1844 and a drain region 1846. The transistor 1840 is non-planar because the source region 1844 and the drain region 1846 are elevated from the substrate surface 1828.

[0172] Fig.18D 1860 is a perspective view of a GAA transistor 1860 including a gate 1862 that controls current flow between multiple elevated source regions 1864 and multiple elevated drain regions 1866. Transistor 1860 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 1840 and 1860 are considered gate-all-around transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Transistors 1840 and 1860 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors, depending on the width of the semiconductor portion extending through the gate (e.g., widths 1848 and 1868 of transistors 1840 and 1860, respectively).

[0173] refer to Fig.17 , transistor 1740 may include a gate 1722 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric material.

[0174] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0175] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1740 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may consist of or include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0176] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0177] In some embodiments, when viewed from a cross-sectional view of the transistor 1740 along the source-channel-drain direction, the gate electrode may consist of or include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1702 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1702. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1702 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 1702. In other embodiments, the gate electrode may consist of or include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0178] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0179] The S / D regions 1720 may be formed within the die substrate 1702 and adjacent to the gates 1722 of the respective transistors 1740. For example, the S / D regions 1720 may be formed using either an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1702 to form the S / D regions 1720. The ion implantation process may be followed by an annealing process that activates the dopants and diffuses them further into the die substrate 1702. In the latter process, the die substrate 1702 may first be etched to form a recess at the location of the S / D regions 1720. Thereafter, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D regions 1720. In some embodiments, the S / D regions 1720 may be made using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (such as germanium or III-V materials or alloys) may be used to form S / D regions 1720. In other embodiments, one or more layers of metals and / or metal alloys may be used to form S / D regions 1720.

[0180] The device layer 1704 may be provided with one or more interconnect layers (in Fig.17 The interconnect layers 1706-1710 (illustrated as interconnect layers 1706-1710) route electrical signals (e.g., power signals and / or input / output (I / O) signals) to and / or from devices (e.g., transistors 1740) of the device layer 1704. For example, conductive features (e.g., gates 1722 and S / D contacts 1724) of the device layer 1704 can be electrically coupled to interconnect structures 1728 of the interconnect layers 1706-1710. One or more interconnect layers 1706-1710 can form a metallization stack (also referred to as an "ILD stack") 1719 of the integrated circuit device 1700.

[0181] Interconnect structures 1728 (eg, wires) may be arranged within interconnect layers 1706-1710 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to Fig.17 The specific configuration of interconnect structure 1728 is depicted. Fig.17 A particular number of interconnect layers 1706 - 1710 are shown in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0182] In some embodiments, the interconnect structure 1728 may include lines 1728a and / or vias 1728b filled with a conductive material such as a metal. The lines 1728a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 1702 on which the device layer 1704 is formed. For example, the lines 1728a may route electrical signals in a direction into and out of the page and / or across the page. The vias 1728b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the surface of the die substrate 1702 on which the device layer 1704 is formed. In some embodiments, the vias 1728b may electrically couple the lines 1728a of different interconnect layers 1706-1710 together.

[0183] The interconnect layers 1706-1710 may include a dielectric material 1726 disposed between interconnect structures 1728, such as Fig.17 1706-1710. In some embodiments, the dielectric material 1726 disposed between the interconnect structures 1728 in different layers of the interconnect layers 1706-1710 may have different compositions; in other embodiments, the composition of the dielectric material 1726 between different interconnect layers 1706-1710 may be the same. The device layer 1704 may also include a dielectric material 1726 disposed between the transistor 1740 and the bottom layer of the metallization stack. The dielectric material 1726 included in the device layer 1704 may have a different composition than the dielectric material 1726 included in the interconnect layers 1706-1710; in other embodiments, the composition of the dielectric material 1726 in the device layer 1704 may be the same as the composition of the dielectric material 1726 included in any of the interconnect layers 1706-1710.

[0184] A first interconnect layer 1706 (referred to as metal 1 or "M1") can be formed directly on the device layer 1704. In some embodiments, the first interconnect layer 1706 can include lines 1728a and / or vias 1728b, as shown. The lines 1728a of the first interconnect layer 1706 can be coupled to contacts (e.g., S / D contacts 1724) of the device layer 1704. The vias 1728b of the first interconnect layer 1706 can be coupled to the lines 1728a of the second interconnect layer 1708.

[0185] A second interconnect layer 1708 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1706. In some embodiments, the second interconnect layer 1708 may include vias 1728b to couple the wires 1728a of the second interconnect layer 1708 with the wires 1728a of the third interconnect layer 1710. Although the wires 1728a and vias 1728b are structurally outlined with lines within each interconnect layer for clarity, in some embodiments, the wires 1728a and vias 1728b may be structurally and / or materially contiguous (e.g., filled simultaneously in a dual damascene process).

[0186] A third interconnect layer 1710 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) may be formed successively on the second interconnect layer 1708 according to similar techniques and configurations as described in connection with the second interconnect layer 1708 or the first interconnect layer 1706. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 1704) in the metallization stack 1719 in the integrated circuit device 1700 may be thicker than interconnect layers that are lower in the metallization stack 1719, wherein the lines 1728a and vias 1728b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0187] The integrated circuit device 1700 may include a solder resist material 1734 (eg, polyimide or similar material) formed on the interconnect layers 1706-1710 and one or more conductive contacts 1736. Fig.17 , the conductive contact 1736 is shown as taking the form of a bonding pad. The conductive contact 1736 can be electrically coupled to the interconnect structure 1728 and configured to route electrical signals of the transistor(s) 1740 to an external device. For example, a solder joint can be formed on one or more of the conductive contacts 1736 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1700 to other components (e.g., a printed circuit board). The integrated circuit device 1700 may include additional or alternative structures to route electrical signals from the interconnect layers 1706-1710; for example, the conductive contact 1736 may include other similar features (e.g., pillars) to route electrical signals to external components.

[0188] In some embodiments where the integrated circuit device 1700 is a double-sided die, the integrated circuit device 1700 may include another metallization stack (not shown) on an opposite side of the device layer(s) 1704. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1706-1710, thereby providing a conductive path (e.g., including conductive lines and vias) between the device layer(s) 1704 and additional conductive contacts (not shown) on an opposite side of the integrated circuit device 1700 from the conductive contacts 1736.

[0189] In other embodiments where the integrated circuit device 1700 is a double-sided die, the integrated circuit device 1700 may include one or more through silicon vias (TSVs) through the die substrate 1702; these TSVs may make contact with the device layer(s) 1704 and may provide a conductive path between the device layer(s) 1704 and additional conductive contacts (not shown) located on the side of the integrated circuit device 1700 opposite the conductive contacts 1736. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from conductive contacts located on the side of the integrated circuit device 1700 opposite the conductive contacts 1736 to the transistor 1740 and any other components integrated into the integrated circuit device (e.g., die) 1700, and the metallization stack 1719 may be used to route I / O signals from the conductive contacts 1736 to the transistor 1740 and any other components integrated into the integrated circuit device (e.g., die) 1700.

[0190] Multiple integrated circuit devices 1700 can be stacked, wherein one or more TSVs in each stacked device provide a connection between one of the devices in the stack and any other device. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between the individual HBM and the base integrated circuit die. The conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0191] Fig.191 is a cross-sectional side view of an integrated circuit device assembly 1900 that may include an IC component (e.g., a die) as disclosed herein, which is selectively transferred from a donor wafer. In some embodiments, the integrated circuit device assembly 1900 may be a microelectronic assembly. The integrated circuit device assembly 1900 includes several components disposed on a circuit board 1902 (which may be a motherboard, a system board, a mainboard, etc.). The integrated circuit device assembly 1900 includes components disposed on a first side 1940 of the circuit board 1902 and an opposite second side 1942 of the circuit board 1902; in general, the components may be disposed on one or both of the sides 1940 and 1942.

[0192] In some embodiments, circuit board 1902 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1902 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1902 may be a substrate other than a PCB. Fig.19 The integrated circuit device assembly 1900 shown in FIG. 1 includes a package-on-interposer structure 1936 coupled to a first side 1940 of a circuit board 1902 via a coupling component 1916. The coupling component 1916 can electrically and mechanically couple the package-on-interposer structure 1936 to the circuit board 1902 and can include solder balls (e.g., Fig.19 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0193] The package-on-interposer structure 1936 may include an integrated circuit component 1920 coupled to the interposer 1904 via a coupling component 1918. The coupling component 1918 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1916. Fig.19 A single integrated circuit component 1920 is shown, but multiple integrated circuit components may be coupled to interposer 1904; indeed, additional interposers may be coupled to interposer 1904. Interposer 1904 may provide an intervening substrate for bridging circuit board 1902 and integrated circuit component 1920.

[0194] Integrated circuit component 1920 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Fig.16 The tube core 1602, Fig.17The integrated circuit device 1700 of the package includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 1920, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1904. The integrated circuit component 1920 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 1920 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices and memory devices.

[0195] In embodiments where integrated circuit component 1920 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0196] In addition to including one or more processor units, the integrated circuit component 1920 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or may be located on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)) or a combination thereof.

[0197] In general, interposer 1904 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1904 can couple integrated circuit component 1920 to a set of ball grid array (BGA) conductive contacts of coupling component 1916 for coupling to circuit board 1902. Fig.19In the illustrated embodiment, integrated circuit component 1920 and circuit board 1902 are attached to opposite sides of interposer 1904; in other embodiments, integrated circuit component 1920 and circuit board 1902 may be attached to the same side of interposer 1904. In some embodiments, three or more components may be interconnected via interposer 1904.

[0198] In some embodiments, interposer 1904 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 1904 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 1904 may be formed of alternating rigid or flexible materials, which may include the same materials as described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1904 may include metal interconnects 1908 and vias 1910, which include but are not limited to through-hole vias 1910-1 (which extend from the first side 1950 of the interposer 1904 to the second side 1954 of the interposer 1904), blind vias 1910-2 (which extend from the first side 1950 or the second side 1954 of the interposer 1904 to internal metal layers), and buried vias 1910-3 (which connect internal metal layers).

[0199] In some embodiments, interposer 1904 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1904 including a silicon interposer may further include one or more routing layers for routing connections on a first side of interposer 1904 to an opposite second side of interposer 1904.

[0200] Interposer 1904 may also include embedded devices 1914, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 1904. Package-on-interposer structure 1936 may take the form of any package-on-interposer structure known in the art.

[0201] The integrated circuit device assembly 1900 may include an integrated circuit component 1924 coupled to the first side 1940 of the circuit board 1902 via a coupling component 1922. The coupling component 1922 may take the form of any of the embodiments discussed above with reference to the coupling component 1916, and the integrated circuit component 1924 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1920.

[0202] Fig.19 The integrated circuit device assembly 1900 shown in FIG. 1 includes a package-on-package structure 1934 coupled to a second side 1942 of a circuit board 1902 via a coupling component 1928. The package-on-package structure 1934 may include an integrated circuit component 1926 and an integrated circuit component 1932 coupled together via a coupling component 1930 such that the integrated circuit component 1926 is disposed between the circuit board 1902 and the integrated circuit component 1932. The coupling components 1928 and 1930 may take the form of any of the embodiments of the coupling component 1916 discussed above, and the integrated circuit components 1926 and 1932 may take the form of any of the embodiments of the integrated circuit component 1920 discussed above. The package-on-package structure 1934 may be configured according to any package-on-package structure known in the art.

[0203] Fig. 20 A block diagram of an exemplary electrical device 2000 is shown that may include IC components (e.g., dies) selectively transferred from a donor wafer as disclosed herein. For example, any suitable components of the electrical device 2000 may include one or more of the integrated circuit device assembly 1900, the integrated circuit component 1920, the integrated circuit device 1700, the integrated circuit die 1602, or other components disclosed herein. Fig. 20 Several components are illustrated as included in the electrical device 2000, but any one or more of these components may be omitted or doubled, depending on the application. In some embodiments, some or all of the components included in the electrical device 2000 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0204] Furthermore, in various embodiments, the electrical device 2000 may not include Fig. 20The electronic device 2000 may include one or more of the components shown, but the electronic device 2000 may include an interface circuit system for coupling to one or more components. For example, the electronic device 2000 may not include the display device 2006, but may include a display device interface circuit system (e.g., a connector and a driver circuit system), and the display device 2006 may be coupled to the interface circuit system. In another set of examples, the electronic device 2000 may not include the audio input device 2024 or the audio output device 2008, but may include an audio input or output device interface circuit system (e.g., a connector and a support circuit system), and the audio input device 2024 or the audio output device 2008 may be coupled to the interface circuit system.

[0205] The electrical device 2000 may include one or more processor units 2002 (e.g., one or more processor units). As used herein, the term "processor unit", "processing unit" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 2002 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, a processor unit may be referred to as an XPU (or xPU).

[0206] The electrical device 2000 may include a memory 2004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 2004 may include memory located on the same integrated circuit die as the processor unit 2002. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0207] In some embodiments, the electrical device 2000 may include one or more processor units 2002 that are heterogeneous or asymmetric with respect to another processor unit 2002 in the electrical device 2000. There may be a variety of differences between the processing units 2002 in the system with respect to a range of quality metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may manifest themselves substantially as asymmetry and heterogeneity between the processor units 2002 in the electrical device 2000.

[0208] In some embodiments, the electrical device 2000 may include a communication component 2012 (e.g., one or more communication components). For example, the communication component 2012 may manage wireless communications for transmitting data to and from the electrical device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0209] The communication component 2012 can implement any of a wide variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment)), Long Term Evolution (LTE) project together with any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication component 2012 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 2012 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 2012 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 2012 can operate according to other wireless protocols. The electrical device 2000 may include an antenna 2022 to facilitate wireless communications and / or receive other wireless communications (such as amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0210] In some embodiments, the communication component 2012 can manage wired communications, such as electrical, optical or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 2012 can include multiple communication components. For example, the first communication component 2012 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 2012 can be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others. In some embodiments, the first communication component 2012 can be dedicated to wireless communications, and the second communication component 2012 can be dedicated to wired communications.

[0211] The electrical device 2000 may include a battery / power circuit system 2014. The battery / power circuit system 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 2000 to an energy source separate from the electrical device 2000 (e.g., AC line power).

[0212] The electrical device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0213] The electrical device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any embedded or wired or wirelessly connected external device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0214] The electrical device 2000 may include an audio input device 2024 (or a corresponding interface circuit system, as discussed above). The audio input device 2024 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 2000 may include a global navigation satellite system (GNSS) device 2018 (or a corresponding interface circuit system, as discussed above), such as a global positioning system (GPS) device. The GNSS device 2018 may communicate with a satellite-based system and may determine the geographic location of the electrical device 2000 based on information received from one or more GNSS satellites, as is known in the art.

[0215] The electrical device 2000 may include other output devices 2010 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0216] The electrical device 2000 may include other input devices 2020 (or corresponding interface circuit systems, as discussed above). Examples of other input devices 2020 may include an accelerometer, a gyroscope, a compass, an image acquisition device (e.g., a monoscopic or stereoscopic imaging camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0217] The electrical device 2000 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 2000 can be any other electronic device that processes data. In some embodiments, the electrical device 2000 can include multiple discrete physical components. In view of the range of devices that the electrical device 2000 can be in various embodiments, in some embodiments, the electrical device 2000 can be referred to as a computing device or a computing system.

[0218] Throughout the entire text of this specification, multiple instances can implement parts, operations or structures that are described as single instances. Although each operation of one or more methods is illustrated and described as a separate operation, one or more of each operation can be performed simultaneously, and it is not required to perform these operations in the illustrated order. The structure and function introduced as a separate component in the exemplary configuration can be implemented as a combined structure or component. Similarly, the structure and function introduced as a single component can be implemented as a separate component. These and other changes, modifications, additions and improvements fall within the scope of the theme of this paper.

[0219] It should also be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not intended to imply that the objects described in this way must be in a given order in time, space, order, or in any other way. For example, the first contact portion can be referred to as the second contact portion, and similarly, the second contact portion can be referred to as the first contact portion without departing from the scope of this exemplary embodiment. Both the first contact portion and the second contact portion are contacts, but they are not the same contact portion.

[0220] As used in the description of exemplary embodiments and the appended claims, the singular forms of "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the items listed in association. For example, the phrase "A and / or B" means (A), (B), or (A and B), while the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0221] As used throughout this application and the claims, a list of items linked by the phrases "at least one of" or "one or more of" may mean any combination of the listed items.

[0222] It will also be understood that the term "comprising", when used in this specification, specifies the presence of stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. In addition, the terms "comprising", "including", "having", etc. used in connection with the embodiments of the present disclosure are synonymous.

[0223] The description may use the phrases "in an embodiment," "according to some embodiments," "according to an embodiment," or "in an embodiment," which may all refer to one or more of the same or different embodiments.

[0224] As used herein, the term "module" refers to: an ASIC, an electronic circuit, a system on a chip, a processor (shared, dedicated, or group), a solid-state device, a memory (shared, dedicated, or group) that executes one or more software or firmware programs; a combinational logic circuit; and / or other appropriate components that provide the described functionality.

[0225] As used herein, in some examples, "conductive" may refer to a material having a conductivity greater than or equal to 10 at 20 degrees Celsius. 7The property of electrical conductivity in Siemens per meter (S / m). Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0226] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0227] The term "connected" as used throughout the specification and in the claims refers to a direct connection, such as an electrical, mechanical or magnetic connection, between the elements being connected without any intermediate devices. The term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between the elements being connected, or an indirect connection through one or more passive or active intermediate devices.

[0228] The description may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are merely for convenience of discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0229] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer that is above or below another material or layer may be in direct contact or may have one or more intervening materials or layers. Additionally, a material that is between two materials or layers may be in direct contact with both materials / layers or may have one or more intervening materials / layers. Conversely, a first material or layer that is "above" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of the second material / layer. Similar distinctions may be made in the context of component assemblies.

[0230] As used herein, "A is adjacent to B" means that at least a portion of A is in direct physical contact with at least a portion of B.

[0231] As used herein, “A is near B” may mean that A is adjacent to B or A is otherwise close to B.

[0232] Unless otherwise specified in a particular context of use, the term "predominantly" means more than 50% or more than half. For example, a composition that is predominantly the first component means that more than half (e.g., by volume) of the composition is the first component (e.g., >50 atomic percent). The term "primarily" means the most or largest portion. For example, a composition that is primarily the first component means that the composition has more of the first component (e.g., by volume) than any other component. A composition that is primarily the first and second components means that the composition has more of the first and second components than any other component. In this context, the term "substantially" means that only accidental variations exist. For example, a composition that is primarily the first component means that the composition may further include <1% of any other component. A composition that is primarily the first and second components means that the composition may further include <1% of any component as a replacement for the first component or the second component.

[0233] The terms "substantially," "close," "approximately," "approximately," and "about" generally mean within + / - 10% of a target value (unless otherwise specified).

[0234] Unless otherwise indicated in the explicit context of use, the terms "substantially equal to", "approximately equal to" or "approximately equal to" indicate that there is at most an accidental variation between the two things so described. In the art, such variations usually do not exceed + / -10% of the predetermined target value.

[0235] In the corresponding drawings of the embodiments, lines can be used to represent signals, electrical paths, electrical bias or magnetic polarity or electrical polarity. Some lines may be thicker to indicate more signal paths, and / or have arrows at one or both ends to indicate the main information flow direction. Such indications are not intended to be limited. On the contrary, these lines are used in connection with one or more exemplary embodiments to promote easier understanding of circuits or logic units. Any represented signal, polarity, current, voltage, etc. (specified according to design needs or preferences) can actually include one or more signals, which can propagate in either direction and can be implemented with the signal scheme of any appropriate type.

[0236] The material described herein is illustrated in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where deemed appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements.

[0237] Although the drawings may illustrate embodiments where structures are substantially aligned to Cartesian axes (e.g., device structures have substantially vertical sidewalls), both positively and negatively (reentrant) tilted feature sidewalls are common in practice. For example, manufacturing imperfections may result in one or more structural features having tilted sidewalls. Thus, the illustrated properties are idealized for the sole purpose of clearly describing the salient features. It is to be understood that the schematics may not reflect actual process limitations that may cause features to appear less than "ideal" when, for example, any structure described herein is examined using scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In such images of actual structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tilted vias or other openings, accidental rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing.

[0238] Illustrative examples of the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include any one or more of the examples described below and any combination thereof. In some embodiments, at least one of the systems or components described in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes and / or methods described in the following examples.

[0239] Example 1 is an electronic device including: an integrated circuit (IC) die; a mesa structure formed on the IC die; and a die bonded to the IC die via the mesa structure.

[0240] Example 2 includes the subject matter of Example 1, and wherein the die bonded to the IC die comprises a predominant material having a higher thermal conductivity than silicon.

[0241] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the die bonded to the IC die includes at least one of diamond and silicon carbide.

[0242] Example 4 includes the subject matter of any of Examples 1-3, and wherein the mesa structures include an organic material.

[0243] Example 5 includes the subject matter of any of Examples 1-4, and wherein the mesa structures include an inorganic material.

[0244] Example 6 includes the subject matter of any of Examples 1-5, and wherein the mesa structure comprises metal.

[0245] Example 7 includes the subject matter of any of Examples 1-6, and wherein the mesa structure comprises a first material and a second material, wherein the first material has a higher thermal conductivity than the second material.

[0246] Example 8 includes the subject matter of any of Examples 1-7, and wherein the first material includes a plurality of filler particles within the second material.

[0247] Example 9 includes the subject matter of any of Examples 1-8, and wherein the mesa structure comprises a thermoelectric cooler having an n-type material and a p-type material.

[0248] Example 10 includes the subject matter of any of Examples 1-9, and further includes a second IC die bonded to the IC die.

[0249] Example 11 includes the subject matter of any of Examples 1-10, and further includes a structural material formed over the second IC die and the IC die.

[0250] Example 12 includes the subject matter of any of Examples 1-11, and wherein the die is located within a cavity of the IC die.

[0251] Example 13 includes the subject matter of any of Examples 1-12, and further includes a printed circuit board coupled to a packaging substrate, wherein the IC die is coupled to the packaging substrate.

[0252] Example 14 includes the subject matter of any of Examples 1-13, and further includes a second IC die coupled to the printed circuit board.

[0253] Example 15 includes a method comprising: receiving a first wafer including a plurality of thermal management dies; and simultaneously transferring a first plurality of the plurality of thermal management dies to a second wafer; and simultaneously transferring a second plurality of the plurality of thermal management dies to a third wafer.

[0254] Example 16 includes the subject matter of Example 15, and wherein a thermal management die in the plurality of thermal management dies has a thermal conductivity that is higher than a thermal conductivity of silicon.

[0255] Example 17 includes the subject matter of any of Examples 15 and 16, and wherein a thermal management die in the plurality of thermal management dies comprises at least one of diamond, silicon carbide, aluminum nitride, graphene, boron arsenide, copper, aluminum, silver, or gold.

[0256] Example 18 includes the subject matter of any of Examples 15-17, and wherein the mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer comprises an organic material.

[0257] Example 19 includes the subject matter of any of Examples 15-18, and wherein the mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer comprises metal.

[0258] Example 20 includes the subject matter of any of Examples 15-19, and wherein the mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer comprises a first material and a second material, wherein the first material has a higher thermal conductivity than the second material.

[0259] Example 21 includes the subject matter of any of Examples 15-20, and wherein the first material includes a plurality of filler particles within the second material.

[0260] Example 22 includes the subject matter of any of Examples 15-21, and wherein the mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer comprises a thermoelectric cooler having an n-type material and a p-type material.

[0261] Example 23 includes the subject matter of any of Examples 15-22, and further includes forming a structural material over the first plurality of thermal management die.

[0262] Example 24 includes a semiconductor package comprising: an integrated circuit (IC) die on a package substrate; and a thermal management die bonded to a mesa structure protruding upward from the IC die.

[0263] Example 25 includes the subject matter of Example 24, and wherein the mesa structures comprise an organic material.

[0264] Example 26 includes the subject matter of any of Examples 24 and 25, and further includes a second IC die bonded to the first IC die, and no mesa structure is between the second IC die and the first IC die.

[0265] Example 27 includes the subject matter of any of Examples 24-26, and wherein the thermal management die includes a predominant material having a higher thermal conductivity than silicon.

[0266] Example 28 includes the subject matter of any of Examples 24-27, and wherein the thermal management die comprises diamond.

[0267] Example 29 includes the subject matter of any of Examples 24-28, and wherein the thermal management die comprises silicon carbide.

[0268] Example 30 includes the subject matter of any of Examples 24-29, and wherein the mesa structure comprises metal.

[0269] Example 31 includes the subject matter of any of Examples 24-30, and wherein the mesa structure comprises a first material and a second material, wherein the first material has a higher thermal conductivity than the second material.

[0270] Example 32 includes the subject matter of any of Examples 24-31, and wherein the first material includes a plurality of filler particles within the second material.

[0271] Example 33 includes the subject matter of any of Examples 24-32, and wherein the mesa structure comprises a thermoelectric cooler having an n-type material and a p-type material.

[0272] Example 34 includes the subject matter of any of Examples 24-33, and further includes a second IC die bonded to the IC die.

[0273] Example 35 includes the subject matter of any of Examples 24-34, and further includes a structural material formed over the second IC die and the IC die.

[0274] Example 36 includes the subject matter of any of Examples 24-35, and wherein the thermal management die is located within a cavity of the IC die.

[0275] Example 37 includes the subject matter of any of Examples 24-36, and further includes a second IC die coupled to the printed circuit board.

[0276] Example 38 includes the subject matter of any of Examples 24-37, and wherein the mesa structures include an inorganic material.

[0277] For the purpose of explanation, the foregoing description has been given with reference to specific exemplary embodiments. However, the illustrative discussion above is not intended to be exhaustive or to limit possible exemplary embodiments to the exact form disclosed. In view of the above teachings, many modifications and variations are possible. These exemplary embodiments are selected and described in order to best illustrate the principles involved and their practical application, thereby enabling those skilled in the art to best utilize the various embodiments together with various modifications suitable for the specific purpose contemplated.

Claims

1. An electronic device, comprising: Integrated circuit (IC) die; a mesa structure formed on the IC die; as well as A die is bonded to the IC die through the mesa structure.

2. The electronic device according to claim 1, wherein: The die bonded to the IC die includes a predominant material having a higher thermal conductivity than silicon.

3. The electronic device according to claim 1, wherein: The die bonded to the IC die includes at least one of diamond or silicon carbide.

4. The electronic device according to claim 1, wherein: The mesa structure includes an inorganic material.

5. The electronic device according to claim 1, wherein: The mesa structure includes an organic material.

6. The electronic device according to claim 1, wherein: The mesa structure includes metal.

7. The electronic device according to claim 1, wherein: The mesa structure includes a first material and a second material, wherein the first material has a higher thermal conductivity than the second material.

8. The electronic device according to claim 7, wherein: The first material includes a plurality of filler particles within the second material.

9. The electronic device according to claim 1, wherein: The mesa structure includes a thermoelectric cooler having an n-type material and a p-type material.

10. The electronic device of claim 1 further comprising a second IC die bonded to the IC die.

11. The electronic device of claim 10, further comprising a structural material formed over the second IC die and the IC die.

12. The electronic device according to claim 1, wherein: The die is located within the cavity of the IC die.

13. The electronic device according to any one of claims 1 to 12, further comprising a printed circuit board coupled to the package substrate, wherein: The IC die is coupled to the package substrate.

14. The electronic device of claim 13, further comprising a second IC die coupled to the printed circuit board.

15. A method comprising: receiving a first wafer including a plurality of thermal management dies; transferring a first plurality of thermal management dies from the plurality of thermal management dies to a second wafer simultaneously; as well as A second plurality of thermal-management dies among the plurality of thermal-management dies are simultaneously transferred to a third wafer.

16. The method according to claim 15, wherein: A thermal management die of the plurality of thermal management dies has a thermal conductivity higher than a thermal conductivity of silicon.

17. The method according to claim 15, wherein: The mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer includes an organic material.

18. The method according to claim 15, wherein: The mesa structure between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer includes metal.

19. The method according to claim 15, wherein: A mesa structure located between the integrated circuit die of the second wafer and the thermal management die transferred to the second wafer includes a first material and a second material, wherein the first material has a higher thermal conductivity than the second material.

20. The method according to claim 19, wherein: The first material includes a plurality of filler particles within the second material.

21. The method according to any one of claims 15 to 20, wherein: A thermal management die of the plurality of thermal management dies includes at least one of diamond, silicon carbide, aluminum nitride, graphene, boron arsenide, copper, aluminum, silver, or gold.

22. A semiconductor package, comprising: an integrated circuit (IC) die on a package substrate; as well as A thermal management die is bonded to the mesa structure that protrudes upward from the first IC die.

23. The semiconductor package according to claim 22, wherein: The mesa structure includes an organic material.

24. The semiconductor package according to claim 22, wherein: The mesa structure includes an inorganic material.

25. The semiconductor package of any of claims 22-24, further comprising a second IC die bonded to the first IC die without a mesa structure between the second IC die and the first IC die.

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