Plane gate GaN vertical complementary field effect transistor inverter

Abstract

The invention relates to the technical field of semiconductors, and discloses a planar gate GaN vertical complementary field effect transistor inverter, which structurally comprises a substrate, a first transistor, a graphene layer and a second transistor from bottom to top, and is characterized in that a first source electrode and a first drain electrode are arranged at two ends of an n-tube GaN channel layer along the horizontal direction; the second source electrode and the second drain electrode are arranged at the two ends of the p-tube GaN channel layer in the horizontal direction, and a gate electrode capable of controlling the first transistor and the second transistor at the same time is arranged on the graphene layer between the first transistor and the second transistor. On the basis of the structure, the drain electrodes of the n-type transistor and the p-type transistor are connected through an air bridge structure and serve as the output end, the grid electrodes serve as the input end, the source electrode of the p-type transistor is connected with high level, the source electrode of the n-type transistor is connected with low level, the inverter is achieved, the grid control capacity is high, electric leakage is small, the efficient and low-power-consumption electronic transmission characteristic is achieved, and the performance is kept while the performance is improved. The occupied area is smaller, and the integration level is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a planar gate GaN vertical complementary field effect transistor inverter. Background Art

[0002] As a group III nitride material, GaN has shown many excellent physical properties in the current era, such as wide bandgap, high critical breakdown electric field, high electron mobility and high electron saturation drift velocity. In addition, its high polarizability promotes the formation of high-density two-dimensional electron gas at the heterojunction interface.

[0003] Thanks to these material properties, GaN high electron mobility transistors (HEMTs) have the following advantages: high breakdown voltage, low on-resistance, low gate charge, fast switching response, and efficient energy conversion performance. These characteristics make GaN HEMT a core power semiconductor device supporting the development of electric vehicles, smart grids, high-speed railways, and consumer electronics power modules.

[0004] As RF and power electronic systems move towards miniaturization, the demand for GaN chips with integrated digital and analog functions becomes more urgent. Traditional solutions rely on independent SicmOS drive circuit modules, which not only increases the volume of the system but also increases the complexity of the design. Therefore, it is extremely critical to develop GaN digital and analog circuits that can be monolithically integrated with GaN HEMT RF and power electronic devices. In the design of GaN digital and analog circuits, GaN field effect transistors and inverters are crucial components. However, the technology for GaN complementary field effect transistors and inverters is not yet mature. Some research literature attempts to form PMOS by using p-GaN gate materials in normally-off GaN HEMTs, and to construct NMOS using HEMT structures. However, this method encounters some technical difficulties, such as the high p-type doping ionization energy of p-GaN, which leads to insufficient hole concentration and relatively low hole mobility. These factors make the output current of p-GaN PMOS small. In addition, the horizontal layout of NMOS and PMOS leads to a large chip area, which is not conducive to achieving high-density integration and miniaturized devices.

[0005] To this end, we propose a planar gate GaN vertical complementary field effect transistor inverter, which can make the complementary field effect transistor and inverter have higher performance and smaller footprint. Summary of the invention

[0006] In order to make up for the deficiencies of the prior art, the present invention provides the following technical solutions: a planar gate GaN vertical complementary field effect transistor (VCFET) inverter, the device includes a substrate, a first transistor, a second transistor and a graphene layer, wherein the first transistor, the graphene layer and the second transistor are stacked vertically on the substrate in sequence, the first transistor is an n-type transistor, including a GaN buffer layer, an n-tube GaN channel layer, an n-tube AlGaN barrier layer, a first source electrode and a first drain electrode, the first source electrode and the first drain electrode are arranged at both ends of the n-tube GaN channel layer in a horizontal direction, and a two-dimensional electron gas (2DEG) is formed at a heterojunction interface between the GaN channel layer and the n-tube AlGaN barrier layer, and the 2DEG region will serve as an n-type channel, that is, a conductive channel of the first transistor, the second transistor is a p-type transistor, including a p-tube GaN doping layer, ... A p-tube GaN channel layer, a p-tube AlGaN barrier layer, a second source electrode and a second drain electrode, the second source electrode and the second drain electrode are arranged at both ends of the p-tube GaN channel layer in a horizontal direction, holes accumulate at the heterojunction interface between the p-tube GaN channel layer and the p-tube AlGaN barrier layer to form a two-dimensional hole gas (2DHG), the 2DHG region will serve as a p-type channel, i.e., a conductive channel of the second transistor, the n-type and p-type channels are vertically stacked, a graphene layer is arranged between the first transistor and the second transistor, and gate electrodes are arranged on both horizontal sides of the graphene layer, the graphene layer has good conductive properties, and can be used as the gate electrode of the first transistor and the second transistor together with the gate electrode, and at the same time control the n-type channel and the p-type channel. The existence of the graphene layer can make the gate electrode more effective in controlling the channel layer, and can more accurately control the current of the p-tube and the n-tube. The gate electrode is used as the input terminal, the first drain electrode and the second drain electrode are connected with metal to form an air bridge structure and used as the output terminal, the first source electrode is connected to a low level, and the second source electrode is connected to a high level to achieve logical inversion between the output terminal and the input terminal.

[0007] Preferably, the underlying metal of the gate electrode is one of Ni, Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti; the underlying metal of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode is one of Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti.

[0008] Preferably, the substrate is Si, SiC, sapphire or diamond.

[0009] Preferably, the graphene layer has a thickness of 1-20 nm, providing a common gate electrode for the first transistor and the second transistor, the n-tube AlGaN barrier layer is unintentionally doped, the aluminum component is 5-100%, the thickness is between 3-30 nm, the polarization charge on its lower surface induces the generation of a two-dimensional electron gas near the upper surface of the n-tube GaN channel layer, and in addition, sufficient barrier height is provided to prevent leakage current, the n-tube GaN channel layer has a thickness of 50-500 nm, is unintentionally doped, or n-type doped, and its upper surface forms a two-dimensional The electron gas is used as a conductive channel of the first transistor. The p-tube AlGaN barrier layer is unintentionally doped, the aluminum content is 5-100%, and the thickness is between 3-30nm to provide sufficient barrier height to prevent leakage current. The p-tube GaN channel layer has a thickness of 10-30nm and is unintentionally doped or p-type doped to provide a conductive channel for the second transistor. The p-tube GaN doping layer has a thickness of 10-150nm and is unintentionally doped or heavily p-type doped. The doping impurities are Mg or Zn, and the impurity concentration is 1x10 18 -1x10 21 cm -3 , providing a source of holes for the p-tube GaN channel layer.

[0010] Preferably, the air bridge connection metal material is Au, Ti or Pt.

[0011] Beneficial Effects

[0012] Compared with the prior art, the present invention provides a planar gate GaN vertical complementary field effect transistor inverter, which has the following beneficial effects:

[0013] 1. Since the VCFET structure stacks the first transistor (N-type transistor) and the second transistor (P-type transistor) vertically in sequence on the substrate layer, the area occupied by the two transistors on the horizontal plane is significantly reduced, so that a higher transistor density can be achieved on a smaller chip area. In other words, the VCFET structure achieves a significant reduction in device volume in both the horizontal and vertical dimensions.

[0014] 2. The graphene layer of the VCFET structure has a very low charge density, which means that when the gate voltage changes, the gate charge changes less, which helps to increase the switching speed and reduce power consumption. In addition, graphene has good mechanical properties and can provide a certain mechanical strength and flexibility during device manufacturing and operation, which helps to improve the reliability and durability of the device. Graphene also has excellent thermal conductivity and can effectively conduct and disperse the heat generated by the flow of current, which helps to reduce the operating temperature of the device and improve its thermal stability.

[0015] 3. The vertical stacking structure of the VCFET helps to reduce parasitic capacitance and resistance and improve the integrity of the device.

[0016] 4. In the VCFET structure, by using a double heterostructure of p-tube GaN layer-p-tube AlGaN barrier layer and n-tube GaN layer-n-tube AlGaN barrier layer, the conductive channels of N-type transistors and P-type transistors can be simultaneously produced, and the thickness of the conductive channel can be reduced to a certain extent, thereby further miniaturizing the size and thickness of the device.

[0017] 5. Since n-type and p-type transistors are closely arranged, they can provide faster switching speeds, which is an important advantage for CMOS inverters, especially in high-speed digital logic applications. Due to the low leakage current of the VCFET structure, the power consumption of CMOS inverters in static and dynamic operations will also be reduced accordingly.

[0018] 6. Since the vertical stacking structure of the transistor helps vertical conduction of heat rather than horizontal conduction in a planar structure, this helps to improve the thermal management of the CMOS inverter, reduce thermal resistance, and improve the long-term stability of the device. The vertical stacking structure also helps to reduce parasitic capacitance and resistance and improve the overall electrical performance of the CMOS inverter.

[0019] 7. In the inverter made based on the VCFET structure, the drain electrodes of the n-type transistor and the p-type transistor are connected by an air bridge structure. The air gap of the air bridge reduces the parasitic capacitance between the signal lines, thereby improving the speed and integrity of signal transmission. In addition, reducing parasitic effects also helps to improve the quality of RF signals, which is particularly important for RF and high-speed digital circuits.

[0020] 8. The technology proposed by the present invention is compatible with the original process, and the process manufacturing steps are relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A three-dimensional structural diagram of a device of a planar-gate GaN vertical complementary field-effect transistor inverter according to the present invention;

[0022] Figure 2-15 A schematic diagram of a device preparation process of a planar-gate GaN vertical complementary field-effect transistor inverter according to the present invention;

[0023] Fig.16 It is a schematic diagram of a planar gate GaN vertical complementary field effect transistor inverter of the present invention.

[0024] In the figure: 10, substrate; 20, first transistor; 21, GaN buffer layer; 22, n-tube GaN channel layer; 23, n-tube AlGaN barrier layer; 24, first source electrode; 25, first drain electrode; 31, graphene layer; 32, gate electrode; 40, second transistor; 41, p-tube GaN doping layer; 42, p-tube GaN channel layer; 43, n-tube AlGaN barrier layer; 44, second source electrode; 45, second drain electrode; 50, air bridge. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] Embodiment 1:

[0027] The present invention is a planar gate GaN vertical complementary field effect transistor inverter, such as Figure 1As shown, the device structure of the VCFET is characterized in that it includes a substrate 10, a first transistor 20, a second transistor 40 and a graphene layer 31, wherein the first transistor 20, the graphene layer 31 and the second transistor 40 are stacked vertically on the substrate 10 in sequence, the first transistor 20 is an n-type transistor, including a GaN buffer layer 21, an n-tube GaN channel layer 22, an n-tube AlGaN barrier layer 23, a first source electrode 24 and a first drain electrode 25, and the first source electrode 24 and the first drain electrode 25 are arranged in a horizontal direction. The n-tube GaN channel layer 22 is disposed at both ends thereof, and a two-dimensional electron gas (2DEG) is formed at a heterojunction interface between the n-tube GaN channel layer 22 and the n-tube AlGaN barrier layer 23. The 2DEG region will serve as an n-type channel, i.e., a conductive channel of the first transistor 20. The second transistor 40 is a p-type transistor, including a p-tube GaN doping layer 41, a p-tube GaN channel layer 42, a p-tube AlGaN barrier layer 43, a second source electrode 44 and a second drain electrode 45. The second source electrode 44 and the second drain electrode 45 are 5 are arranged at both ends of the p-tube GaN channel layer 42 in the horizontal direction. At the heterojunction interface between the p-tube GaN channel layer 42 and the p-tube AlGaN barrier layer 43, holes accumulate to form a two-dimensional hole gas (2DHG). The 2DHG region will serve as a p-type channel, that is, a conductive channel of the second transistor 40. The n-type and p-type channels are vertically stacked. A graphene layer 31 is arranged between the first transistor 20 and the second transistor 40. The gate electrode 32 is arranged on both horizontal sides of the graphene layer 31. Since the graphene layer 31 has good conductive properties, it can be used together with the gate electrode 32 as the gate electrode 32 of the first transistor 20 and the second transistor 40 to achieve simultaneous control of the n-type channel and the p-type channel. The existence of the graphene layer 31 can make the gate electrode 32 control the channel layer more effectively, and can more accurately control the current of the p-tube and the n-tube. The complementary field effect transistor provided in the embodiment of the present invention reduces the area occupied by the two transistors on the horizontal plane by stacking the first transistor 20 and the second transistor 40 vertically in sequence on the substrate 10.

[0028] For example, the underlying metal of the gate electrode 32 is one of Ni, Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti. The underlying metal of the first source electrode 24, the first drain electrode 25, the second source electrode 44, and the second drain electrode 45 is one of Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti.

[0029] Specifically, the metal of the gate electrode 32 is Ni / Au from bottom to top.

[0030] Particularly, the metals of the first source electrode 24 , the first drain electrode 25 , the second source electrode 44 , and the second drain electrode 45 are all Ti / Al / Ni / Au from bottom to top.

[0031] By way of example, the substrate 10 is Si, or SiC, or sapphire, or diamond.

[0032] Particularly, the material of the substrate 10 is Si.

[0033] Illustratively, the graphene layer 31 has a thickness between 1 nm and 20 nm to provide a common gate electrode 32 for the first transistor 20 and the second transistor 40 .

[0034] Particularly, the graphene layer 31 has a thickness of 10 nm.

[0035] For example, the n-tube AlGaN barrier layer 23 is unintentionally doped, with an aluminum content of 5-100% and a thickness of 3-30 nm to provide a sufficient barrier height to prevent leakage current.

[0036] Specifically, the n-tube AlGaN barrier layer 23 has an aluminum content of 25% and a thickness of 20 nm.

[0037] For example, the thickness of the n-tube GaN channel layer 22 is 50-500 nm, and it is unintentionally doped, or n-type doped.

[0038] In particular, the thickness of the n-tube GaN channel layer 22 is 200 nm and is not intentionally doped.

[0039] For example, the p-tube AlGaN barrier layer 43 is unintentionally doped, with an aluminum content of 5-100% and a thickness of 3-30 nm to provide a sufficient barrier height to prevent leakage current.

[0040] Specifically, the p-tube AlGaN barrier layer 43 has an aluminum composition of 25% and a thickness of 20 nm.

[0041] For example, the p-tube GaN channel layer 42 has a thickness of 10-30 nm and is unintentionally doped, or p-type doped.

[0042] In particular, the p-tube GaN channel layer 42 has a thickness of 20 nm and is not intentionally doped.

[0043] For example, the p-type GaN doping layer 41 has a thickness of 10-150 nm, is unintentionally doped, or heavily doped with p-type, and the doping impurities are Mg or Zn, and the impurity concentration is 1×10 18 -1x10 21 cm -3 .

[0044] In particular, the p-tube GaN doping layer 41 has a thickness of 80 nm, is doped with Mg, and has an impurity concentration of 1×10 20 cm -3 .

[0045] For example, a planar gate GaN vertical complementary field effect transistor inverter is used, the gate electrode 32 metal is the input terminal, the first drain electrode 25 and the second drain electrode 45 are connected and serve as the output terminal, the first source electrode 24 is connected to a low level, and the second source electrode 44 is connected to a high level, so as to realize the logical inversion of the output terminal and the input terminal.

[0046] Example 2

[0047] The present invention provides a process flow of manufacturing a planar gate GaN vertical complementary field effect transistor (VCFET) as follows:

[0048] Embodiment: The substrate 10 is made of silicon with a thickness of 800 μm. The GaN buffer layer 21 and the n-tube GaN channel layer 22 are n-type doped with silicon (Si) at a doping concentration of 1×10 18 m -3 The buffer layer thickness is 1000nm, the channel layer thickness is 300nm, the n-tube AlGaN barrier layer 23 and the p-tube AlGaN barrier layer 43 are undoped, the aluminum component is 0.3, the thickness is 30nm, the p-tube GaN doping layer 41 and the p-tube GaN channel layer 42 are p-type doped, doped with magnesium (Mg), and the doping concentration is 1x10 18 cm -3 The thickness of the doping layer is 1000 nm, the thickness of the channel layer is 300 nm, the first source electrode 24, the first drain electrode 25, the second source electrode 44 and the second drain electrode 45 of the transistor are all made of Ti / Al / Ni / Au, the gate electrode 32 is made of Ti / Au, and the gate dielectric layer is made of hafnium oxide.

[0049] Step 1: forming a silicon oxide film on the surface of the silicon substrate 10 on which the first transistor 20 and the second transistor 40 are stacked, and then cleaning the silicon substrate 10. Figure 2 shown.

[0050] At a high temperature of 1000° C., hydrogen is introduced into the reaction chamber to remove pollutants on the surface of the substrate 10 and to form a microscopic step structure on the surface of the substrate 10 so as to facilitate the subsequent epitaxial growth of various epitaxial layers.

[0051] Step 2: epitaxially grow a GaN buffer layer 21 on the substrate 10, such as Figure 3 shown.

[0052] The temperature is raised to 1000° C., and a GaN buffer layer 21 having a thickness of 1000 nm is grown on the substrate 10 by the MOCVD method.

[0053] Step 3: Prepare n-tube GaN channel layer 22, such as Figure 4 shown.

[0054] An n-tube GaN channel layer 22 with a thickness of 300 nm was grown on the GaN buffer layer 21 at a temperature of 1000° C. using a MOCVD method.

[0055] Step 4: fabricate an n-tube AlGaN barrier layer 23, such as Figure 5 shown.

[0056] The MOCVD method is continued to be adopted to grow an n-tube AlGaN barrier layer 23 with a thickness of 20 nm on the n-tube GaN channel layer 22 at a temperature of 1000° C.

[0057] Step 5: Prepare the graphene layer 31, such as Figure 6 shown.

[0058] By using the MOCVD method, at a temperature of 900° C., gases such as hydrogen (H 2 ) and methane (CH 4 ) are introduced as carbon sources and reducing agents to grow a graphene layer 31 with a thickness of 10 nm on the n-tube AlGaN barrier layer 23 .

[0059] Step 6: Form a first source electrode 24 and a first drain electrode 25 on both sides of the n-tube GaN channel layer 22 in the horizontal direction. Figure 7-8 shown.

[0060] A photolithography process is used to make a photoresist mask, and the corresponding parts of the n-tube AlGaN barrier layer 23 and the graphene layer 31 are etched away to expose the first source electrode 24 and the first drain electrode 25 of the first transistor 20 to be manufactured. Then, multilayer metal Ti / Al / Ni / Au is grown in this area by electron beam evaporation, that is, 50nm thick Ti, 150nm thick Al, 50nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the first source electrode 24 and the first drain electrode 25 are formed.

[0061] Step 7: Continue to make the p-tube AlGaN barrier layer 43, such as Fig. 9 shown.

[0062] A 30 nm thick p-tube AlGaN barrier layer 43 is epitaxially grown on the graphene layer 31 , and the Al composition is 0.3.

[0063] Step eight, fabricate a p-tube GaN channel layer 42, such as Fig.10 shown.

[0064] A p-tube GaN channel layer 42 with a thickness of 300 nm is grown on the p-tube AlGaN barrier layer 43 at a temperature of 1000° C. using a MOCVD method.

[0065] Step nine, making a p-tube GaN doping layer 41, such as Fig.11 shown.

[0066] The p-tube GaN doping layer 41 with a thickness of 1000 nm is grown on the p-tube GaN channel layer 42 at a temperature of 1000° C. using a MOCVD method.

[0067] Step 10: Make gate electrodes 32 on both sides of the graphene layer 31, such as Figure 12-13 shown.

[0068] A photolithography process is used to make a photoresist mask, and the corresponding parts of the p-tube GaN doping layer 41, the p-tube GaN channel layer 42 and the p-tube AlGaN barrier layer 43 are etched away to expose the gate electrode 32 area to be made, and then multilayer metal Ti / Al / Ni / Au is grown in this area by electron beam evaporation, that is, 50nm thick Ti, 150nm thick Al, 50nm thick Ni, and 50nm thick Au from bottom to top, and the gate electrode 32 is formed after peeling.

[0069] Step 11: Form a second source electrode 44 and a second drain electrode 45 on both sides of the p-tube GaN channel layer 42 in the horizontal direction. Figure 14-15 shown.

[0070] A photolithography process is used to make a photoresist mask to expose the second source electrode 44 and the second drain electrode 45 of the second transistor 40 to be manufactured, and then multiple layers of metal Ti / Al / Ni / Au are grown in the area by electron beam evaporation, namely, 50nm thick Ti, 150nm thick Al, 50nm thick Ni, and 50nm thick Au from bottom to top. After peeling, the second source electrode 44 and the second drain electrode 45 are formed.

[0071] Example 3

[0072] On the basis of Example 2, a planar gate GaN vertical complementary field effect transistor (VCFET) inverter is manufactured, such as Fig.16 shown.

[0073] The first drain electrode 25 of the first transistor 20 of the device is connected to the second drain electrode 45 of the second transistor 40 by metal to form an air bridge 50 structure. First, an arched photoresist patterning bridge is made at the corresponding position, then an electroplating seed layer is made, and then a bridge metal is electroplated on the layer. Finally, the patterning bridge and the seed layer metal are removed to form the air bridge 50.

[0074] The gate electrode 32 is used as an input terminal, the air bridge 50 is connected to the output terminal, the first source electrode 24 is connected to a low level, and the second source electrode 44 is connected to a high level, and the VCFET can be used to make an inverter.

[0075] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus.

[0076] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and the scope of the invention is defined by the appended claims and their equivalents.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A planar-gate GaN vertical complementary field-effect transistor inverter, characterized in that: The invention comprises a substrate (10), a first transistor (20), a second transistor (40) and a graphene layer (31), wherein the first transistor (20), the graphene layer (31) and the second transistor (40) are stacked vertically in sequence on the substrate (10), the first transistor (20) is an n-type transistor, comprising a GaN buffer layer (21), an n-tube GaN channel layer (22), an n-tube AlGaN barrier layer (23), a first source electrode (24) and a first drain electrode (25), and the first source electrode (24) and the first drain electrode (25) are arranged in a horizontal direction on the n-tube GaN channel layer (2 2), a two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the GaN channel layer (22) and the n-tube AlGaN barrier layer (23), and the 2DEG region will serve as an n-type channel, that is, a conductive channel of the first transistor (20). The second transistor (40) is a p-type transistor, including a p-tube GaN doping layer (41), a p-tube GaN channel layer (42), a p-tube AlGaN barrier layer (43), a second source electrode (44) and a second drain electrode (45), and the second source electrode (44) and the second drain electrode (45) are arranged in a horizontal direction on the p-tube GaN channel layer. At both ends of the layer (42), at the heterojunction interface between the p-tube GaN channel layer (42) and the p-tube AlGaN barrier layer (43), holes accumulate to form a two-dimensional hole gas (2DHG), and the 2DHG region will serve as a p-type channel, that is, a conductive channel of the second transistor (40). The n-type and p-type channels are vertically stacked, and a graphene layer (31) is arranged between the first transistor (20) and the second transistor (40). Gate electrodes (32) are arranged on both horizontal sides of the graphene layer (31). The graphene layer (31) has good conductive properties and can serve as the first transistor together with the gate electrode (32). The gate electrode (32) of the body transistor (20) and the second transistor (40) realizes the control of the n-type channel and the p-type channel at the same time. The existence of the graphene layer (31) can make the gate electrode (32) control the channel layer more effectively, and can more accurately control the current of the p-tube and the n-tube. The gate electrode (32) is used as the input end, the first drain electrode (25) and the second drain electrode (45) are connected by metal to form an air bridge (50) structure and serve as the output end. The first source electrode (24) is connected to a low level, and the second source electrode (44) is connected to a high level to form an inverter, so as to realize the reverse logic between the output end and the input end.

2. A planar gate GaN vertical complementary field effect transistor inverter according to claim 1, characterized in that: The bottom layer metal of the gate electrode (32) is one of Ni, Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti. The bottom layer metal of the first source electrode (24), the first drain electrode (25), the second source electrode (44), and the second drain electrode (45) is one of Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti.

3. The planar gate GaN vertical complementary field effect transistor inverter according to claim 1, characterized in that: The substrate (10) is Si, SiC, sapphire or diamond.

4. The planar gate GaN vertical complementary field effect transistor inverter according to claim 1, characterized in that: The graphene layer (31) has a thickness of 1-20 nm and provides a common gate electrode (32) for the first transistor (20) and the second transistor (40). The n-tube AlGaN barrier layer (23) is unintentionally doped, has an aluminum component of 5-100%, and has a thickness of 3-30 nm. The polarization charge on its lower surface induces the generation of a two-dimensional electron gas near the upper surface of the n-tube GaN channel layer (22), and provides a sufficient barrier height to prevent leakage current. The n-tube GaN channel layer (22) has a thickness of 50-500 nm and is unintentionally doped or n-type doped. The upper surface of the n-tube GaN channel layer (22) forms a The invention discloses a two-dimensional electron gas, which is used as a conductive channel of a first transistor (20). The p-tube AlGaN barrier layer (43) is unintentionally doped, and the aluminum component is 5-100%, and the thickness is between 3-30nm, so as to provide a sufficient barrier height to prevent leakage current. The p-tube GaN channel layer (42) has a thickness of 10-30nm, is unintentionally doped, or p-type doped, and provides a conductive channel for the second transistor (40). The p-tube GaN doping layer (41) has a thickness of 10-150nm, is unintentionally doped, or p-type heavily doped, and the doping impurity is Mg or Zn, and the impurity concentration is 1x10 18 -1x10 21 cm -3 , providing a hole source for the p-tube GaN channel layer (42).

5. The planar gate GaN vertical complementary field effect transistor inverter according to claim 1, characterized in that: The connecting metal material of the air bridge (50) is Au, Ti or Pt.

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