A planar gate GaN vertical complementary field-effect transistor inverter

Abstract

This invention relates to the field of semiconductor technology and discloses a planar gate GaN vertical complementary field-effect transistor inverter. The device structure, from bottom to top, includes a substrate, a first transistor, a graphene layer, and a second transistor. A first source electrode and a first drain electrode are arranged horizontally at both ends of the n-type GaN channel layer, and a second source electrode and a second drain electrode are arranged horizontally at both ends of the p-type GaN channel layer. A gate electrode capable of simultaneously controlling both the first and second transistors is arranged on the graphene layer between the first and second transistors. Based on this structure, the drains of the n-type and p-type transistors are connected by an air bridge structure and used as the output terminal, with the gate as the input terminal. The source of the p-type transistor is connected to a high level, and the source of the n-type transistor is connected to a low level, thus realizing an inverter. It exhibits strong gate control capability, low leakage current, and efficient, low-power electron transport characteristics. While maintaining high performance, it has a smaller footprint, improving integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a planar gate GaN vertical complementary field-effect transistor inverter. Background Technology

[0002] GaN, as a group III nitride material, exhibits numerous outstanding physical properties in the current era, such as a wide bandgap, a high critical breakdown electric field, high electron mobility, and high electron saturation drift velocity. Furthermore, its high polarizability promotes the formation of a high-density two-dimensional electron gas at the heterojunction interface.

[0003] Thanks to these material properties, GaN high electron mobility transistors (HEMTs) possess the following advantages: high breakdown voltage, low on-resistance, low gate charge, fast switching response, and high energy conversion efficiency. These characteristics make GaN HEMTs a core power semiconductor device supporting the development of electric vehicles, smart grids, high-speed railways, and consumer electronics power modules.

[0004] As RF and power electronic systems become increasingly miniaturized, the demand for GaN chips integrating digital and analog functions is becoming more urgent. Traditional solutions rely on separate SicmOS driver circuit modules, which increases both system size and design complexity. Therefore, developing GaN digital and analog circuits that can be monolithically integrated with GaN HEMT RF and power electronic devices is crucial. GaN field-effect transistors (FETs) and inverters are essential components in GaN digital and analog circuit design. However, current technologies for GaN complementary field-effect transistors (FETs) and inverters are still immature. Some research has attempted to form PMOS using p-GaN gate materials in normally-off GaN HEMTs and to construct NMOS using HEMT structures. However, these methods have encountered several technical challenges. For example, the high p-type doping ionization energy of p-GaN leads to insufficient hole concentration and relatively low hole mobility, resulting in lower output current for p-GaN PMOS. Furthermore, the horizontal layout of NMOS and PMOS results in a larger chip area, which is detrimental to achieving high-density integration and miniaturized devices.

[0005] To address this, we propose a planar gate GaN vertical complementary field-effect transistor inverter, which enables complementary field-effect transistors and inverters to achieve higher performance and a smaller footprint. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention provides the following technical solution: a planar gate GaN vertical complementary field-effect transistor (VCFET) inverter, the device comprising a substrate, a first transistor, a second transistor, and a graphene layer, wherein the first transistor, the graphene layer, and the second transistor are vertically stacked sequentially on the substrate. The first transistor is an n-type transistor, including a GaN buffer layer, an n-type GaN channel layer, an n-type AlGaN barrier layer, a first source electrode, and a first drain electrode. The first source electrode and the first drain electrode are arranged horizontally at both ends of the n-type GaN channel layer. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the GaN channel layer and the n-type AlGaN barrier layer. The 2DEG region serves as the n-type channel, i.e., the conductive channel of the first transistor. The second transistor is a p-type transistor, including a p-type GaN doped layer, a p-type GaN doped layer, and a p-type GaN doped layer. The transistor consists of a GaN channel layer, an AlGaN barrier layer, a second source electrode, and a second drain electrode. The second source electrode and the second drain electrode are arranged horizontally at both ends of the GaN channel layer. At the heterojunction interface between the GaN channel layer and the AlGaN barrier layer, holes accumulate to form a two-dimensional hole gas (2DHG). The 2DHG region will serve as the p-type channel, i.e., the conductive channel of the second transistor. The n-type and p-type channels are stacked vertically. A graphene layer is placed between the first transistor and the second transistor. Gate electrodes are arranged on both sides of the graphene layer. The graphene layer has good conductivity and can be used together with the gate electrode as the gate electrode of the first transistor and the second transistor, simultaneously controlling the n-type channel and the p-type channel. The presence of the graphene layer makes the gate electrode control of the channel layer more effective and allows for more precise control of the current of the p-type and n-type transistors. The gate electrode is used as the input terminal, and the first drain electrode and the second drain electrode are connected by a metal phase to form an air bridge structure, which serves as the output terminal. The first source electrode is connected to a low level, and the second source electrode is connected to a high level, so that the logic of the output terminal is reversed with that of the input terminal.

[0007] Preferably, the bottom metal of the gate electrode is one of Ni, Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti. The bottom metal of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode is one of Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti.

[0008] Preferably, the substrate is Si, SiC, sapphire, or diamond.

[0009] Preferably, the graphene layer thickness is between 1-20 nm, providing the common gate electrode for the first and second transistors. The n-transistor AlGaN barrier layer is unintentionally doped, with an aluminum composition of 5-100% and a thickness between 3-30 nm. The polarization charge on its lower surface induces a two-dimensional electron gas near the upper surface of the n-transistor GaN channel layer. Additionally, to provide sufficient barrier height to prevent leakage current, the n-transistor GaN channel layer thickness is 50-500 nm, unintentionally doped, or n-type doped, with a two-dimensional electron gas formed on its upper surface. The electron gas serves as the conductive channel for the first transistor. The AlGaN barrier layer of the p-transistor is unintentionally doped, with an aluminum composition of 5-100% and a thickness between 3-30 nm, to provide sufficient barrier height to prevent leakage current. The GaN channel layer of the p-transistor is 10-30 nm thick, unintentionally doped, or p-type doped, providing the conductive channel for the second transistor. The GaN doped layer of the p-transistor is 10-150 nm thick, unintentionally doped, or heavily p-type doped, with Mg or Zn as the dopant impurity at a concentration of 1 x 10⁻⁶. 18 -1x10 21 cm -3 This provides a hole source for the GaN channel layer of the p-tube.

[0010] Preferably, the metal material for the air bridge connection is Au, Ti, or Pt.

[0011] Beneficial effects

[0012] Compared with the prior art, the present invention provides a planar gate GaN vertical complementary field-effect transistor inverter, which has the following advantages:

[0013] 1. Because the VCFET structure stacks the first transistor (N-type transistor) and the second transistor (P-type transistor) vertically on the substrate layer, it significantly reduces the area occupied by the two transistors in the horizontal plane, enabling higher transistor density in a smaller chip area. In other words, the VCFET structure achieves a significant reduction in device size in both the horizontal and vertical dimensions.

[0014] 2. The graphene layer of this VCFET structure has a very low charge density, which means that the change in gate charge is small when the gate voltage changes, thus helping to improve switching speed and reduce power consumption. In addition, graphene has good mechanical properties, which can provide a certain mechanical strength and flexibility during device manufacturing and operation, helping to improve the reliability and durability of the device. Graphene also has excellent thermal conductivity, which can effectively conduct and disperse the heat generated by current flow, helping to reduce the operating temperature of the device and improve its thermal stability.

[0015] 3. The vertical stacking structure of this VCFET helps to reduce parasitic capacitance and resistance, and improve the overall integrity of the device.

[0016] 4. In this VCFET structure, by using a dual heterostructure of p-type GaN layer-p-type AlGaN barrier layer and n-type GaN layer-n-type AlGaN barrier layer, it is possible to simultaneously fabricate conductive channels for both N-type and P-type transistors, and to reduce the thickness of the conductive channels to a certain extent, thereby further miniaturizing the device size and thickness.

[0017] 5. Due to the close arrangement of n-type and p-type transistors, faster switching speeds can be provided, which is an important advantage for CMOS inverters, especially in high-speed digital logic applications. Since the leakage current of the VCFET structure is low, the power consumption of CMOS inverters is also reduced in both static and dynamic operations.

[0018] 6. Since the vertical stacking structure of the transistors facilitates vertical heat conduction rather than horizontal conduction in a planar structure, this helps improve the thermal management of the CMOS inverter, reduce thermal resistance, and improve the long-term stability of the device. The vertical stacking structure also helps reduce parasitic capacitance and resistance, thereby improving the overall electrical performance of the CMOS inverter.

[0019] 7. In the inverter based on the VCFET structure, the drain electrodes of the n-type transistor and the p-type transistor are connected by an air bridge structure. The air gap of the air bridge reduces the parasitic capacitance between signal lines, thereby improving the speed and integrity of signal transmission. In addition, reducing parasitic effects also helps to improve the quality of radio frequency signals, which is especially important for radio frequency and high-speed digital circuits.

[0020] 8. The technology proposed in this invention is compatible with existing processes, and the manufacturing steps are relatively simple. Attached Figure Description

[0021] Figure 1 This is a three-dimensional structural diagram of a planar gate GaN vertical complementary field-effect transistor inverter according to the present invention;

[0022] Figure 2-15 This is a schematic diagram of the fabrication process of a planar gate GaN vertical complementary field-effect transistor inverter according to the present invention.

[0023] Figure 16 This is a schematic diagram of a planar gate GaN vertical complementary field-effect transistor inverter according to the present invention.

[0024] In the figure: 10, substrate; 20, first transistor; 21, GaN buffer layer; 22, n-transistor GaN channel layer; 23, n-transistor AlGaN barrier layer; 24, first source electrode; 25, first drain electrode; 31, graphene layer; 32, gate electrode; 40, second transistor; 41, p-transistor GaN doped layer; 42, p-transistor GaN channel layer; 43, n-transistor AlGaN barrier layer; 44, second source electrode; 45, second drain electrode; 50, air bridge. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] Example 1:

[0027] This invention relates to a planar gate GaN vertical complementary field-effect transistor inverter, such as... Figure 1As shown, the VCFET device structure features a substrate 10, a first transistor 20, a second transistor 40, and a graphene layer 31. The first transistor 20, the graphene layer 31, and the second transistor 40 are stacked vertically on the substrate 10. The first transistor 20 is an n-type transistor, including a GaN buffer layer 21, an n-type GaN channel layer 22, an n-type AlGaN barrier layer 23, a first source electrode 24, and a first drain electrode 25. The first source electrode 24 and the first drain electrode 25 are arranged horizontally. A two-dimensional electron gas (2DEG) is formed at both ends of the n-type GaN channel layer 22 and the heterojunction interface between the n-type GaN channel layer 22 and the n-type AlGaN barrier layer 23. The 2DEG region will serve as the n-type channel, i.e., the conductive channel of the first transistor 20. The second transistor 40 is a p-type transistor, including a p-type GaN doped layer 41, a p-type GaN channel layer 42, a p-type AlGaN barrier layer 43, a second source electrode 44, and a second drain electrode 45. 5. Arranged horizontally at both ends of the p-type GaN channel layer 42, at the heterojunction interface between the p-type GaN channel layer 42 and the p-type AlGaN barrier layer 43, holes accumulate to form a two-dimensional hole gas (2DHG). The 2DHG region will serve as the p-type channel, i.e., the conductive channel of the second transistor 40. The n-type and p-type channels are stacked vertically. A graphene layer 31 is disposed between the first transistor 20 and the second transistor 40. Gate electrodes 32 are arranged on both sides of the graphene layer 31 horizontally. Since the graphene layer 31 has good conductivity, it can be used together with the gate electrode 32 as the gate electrode 32 of the first transistor 20 and the second transistor 40 to achieve simultaneous control of the n-type channel and the p-type channel. The presence of the graphene layer 31 can make the control of the channel layer by the gate electrode 32 more effective and can more accurately control the current of the p-type and n-type transistors. The complementary field-effect transistor provided in this embodiment of the invention reduces the area occupied by the two transistors on the horizontal plane by vertically stacking the first transistor 20 and the second transistor 40 on the substrate 10 in sequence.

[0028] For example, the bottom metal of the gate electrode 32 is one of Ni, Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti. The bottom metals of the first source electrode 24, the first drain electrode 25, the second source electrode 44, and the second drain electrode 45 are one of Ti, Mo, and Ta, and the other metals are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti.

[0029] Specifically, the metal of the gate electrode 32 is Ni / Au from bottom to top.

[0030] Specifically, the metals of the first source electrode 24, the first drain electrode 25, the second source electrode 44, and the second drain electrode 45 are all Ti / Al / Ni / Au from bottom to top.

[0031] For example, substrate 10 is Si, or SiC, or sapphire, or diamond.

[0032] Specifically, the substrate 10 is made of Si.

[0033] For example, the graphene layer 31 has a thickness between 1 and 20 nm to provide a common gate electrode 32 for the first transistor 20 and the second transistor 40.

[0034] Specifically, the graphene layer 31 is 10 nm thick.

[0035] For example, the n-tube AlGaN barrier layer 23 is unintentionally doped, with an aluminum composition of 5-100% and a thickness between 3-30 nm, to provide sufficient barrier height to prevent leakage current.

[0036] Specifically, the aluminum composition of the n-tube AlGaN barrier layer 23 is 25%, and the thickness is 20 nm.

[0037] For example, the thickness of the n-channel GaN channel layer 22 is 50-500 nm, and it is unintentionally doped or n-type doped.

[0038] Specifically, the thickness of the n-tube GaN channel layer 22 is 200nm, and it is not intentionally doped.

[0039] For example, the AlGaN barrier layer 43 of the p-tube is unintentionally doped, with an aluminum composition of 5-100% and a thickness between 3-30 nm, to provide sufficient barrier height to prevent leakage current.

[0040] Specifically, the aluminum composition of the p-tube AlGaN barrier layer 43 is 25%, and the thickness is 20 nm.

[0041] For example, the GaN channel layer 42 of the p-tube has a thickness of 10-30 nm and is unintentionally doped or p-type doped.

[0042] Specifically, the thickness of the GaN channel layer 42 in the p-tube is 20nm, which is not intentionally doped.

[0043] For example, the GaN doped layer 41 of the p-type transistor has a thickness of 10-150 nm, is unintentionally doped, or heavily p-type doped, and the dopant is Mg or Zn with an impurity concentration of 1 x 10⁻⁶. 18 -1x10 21 cm -3 .

[0044] Specifically, the GaN doped layer 41 of the p-tube is 80 nm thick, and the dopant is Mg with an impurity concentration of 1 x 10⁻⁶. 20 cm -3 .

[0045] For example, in a planar gate GaN vertical complementary field-effect transistor inverter, the gate electrode 32 is metal as the input terminal, the first drain electrode 25 and the second drain electrode 45 are connected and serve as the output terminal, the first source electrode 24 is connected to a low level, and the second source electrode 44 is connected to a high level, so as to realize the logic inversion between the output terminal and the input terminal.

[0046] Example 2

[0047] The present invention provides a fabrication process for a planar gate GaN vertical complementary field-effect transistor (VCFET) as follows:

[0048] Example: The substrate 10 is made of silicon with a thickness of 800 μm. The GaN buffer layer 21 and the n-type GaN channel layer 22 are n-type doped using silicon (Si) doping with a doping concentration of 1 x 10⁻⁶. 18 m -3 The buffer layer is 1000 nm thick, the channel layer is 300 nm thick, the n-tube AlGaN barrier layer 23 and p-tube AlGaN barrier layer 43 are undoped, the aluminum composition is 0.3 and the thickness is 30 nm, the p-tube GaN doped layer 41 and p-tube GaN channel layer 42 are p-type doped with magnesium (Mg) doping at a concentration of 1 x 10⁻⁶. 18 cm -3 The doped layer has a thickness of 1000 nm, the channel layer has a thickness of 300 nm, the first source electrode 24, the first drain electrode 25, the second source electrode 44 and the second drain electrode 45 of the transistor are all made of Ti / Al / Ni / Au, the gate electrode 32 is made of Ti / Au, and the gate dielectric layer is made of hafnium oxide.

[0049] Step 1: A thin silicon oxide film is formed on the side of the silicon substrate 10 on which the first transistor 20 and the second transistor 40 are stacked. Then, the silicon substrate 10 is cleaned, as follows: Figure 2 As shown.

[0050] At a high temperature of 1000℃, hydrogen gas is introduced into the reaction chamber to remove contaminants on the surface of substrate 10 and form a microscopic step structure on the surface of substrate 10 so that various epitaxial layers can be grown in subsequent epitaxial processes.

[0051] Step two, epitaxially grow a GaN buffer layer 21 on substrate 10, such as... Figure 3 As shown.

[0052] The temperature was raised to 1000℃, and a GaN buffer layer 21 with a thickness of 1000 nm was grown on the substrate 10 using the MOCVD method.

[0053] Step 3, fabricate the n-tube GaN channel layer 22, as follows: Figure 4 As shown.

[0054] Using MOCVD, an n-tube GaN channel layer 22 with a thickness of 300 nm was grown on the GaN buffer layer 21 at a temperature of 1000 °C.

[0055] Step 4: Fabricate the n-tube AlGaN barrier layer 23, as follows Figure 5 As shown.

[0056] Continuing with the MOCVD method, an n-tube AlGaN barrier layer 23 with a thickness of 20 nm was grown on the n-tube GaN channel layer 22 at a temperature of 1000 °C.

[0057] Step 5, fabricate graphene layer 31, as follows: Figure 6 As shown.

[0058] Using the MOCVD method, hydrogen (H2) and methane (CH4) gases were introduced at a temperature of 900℃ as carbon source and reducing agent to grow a graphene layer 31 with a thickness of 10 nm on the n-tube AlGaN barrier layer 23.

[0059] Step six: Fabricate the first source electrode 24 and the first drain electrode 25 on both sides of the horizontal direction of the GaN channel layer 22 of the n-tube, as follows: Figure 7-8 As shown.

[0060] A photoresist mask is fabricated using photolithography to etch away the corresponding portions of the AlGaN barrier layer 23 and the graphene layer 31 of the n-tube, exposing the first source electrode 24 and the first drain electrode 25 of the first transistor 20 to be fabricated. Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this region by electron beam evaporation, namely, Ti with a thickness of 50 nm, Al with a thickness of 150 nm, Ni with a thickness of 50 nm, and Au with a thickness of 50 nm from bottom to top. After peeling, the first source electrode 24 and the first drain electrode 25 are formed.

[0061] Step 7, continue fabricating the p-tube AlGaN barrier layer 43, as follows: Figure 9 As shown.

[0062] A 30 nm thick p-tube AlGaN barrier layer 43 is epitaxially formed on graphene layer 31, with an Al composition of 0.3.

[0063] Step 8: Fabricate the GaN channel layer 42 for the p-tube, as shown below. Figure 10 As shown.

[0064] Using MOCVD, a 300 nm thick p-tube GaN channel layer 42 was grown on the p-tube AlGaN barrier layer 43 at a temperature of 1000 °C.

[0065] Step 9: Fabricate the p-tube GaN doped layer 41, as follows Figure 11 As shown.

[0066] Using MOCVD, a 1000 nm thick p-tube GaN doped layer 41 was grown on the p-tube GaN channel layer 42 at a temperature of 1000 °C.

[0067] Step 10: Fabricate gate electrodes 32 on both sides of the graphene layer 31, such as... Figure 12-13 As shown.

[0068] A photoresist mask is fabricated using photolithography to etch away the corresponding portions of the p-tube GaN doped layer 41, p-tube GaN channel layer 42, and p-tube AlGaN barrier layer 43, exposing the area to be fabricated as gate electrode 32. Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this area by electron beam evaporation, consisting of a 50nm thick Ti layer, a 150nm thick Al layer, a 50nm thick Ni layer, and a 50nm thick Au layer from bottom to top. After peeling, the gate electrode 32 is formed.

[0069] Step 11: Fabricate a second source electrode 44 and a second drain electrode 45 on both sides of the horizontal direction of the p-tube GaN channel layer 42, as follows: Figure 14-15 As shown.

[0070] A photoresist mask is fabricated using photolithography to expose the second source electrode 44 and the second drain electrode 45 of the second transistor 40 to be fabricated. Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this region by electron beam evaporation, namely, Ti with a thickness of 50 nm, Al with a thickness of 150 nm, Ni with a thickness of 50 nm, and Au with a thickness of 50 nm from bottom to top. After peeling, the second source electrode 44 and the second drain electrode 45 are formed.

[0071] Example 3

[0072] Based on Example 2, a planar gate GaN vertical complementary field-effect transistor (VCFET) inverter was fabricated, such as... Figure 16 As shown.

[0073] The first drain electrode 25 of the first transistor 20 and the second drain electrode 45 of the second transistor 40 are connected by metal to form an air bridge 50 structure. First, an arched photoresist shaping bridge is made at the corresponding position. Then, an electroplated seed layer is made. Then, bridge metal is electroplated on the layer. Finally, the shaping bridge and seed layer metal are removed to form the air bridge 50.

[0074] With the gate electrode 32 as the input terminal and the air bridge 50 as the output terminal, the first source electrode 24 connected to a low level and the second source electrode 44 connected to a high level, the VCFET can be used to make an inverter.

[0075] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0076] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A planar gate GaN vertical complementary field-effect transistor inverter, characterized in that: The structure includes a substrate (10), a first transistor (20), a second transistor (40), and a graphene layer (31). The first transistor (20), the graphene layer (31), and the second transistor (40) are stacked vertically on the substrate (10). The first transistor (20) is an n-type transistor, including a GaN buffer layer (21), an n-type GaN channel layer (22), an n-type AlGaN barrier layer (23), a first source electrode (24), and a first drain electrode (25). The first source electrode (24) and the first drain electrode (25) are arranged horizontally on the n-type GaN channel layer. At both ends of 22), a two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the n-type GaN channel layer (22) and the n-type AlGaN barrier layer (23). The 2DEG region will serve as the n-type channel, i.e., the conductive channel of the first transistor (20). The second transistor (40) is a p-type transistor, including a p-type GaN doped layer (41), a p-type GaN channel layer (42), a p-type AlGaN barrier layer (43), a second source electrode (44), and a second drain electrode (45). The second source electrode (44) and the second drain electrode (45) are arranged horizontally on the p-type GaN channel layer (22). At both ends of the aN channel layer (42), at the heterojunction interface between the p-type GaN channel layer (42) and the p-type AlGaN barrier layer (43), holes accumulate to form a two-dimensional hole gas (2DHG). The 2DHG region will serve as the p-type channel, i.e., the conductive channel of the second transistor (40). The n-type and p-type channels are stacked vertically. A graphene layer (31) is placed between the first transistor (20) and the second transistor (40). Gate electrodes (32) are arranged on both sides of the graphene layer (31). The graphene layer (31) has good conductivity and together with the gate electrodes (32) serves as... The gate electrode (32) of the first transistor (20) and the second transistor (40) enables simultaneous control of the n-type channel and the p-type channel. The presence of the graphene layer (31) makes the gate electrode (32) more effective in controlling the channel layer and more accurately controls the current of the p-type and n-type transistors. The gate electrode (32) is used as the input terminal. The first drain electrode (25) and the second drain electrode (45) are connected by a metal phase to form an air bridge (50) structure and serve as the output terminal. The first source electrode (24) is connected to a low level and the second source electrode (44) is connected to a high level to form an inverter, realizing the logic inversion between the output terminal and the input terminal.

2. The planar gate GaN vertical complementary field-effect transistor inverter according to claim 1, characterized in that: The bottom metal of the gate electrode (32) is one of Ni, Ti, Mo, and Ta, and the bottom metal of the first source electrode (24), the first drain electrode (25), the second source electrode (44), and the second drain electrode (45) is one of Ti, Mo, and Ta.

3. The planar gate GaN vertical complementary field-effect transistor inverter according to claim 1, characterized in that: The substrate (10) is Si, SiC, sapphire or diamond.

4. The planar gate GaN vertical complementary field-effect transistor inverter according to claim 1, characterized in that: The graphene layer (31) has a thickness between 1 and 20 nm and provides the common gate electrode (32) for the first transistor (20) and the second transistor (40). The n-tube AlGaN barrier layer (23) is unintentionally doped, with an aluminum composition of 5-100% and a thickness between 3 and 30 nm. The polarization charge on its lower surface induces a two-dimensional electron gas near the upper surface of the n-tube GaN channel layer (22). In addition, it provides sufficient barrier height to prevent leakage current. The n-tube GaN channel layer (22) has a thickness of 50-500 nm and is unintentionally doped or n-type doped. Its upper surface forms Two-dimensional electron gas serves as the conductive channel for the first transistor (20). The p-tube AlGaN barrier layer (43) is unintentionally doped with an aluminum composition of 5-100% and a thickness of 3-30 nm to provide sufficient barrier height to prevent leakage current. The p-tube GaN channel layer (42) is 10-30 nm thick, unintentionally doped, or p-type doped to provide the conductive channel for the second transistor (40). The p-tube GaN doped layer (41) is 10-150 nm thick, unintentionally doped, or heavily p-type doped, with Mg or Zn as the doping impurity and an impurity concentration of 1 x 10⁻⁶. 18 -1x10 21 cm -3 This provides a hole source for the GaN channel layer (42) of the p-tube.

5. The planar gate GaN vertical complementary field-effect transistor inverter according to claim 1, characterized in that: The air bridge (50) is connected by metal materials of Au, Ti or Pt.

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