Back-incident semiconductor light detection element

Abstract

The semiconductor substrate (11) has a first main surface (11a) and a second main surface (11b) facing each other. The semiconductor substrate (11) has: a first semiconductor region (13) of a first conductivity type; and a plurality of second semiconductor regions (15) of a second conductivity type that constitute a pn junction with the first semiconductor region (13). The semiconductor substrate (11) is provided with a plurality of second semiconductor regions (15) on the second main surface (11b) side. Each of the plurality of second semiconductor regions (15) has: a first region (17) having a textured surface (TS); and a second region (19) having no textured surface. The thickness (TH1) of the first region (17) at the deepest position of the depression of the textured surface (TS) is smaller than the distance (D1) between the surface of the second region (19) and the deepest position in the thickness direction of the semiconductor substrate (11). The first main surface (11a) is a light incident surface on the semiconductor substrate (11).

Description

[0001] This application is filed on April 11, 2019 、Application No. 201980026039.1 、The name of the invention is Back entry Emission type semiconductor light detection element A divisional application for a patent application. Technical Field

[0002] The present invention relates to a back-illuminated semiconductor light detecting element. Background Art

[0003] It is known that there is a back-illuminated semiconductor light detecting element having a semiconductor substrate having a first main surface and a second main surface opposite to each other (for example, refer to patent documents 1 and 2). In the back-illuminated semiconductor light detecting element described in patent document 2, the semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The semiconductor substrate has a plurality of second semiconductor regions on the second main surface side. Each second semiconductor region forms a pn junction with the first semiconductor region. The first main surface is a light incident surface of the semiconductor substrate. The plurality of second semiconductor regions have a textured surface.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent Application Publication No. 2012 / 0313204

[0007] Patent Document 2: Japanese Patent Application Publication No. 2011-023417 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] An object of one embodiment of the present invention is to provide a back-illuminated semiconductor light detecting element having further improved spectral sensitivity characteristics in a long wavelength region, such as a near-infrared wavelength region.

[0010] Technical means of solving problems

[0011] A back-illuminated semiconductor light detecting element according to one embodiment of the present invention comprises a semiconductor substrate having a first main surface and a second main surface opposite to each other. The first main surface is a light incident surface of the semiconductor substrate. The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions of the second conductivity type are arranged on the second main surface side and form a pn junction with the first semiconductor region. The plurality of second semiconductor regions respectively include: a first region having a textured surface; and a second region not having a textured surface. The thickness of the first region at the deepest position of the depression of the textured surface is smaller than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate.

[0012] In the back-illuminated semiconductor light detection element involved in one of the above methods, the first region of the second semiconductor region has a textured surface. The light in the long wavelength region has a smaller absorption coefficient than the light in the short wavelength region. Therefore, the light in the long wavelength region incident on the semiconductor substrate from the first main surface travels in the semiconductor substrate and reaches the textured surface. The light reaching the textured surface is reflected or diffused on the textured surface and further travels in the semiconductor substrate. Because the light in the long wavelength region travels a long distance in the semiconductor substrate, the light in the long wavelength region is absorbed by the semiconductor substrate. As a result, the above method improves the spectral sensitivity characteristics in the long wavelength region.

[0013] Carriers generated by light absorption in the semiconductor substrate may recombine in the second semiconductor region. Carriers recombined in the second semiconductor region do not contribute to detection sensitivity, so the spectral sensitivity characteristics may be reduced.

[0014] In a structure where the thickness of the second semiconductor region is large, the recombination of carriers in the second semiconductor region is more likely to occur than in a structure where the thickness of the second semiconductor region is small. That is, in a structure where the distance from the surface of the second semiconductor region to the pn junction is large, the recombination of carriers in the second semiconductor region is more likely to occur than in a structure where the distance from the surface of the second semiconductor region to the pn junction is small.

[0015] In the above-mentioned one embodiment, the thickness of the first region at the deepest position of the depression of the texture surface is smaller than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate. In the above-mentioned one embodiment, the distance from the texture surface to the pn junction is smaller than the structure in which the thickness of the first region at the deepest position of the depression of the texture surface is greater than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate. Therefore, the recombination of carriers in the second semiconductor region caused by light incident on the semiconductor substrate is suppressed. As a result, the above-mentioned one embodiment further improves the spectral sensitivity characteristics in the long wavelength region.

[0016] In the above-described aspect, the thickness of the second region in the thickness direction of the semiconductor substrate may be greater than the thickness of the first region in the thickness direction of the semiconductor substrate.

[0017] When stress acts on the semiconductor substrate, carriers that are not caused by the incidence of light may be generated. Carriers that are not caused by the incidence of light cause dark current to be generated. Stress is more likely to act on the second region than on the first region. Therefore, carriers that are not caused by the incidence of light are more likely to be generated in the second region than in the first region. In a structure in which the thickness of the second region is greater than the thickness of the first region, recombination of carriers that are not caused by the incidence of light is more likely to occur in the second region than in a structure in which the thickness of the second region is less than the thickness of the first region. Therefore, this structure suppresses the generation of dark current.

[0018] The above-mentioned one aspect may include an electrode disposed in the second region and in contact with the second region.

[0019] In this structure, the electrode contacts the second region whose thickness in the thickness direction of the semiconductor substrate is greater than that of the first region. When the electrode contacts the semiconductor substrate, the material constituting the electrode and the material constituting the semiconductor substrate are alloyed, and an alloy peak may be generated in the semiconductor substrate. When the alloy peak reaches the pn junction, the alloy peak increases the leakage current. In a structure in which the thickness of the second region is greater than that of the first region, the alloy peak is difficult to reach the pn junction compared to a structure in which the thickness of the second region is less than the thickness of the first region. Therefore, this structure suppresses the increase of the leakage current.

[0020] In the above aspect, the textured surface of the first region may be located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate.

[0021] In this case, stress is difficult to act on the first region. Therefore, in the first region, the generation of carriers not caused by the incidence of light is suppressed. As a result, the present structure suppresses the generation of dark current. In the present structure, for example, when a textured surface is formed in the second semiconductor region, the distance from the textured surface to the pn junction can be further reduced. Therefore, the present structure can further improve the spectral sensitivity characteristics in the long wavelength region.

[0022] In the above-mentioned aspect, an edge region of the textured surface of the first region may be continuous with the surface of the second region and may be inclined with respect to the thickness direction of the semiconductor substrate.

[0023] When the texture surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate, stress is more likely to act on the second region. In a structure in which the edge region of the texture surface of the first region is inclined relative to the thickness direction of the semiconductor substrate, the stress acting on the second region is more likely to be dispersed than in a structure in which the edge region of the texture surface of the first region is parallel to the thickness direction of the semiconductor substrate. Therefore, when stress acts on the second region, the concentration of stress to the second region is also suppressed. This structure suppresses the generation of carriers that are not caused by the incidence of light. As a result, this structure suppresses the generation of dark current.

[0024] Effects of the Invention

[0025] One embodiment of the present invention provides a back-illuminated semiconductor light detecting element having further improved spectral sensitivity characteristics in a long wavelength region. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The diagram is a top view of a back-illuminated semiconductor light detecting element according to one embodiment.

[0027] Figure 2 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to the present embodiment.

[0028] Figure 3 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to the present embodiment.

[0029] Figure 4 This is a SEM image obtained by observing the textured surface.

[0030] Figure 5 This is a SEM image obtained by observing the textured surface.

[0031] Figure 6 This is a diagram showing the cross-sectional structure of one pixel.

[0032] Figure 7 It is a line graph showing the distribution of impurity concentration.

[0033] Figure 8 It is a schematic diagram showing an example of a manufacturing process of the back-illuminated semiconductor light detecting element according to the present embodiment.

[0034] Fig. 9 It is a schematic diagram showing an example of a manufacturing process of the back-illuminated semiconductor light detecting element according to the present embodiment.

[0035] Fig.10 It is a schematic diagram showing an example of a manufacturing process of the back-illuminated semiconductor light detecting element according to the present embodiment.

[0036] Fig.11 It is a diagram showing a cross-sectional structure of an electronic component device including a back-illuminated semiconductor light detecting element according to the present embodiment.

[0037] Fig.12 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a first modified example of the present embodiment.

[0038] Fig.13 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a first modification.

[0039] Fig.14 It is a diagram showing a cross-sectional structure of an electronic component device including a back-illuminated semiconductor light detecting element according to a first modification.

[0040] Fig.15 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a second modification of the present embodiment.

[0041] Fig.16 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a second modification.

[0042] Fig.17 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a third modified example of the present embodiment.

[0043] Fig.18 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a third modification.

[0044] Fig.19 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a fourth modified example of the present embodiment.

[0045] Fig. 20 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a fifth modification of the present embodiment.

[0046] Fig.21 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a sixth modification of the present embodiment.

[0047] Fig. 22 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a seventh modification of the present embodiment.

[0048] Fig.23 This is a diagram showing the cross-sectional structure of one pixel.

[0049] Fig.24 It is a schematic diagram showing an example of a manufacturing process of a back-illuminated semiconductor light detecting element according to the seventh modification.

[0050] Fig.25 It is a schematic diagram showing an example of a manufacturing process of a back-illuminated semiconductor light detecting element according to the seventh modification.

[0051] Fig.26 It is a line graph showing the distribution of impurity concentration. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same functions, and repeated descriptions are omitted.

[0053] Reference Figure 1 to Figure 6 , the structure of the back-illuminated semiconductor light detecting element 1 according to the present embodiment will be described. Figure 1 It is a top view of the back-illuminated semiconductor light detecting element according to the present embodiment. Figure 2 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to the present embodiment. Figure 3 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to the present embodiment. Figure 4 and Figure 5 This is a SEM image obtained by observing the textured surface. Figure 6 This is a diagram showing the cross-sectional structure of one pixel. Figure 6 In the figure, hatching indicating cross sections is omitted.

[0054] like Figure 1 and Figure 2 As shown, the semiconductor light detecting element 1 includes a semiconductor substrate 11. The semiconductor substrate 11 is a substrate made of silicon (Si). The semiconductor substrate 11 has a main surface 11a and a main surface 11b opposite to each other. The main surface 11a is a light incident surface of the semiconductor substrate 11. The main surface 11a is the back surface, and the main surface 11b is the front surface. The semiconductor substrate 11 is, for example, polygonal in plan view. In the present embodiment, the semiconductor substrate 11 is rectangular in plan view. The thickness of the semiconductor substrate 11 is, for example, 150 μm. The thickness direction of the semiconductor substrate 11 is, for example, a direction parallel to the Z axis. In the present embodiment, the thickness direction of the semiconductor substrate 11 is consistent with the direction opposite to the main surface 11a and the main surface 11b. The thickness direction of the semiconductor substrate 11 is consistent with the direction orthogonal to the semiconductor substrate 11, the direction orthogonal to the main surface 11a, and the direction orthogonal to the main surface 11b.

[0055] The semiconductor substrate 11 has a semiconductor region 13 of a first conductivity type, a plurality of semiconductor regions 15 of a second conductivity type, and a semiconductor region 16 of a first conductivity type. The semiconductor substrate 11 has a plurality of semiconductor regions 15 on the main surface 11b side. The semiconductor substrate 11 has a plurality of semiconductor regions 15 disposed on the main surface 11b side. The semiconductor substrate 11 has a semiconductor region 16 on the main surface 11a side. The semiconductor substrate 11 has a semiconductor region 16 disposed on the main surface 11a side. The semiconductor region 16 functions as an accumulation layer. The first conductivity type is, for example, an n-type. The second conductivity type is, for example, a p-type. In the case where the semiconductor substrate 11 is composed of Si, the p-type impurity includes, for example, a Group 13 element, and the n-type impurity includes, for example, a Group 15 element. The p-type impurity is, for example, boron (B). The n-type impurity is, for example, nitrogen (N), phosphorus (P), or arsenic (As). The first conductivity type may also be a p-type and the second conductivity type may be an n-type.

[0056] The semiconductor region 13 has a low impurity concentration. The semiconductor regions 15 and 16 have a high impurity concentration. The semiconductor regions 15 and 16 have higher impurity concentrations than the semiconductor region 13. The impurity concentration of the semiconductor region 13 is, for example, 5×10 12 cm -3 The impurity concentration of the semiconductor region 15 is, for example, 1×10 19 cm -3 The impurity concentration of the semiconductor region 16 is, for example, 1×10 15 cm -3 The maximum thickness of the semiconductor region 15 is, for example, 5 μm. The thickness of the semiconductor region 16 is, for example, 1 μm.

[0057] The plurality of semiconductor regions 15 are arranged two-dimensionally when viewed from a direction orthogonal to the semiconductor substrate 11. In the present embodiment, the plurality of semiconductor regions 15 are arranged along a first direction and a second direction orthogonal to each other. The plurality of semiconductor regions 15 are arranged in M ​​rows and N columns. M and N are integers greater than 2. The first direction is, for example, a direction parallel to the X-axis. The second direction is, for example, a direction parallel to the Y-axis. Each semiconductor region 15 is, for example, polygonal when viewed from a direction orthogonal to the semiconductor substrate 11. In the present embodiment, each semiconductor region 15 is rectangular. Each semiconductor region 15 may also be circular when viewed from a direction orthogonal to the semiconductor substrate 11. In the present embodiment, one semiconductor region 15 constitutes one pixel. The semiconductor light detecting element 1 has a plurality of pixels arranged two-dimensionally. The semiconductor region 13 and each semiconductor region 15 constitute a pn junction. The pn junction is formed at the boundary between the semiconductor region 13 and each semiconductor region 15. In each pixel, the region including the semiconductor region 15 and the pn junction is a light sensing region. The rectangular shape includes a shape with chamfered corners and a shape with rounded corners.

[0058] The semiconductor substrate 11 has a semiconductor region 14 of a first conductivity type. The semiconductor substrate 11 has a semiconductor region 14 on the main surface 11b side. The semiconductor substrate 11 has a semiconductor region 14 provided on the main surface 11b side. The semiconductor region 14 is frame-shaped when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 14 is provided along the edge of the main surface 11b in a manner surrounding a region where a plurality of semiconductor regions 15 are arranged when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 14 functions as a channel stop layer and suppresses the depletion layer from reaching the side surface of the semiconductor substrate 11.

[0059] Each semiconductor region 15 includes a region 17 having a textured surface TS and a region 19 not having a textured surface TS. Figure 4 and Figure 5 As shown, it is a surface formed with fine concavo-convex. Region 17 is a region formed with fine concavo-convex on the surface. Fine concavo-convex is formed on the entire surface of region 17. Region 17 has a textured surface TS on the entire surface. The textured surface TS is formed, for example, by wet etching. The textured surface TS can also be formed by dry etching or laser irradiation. The region whose surface is the textured surface TS is a textured region. Figure 4 The textured surface TS shown is formed by wet etching. Figure 5 The textured surface TS shown is formed by dry etching. Figure 3 In the figure, in order to easily understand the area serving as the texture surface TS, the area serving as the texture surface TS is shaded.

[0060] The concavities and convexities of the texture surface TS are formed irregularly. The so-called irregular concavities and convexities of the texture surface TS include at least one of irregular changes in the spacing between the tops of the concavities and convexities and irregular changes in the height difference of the concavities and convexities. In the present embodiment, the spacing between the tops of the concavities and convexities changes irregularly, and the height difference of the concavities and convexities changes irregularly. The spacing between the tops of the concavities and convexities of the texture surface TS is, for example, 0.1 to 1.0 μm. The height difference of the concavities and convexities of the texture surface TS is, for example, 0.5 to 1.5 μm. The concavities and convexities of the texture surface TS can also be formed regularly.

[0061] Area 17 Figure 3As shown, when viewed from a direction perpendicular to the semiconductor substrate 11, it is located on the inner side of the region 19. In the present embodiment, when viewed from a direction perpendicular to the semiconductor substrate 11, the region 17 extends over the entire edge of the region 17 and is surrounded by the region 19. The surface of the region 19 is flat. The region 19 has two regions 19a and 19b that are continuous with each other. The region 19a is positioned along the edge of the semiconductor region 15. The region 19b is located at a corner of the semiconductor region 15. The surface of the region 19a and the surface of the region 19b are located on the same plane. When viewed from a direction perpendicular to the semiconductor substrate 11, the region 17 has a rectangular shape in which one corner is cut out in a rectangular shape. The regions 17 and 19b are as shown in FIG. Figure 3 As shown, when viewed from a direction perpendicular to the semiconductor substrate 11, they are adjacent to each other in a direction intersecting the first direction and the second direction.

[0062] like Figure 6 As shown, the thickness TH1 of the region 17 at the deepest position of the depression of the texture surface TS is smaller than the distance D1 between the surface of the region 19 (region 19b) and the deepest position in the thickness direction of the semiconductor substrate 11. The deepest position is, for example, the deepest position of the deepest depression among all the depressions. The deepest position may also be the deepest position of any one of all the depressions. The deepest position may also be the average position of the deepest positions of all the depressions.

[0063] The impurity concentration of the semiconductor region 15 is, for example, Figure 7 That is, the impurity concentration of the semiconductor region 15 changes with the distance from the main surface 11 b in the thickness direction of the semiconductor substrate 11 , for example. Figure 7 It is a line graph showing the distribution of impurity concentration. Figure 7 The impurity concentration distribution shown is the distribution when the impurities are thermally diffused by the following process. After the semiconductor region 15 is formed, the texture surface TS is formed. Thereafter, the impurities are thermally diffused by high-temperature heat treatment. This process will be described later as a manufacturing process of the semiconductor light detection element 1 involved in this embodiment.

[0064] The impurity concentration of the semiconductor region 15 remains high until a predetermined depth position, and gradually decreases from the predetermined depth position toward the main surface 11a. The semiconductor region 15 has a region R1 located near the main surface 11b and a region R2 located closer to the main surface 11a than the region R1, according to the distribution of the impurity concentration. The region R1 and the region R2 are continuous. The region R1 is a region with a high impurity concentration. The region R2 is a transition region where the impurity concentration gradually decreases from the impurity concentration in the region R1. In the present embodiment, the predetermined depth is, for example, about 3 μm.

[0065] In this embodiment, the deepest position of the depression of the texture surface TS is located near the boundary between the region R1 and the region R2. That is, the deepest position is located near the region where the impurity concentration of the semiconductor region 15 begins to decrease. In the region 17, the proportion occupied by the region R2 is greater than the proportion occupied by the region R1. The region 17 may also be composed of only the region R2.

[0066] The thickness of the semiconductor region 15 (regions 17 and 19) is defined, for example, by the distance from the surface to the depth at which the impurity concentration of the semiconductor region 15 is equal to the impurity concentration of the semiconductor region 16. This distance is also the distance in the thickness direction of the semiconductor substrate 11. In this case, the thickness TH1 is defined by the distance from the deepest position of the depression of the texture surface TS to the depth at which the impurity concentration of the semiconductor region 15 is equal to the impurity concentration of the semiconductor region 16. The deepest position of the depression is, for example, the deepest position of the deepest depression among all the depressions. In this case, the thickness TH1 represents the minimum value of the thickness of the region 17. The deepest position of the depression may also be, for example, the deepest position of the shallowest depression among all the depressions. In this case, the thickness TH1 represents the maximum value of the thickness of the region 17. The deepest position of the depression may also be, for example, the average position of the deepest positions of all the depressions. In this case, the thickness TH1 represents the average value of the thickness of the region 17. The thickness TH1 is, for example, 0.1 to 1.0 μm.

[0067] The thickness of the semiconductor region 15 (regions 17 and 19) can also be defined by, for example, the distance from the surface to the position where the region R2 ends in the thickness direction of the semiconductor substrate 11. The position where the region R2 ends is defined by Figure 7 As can be clearly seen, this is the position where the reduction in impurity concentration ends. In this case, thickness TH1 is defined by the distance from the deepest position of the depression of texture surface TS to the position where region R2 ends.

[0068] The interval D1 is the depth of the depression of the texture surface TS. When the deepest position is the deepest position of the deepest depression, the interval D1 is the maximum value of the depth of the depression of the texture surface TS. When the deepest position is the deepest position of the shallowest depression, the interval D1 is the minimum value of the depth of the depression of the texture surface TS. When the deepest position is the average position of the deepest positions of all depressions, the interval D1 is the average depth of the depression of the texture surface TS. The interval D1 is, for example, 1.0 to 2.5 μm.

[0069] The thickness TH2 of the region 19 (region 19b) in the thickness direction of the semiconductor substrate 11 is greater than the thickness TH3 of the region 17 in the thickness direction of the semiconductor substrate 11. The thickness TH2 is 5 μm, for example. In the present embodiment, the thickness TH2 is also the maximum thickness of the semiconductor region 15.

[0070] The thickness TH3 of the region 17 varies in accordance with the concavity and convexity of the texture surface TS. The thickness TH3 is, for example, the thickness at the deepest position of the concavity of the texture surface TS. In this case, the thickness TH3 is equal to the thickness TH1. The thickness TH3 may be, for example, the thickness at the top of the texture surface TS. The top of the predetermined thickness TH3 is, for example, the highest top among all the tops. The highest top is the top located closest to the main surface 11b in the thickness direction of the semiconductor substrate 11. In this case, the thickness TH3 represents the maximum thickness of the region 17. The top of the predetermined thickness TH3 may be, for example, the lowest top among all the tops. The lowest top is the top located closest to the main surface 11a in the thickness direction of the semiconductor substrate 11. The thickness TH3 may be, for example, the distance from the average height position of the concavity and convexity of the texture surface TS to the position where the region R2 ends. The thickness TH3 is, for example, 0.1 to 1.5 μm.

[0071] The texture surface TS is located closer to the main surface 11a than the surface of the region 19 (regions 19a, 19b) in the thickness direction of the semiconductor substrate 11. That is, the texture surface TS is located closer to the main surface 11a than the virtual plane VP including the surface of the region 19 (regions 19a, 19b). The main surface 11b is recessed in the region 17. A step difference is formed between the texture surface TS and the surface of the region 19. The edge region TSa of the texture surface TS of the region 17 is continuous with the surface of the region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. In the present embodiment, the edge region TSa is inclined in such a manner that the thickness of the region 17 in the edge region TSa gradually increases as it moves from the region 17 toward the region 19.

[0072] The semiconductor light detecting element 1 includes a plurality of insulating films 21, 23, 25, a plurality of pad electrodes 31, a plurality of UBMs (under-bump metals) 33, and a plurality of bump electrodes 35. In the present embodiment, the semiconductor light detecting element 1 includes a pad electrode 31, a UBM 33, and a bump electrode 35 in each semiconductor region 15. The semiconductor light detecting element 1 includes an electrode (not shown) electrically connected to the semiconductor region 14. The electrode electrically connected to the semiconductor region 14 is arranged on the main surface 11b side.

[0073] The insulating film 21 is arranged on the main surface 11a of the semiconductor substrate 11. The insulating film 21 is formed on the main surface 11a. The insulating film 21 is, for example, an oxide film. In the present embodiment, the insulating film 21 is composed of silicon oxide (SiO2). The insulating film 21 is, for example, a silicon thermal oxide film. The insulating film 21 may also be composed of silicon nitride (SiN). In this case, the insulating film 21 is formed, for example, by plasma CVD (Plasma-enhanced Chemical Vapor Deposition). The insulating film 21 functions as an anti-reflection film. The thickness of the insulating film 21 is, for example, 0.1 μm.

[0074] The insulating film 23 is arranged on the main surface 11b of the semiconductor substrate 11. The insulating film 23 is formed on the main surface 11b. The insulating film 23 is, for example, an oxide film. In the present embodiment, the insulating film 21 is made of silicon oxide. The insulating film 23 is, for example, a silicon thermal oxide film. The insulating film 23 covers the surface of each semiconductor region 15. The insulating film 23 directly covers the entire texture surface TS. The insulating film 23 is in contact with the main surface 11b (texture surface TS). The insulating film 23 may also be made of silicon nitride. In this case, the insulating film 23 is formed by low-pressure CVD (Low-pressure Chemical Vapor Deposition). The insulating film 23 may also be made of aluminum oxide (Al2O3). In this case, the insulating film 23 is formed by ALD (Atomic Layer Deposition). The thickness of the insulating film 23 is, for example, 0.2μm.

[0075] The insulating film 25 is arranged on the main surface 11b of the semiconductor substrate 11. The insulating film 25 is formed on the insulating film 23. The insulating film 25 is in contact with the insulating film 23. The insulating film 25 is, for example, a nitride film. In the present embodiment, the insulating film 25 is made of silicon nitride. The insulating film 23 is located between the semiconductor substrate 11 and the insulating film 25. The insulating film 25 is indirectly arranged on the semiconductor substrate 11. The insulating film 25 indirectly covers the surface of each semiconductor region 15. The insulating film 25 directly covers the region corresponding to the region 17 in the insulating film 23. The insulating film 25 indirectly covers the entire texture surface TS. The insulating film 25 can also be made of silicon oxide. In this case, the insulating film 25 is formed, for example, by plasma CVD. The insulating film 25 acts as a passivation film. The thickness of the insulating film 25 is, for example, 0.1 to 0.4 μm.

[0076] The pad electrode 31 is arranged in the region 19. In the present embodiment, the pad electrode 31 is arranged in the region 19b. The pad electrode 31 is formed on the region 19b and on the insulating film 23. The pad electrode 31 is connected to the region 19b through the contact hole H1 formed in the insulating film 23. The pad electrode 31 is in contact with the region 19 and the insulating film 23. The pad electrode 31 is directly arranged on the region 19b. The pad electrode 31 is in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrode 31. The pad electrode 31 is made of a conductive material. The pad electrode 31 is made of, for example, aluminum (Al). In this case, the pad electrode 31 is formed by a sputtering method or a vapor deposition method.

[0077] The pad electrode 31 is as follows Figure 3 As shown, there are two electrode regions 31a and 31b. In this embodiment, the pad electrode 31 is composed of two electrode regions 31a and 31b. The electrode region 31a is arranged in the region 19. In this embodiment, the electrode region 31a is arranged in the region 19b. The electrode region 31a is in contact with the region 19b. The electrode region 31a is directly arranged on the region 19b. The electrode region 31b is arranged in at least a part of the region corresponding to the region 17 in the insulating film 23. The electrode region 31b is arranged in the region 17 in such a way that the insulating film 23 is located between the region 17 and the electrode region 31b. The electrode region 31b is continuous with the electrode region 31a. The pad electrode 31 overlaps with the entire boundary between the region 17 and the region 19b when viewed from a direction orthogonal to the semiconductor substrate 11. In this embodiment, the electrode region 31b overlaps with the edge region TSa continuous with the region 19b when viewed from a direction orthogonal to the semiconductor substrate 11. The electrode region 31b is indirectly arranged on the edge region TSa. Figure 3 In the figure, the insulating films 23 and 25 are omitted.

[0078] UBM33 is configured in region 19. In the present embodiment, UBM33 is configured in region 19b. UBM33 is formed on region 19b and on insulating film 25. UBM33 is connected to pad electrode 31 through contact hole H2 formed in insulating film 25. UBM33 is in contact with pad electrode 31. UBM33 is in contact with insulating film 25. UBM33 is made of a material having excellent electrical and physical connection with bump electrode 35. UBM33 is made of, for example, a laminated body including a layer made of titanium (Ti) and a layer made of platinum (Pt). UBM33 is formed, for example, by a laminated evaporation method.

[0079] The bump electrode 35 is arranged in the region 19. In the present embodiment, the bump electrode 35 is arranged in the region 19b. The bump electrode 35 is formed on the UBM 33. The bump electrode 35 is in contact with the UBM 33. The UBM 33 is located between the pad electrode 31 and the bump electrode 35. The bump electrode 35 is indirectly arranged on the region 19. The bump electrode 35 is indirectly arranged on the pad electrode 31. The bump electrode 35 is electrically connected to the region 19b (semiconductor region 15) through the UBM 33 and the pad electrode 31. The bump electrode 35 is made of a solder material. The bump electrode 35 is made of, for example, indium (In). The bump electrode 35 is formed, for example, by a vapor deposition method.

[0080] In the semiconductor light detecting element 1, the semiconductor region 13 is completely depleted by application of a bias voltage, that is, a depletion layer extending from the semiconductor region 15 reaches the semiconductor region 13. The semiconductor region 13 may not be completely depleted.

[0081] Next, refer to Figure 8 to Figure 10 An example of a manufacturing process of the semiconductor light detecting element 1 will be described. Figure 8 to Figure 10 It is a schematic diagram showing an example of a manufacturing process of the back-illuminated semiconductor light detecting element according to the present embodiment. Figure 8 to Figure 10 In the figure, hatching indicating cross sections is omitted.

[0082] like Figure 8 As shown in (a), an n-type semiconductor substrate 11 is prepared. An oxide film 51 is formed on the main surface 11a, and an oxide film 53 is formed on the main surface 11b. The oxide films 51 and 53 are formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. Figure 8 In the state shown in (a), the semiconductor substrate 11 is composed of the semiconductor region 13 and does not have the semiconductor region 15 and the semiconductor region 16 .

[0083] like Figure 8 As shown in (b), a plurality of semiconductor regions 15 and a semiconductor region 16 are formed on the semiconductor substrate 11. Through this process, the semiconductor substrate 11 having the semiconductor region 13, the plurality of semiconductor regions 15, and the semiconductor region 16 is prepared.

[0084] The semiconductor region 15 is formed as follows. The opening 53a is formed in the oxide film 53 by patterning the oxide film 53. The opening 53a is rectangular. The p-type impurity is added to the semiconductor substrate 11 from the main surface 11b through the opening 53a of the oxide film 53. The added p-type impurity is diffused in the semiconductor substrate 11 by high-temperature heat treatment. The semiconductor region 15 is formed by the p-type impurity diffused from the main surface 11b at a high concentration. By the above-mentioned high-temperature heat treatment, the oxide film 55 is formed on the semiconductor region 15 (refer to Figure 8 (c)).

[0085] The semiconductor region 16 is formed as follows. An n-type impurity is added from the main surface 11a to the semiconductor substrate 11. The added n-type impurity diffuses in the semiconductor substrate 11 by the high-temperature heat treatment described above. The semiconductor region 16 is formed of the n-type impurity diffused at a high concentration from the main surface 11a.

[0086] like Figure 8 As shown in (c), the contact hole H1 is formed in the oxide film 55 by patterning the oxide film 55. After the contact hole H1 is formed, the silicon nitride film 57 is formed on the oxide films 51 and 55. The silicon nitride film 57 is formed by, for example, reduced pressure CVD.

[0087] like Fig. 9 As shown in (a) of FIG. 1 , the silicon nitride film 57 formed on the oxide film 55 and the oxide film 55 are patterned, and an opening 59 is formed at a position corresponding to the region 17 of the semiconductor region 15. The opening 59 is formed by dry etching, for example.

[0088] like Fig. 9 As shown in (b) of FIG. 1 , the texture surface TS is formed in a region of the semiconductor region 15 exposed from the opening 59. The texture surface TS is formed by wet etching, for example, as described above. Fig. 9 In the drawings after (b), the cross-hatched area is the area where the textured surface TS is formed.

[0089] like Fig. 9 As shown in (c), the oxide film 61 is formed in the region of the semiconductor region 15 exposed from the opening 59. The oxide film 61 is formed on the texture surface TS. The oxide film 61 is formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. The oxide films 53 and 61 constitute the insulating film 23.

[0090] like Fig.10 As shown in (a), the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (oxide films 53, 61). By removing the silicon nitride film 57, the semiconductor region 15 is exposed through the contact hole H1. Thereafter, the pad electrode 31 is formed in the region of the semiconductor region 15 exposed through the contact hole H1. The pad electrode 31 is also formed in a manner located on the region around the contact hole H1 of the insulating film 23. The oxide film 51 constitutes the insulating film 21.

[0091] like Fig.10 As shown in (b), after the insulating film 25 is formed on the insulating film 23, the contact hole H2 is formed in the insulating film 25 by patterning the insulating film 25. By forming the contact hole H2, a part of the pad electrode 31 is exposed.

[0092] like Fig.10As shown in (c), UBM33 is formed in the region of pad electrode 31 exposed from contact hole H2. UBM33 is also formed in a manner located on the region around contact hole H2 of insulating film 25. That is, UBM33 is also formed in a manner indirectly configured on region 19. Thereafter, bump electrode 35 is formed on UBM33. Through these processes, semiconductor light detecting element 1 is obtained.

[0093] Next, refer to Fig.11 , the structure of the electronic component device ED including the semiconductor light detecting element 1 will be described. Fig.11 It is a diagram showing a cross-sectional structure of an electronic component device including a back-illuminated semiconductor light detecting element according to the present embodiment.

[0094] The electronic component device ED includes a semiconductor light detecting element 1, an electronic component EC on which the semiconductor light detecting element 1 is mounted, and a resin layer RL. The electronic component EC includes, for example, a wiring board or an ASIC (Application Specific Integrated Circuit).

[0095] The electronic component EC includes a plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75. The plurality of pad electrodes 71, the plurality of UBMs 73, and the plurality of bump electrodes 75 are arranged at positions corresponding to the plurality of bump electrodes 35 provided on the semiconductor light detecting element 1. The semiconductor light detecting element 1 is mounted on the electronic component EC by bonding the corresponding bump electrodes 35 and bump electrodes 75. The electrode electrically connected to the semiconductor region 14 is also bonded to the bump electrode (not shown) of the electronic component EC.

[0096] The resin layer RL is disposed between the semiconductor light detecting element 1 and the electronic component EC. The resin layer RL functions as an underfill layer. The resin layer RL is formed by curing a resin material that fills a space formed between the semiconductor light detecting element 1 and the electronic component EC. The resin layer RL includes, for example, an epoxy resin, a polyurethane resin, a silicone resin, or an acrylic resin.

[0097] As described above, in the semiconductor light detecting element 1, the region 17 of the semiconductor region 15 has a textured surface TS. The light in the long wavelength region has a smaller absorption coefficient than the light in the short wavelength region. Therefore, the light in the long wavelength region incident on the semiconductor substrate 11 from the main surface 11a travels in the semiconductor substrate 11 and reaches the textured surface TS. The light reaching the textured surface TS is reflected or diffused on the textured surface TS and further travels in the semiconductor substrate 11. Because the light in the long wavelength region travels a long distance in the semiconductor substrate 11, the light in the long wavelength region is absorbed by the semiconductor substrate 11. As a result, the semiconductor light detecting element 1 improves the spectral sensitivity characteristics in the long wavelength region.

[0098] Carriers generated by light absorption by the semiconductor substrate 11 may be recombined in the semiconductor region 15. Carriers recombined in the semiconductor region 15 do not contribute to detection sensitivity, so the spectral sensitivity characteristics may be reduced. In a structure in which the thickness of the semiconductor region 15 is large, the recombination of carriers in the semiconductor region 15 is easy to occur compared with a structure in which the thickness of the semiconductor region 15 is small. That is, in a structure in which the distance from the surface of the semiconductor region 15 to the pn junction is large, the recombination of carriers in the semiconductor region 15 is easy to occur compared with a structure in which the distance from the surface of the semiconductor region 15 to the pn junction is small.

[0099] In the semiconductor light detecting element 1, the thickness TH1 is smaller than the interval D1. In the semiconductor light detecting element 1, the distance from the texture surface TS to the pn junction is smaller than that of the structure in which the thickness TH1 is greater than the interval D1. Therefore, the recombination of carriers in the semiconductor region 15 caused by the light incident on the semiconductor substrate 11 is suppressed. As a result, the semiconductor light detecting element 1 further improves the spectral sensitivity characteristics in the long wavelength region.

[0100] In the above-mentioned manufacturing process, before the texture region (texture surface TS) is formed on the main surface 11b, a plurality of semiconductor regions 15 are formed in a plurality of predetermined regions. After the plurality of semiconductor regions 15 are formed, it is necessary to reliably prevent the texture region from reaching the pn junction during the process of forming the texture region. In order to reliably prevent the texture region from reaching the pn junction, it is considered to increase the thickness of each semiconductor region 15. However, in a structure in which the thickness of each semiconductor region 15 is large, as described above, the improvement of the spectral sensitivity characteristics may be suppressed.

[0101] Although the manufacturing process of the semiconductor light detecting element 1 includes a process of forming a texture region after forming a plurality of semiconductor regions 15, the thickness TH1 is smaller than the distance D1 in the semiconductor light detecting element 1. Therefore, it is difficult for the semiconductor light detecting element 1 to suppress improvement in spectral sensitivity characteristics.

[0102] When stress acts on the semiconductor substrate 11, carriers not caused by the incidence of light may be generated. Carriers not caused by the incidence of light cause dark current to be generated. Stress is more likely to act on the region 19 than on the region 17, and carriers not caused by the incidence of light are more likely to be generated.

[0103] In the semiconductor light detecting element 1, the thickness TH2 is greater than the thickness TH3. Therefore, in the semiconductor light detecting element 1, compared with a structure in which the thickness TH2 is less than the thickness TH3, carrier recombination that is not caused by the incidence of light is more likely to occur in the region 19. As a result, the semiconductor light detecting element 1 suppresses the generation of dark current.

[0104] In the semiconductor light detecting element 1, the pad electrode 31 is in contact with the region 19 (region 19b). When the pad electrode 31 is in contact with the semiconductor substrate 11, the material (Al) constituting the pad electrode 31 and the material (Si) constituting the semiconductor substrate 11 may alloy to generate an alloy spike in the semiconductor substrate 11. When the alloy spike reaches the pn junction, the alloy spike increases the leakage current.

[0105] In the semiconductor light detecting element 1 , the thickness TH2 is larger than the thickness TH3 . Therefore, in the semiconductor light detecting element 1 , the alloy peak is less likely to reach the pn junction compared to a structure in which the thickness TH2 is equal to or smaller than the thickness TH3 . The semiconductor light detecting element 1 suppresses an increase in leakage current.

[0106] In the semiconductor light detecting element 1, the texture surface TS is located closer to the main surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11. That is, the texture surface TS is located closer to the main surface 11a than the virtual plane VP. In this case, stress is difficult to act on the region 17. Therefore, in the region 17, the generation of carriers not caused by the incidence of light is suppressed. As a result, the semiconductor light detecting element 1 suppresses the generation of dark current.

[0107] In the semiconductor light detecting element 1 , when the textured surface TS is formed in the semiconductor region 15 as described in the above manufacturing process, the distance from the textured surface TS to the pn junction is further reduced. Therefore, the semiconductor light detecting element 1 further improves the spectral sensitivity characteristics in the long wavelength region.

[0108] The semiconductor light detecting element 1 is mounted on the electronic component EC via the bump electrode 35. Therefore, when the semiconductor light detecting element 1 is mounted on the electronic component EC, stress acts on the region 19 (region 19b). The texture surface TS is located closer to the main surface 11a than the virtual plane VP, so even when the semiconductor light detecting element 1 is mounted on the electronic component EC, stress is difficult to act on the region 17. Therefore, in the region 17, the generation of carriers not caused by the incidence of light is suppressed. The semiconductor light detecting element 1 further suppresses the generation of dark current.

[0109] When the bump electrode 35 (or the bump electrode 75) is crushed when the semiconductor light detecting element 1 is mounted on the electronic component EC, the crushed bump electrode 35 (or the bump electrode 75) may physically interfere with a portion other than the bump electrode 35 of the semiconductor light detecting element 1. The portion other than the bump electrode 35 includes, for example, a wiring conductor or a textured surface TS. When the bump electrode 35 (or the bump electrode 75) physically interferes with the wiring conductor, the bump electrode 35 (or the bump electrode 75) and the wiring conductor may be short-circuited. When the bump electrode 35 (or the bump electrode 75) physically interferes with the textured surface TS, the textured surface TS may be physically damaged, resulting in an adverse effect on the spectral sensitivity characteristics in the long wavelength region.

[0110] In the semiconductor light detecting element 1, the texture surface TS is located closer to the main surface 11a than the virtual plane VP. A step difference is formed between the texture surface TS and the surface of the region 19. Therefore, when the semiconductor light detecting element 1 is mounted on the electronic component EC, the crushed bump electrode 35 (or bump electrode 75) is unlikely to interfere with a portion other than the bump electrode 35 of the semiconductor light detecting element 1. The semiconductor light detecting element 1 suppresses the occurrence of a short circuit between the bump electrode 35 (or bump electrode 75) and the wiring conductor, and suppresses the adverse effects on the spectral sensitivity characteristics in the long wavelength region.

[0111] When forming the bump electrode 35, the device for forming the bump electrode 35 may physically interfere with the texture surface TS. When the device for forming the bump electrode 35 physically interferes with the texture surface TS, the texture surface TS may be physically damaged, which may adversely affect the spectral sensitivity characteristics in the long wavelength region.

[0112] In the semiconductor light detecting element 1, the texture surface TS is located closer to the main surface 11a than the virtual plane VP. Therefore, it is difficult for the device forming the bump electrode 35 to physically interfere with the texture surface TS. When the bump electrode 35 is formed in the semiconductor light detecting element 1, the adverse effect on the spectral sensitivity characteristics in the long wavelength region is suppressed.

[0113] In the semiconductor light detecting element 1, the edge region TSa of the texture surface TS is continuous with the surface of the region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. When the texture surface TS is located closer to the main surface 11a than the virtual plane VP, stress is more likely to act on the region 19.

[0114] In the semiconductor light detection element 1, the stress acting on the region 19 is easily dispersed compared to the structure in which the edge region TSa is parallel to the thickness direction of the semiconductor substrate. Therefore, even when stress acts on the region 19, the concentration of stress on the region 19 is suppressed. The semiconductor light detection element 1 suppresses the generation of carriers that are not caused by the incidence of light. As a result, the semiconductor light detection element 1 further suppresses the generation of dark current.

[0115] In the semiconductor light detecting element 1 , the region 19 (regions 19 a and 19 b ) does not have the textured surface TS. In the semiconductor light detecting element 1 , it is easier to form the pad electrode 31 in the region 19 (region 19 b ) than in a structure where the region 19 has the textured surface TS.

[0116] The light reaching the surface of the textured surface TS is reflected or scattered on the textured surface TS as described above. Compared with the light reflected on the flat surface, the light reflected or scattered on the textured surface TS travels in various directions intersecting the thickness direction of the semiconductor substrate 11. Therefore, the light reflected or diffused on the textured surface TS may enter adjacent pixels, causing crosstalk between pixels. Crosstalk is a major cause of noise.

[0117] In the semiconductor light detecting element 1, the texture surface TS is provided in each semiconductor region 15. The texture surface TS is not provided in the region other than the semiconductor region 15 of the main surface 11b. The structure in which the texture surface TS is provided in each semiconductor region 15 limits the occurrence of crosstalk compared to the structure in which the texture surface TS is provided in the entire main surface 11b. Therefore, the semiconductor light detecting element 1 suppresses the occurrence of crosstalk.

[0118] In the semiconductor light detecting element 1, the pad electrode 31 has an electrode region 31a and an electrode region 31b. The electrode region 31a is arranged in the region 19 (region 19b). The electrode region 31b is arranged in the region 17 in such a manner that the insulating film 23 is located between the region 17. The electrode region 31a and the electrode region 31b are continuous. That is, the pad electrode 31 is arranged in such a manner that it covers the region 19b and the region 17. In this structure, the area of ​​the pad electrode 31 is larger than that of the structure in which the pad electrode 31 is arranged only in the region 19b. The UBM 33 and the bump electrode 35 are arranged on the pad electrode 31 with a large area. Therefore, the semiconductor light detecting element 1 improves the reliability and stability of the electrical connection between the semiconductor region 15 (region 19) and the bump electrode 35.

[0119] The structure with a large area of ​​the texture surface TS (region 17) improves the spectral sensitivity characteristics in the long wavelength region compared to the structure with a small area of ​​the texture surface TS (region 17). Therefore, in order to improve the spectral sensitivity characteristics in the long wavelength region, it is required that the area of ​​region 17 is as large as possible and the area of ​​region 19 (region 19b) is as small as possible.

[0120] The pad electrode 31 contacts the region 19b through the contact hole H1. In order to easily form the contact hole H1, the contact hole H1 is formed in the region of the insulating film 23 located on the region 19b. The surface of the region 19b is flat, so the contact hole H1 is easily formed in the insulating film 23. In the case where the pad electrode 31 is formed offset from the contact hole H1, the region 19b is exposed through the contact hole H1. In this case, there is a possibility that the withstand voltage characteristics deteriorate and the reliability decreases. Therefore, the area of ​​the pad electrode 31 is set in consideration of the accuracy of the formation position of the contact hole H1 and the accuracy of the formation position of the pad electrode 31. As a result, the area of ​​the pad electrode 31 has to be increased.

[0121] In the structure in which the pad electrode 31 does not have the electrode region 31b, the pad electrode 31 and the region 17 do not overlap when viewed from a direction perpendicular to the main surface 11b. In this structure, in order to ensure the area of ​​the pad electrode 31, the area of ​​the region 19b needs to be expanded, and the area of ​​the region 17 needs to be reduced. Therefore, the structure in which the pad electrode 31 does not have the electrode region 31b makes it difficult to improve the spectral sensitivity characteristics in the long wavelength region.

[0122] In the semiconductor light detecting element 1, the pad electrode 31 has an electrode region 31b. That is, the pad electrode 31 and at least a portion of the region 17 overlap each other when viewed from a direction orthogonal to the main surface 11b. Therefore, even when the area of ​​the pad electrode 31 is ensured, the semiconductor light detecting element 1 improves the spectral sensitivity characteristics in the long wavelength region.

[0123] In the semiconductor light detecting element 1, the insulating film 25 covers the periphery of the pad electrode 31. Therefore, the insulating film 25 suppresses peeling of the pad electrode 31. The insulating film 25 suppresses the material components of the bump electrode 35 from invading from the interface between the pad electrode 31 and the insulating film 23. The insulating film 25 suppresses the occurrence of leakage current and short circuit.

[0124] In the semiconductor light detecting element 1, the insulating film 25 covers the region corresponding to the region 17 in the insulating film 23. The laminated film composed of the insulating film 23 and the insulating film 25 covers the entire texture surface TS. By setting the thickness of the insulating film 23 and the thickness of the insulating film 25 to desired values, the laminated film (insulating films 23, 25) can constitute a high reflection film. In the structure in which the laminated film (insulating films 23, 25) constitutes a high reflection film, the spectral sensitivity characteristics in the long wavelength region are further improved.

[0125] The insulating film 23 is an oxide film, and the insulating film 25 is a nitride film. Therefore, the laminated film (insulating films 23 and 25) can easily constitute a high reflection film.

[0126] When the insulating film 23 is a silicon thermal oxide film, the unevenness of the texture surface TS becomes smooth by heat treatment in the process of forming the insulating film 23. When the unevenness of the texture surface TS is smooth, the formation process of the metal wiring including the pad electrode 31 is easy.

[0127] Next, refer to Fig.12 and Fig.13 , a structure of a semiconductor light detecting element 1 according to a first modified example of the above-described embodiment will be described. Fig.12 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a first modification. Fig.13 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a first modification. Fig.13 In the figure, the insulating films 23 and 25 are omitted. Fig.13 In order to easily understand the area as the texture surface TS, the area as the texture surface TS is marked with hatching. The first modification example is roughly similar to or the same as the above-mentioned embodiment. However, the first modification example is different from the above-mentioned embodiment in terms of the structure of the semiconductor substrate 11. The following mainly describes the differences between the above-mentioned embodiment and the first modification example.

[0128] The semiconductor substrate 11 has a semiconductor region 20 of the first conductivity type. The semiconductor substrate 11 has the semiconductor region 20 on the main surface 11b side. The semiconductor substrate 11 has the semiconductor region 20 provided on the main surface 11b side. The semiconductor region 20 has a high impurity concentration. The impurity concentration of the semiconductor region 20 is, for example, 1×10 18 cm -3 . The thickness of the semiconductor region 20 is, for example, 1.5 μm. The semiconductor region 20 has a lattice shape when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 20 is located between semiconductor regions 15 adjacent to each other in the first direction, and is located between semiconductor regions 15 adjacent to each other in the second direction, when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 20 is continuous with the semiconductor region 14. The semiconductor region 20 acts as a channel blocking layer to suppress the expansion of the depletion layer between pixels. The semiconductor region 20 can also be divided into a plurality of regions when viewed from a direction perpendicular to the main surface 11b.

[0129] The semiconductor light detecting element 1 includes a plurality of pad electrodes 41 , a plurality of UBMs (under-bump metals) 43 , and a plurality of bump electrodes 45 .

[0130] Each pad electrode 41 is arranged in the semiconductor region 20. Each pad electrode 41 is arranged at a predetermined interval when viewed from a direction perpendicular to the main surface 11b. The pad electrode 41 is formed on the insulating film 23. The pad electrode 41 is connected to the semiconductor region 20 through a contact hole formed in the insulating film 23. The pad electrode 41 is in contact with the semiconductor region 20 and the insulating film 23. The pad electrode 41 is directly arranged on the semiconductor region 20. The pad electrode 41 is in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrode 41. The pad electrode 41 is made of a conductive material. The pad electrode 41 is made of aluminum, for example. In this case, the pad electrode 41 is formed by sputtering or evaporation.

[0131] The UBM 43 is arranged in the semiconductor region 20. The UBM 43 is formed on the semiconductor region 20 and on the insulating film 25. The UBM 43 is connected to the pad electrode 41 through a contact hole formed in the insulating film 25. The UBM 43 is in contact with the pad electrode 41. The UBM 43 is in contact with the insulating film 25. The UBM 43 is made of a material that is excellent in electrical and physical connection with the bump electrode 45. The UBM 43 is made of, for example, a laminated body including a layer made of titanium and a layer made of platinum. The UBM 43 is formed, for example, by a laminated evaporation method.

[0132] The bump electrode 45 is arranged on the semiconductor region 20. The bump electrode 45 is formed on the UBM 43. The bump electrode 45 is in contact with the UBM 43. The UBM 43 is located between the pad electrode 41 and the bump electrode 45. The bump electrode 45 is indirectly arranged on the semiconductor region 20. The bump electrode 45 is indirectly arranged on the pad electrode 41. The bump electrode 45 is electrically connected to the semiconductor region 20 through the UBM 43 and the pad electrode 41. The bump electrode 45 is made of a solder material. The bump electrode 45 is made of, for example, indium. The bump electrode 45 is formed, for example, by a vapor deposition method.

[0133] Next, refer to Fig.14 The structure of an electronic component device ED including the semiconductor light detecting element 1 according to the first modification example will be described. Fig.14 It is a diagram showing a cross-sectional structure of an electronic component device including a back-illuminated semiconductor light detecting element according to a first modification.

[0134] The electronic component device ED includes a semiconductor light detecting element 1 according to the first modified example and an electronic component EC. The electronic component EC includes a plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75. The plurality of pad electrodes 71, the plurality of UBMs 73, and the plurality of bump electrodes 75 are arranged at positions corresponding to the plurality of bump electrodes 35, 45 included in the semiconductor light detecting element 1. The semiconductor light detecting element 1 is mounted on the electronic component EC by bonding the corresponding bump electrodes 35, 45 and the bump electrodes 75.

[0135] Next, refer to Fig.15 and Fig.16 , a structure of a semiconductor light detecting element 1 according to a second modified example of the above-described embodiment will be described. Fig.15 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a second modification. Fig.16 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a second modification. Fig.16 In the figure, the insulating films 23 and 25 are omitted. Fig.16 In order to easily understand the area as the texture surface TS, the area as the texture surface TS is marked with hatching. The second modification is roughly similar to or the same as the above-mentioned embodiment. However, the second modification is different from the above-mentioned embodiment in terms of the structure of the semiconductor substrate 11. The following mainly describes the differences between the above-mentioned embodiment and the second modification.

[0136] A trench TR is formed in the semiconductor substrate 11 in such a manner as to separate the pixels from each other. The trench TR opens in the main surface 11b. The trench TR is formed in such a manner as to divide the semiconductor region 20 as viewed from a direction perpendicular to the main surface 11b. The trench TR is formed in a lattice shape as viewed from a direction perpendicular to the main surface 11b so as to pass between the semiconductor regions 15 adjacent in the first direction and between the semiconductor regions 15 adjacent in the second direction. The width of the opening of the trench TR is, for example, 5 μm. The depth of the trench TR is greater than the thickness TH2. The depth of the trench TR is, for example, 50 μm. The trench TR is formed, for example, by reactive ion etching (RIE). The trench TR may also be formed discontinuously as viewed from a direction perpendicular to the main surface 11b. In this case, for example, a plurality of trenches extending in the first direction as viewed from a direction perpendicular to the main surface 11b and a plurality of trenches extending in the second direction as viewed from a direction perpendicular to the main surface 11b are formed in the semiconductor substrate 11.

[0137] An insulating film 23 is formed on the inner surface (specifically, the side surface and the bottom surface) of the trench TR. The insulating film 23 reaches the trench TR from the main surface 11b. An insulating film 25 is formed on the insulating film 23 formed on the inner surface of the trench TR. The insulating film 25 reaches the trench TR from the insulating film 23 located on the main surface 11b. A buried layer may also be arranged in the trench TR. The buried layer is composed of, for example, a metal. In this case, the buried layer (metal layer) is formed, for example, by CVD or electrolytic plating.

[0138] The trench TR prevents light reflected or diffused on the texture surface TS from entering adjacent pixels. Therefore, the semiconductor light detection element 1 according to the second modification further prevents the occurrence of crosstalk. The trench TR also prevents carriers from migrating between adjacent pixels.

[0139] The semiconductor light detecting element 1 according to the second modification may also be Fig.11 In this case, the electronic component device ED includes the semiconductor light detecting element 1 according to the second modification and the electronic component EC.

[0140] Next, refer to Fig.17 and Fig.18 The structure of the semiconductor light detecting element 1 according to the third modified example of the above-mentioned embodiment will be described. Fig.17 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a third modification. Fig.18 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a third modification. Fig.18 In the figure, the insulating films 23 and 25 are omitted. Fig.18 In order to easily understand the area as the texture surface TS, the area as the texture surface TS is marked with hatching. The third modification example is roughly similar to or the same as the above-mentioned embodiment. However, the third modification example is different from the above-mentioned embodiment in terms of the structure of the pad electrode 31. The following mainly describes the differences between the above-mentioned embodiment and the third modification example.

[0141] The pad electrode 31 is configured to cover the entire semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b is indirectly configured on the entire region corresponding to the region 17 in the insulating film 23. The electrode region 31b overlaps the entire edge region TSa continuous with the region 19 (regions 19a, 19b) when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 overlaps the entire boundary between the region 17 and the region 19 when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 is indirectly configured on the entire semiconductor region 15.

[0142] When the pad electrode 31 is made of Al, the pad electrode 31 may absorb light (for example, near infrared light) reaching the pad electrode 31. The absorption of light in the pad electrode 31 reduces the spectral sensitivity characteristics in the long wavelength region.

[0143] In the semiconductor light detecting element 1, the insulating films 23 and 25 disposed on the textured surface TS reflect or diffuse the light reaching the insulating films 23 and 25. Therefore, the light passing through the insulating films 23 and 25 is reduced. As a result, the semiconductor light detecting element 1 suppresses the reduction of the spectral sensitivity characteristics in the long wavelength region.

[0144] Next, refer to Fig.19 and Fig. 20 The structures of the semiconductor light detecting elements 1 according to the fourth and fifth modified examples of the above-described embodiment will be described. Fig.19 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a fourth modification. Fig. 20 It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a fifth modification. Fig.19 and Fig. 20 In the figure, the insulating films 23 and 25 are omitted. Fig.19 and Fig. 20 In order to easily understand the region as the texture surface TS, the region as the texture surface TS is shaded. The fourth and fifth variations are roughly similar to or the same as the above-mentioned embodiment. However, the fourth variation is different from the above-mentioned embodiment in terms of the structure of the semiconductor region 15, and the fifth variation is different from the above-mentioned embodiment in terms of the structure of the semiconductor region 15 and the pad electrode 31. The following mainly describes the differences between the above-mentioned embodiment and the fourth and fifth variations.

[0145] Area 19b Fig.19 As shown, the region 19b is located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11. The region 19b is separated from the region 19a. The region 17 (texture surface TS) is located between the region 19a and the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b overlaps the entire edge region TSa continuous with the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 overlaps the entire boundary between the region 17 and the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11.

[0146] like Fig. 20 As shown, region 19b is located at the center of semiconductor region 15 as seen from the direction perpendicular to semiconductor substrate 11, similarly to the fourth modification. Pad electrode 31 is configured to cover the entire semiconductor region 15 as seen from the direction perpendicular to semiconductor substrate 11, similarly to the third modification. Electrode region 31b overlaps with the entire edge region TSa continuous with region 19a and the entire edge region TSa continuous with region 19b as seen from the direction perpendicular to semiconductor substrate 11. Pad electrode 31 overlaps with the entire boundary between region 17 and region 19a and the entire boundary between region 17 and region 19b as seen from the direction perpendicular to semiconductor substrate 11.

[0147] In the structure where the region 19b is located in the center of the semiconductor region 15, the carrier movement distance is shorter and the time from light incidence to output signal is shorter than that in the structure where the region 19b is located in one corner of the semiconductor region 15. Therefore, each semiconductor light detecting element 1 of the fourth and fifth modified examples improves the response speed.

[0148] Next, refer to Fig.21 The structure of the semiconductor light detecting element 1 according to the sixth modification of the above-mentioned embodiment will be described. Fig.21It is a plan view showing the structure of a back-illuminated semiconductor light detecting element according to a sixth modification. Fig.21 In the figure, the insulating films 23 and 25 are omitted. Fig.21 In order to easily understand the area as the texture surface TS, the area as the texture surface TS is marked with hatching. The sixth modification is roughly similar to or the same as the above-mentioned embodiment. However, the sixth modification is different from the above-mentioned embodiment in terms of the structure of the semiconductor region 15 and the pad electrode 31. The following mainly describes the differences between the above-mentioned embodiment and the sixth modification.

[0149] Region 17 and region 19b are adjacent in the first direction when viewed from a direction perpendicular to the semiconductor substrate 11. Region 17 and regions 19a and 19b are rectangular when viewed from a direction perpendicular to the semiconductor substrate 11. Region 19b is located outside region 19a. One side of the edge constituting region 19a is in contact with one side of the edge constituting region 19b. When viewed from a direction perpendicular to the semiconductor substrate 11, the area of ​​region 19b is smaller than the area of ​​region 19a. The pad electrode 31 is not located on region 17 (texture surface TS). That is, the pad electrode 31 does not have an electrode region 31b. When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 does not overlap with the texture surface TS. In the sixth variant, the semiconductor substrate 11 has the semiconductor region 20, but the semiconductor substrate 11 may not have the semiconductor region 20. Region 17 and region 19b may also be adjacent in the second direction when viewed from a direction perpendicular to the semiconductor substrate 11.

[0150] Next, refer to Fig. 22 and Fig.23 The structure of the semiconductor light detecting element 1 according to the seventh modification of the above-mentioned embodiment will be described. Fig. 22 It is a diagram showing a cross-sectional structure of a back-illuminated semiconductor light detecting element according to a seventh modification. Fig.23 This is a diagram showing the cross-sectional structure of one pixel. Fig.23 In the figure, hatching lines indicating cross sections are omitted. The seventh modification is roughly similar to or the same as the above-mentioned embodiment. However, the seventh modification is different from the above-mentioned embodiment in terms of the structure of the semiconductor region 15. The following mainly describes the differences between the above-mentioned embodiment and the seventh modification.

[0151] Region 17 of semiconductor region 15 is formed along texture surface TS. The boundary surface between region 17 and semiconductor region 13 has a concavo-convex shape corresponding to the concavo-convex shape of texture surface TS. The boundary surface between region 17 and semiconductor region 13 has a concavo-convex shape that is, for example, gentler than the concavo-convex shape of texture surface TS. Region 19 of semiconductor region 15 is formed along main surface 11b. The thickness TH2 of region 19 in the thickness direction of semiconductor substrate 11 is equal to the thickness TH3 of region 17 in the thickness direction of semiconductor substrate 11. As described above, region 17 is formed along texture surface TS. Therefore, thickness TH3 is difficult to change in accordance with the concavo-convex of texture surface TS. In the seventh variant, thickness TH3 is, for example, substantially constant. The thickness TH1 of region 17 at the deepest position of the depression of texture surface TS is equal to thickness TH2 and thickness TH3. Thickness TH1, thickness TH2 and thickness TH3 are, for example, 0.5 μm.

[0152] The semiconductor substrate 11 may also include a semiconductor region 20 as in the first modification. A trench TR may also be formed in the semiconductor substrate 11 as in the second modification. The pad electrode 31 may also be arranged to cover the entire semiconductor region 15 as in the third modification. The region 19b may also be located at the center of the semiconductor region 15 as viewed in a direction perpendicular to the semiconductor substrate 11 as in the fourth and fifth modifications. The region 17 and the region 19b may also be adjacent in the first direction or the second direction as viewed in a direction perpendicular to the semiconductor substrate 11 as in the sixth modification.

[0153] Next, refer to Fig.24 and Fig.25 An example of a manufacturing process of the semiconductor light detecting element 1 according to the seventh modification example will be described. Fig.24 and Fig.25 It is a schematic diagram showing an example of a manufacturing process of a back-illuminated semiconductor light detecting element according to the seventh modification.

[0154] Fig.24 and Fig.25 In the figure, hatching indicating the cross section is omitted. The following mainly describes the difference between the manufacturing process in the above-mentioned embodiment and the manufacturing process in the seventh modification.

[0155] A semiconductor substrate 11 is prepared in which an oxide film 51 is formed on the main surface 11a and an oxide film 53 is formed on the main surface 11b (see Fig. 9 (a)). That is, a semiconductor substrate 11 having a semiconductor region 13 is prepared. The semiconductor substrate 11 has a plurality of predetermined regions PR in which a plurality of semiconductor regions 15 are formed on the main surface 11b side. Fig.24 and Fig.25 In FIG, only one predetermined region PR is shown.

[0156] like Fig.24 As shown in (a), a plurality of semiconductor regions 151 and a semiconductor region 16 are formed on a semiconductor substrate 11. Each semiconductor region 151 is formed in a corresponding predetermined region PR among a plurality of predetermined regions PR. The semiconductor region 151 is formed by the same process as the formation process of the semiconductor region 15 in the above-mentioned embodiment. The semiconductor region 151 is formed by p-type impurities diffused at a high concentration from the main surface 11b. The semiconductor region 16 is formed by the same process as the formation process of the semiconductor region 16 in the above-mentioned embodiment.

[0157] like Fig.24 As shown in (b) of FIG. 1 , the contact hole H1 , the silicon nitride film 57 , and the opening 59 are formed by the same process as the respective formation processes in the above-mentioned embodiment.

[0158] like Fig.24 As shown in (c), the texture surface TS is formed in the region of the semiconductor region 151 exposed from the opening 59 by the same process as each formation process in the above-mentioned embodiment. That is, a plurality of texture regions are formed on the surface of the main surface 11b included in the above-mentioned plurality of predetermined regions PR. The texture region is a region whose surface is the texture surface TS. By forming the texture surface TS, the region of the semiconductor region 151 exposed from the opening 59 is removed. The region of the semiconductor region 151 exposed from the opening 59 does not necessarily need to be completely removed, and a portion of the region exposed from the opening 59 may remain. Fig.24 In the drawings after (c), the cross-hatched area is the area where the textured surface TS is formed.

[0159] like Fig.25 As shown in (a), a plurality of semiconductor regions 152 are formed on the semiconductor substrate 11. The semiconductor region 152 is formed along the texture surface TS. That is, the semiconductor region 152 is formed along the surface shape of the texture region. Each semiconductor region 152 is formed in a corresponding predetermined region PR among a plurality of predetermined regions PR. The semiconductor region 152 is formed by the same process as the formation process of the semiconductor region 15 in the above-mentioned embodiment. The semiconductor region 152 is formed by p-type impurities diffused from the main surface 11b at a high concentration. The p-type impurities also diffuse in a direction orthogonal to the thickness direction of the semiconductor substrate 11. Therefore, the semiconductor region 152 is formed continuously with the semiconductor region 151. The semiconductor region 152 and the semiconductor region 151 are integrated to constitute the semiconductor region 15. The semiconductor region 152 constitutes the region 17. The semiconductor region 151 constitutes the region 19. That is, through this process, a plurality of semiconductor regions 15 are formed on the semiconductor substrate 11. By the high-temperature heat treatment for forming the semiconductor region 152, the oxide film 61 is formed on the texture surface TS (refer to Fig.25 (b) The oxide films 53 and 61 constitute the insulating film 23.

[0160] like Fig.25 As shown in (b) of FIG. 5 , the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (oxide films 53 and 61). By removing the silicon nitride film 57, the semiconductor region 15 (semiconductor region 151) is exposed through the contact hole H1. Fig.25 As shown in (c), the pad electrode 31, the insulating film 25, the UBM 33 and the bump electrode 35 are formed by the same process as the formation process in the above-mentioned embodiment. Through these processes, the semiconductor light detecting element 1 according to the seventh modification is obtained. The oxide film 51 constitutes the insulating film 21.

[0161] The impurity concentration of the semiconductor region 152 is, for example, Fig.26 That is, the impurity concentration of the semiconductor region 152 changes with respect to the distance from the texture surface TS in the thickness direction of the semiconductor substrate 11, for example. Fig.26 It is a line graph showing the distribution of impurity concentration. Fig.26 In FIG. 1 , for convenience of illustration, the texture surface TS and the interface between the semiconductor region 152 and the semiconductor region 13 are shown as being flat. However, in reality, the texture surface TS and the interface between the semiconductor region 152 and the semiconductor region 13 are minutely concave and convex as described above.

[0162] The impurity concentration of the semiconductor region 152 also remains high until a predetermined depth position, and gradually decreases as it moves from the predetermined depth position toward the main surface 11a. The semiconductor region 152 has a region R1 and a region R2 according to the distribution of the impurity concentration. That is, in the seventh modification, the region 17 has a region R1 and a region R2. In the semiconductor region 152 (region 17), the proportion occupied by the region R2 is greater than the proportion occupied by the region R1. In the seventh modification, the deepest position of the depression of the texture surface TS is separated from the region where the impurity concentration of the semiconductor region 15 begins to decrease by the thickness of the region R1. In the seventh modification, the predetermined depth is, for example, about 0.45 μm.

[0163] In the manufacturing process of the seventh modification, after the texture region is formed on the main surface 11b, a plurality of semiconductor regions 15 (a plurality of semiconductor regions 152) are formed in a plurality of predetermined regions PR. In the process of forming the texture region (texture surface TS) after forming the plurality of semiconductor regions 15, in order to reliably prevent the texture region from reaching the pn junction, the thickness of each semiconductor region 15 has to be increased. Therefore, in the process of forming the plurality of semiconductor regions 15 after forming the texture region, the thickness of each semiconductor region 15 can be reduced compared to the process of forming the texture region after forming the plurality of semiconductor regions 15. As a result, the semiconductor light detecting element 1 involved in the seventh modification can further improve the spectral sensitivity characteristics in the long wavelength region.

[0164] In the manufacturing process of the seventh variant, the semiconductor region 152 (region 17) is formed along the surface shape of the texture region. In this case, the thickness of the semiconductor region 152 (region 17) can be further reduced. Therefore, the semiconductor light detection element 1 can reliably further improve the spectral sensitivity characteristics in the long wavelength region.

[0165] In the manufacturing process of the seventh modification, the semiconductor region 152 (region 17) is formed by adding p-type impurities into the predetermined region PR. In this case, the semiconductor region 152 is easily formed by using a conventional method.

[0166] As mentioned above, although embodiment and modification of this invention were described, this invention is not necessarily limited to the said embodiment and modification, Various changes are possible within the range which does not deviate from the summary.

[0167] The texture surface TS may not be located at a position closer to the main surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11. That is, the texture surface TS may not be located at a position closer to the main surface 11a than the virtual plane VP. For example, the top of the texture surface TS may be at the same position as the virtual plane VP. When the texture surface TS is located closer to the main surface 11a than the virtual plane VP, the semiconductor light detection element 1 suppresses the generation of dark current as described above.

[0168] The edge region TSa may not be continuous with the surface of the region 19. For example, the edge region TSa may be separated from the step difference formed between the region 17 and the region 19. For example, the region without the texture surface TS may be located between the step difference formed between the region 17 and the region 19 and the edge region TSa. In this case, for example, the entire edge region TSa may be surrounded by the region without the texture surface TS when viewed from a direction orthogonal to the semiconductor substrate 11. For example, the region 17 may also have a region without the texture surface TS.

[0169] The peripheral region TSa may be substantially parallel to the thickness direction of the semiconductor substrate. When the peripheral region TSa is inclined with respect to the thickness direction of the semiconductor substrate 11 , as described above, the semiconductor light detection element 1 further suppresses the generation of dark current.

[0170] The bump electrode 35 may be directly disposed on the pad electrode 31 . In this case, the semiconductor light detecting element 1 does not include the UBM 33 .

[0171] This specification discloses the following supplementary notes.

[0172] (Note 1)

[0173] A back-incident semiconductor light detection element, wherein:

[0174] A semiconductor substrate having a first main surface and a second main surface facing each other is provided.

[0175] The semiconductor substrate comprises: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions of a second conductivity type, which are provided on the second main surface side and form a pn junction with the first semiconductor region.

[0176] The plurality of second semiconductor regions respectively include: a first region having a textured surface; and a second region,

[0177] The thickness of the first region at the deepest position of the depression of the texture surface is smaller than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate.

[0178] The first main surface is a light incident surface on the semiconductor substrate.

[0179] (Note 2)

[0180] A back-illuminated semiconductor light detecting element as described in Supplementary Note 1, wherein:

[0181] The thickness of the second region in the thickness direction of the semiconductor substrate is greater than the thickness of the first region in the thickness direction of the semiconductor substrate.

[0182] (Note 3)

[0183] A back-illuminated semiconductor light detecting element as described in Supplementary Note 2, wherein:

[0184] An electrode is further provided which is arranged in the second region and in contact with the second region.

[0185] (Note 4)

[0186] A back-illuminated semiconductor light detecting element as described in any one of Supplementary Notes 1 to 3, wherein:

[0187] The textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate.

[0188] (Note 5)

[0189] A back-illuminated semiconductor light detecting element as described in Supplementary Note 4, wherein:

[0190] An edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate.

[0191] (Note 6)

[0192] A back-illuminated semiconductor light detecting element as described in any one of Supplementary Notes 1 to 5, wherein:

[0193] The second region does not have a textured surface.

[0194] In the embodiment of Supplementary Note 1, the second region may have a surface with projections and depressions formed thereon. The second region may have, for example, a textured surface. The second region may have, for example, a surface with projections and depressions of a different form from the textured surface.

[0195] When the second region has a surface with projections and depressions formed thereon, the position of the surface of the second region may be defined as follows.

[0196] The position of the surface of the second region may also be the deepest position of the deepest depression among all the depressions. The position of the surface of the second region may also be the deepest position of the shallowest depression among all the depressions. The position of the surface of the second region may also be the deepest position of any one of all the depressions. The position of the surface of the second region may also be the average position of the deepest positions of all the depressions.

[0197] The position of the surface of the second region may also be specified by the highest vertex among all the vertexes. The position of the surface of the second region may also be specified by the lowest vertex among all the vertexes. The position of the surface of the second region may also be specified by any vertex among all the vertexes. The position of the surface of the second region may also be the average height position of all the vertexes.

[0198] When the second region has a surface with concavoconvex shapes, the thickness of the second region varies in accordance with the concavoconvex shapes of the surface. In this case, the thickness of the second region may be either the maximum thickness of the second region or the minimum thickness of the second region. The thickness of the second region may also be the average thickness of the second region.

[0199] The deepest position of the depression of the texture surface in the first region and the thickness of the first region may also be specified in the same manner as in the above-described embodiment.

[0200] In the embodiment of Supplement 1, the second region may also have a surface with concavoconvex portions and a flat surface. In this case, the position of the surface of the second region may be defined by the surface with concavoconvex portions or by the flat surface. The position of the surface of the second region may also be the average height position of the surface with concavoconvex portions and the flat surface.

[0201] This specification also discloses the following supplementary notes.

[0202] (Note 7)

[0203] A back-incident semiconductor light detection element, wherein:

[0204] A semiconductor substrate having a first main surface and a second main surface facing each other is provided.

[0205] The semiconductor substrate comprises: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions of a second conductivity type, which are provided on the second main surface side and form a pn junction with the first semiconductor region.

[0206] The plurality of second semiconductor regions each have a textured surface.

[0207] The thickness of the second semiconductor region at the deepest position of the depression of the texture surface is smaller than the distance between the top of the texture surface and the deepest position in the thickness direction of the semiconductor substrate.

[0208] The first main surface is a light incident surface on the semiconductor substrate.

[0209] In the embodiment of Supplementary Note 7, the deepest position may be defined as follows.

[0210] The deepest position may also be the deepest position of the deepest depression among all the depressions. The deepest position may also be the deepest position of the shallowest depression among all the depressions. The deepest position may also be the deepest position of any depression among all the depressions. The deepest position may also be the average position of the deepest positions of all the depressions.

[0211] In the embodiment of Supplementary Note 7, the top of the texture surface may also be defined as follows.

[0212] The top of the texture surface may also be the highest top among all the tops. The top of the texture surface may also be the lowest top among all the tops. The top of the texture surface may also be any top among all the tops. The top of the texture surface may also be the average position of all the tops.

[0213] In the embodiment of Supplementary Note 7, the distance between the top and the deepest position of the texture surface in the thickness direction of the semiconductor substrate may be defined as follows.

[0214] The above distance may be the maximum value of the height difference of the concavoconvex or the minimum value of the height difference of the concavoconvex. The above distance may also be the height difference of the concavoconvex at any position on the texture surface. The above distance may also be the average value of the height difference of the concavoconvex.

[0215] In the embodiment of Supplementary Note 7, the entire surface of each second semiconductor region may be a textured surface.

[0216] Industrial Applicability

[0217] The present invention can be used in a back-illuminated semiconductor light detecting element.

[0218] Explanation of symbols

[0219] 1…back-illuminated semiconductor light detecting element, 11…semiconductor substrate, 11a, 11b…main surface, 13, 15…semiconductor region, 17…region with a textured surface, 19…region without a textured surface, 31…pad electrode, D1…the distance between the surface of the region without a textured surface and the deepest position of the depression on the textured surface, TH1…the thickness of the textured surface at the deepest position of the depression, TH2…the thickness of the region without a textured surface in the thickness direction of the semiconductor substrate, TH3…the thickness of the region with a textured surface in the thickness direction of the semiconductor substrate, TS…texture surface, TSa…edge region of the textured surface.

Claims

1. A back-incident semiconductor light detection element, characterized in that: A semiconductor substrate having a first main surface and a second main surface facing each other is provided. The semiconductor substrate comprises: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions of a second conductivity type, which are provided on the second main surface side and form a pn junction with the first semiconductor region. The plurality of second semiconductor regions respectively include: a first region having a textured surface; and the second region, The thickness of the first region at the deepest position of the depression of the texture surface is smaller than the depth at the highest top position among the tops of the texture surface in the thickness direction of the semiconductor substrate. The first main surface is a light incident surface on the semiconductor substrate.

2. The back-illuminated semiconductor light detecting element according to claim 1, wherein: The thickness of the second region in the thickness direction of the semiconductor substrate is greater than the thickness of the first region in the thickness direction of the semiconductor substrate.

3. The back-illuminated semiconductor light detecting element according to claim 2, wherein: An electrode is further provided which is arranged in the second region and in contact with the second region.

4. The back-illuminated semiconductor light detecting element according to any one of claims 1 to 3, wherein: The thickness of the second region in the thickness direction of the semiconductor substrate is larger than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate.

5. The back-illuminated semiconductor light detecting element according to claim 1, wherein: The boundary surface between the first region and the first semiconductor region has a concave-convex shape corresponding to the texture surface, The thickness of the second region in the thickness direction of the semiconductor substrate is equal to the thickness of the first region in the thickness direction of the semiconductor substrate.

6. The back-illuminated semiconductor light detecting element according to any one of claims 1 to 5, wherein: An edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate.

7. The back-illuminated semiconductor light detecting element according to any one of claims 1 to 6, wherein: The thickness of the first region at the deepest position of the recess of the textured surface is smaller than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate.

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