Solar cell and method for manufacturing the same
By depositing tunneling oxide layer and polysilicon layer on the front of the silicon wafer of the solar cell, and performing high-temperature annealing, wet etching, boron diffusion and fleece making, the film layer defects and low performance caused by traditional preparation methods are solved, efficient passivation and contact performance improvement are achieved, and the conversion efficiency of solar cells is significantly improved.
Patent Information
- Application Number
- CN202411720606.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-08
AI Technical Summary
Traditional solar cell preparation methods lead to film defects and damage, reducing passivation effect and contact performance, and limiting the conversion efficiency of TOPCon batteries.
By depositing the tunnel oxide layer and polysilicon layer on the front of the silicon wafer in sequence, performing high-temperature annealing, wet etching, boron diffusion and velvet making steps, the film layer structure is optimized and the passivation and contact performance are improved.
It effectively improves the open circuit voltage, filling factor and conversion efficiency of solar cells, optimizes the film structure, and enhances passivation and contact performance.
Smart Images
Figure CN119789564A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art
[0002] Solar cells are devices that convert light into electrical energy through the photovoltaic effect. As a clean, safe and convenient renewable energy source, they have been widely used. Tunneling oxide passivation contact (TOPCon) technology is the new solar cell technology with the highest production capacity. It achieves chemical passivation and field effect passivation through the stacking of tunneling oxide layers and doped polysilicon layers.
[0003] However, traditional solar cell preparation methods usually use a method combining low-pressure chemical vapor deposition (LPCVD) with non-in-situ diffusion or a method combining plasma chemical vapor deposition (PECVD) with high-temperature annealing to prepare a tunneling oxide layer and a doped polysilicon layer on the velvet surface of a silicon wafer. However, traditional preparation methods can cause defects and damage to the film layer, reduce the passivation effect of the film layer, and reduce the contact performance, thereby affecting the conversion efficiency of the solar cell, thereby limiting the further development and application of TOPCon cells.
[0004] Therefore, there is an urgent need for a preparation method that can improve the passivation performance and contact performance of the front side of a solar cell and improve the cell conversion efficiency. Summary of the invention
[0005] Based on this, it is necessary to provide a solar cell and a method for preparing the same in view of the above problems. The method for preparing the solar cell provided by the present invention can effectively optimize the film structure on the front side of the solar cell, while improving the passivation performance and contact performance, and the prepared solar cell has excellent cell conversion efficiency.
[0006] The present invention provides a method for preparing a solar cell, comprising the following steps:
[0007] S1, double-sided polishing of silicon wafer;
[0008] S2, depositing a front tunneling oxide layer and a polysilicon layer in sequence on the front side of the silicon wafer by low pressure chemical vapor deposition;
[0009] S3, high temperature annealing is performed on the front side of the silicon wafer;
[0010] S4, performing a first wet etching on the front side of the silicon wafer to remove the oxide layer formed on the surface of the polysilicon layer;
[0011] S5, performing boron diffusion on the front side of the silicon wafer to form a boron-doped polysilicon layer from the polysilicon layer;
[0012] S6, performing a second wet etching on the back side of the silicon wafer to remove all layers on the back side of the silicon wafer and corrode part of the silicon wafer;
[0013] S7, performing texturing on the front side of the silicon wafer, removing the borosilicate glass layer on the front side, and forming a texturing surface on the surface of the boron-doped polysilicon layer away from the front tunnel oxide layer;
[0014] S8, preparing a passivation layer and an anti-reflection layer on both sides of the silicon wafer;
[0015] S9. Prepare a positive electrode and a negative electrode.
[0016] In one embodiment, when depositing the front tunnel oxide layer, the temperature is 580° C. to 680° C., the time is 0.2 h to 1 h, and the pressure is 500 Torr to 800 Torr;
[0017] And / or, when depositing the polysilicon layer, the temperature is 550° C. to 700° C., the time is 0.5 h to 2.5 h, and the pressure is 200 Torr to 400 Torr.
[0018] In one embodiment, in the high temperature annealing step, the temperature is 900° C. to 1050° C., and the time is 1 h to 2 h.
[0019] In one of the embodiments, in the high temperature annealing step, the thickness of the formed oxide layer is 15 nm to 18 nm.
[0020] In one embodiment, the first wet etching takes 1 to 5 minutes, and the concentration of HF in the etching solution used is 3% to 5%.
[0021] In one embodiment, in the boron diffusion step, the temperature is 800° C. to 960° C., and the time is 3 h to 4 h.
[0022] In one of the embodiments, the thickness of the front tunneling oxide layer is 3 nm to 6 nm;
[0023] And / or, the thickness of the boron-doped polysilicon layer is 150nm to 350nm;
[0024] And / or, the boron doping concentration of the boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .
[0025] In one of the embodiments, in the second wet etching step, all layers on the back side of the silicon wafer are removed, and the silicon wafer with a thickness of 2 μm to 4 μm is etched.
[0026] In one of the embodiments, after the second wet etching is completed, a back tunneling oxide layer and a phosphorus-doped polysilicon layer are sequentially grown on the back side of the silicon wafer.
[0027] The present invention also provides a solar cell manufactured by the method for manufacturing a solar cell as described above.
[0028] The above-mentioned method for preparing solar cells, on the one hand, effectively promotes the further crystallization of the polysilicon layer and increases the grain size of the polysilicon layer by performing high-temperature annealing in the LPCVD deposition and boron diffusion process, thereby improving the crystal quality of the polysilicon layer, and then effectively improving the contact performance, improving the open circuit voltage and fill factor of the solar cell, and at the same time, it is beneficial to increase the tunnel hole diameter of the front tunneling oxide layer, effectively improve the carrier tunneling effect, and then improve the passivation effect; on the other hand, through the front texturing, the surface of the boron-doped polysilicon layer close to the passivation layer is formed with a velvet surface, which prevents the front tunneling oxide layer from being deposited on the velvet surface of the silicon wafer, thereby improving the passivation performance of the film layer, and ensuring the light absorption efficiency of the front side, thereby improving the conversion efficiency of the solar cell.
[0029] Therefore, the solar cell preparation method provided by the present invention can effectively optimize the film layer structure on the front side of the solar cell, while improving the passivation performance and contact performance, and the prepared solar cell has excellent cell conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 is a schematic structural diagram of a solar cell prepared in one embodiment of the present invention;
[0032] Figure numerals: 1, silicon wafer; 2, front tunneling oxide layer; 3, boron-doped polysilicon layer; 4, passivation layer; 5, anti-reflection layer; 6, positive electrode; 7, negative electrode; 8, back tunneling oxide layer; 9, phosphorus-doped polysilicon layer. DETAILED DESCRIPTION
[0033] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.
[0035] like Figure 1 FIG. 1 is a schematic diagram of a TOPCon solar cell structure prepared in one embodiment of the present invention, and its preparation method comprises the following steps:
[0036] S1, silicon wafer 1 is double-sided polished;
[0037] S2, depositing a front tunneling oxide layer 2 and a polysilicon layer in sequence on the front side of the silicon wafer 1 by low pressure chemical vapor deposition;
[0038] S3, high temperature annealing is performed on the front side of the silicon wafer 1;
[0039] S4, performing a first wet etching on the front side of the silicon wafer 1 to remove the oxide layer formed on the surface of the polysilicon layer;
[0040] S5, performing boron diffusion on the front side of the silicon wafer 1, so that the polysilicon layer forms a boron-doped polysilicon layer 3;
[0041] S6, performing a second wet etching on the back side of the silicon wafer 1 to remove all layers on the back side of the silicon wafer 1 and to etch part of the silicon wafer 1;
[0042] S7, texturing the front side of the silicon wafer 1, removing the borosilicate glass layer on the front side, and forming a textured surface on the surface of the boron-doped polysilicon layer 3 away from the front tunnel oxide layer 2;
[0043] S8, preparing a passivation layer 4 and an anti-reflection layer 5 on both sides of the silicon wafer 1;
[0044] S9, preparing the positive electrode 6 and the negative electrode 7.
[0045] The above-mentioned method for preparing solar cells, on the one hand, effectively promotes the further crystallization of the polysilicon layer and increases the grain size of the polysilicon layer by performing high-temperature annealing in the LPCVD deposition and boron diffusion process, thereby improving the crystal quality of the polysilicon layer, and then effectively improving the contact performance of the boron-doped polysilicon layer 3, improving the open circuit voltage and fill factor of the solar cell, and at the same time, it is beneficial to increase the tunnel hole diameter of the front tunneling oxide layer 2, effectively improve the carrier tunneling effect, and then improve the passivation effect; on the other hand, through the front texturing, the surface of the boron-doped polysilicon layer 3 close to the passivation layer 4 is formed with a velvet surface, avoiding the front tunneling oxide layer 2 from being deposited on the velvet surface of the silicon wafer 1, thereby improving the passivation performance of the film layer, and ensuring the light absorption efficiency of the front side, thereby improving the conversion efficiency of the solar cell.
[0046] Therefore, the solar cell preparation method provided by the present invention can effectively optimize the film layer structure on the front side of the solar cell, while improving the passivation performance and contact performance, and has broad application prospects.
[0047] In one embodiment, in step S1, a trench alkali polishing process is used to perform double-sided polishing on the silicon wafer 1 to remove impurities and damaged layers, so that the width of the tower base is 10 μm to 30 μm.
[0048] In one embodiment, when depositing the front tunneling oxide layer 2, the temperature is 580°C to 680°C, the time is 0.2h to 1h, and the pressure is 500Torr to 800Torr, which is beneficial to further improve the film quality of the front tunneling oxide layer 2, thereby improving its passivation performance, and further improving the conversion efficiency of the solar cell.
[0049] In one embodiment, when depositing the polysilicon layer, the temperature is 550°C to 700°C, the time is 0.5h to 1.5h, and the pressure is 0.1Torr to 5Torr, which is beneficial to further improve the film quality of the polysilicon layer, thereby improving the contact performance of the boron-doped polysilicon layer 3, and further improving the conversion efficiency of the solar cell.
[0050] In one embodiment, in the high temperature annealing step, the temperature is 900°C to 1050°C, and the time is 1h to 2h. The temperature of the high temperature annealing includes but is not limited to any point value among 900°C, 920°C, 930°C, 950°C, 970°C, 990°C, 1000°C, 1020°C, 1030°C, 1040°C, and 1050°C, or a range value between any two of them. The time of the high temperature annealing includes but is not limited to any point value among 1h, 1.1h, 1.2h, 1.5h, 1.6h, 1.8h, 1.9h, and 2h, or a range value between any two of them. The crystallization degree of the polysilicon layer is further improved, and the grain size of the polysilicon layer is further improved, thereby improving the crystal quality of the polysilicon layer, and then effectively improving the contact performance of the boron-doped polysilicon layer 3, and improving the open circuit voltage and fill factor of the solar cell. At the same time, it is beneficial to increase the tunneling hole diameter of the front tunneling oxide layer 2, effectively improve the carrier tunneling effect, and then improve the passivation effect.
[0051] In one embodiment, in the high temperature annealing step, the thickness of the formed oxide layer is 15nm to 18nm, including but not limited to any point value among 15nm, 15.5nm, 16nm, 16.5nm, 17nm, 17.5nm, 18nm or a range between any two of them.
[0052] In order to ensure the complete removal of the oxide layer and improve the passivation performance and contact performance of the solar cell, the first wet etching time is 1 min to 5 min, and the HF concentration in the etching solution used is 3% to 5%.
[0053] In one embodiment, in the boron diffusion step, the temperature is 800°C to 960°C and the time is 3h to 4h, which is beneficial to improving the contact performance of the boron-doped polysilicon layer 3, and at the same time is beneficial to reducing the recombination formed by damage to the silicon wafer 1 caused by the diffusion of boron elements into the silicon wafer 1, thereby improving the contact performance and passivation performance of the solar cell.
[0054] In one embodiment, the thickness of the front tunnel oxide layer 2 is 3 nm to 6 nm, including but not limited to any value among 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm or any range between two values.
[0055] In one embodiment, the boron-doped polysilicon layer 3 has a thickness of 150 nm to 350 nm, including but not limited to any value among 180 nm, 210 nm, 240 nm, 280 nm, 310 nm, 330 nm, and 340 nm, or a range between any two values.
[0056] In one embodiment, the boron doping concentration of the boron doped polysilicon layer 3 is 2.5E 19 cm -3~4.5E 19 cm -3 , including but not limited to 2.8E 19 cm -3 , 3.1E 19 cm -3 , 3.4E 19 cm -3 , 3.7E 19 cm -3 , 4E 19 cm -3 , 4.3E 19 cm -3 Any point value in between or any range of values between them.
[0057] In one embodiment, in the second wet etching step, all layers on the back side of the silicon wafer 1 are removed, and the silicon wafer 1 with a thickness of 2 μm to 4 μm is etched, which is beneficial to ensure that the passivation performance of the back side of the solar cell is not affected.
[0058] It can be understood that all the layers on the back side of the silicon wafer 1 include the coated borosilicate glass layer, the boron-doped polysilicon layer 3, and the front tunneling oxide layer 2. At the same time, the silicon wafer 1 with a thickness of 2μm to 4μm is corroded. This part of the silicon wafer 1 is a boron-doped silicon wafer 1, which is beneficial to ensure that the passivation performance of the back structure of the solar cell produced in the subsequent steps is not affected.
[0059] Specifically, before etching, the thickness of the silicon wafer 1 is 130 μm to 170 μm.
[0060] In one embodiment, after step S6 , a back tunneling oxide layer 8 and a phosphorus-doped polysilicon layer 9 are sequentially grown on the back side of the silicon wafer 1 .
[0061] The present invention has no special restrictions on the preparation method of the back tunneling oxide layer 8 and the phosphorus-doped polysilicon layer 9. For example, they can be prepared by a method combining LPCVD with non-in-situ diffusion, or by a method combining PECVD with high-temperature annealing.
[0062] Preferably, the preparation is carried out by combining LPCVD with non-in-situ diffusion. First, the LPCVD process is used to deposit a back tunneling oxide layer 8 on the back side of the silicon wafer 1 at a temperature of 580°C to 680°C, a time of 0.2h to 1h, and a pressure of 500Torr to 800Torr, which is beneficial to optimizing the structure of the back tunneling oxide layer 8, thereby improving the performance of the solar cell; after depositing the back tunneling oxide layer 8, the back polysilicon layer is continuously deposited at a temperature of 550°C to 700°C, a time of 0.5h to 2.5h, and a pressure of 200Torr to 400Torr, which is beneficial to optimizing the structure of the back polysilicon layer, thereby improving the performance of the solar cell; subsequently, a tubular diffusion furnace is used to diffuse phosphorus on the back side of the silicon wafer 1 at a temperature of 750°C to 940°C and a time of 2h to 3h, which is beneficial to improving the passivation structure and preventing the further inward expansion of the tunneling passivation structure on the front side of the silicon wafer 1, thereby further improving the contact performance and efficiency of the solar cell.
[0063] It can be understood that the above steps are the process of preparing the back structure of the TOPCon solar cell in one embodiment of the present invention. The present invention has no special restrictions on the method for preparing the back structure of the silicon wafer 1. For example, when preparing IBC solar cells and TBC solar cells, the method for preparing the back structure adopts the existing technology.
[0064] It should be noted that steps S8 and S9 are both prepared using existing methods in the industry, which will not be described in detail below.
[0065] The present invention also provides a solar cell prepared by the method for preparing a solar cell as described above, wherein the front side of the solar cell has an excellent film layer structure, and at the same time has good passivation performance and contact performance, and has excellent cell conversion efficiency and broad application prospects.
[0066] like Figure 1 The figure is a schematic diagram of the TOPCon solar cell structure in one embodiment of the present invention. The solar cell comprises a silicon wafer 1, and the front side of the silicon wafer 1 comprises a front tunneling oxide layer 2, a boron-doped polysilicon layer 3, a passivation layer 4, an anti-reflection layer 5 and a positive electrode 6 which are stacked in sequence; wherein the surface of the boron-doped polysilicon layer 3 away from the front tunneling oxide layer 2 is a velvet surface.
[0067] It can be understood that the passivation layer 4 and the anti-reflection layer 5 are also suede, which is beneficial to improve the passivation performance of the front tunneling oxide layer 2, while increasing the light absorption area, ensuring the light absorption efficiency, and thus improving the conversion efficiency of the solar cell.
[0068] It should be noted that the silicon wafer 1 is selected from an N-type silicon wafer or a P-type silicon wafer, preferably an N-type silicon wafer.
[0069] Specifically, the back side of the silicon wafer 1 includes a back side tunneling oxide layer 8 , a phosphorus-doped polysilicon layer 9 and a negative electrode 7 which are stacked in sequence.
[0070] It should be noted that the present invention has no special restrictions on the thickness of the back tunneling oxide layer 8, and the thickness and phosphorus doping concentration of the phosphorus-doped polysilicon layer 9, and those skilled in the art can make selections according to actual needs.
[0071] It can be understood that the present invention has no special restrictions on the back structure of the solar cell. For example, when the solar cell is an IBC solar cell or an IBC solar cell, the back structure can be an interdigitated tunneling passivation structure or a multi-layer composite tunneling passivation structure, and the positive electrode 6 and the negative electrode 7 are both arranged on the back of the solar cell.
[0072] In one embodiment, the passivation layer 4 is an aluminum oxide layer, the anti-reflection layer 5 is a silicon nitride layer, the thickness of the passivation layer 4 is 3nm to 5nm, the thickness of the anti-reflection layer 5 on the front side of the silicon wafer 1 is 70nm to 80nm, and the thickness of the anti-reflection layer 5 on the back side is 80nm to 120nm.
[0073] The solar cell and the method for preparing the same will be further described below by the following specific examples. However, those skilled in the art will appreciate that the following examples are only used to illustrate the present invention and should not be considered to limit the scope of the present invention. If no specific conditions are specified in the examples, the conventional conditions or the conditions recommended by the manufacturer are followed. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.
[0074] Example 1
[0075] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;
[0076] Step 2: Deposit a 6 nm tunnel oxide layer on the front side of the silicon wafer obtained in step 1 by LPCVD deposition process, the deposition temperature is 610° C., the deposition time is 0.9 h, the pressure is 700 Torr, and deposit a 210 nm polysilicon layer, the deposition temperature is 610° C., the deposition time is 1.1 h, and the pressure is 300 Torr;
[0077] Step 3: anneal the front side of the silicon wafer obtained in step 2 at a high temperature of 1045° C. for 2.2 h, and form a 15 nm oxide layer on the surface of the polysilicon layer;
[0078] Step 4, performing a first wet etching on the front side of the silicon wafer obtained in step 3 for 0.2 h, wherein the concentration of HF in the etching solution is 15%, to remove the oxide layer formed on the surface of the polysilicon layer;
[0079] Step 5: Use a tubular diffusion furnace to diffuse boron on the front side of the silicon wafer obtained in step 4, so that the polysilicon layer forms a boron-doped polysilicon layer. The diffusion temperature is 850°C, the diffusion time is 3 hours, and the concentration of boron diffusion in the formed boron-doped polysilicon layer is 3.3E 19 cm -3 ;
[0080] Step 6: Perform a second wet etching on the back of the silicon wafer to remove all layers on the back of the silicon wafer and etch 2 μm of the silicon wafer;
[0081] Step 7: Deposit a 2 nm tunnel oxide layer on the back of the silicon wafer obtained in step 6 by LPCVD deposition process, the deposition temperature is 605° C., the deposition time is 0.3 h, the pressure is 700 Torr, and deposit a 100 nm polysilicon layer, the deposition temperature is 610° C., the deposition time is 0.5 h, and the pressure is 300 Torr;
[0082] Step 8: Use a tubular diffusion furnace to diffuse phosphorus on the back of the silicon wafer obtained in step 7 to form a phosphorus-doped polysilicon layer. The diffusion temperature is 830° C., the diffusion time is 2 h, and the concentration of phosphorus diffusion in the formed phosphorus-doped polysilicon layer is 3E 20 cm -3 ;
[0083] Step 9, texturing the front side of the silicon wafer obtained in step 8, removing the borosilicate glass layer on the front side, and forming a textured surface on the surface of the boron-doped polysilicon layer away from the tunnel oxide layer;
[0084] Step 10, depositing a 4 nm aluminum oxide passivation layer on both sides of the silicon wafer obtained in step 9 by an atomic layer deposition process, and depositing an 80 nm silicon nitride anti-reflection layer on the surface of the aluminum oxide passivation layer by a PECVD process;
[0085] Step 11: Prepare a positive electrode on the front side of the silicon wafer obtained in step 10 and prepare a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.
[0086] Example 2
[0087] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;
[0088] Step 2: Deposit a 3 nm tunnel oxide layer on the front side of the silicon wafer obtained in step 1 by LPCVD deposition process, the deposition temperature is 610° C., the deposition time is 0.45 h, the pressure is 700 Torr, and deposit a 210 nm polysilicon layer, the deposition temperature is 610° C., the deposition time is 1.1 h, and the pressure is 300 Torr;
[0089] Step 3: anneal the front side of the silicon wafer obtained in step 2 at a high temperature of 1045° C. for 2.2 h, and form a 15 nm oxide layer on the surface of the polysilicon layer;
[0090] Step 4, performing a first wet etching on the front side of the silicon wafer obtained in step 3 for 0.2 h, wherein the concentration of HF in the etching solution is 15%, to remove the oxide layer formed on the surface of the polysilicon layer;
[0091] Step 5: Use a tubular diffusion furnace to diffuse boron on the front side of the silicon wafer obtained in step 4, so that the polysilicon layer forms a boron-doped polysilicon layer. The diffusion temperature is 845°C, the diffusion time is 3 hours, and the concentration of boron diffusion in the formed boron-doped polysilicon layer is 3.1E 19 cm -3 ;
[0092] Step 6: Perform a second wet etching on the back of the silicon wafer to remove all layers on the back of the silicon wafer and etch 2 μm of the silicon wafer;
[0093] Step 7: Deposit a 2 nm tunnel oxide layer on the back of the silicon wafer obtained in step 6 by LPCVD deposition process, the deposition temperature is 605° C., the deposition time is 0.3 h, the pressure is 700 Torr, and deposit a 100 nm polysilicon layer, the deposition temperature is 610° C., the deposition time is 0.5 h, and the pressure is 300 Torr;
[0094] Step 8: Use a tubular diffusion furnace to diffuse phosphorus on the back of the silicon wafer obtained in step 7 to form a phosphorus-doped polysilicon layer. The diffusion temperature is 830° C., the diffusion time is 2 h, and the concentration of phosphorus diffusion in the formed phosphorus-doped polysilicon layer is 3E 20 cm -3 ;
[0095] Step 9, texturing the front side of the silicon wafer obtained in step 8, removing the borosilicate glass layer on the front side, and forming a textured surface on the surface of the boron-doped polysilicon layer away from the tunnel oxide layer;
[0096] Step 10, depositing a 4 nm aluminum oxide passivation layer on both sides of the silicon wafer obtained in step 9 by an atomic layer deposition process, and depositing an 80 nm silicon nitride anti-reflection layer on the surface of the aluminum oxide passivation layer by a PECVD process;
[0097] Step 11: Prepare a positive electrode on the front side of the silicon wafer obtained in step 10 and prepare a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.
[0098] Example 3
[0099] Step 1: Double-sided polishing of the silicon wafer is performed using a tank-type alkali polishing process to remove impurities and damaged layers;
[0100] Step 2: Deposit a 6 nm tunnel oxide layer on the front side of the silicon wafer obtained in step 1 by LPCVD deposition process, the deposition temperature is 610° C., the deposition time is 0.9 h, the pressure is 700 Torr, and deposit a 210 nm polysilicon layer, the deposition temperature is 630° C., the deposition time is 0.8 h, and the pressure is 300 Torr;
[0101] Step 3, high-temperature annealing is performed on the front side of the silicon wafer obtained in step 2 at a temperature of 1045° C. for 2.5 hours, and a 16 nm oxide layer is formed on the surface of the polysilicon layer;
[0102] Step 4, performing a first wet etching on the front side of the silicon wafer obtained in step 3 for 0.2 h, wherein the concentration of HF in the etching solution is 16%, to remove the oxide layer formed on the surface of the polysilicon layer;
[0103] Step 5: Use a tubular diffusion furnace to diffuse boron on the front side of the silicon wafer obtained in step 4, so that the polysilicon layer forms a boron-doped polysilicon layer. The diffusion temperature is 850°C, the diffusion time is 3 hours, and the concentration of boron diffusion in the formed boron-doped polysilicon layer is 3.5E 19 cm -3 ;
[0104] Step 6: Perform a second wet etching on the back of the silicon wafer to remove all layers on the back of the silicon wafer and etch 2 μm of the silicon wafer;
[0105] Step 7: Deposit a 2 nm tunnel oxide layer on the back of the silicon wafer obtained in step 6 by LPCVD deposition process, the deposition temperature is 605° C., the deposition time is 0.3 h, the pressure is 700 Torr, and deposit a 100 nm polysilicon layer, the deposition temperature is 610° C., the deposition time is 0.5 h, and the pressure is 300 Torr;
[0106] Step 8: Use a tubular diffusion furnace to diffuse phosphorus on the back of the silicon wafer obtained in step 7 to form a phosphorus-doped polysilicon layer. The diffusion temperature is 830° C., the diffusion time is 2 h, and the concentration of phosphorus diffusion in the formed phosphorus-doped polysilicon layer is 3E 20 cm -3 ;
[0107] Step 9, texturing the front side of the silicon wafer obtained in step 8, removing the borosilicate glass layer on the front side, and forming a textured surface on the surface of the boron-doped polysilicon layer away from the tunnel oxide layer;
[0108] Step 10, depositing a 4 nm aluminum oxide passivation layer on both sides of the silicon wafer obtained in step 9 by an atomic layer deposition process, and depositing an 80 nm silicon nitride anti-reflection layer on the surface of the aluminum oxide passivation layer by a PECVD process;
[0109] Step 11: Prepare a positive electrode on the front side of the silicon wafer obtained in step 10 and prepare a negative electrode on the back side of the silicon wafer by screen printing sintering, light injection and laser assisted sintering processes.
[0110] Comparative Example 1
[0111] The difference between Comparative Example 1 and Example 1 is that step 3 and step 4 are not performed, and boron diffusion is directly performed on the polysilicon layer obtained by LPCVD deposition.
[0112] Comparative Example 2
[0113] The difference between Comparative Example 2 and Example 1 is that in step 1, the front side of the silicon wafer is textured, so that in the finally obtained solar cell, the front side of the silicon wafer is a textured surface.
[0114] The performance of the solar cells prepared in all the embodiments and comparative examples was tested using a Halm tester to measure the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and conversion efficiency (Eta). All test results are shown in Table 1.
[0115] Table 1
[0116]
[0117]
[0118] According to the results in Table 1, the solar cells prepared in all the embodiments have a high cell conversion efficiency, and the open circuit voltage, short circuit current density, and fill factor are high, while the conversion efficiency, open circuit voltage, short circuit current density, and fill factor of the solar cells in all the comparative examples are significantly lower. Therefore, the solar cell preparation method provided by the present invention can effectively optimize the film layer structure on the front side of the solar cell, while improving the passivation performance and contact performance, and the prepared solar cell has excellent cell conversion efficiency.
[0119] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0120] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: S1, double-sided polishing of silicon wafer; S2, depositing a front tunneling oxide layer and a polysilicon layer in sequence on the front side of the silicon wafer by low pressure chemical vapor deposition; S3, high temperature annealing is performed on the front side of the silicon wafer; S4, performing a first wet etching on the front side of the silicon wafer to remove the oxide layer formed on the surface of the polysilicon layer; S5, performing boron diffusion on the front side of the silicon wafer to form a boron-doped polysilicon layer from the polysilicon layer; S6, performing a second wet etching on the back side of the silicon wafer to remove all layers on the back side of the silicon wafer and corrode part of the silicon wafer; S7, performing texturing on the front side of the silicon wafer, removing the borosilicate glass layer on the front side, and forming a texturing surface on the surface of the boron-doped polysilicon layer away from the front tunnel oxide layer; S8, preparing a passivation layer and an anti-reflection layer on both sides of the silicon wafer; S9. Prepare a positive electrode and a negative electrode.
2. The method for preparing a solar cell according to claim 1, characterized in that: When depositing the front tunnel oxide layer, the temperature is 580° C. to 680° C., the time is 0.2 h to 1 h, and the pressure is 500 Torr to 800 Torr; And / or, when depositing the polysilicon layer, the temperature is 550° C. to 700° C., the time is 0.5 h to 2.5 h, and the pressure is 200 Torr to 400 Torr.
3. The method for preparing a solar cell according to claim 1, characterized in that: In the high temperature annealing step, the temperature is 900° C. to 1050° C., and the time is 1 h to 2 h.
4. The method for preparing a solar cell according to claim 1 or 3, characterized in that: In the high temperature annealing step, the thickness of the formed oxide layer is 15nm-18nm.
5. The method for preparing a solar cell according to claim 1, characterized in that: The first wet etching takes 1 to 5 minutes, and the concentration of HF in the etching solution used is 3% to 5%.
6. The method for preparing a solar cell according to claim 1, characterized in that: In the boron diffusion step, the temperature is 800° C. to 960° C., and the time is 3 h to 4 h.
7. The method for preparing a solar cell according to claim 1, characterized in that: The thickness of the front tunneling oxide layer is 3nm to 6nm; And / or, the thickness of the boron-doped polysilicon layer is 150nm to 350nm; And / or, the boron doping concentration of the boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .
8. The method for preparing a solar cell according to claim 1, characterized in that: In the second wet etching step, all layers on the back side of the silicon wafer are removed, and the silicon wafer having a thickness of 2 μm to 4 μm is etched.
9. The method for preparing a solar cell according to claim 1 or 8, characterized in that: After the second wet etching is completed, a back-side tunneling oxide layer and a phosphorus-doped polysilicon layer are sequentially grown on the back side of the silicon wafer.
10. A solar cell manufactured by the method for manufacturing a solar cell according to any one of claims 1 to 9.