A method for characterizing thermal properties of non-flat surfaces based on scanning thermal microscopy

Abstract

The present invention discloses a method for characterizing the thermal properties of non-flat surfaces based on a scanning thermal microscope. The present invention first obtains a working voltage load range applicable to each height step based on the influence of different voltage loads on each height step, thereby avoiding the introduction of additional effects due to excessively high voltage loads. Then, a first working voltage load applicable to each height step is selected, and the first working voltage load is applied to each height step, thereby avoiding a large influence of the voltage load on the probe temperature difference. The relationship model between each height step and the probe temperature difference can be accurately obtained. The step height upper limit value is obtained through the relationship model between the step height and the probe temperature difference based on a set minimum temperature resolution value. The test samples whose surface morphology meets the step height upper limit value are screened and scanned by a scanning thermal microscope, thereby suppressing the "artifact" phenomenon and obtaining more accurate thermal performance characterization results.

Description

Technical Field

[0001] The present invention belongs to the field of thermal property characterization of micro-nanoscale materials, and particularly relates to a method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope. Background Art

[0002] In the context of the current rapid development of science and technology, research at the micro-nanoscale has become the key to achieving breakthroughs in many cutting-edge fields. As materials science moves towards higher precision and complexity, new nanomaterials such as carbon nanotube composites continue to emerge, in which microscopic thermal conductivity properties play a vital role in macroscopic application performance. In the field of electronic devices, with the miniaturization of devices and the increase in high-performance requirements, heat dissipation problems are becoming increasingly severe, especially the heat accumulation and dissipation mechanism in tiny areas inside the chip, which has become a core element to ensure stable operation of the device. In nano-processing technology, due to the continuous improvement of processing precision, the precise control of thermal changes during the processing process is becoming more and more important. Small temperature differences may have a significant impact on the quality of the final product.

[0003] Scanning thermal microscopy (SThM) has emerged as a core tool for micro- and nanoscale heat transfer research and local thermal performance characterization, and is widely used in various key fields. In materials science, SThM can deeply reveal the heat conduction path at the atomic level and provide guidance for the optimization of material microstructures to meet specific thermal performance requirements; in thermal management of electronic devices, SThM can accurately locate high heat density areas, providing an important basis for the design and optimization of heat dissipation systems; in the nano-processing process, SThM can monitor thermal fluctuations in real time and assist in calibrating processing parameters to ensure accurate engraving of nanostructures. As a highly sensitive comprehensive characterization tool that integrates multiple signals such as heat, force, and electricity, SThM has become an important means in the field of nano-heat conduction research due to its excellent spatial resolution and sensitivity.

[0004] However, when SThM is used for thermal characterization, the accuracy and reliability of test results face challenges. A key issue is the influence of sample surface topography on the thermal signal. According to the SThM testing principle, the topography and thermal signals are obtained from two separate circuits, theoretically preventing artifacts. However, a deeper understanding of the core SThM testing mechanism reveals that the total heat input from the thermal probe tip to the sample is the sum of heat dissipated at the tip / sample interface and heat transferred into the sample interior. The tip / sample contact interface can be considered the thermal resistance connecting the tip and sample. Only by eliminating the influence of contact thermal resistance can the thermal feedback signal reflect the actual thermal performance of the sample. Contact thermal resistance is related to the actual contact area between the tip and sample. Fluctuations in the sample's surface topography can cause changes in the actual contact area between the probe and sample, which in turn changes the contact thermal resistance at the interface and the heat flowing into the sample, resulting in topography-related artifacts. Suppressing or eliminating this topography artifact is a key issue that needs to be addressed.

[0005] Although existing technologies attempt to reduce morphological artifacts by optimizing probe structures or adjusting test parameters, they fail to provide systematic and quantitative suppression strategies, resulting in large deviations in test results. Summary of the Invention

[0006] The present invention provides a method for characterizing the thermal properties of non-flat surfaces based on a scanning thermal microscope. This method can suppress the "artifact" phenomenon and obtain more accurate test results.

[0007] The present invention provides a method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope, comprising:

[0008] Electron beam exposure and dry etching are used to form multiple steps of different heights on the surface of the silicon wafer;

[0009] Using a scanning thermal microscope, a nano-thermal probe is used to apply different voltage loads to each height step to obtain a corresponding probe temperature difference. The corresponding working voltage load range is obtained when the detection temperature difference impact value corresponding to each height step is less than the detection temperature difference impact value threshold. The voltage loads that fall within the different working voltage load ranges are used as the first working voltage load.

[0010] Applying the first working voltage load to steps of different heights through a nano thermal probe to obtain corresponding probe temperature differences, thereby obtaining a relationship model between step height and probe temperature difference;

[0011] Obtaining an upper limit value of the step height based on a set minimum temperature resolution value through a relationship model between the step height and the probe temperature difference;

[0012] If the maximum value of the morphology height of the sample to be tested is higher than the upper limit value of the step height, the morphology height of the sample to be tested is lowered. If the maximum value of the morphology height of the sample to be tested is lower than the upper limit value of the step height, based on the different morphology heights of the sample to be tested, the corresponding second working voltage load is selected from the corresponding working voltage load range for scanning thermal microscope scanning.

[0013] Preferably, when the step height is 0 nm to 10 nm, the voltage load range is 50 mV to 200 mV;

[0014] When the step height is 10nm to 20nm, the voltage load range is 50mV to 120mV;

[0015] When the step height is 20nm to 35nm, the voltage load range is 50mV to 80mV;

[0016] When the step height is 35 nm to 55 nm, the voltage load range used is 50 mV to 60 mV.

[0017] Preferably, the relationship model between the step height and the probe temperature difference includes a non-affected area, a transition area and a significant affected area;

[0018] In the unaffected zone, the probe temperature difference is 0 K as the step height changes;

[0019] In the transition region, the probe temperature difference is less than 0.002 K as the step height changes;

[0020] In the obvious affected area, the step height is linearly related to the probe temperature difference, and the upper limit of the step height is obtained through the linear relationship based on the set minimum temperature resolution value.

[0021] Preferably, when the first operating voltage load is 50-60 mV, the step height in the unaffected area is ≤10 nm;

[0022] In the transition region, the step height is between 10 and 20 nm;

[0023] In the obvious affected area, the step height is greater than 20 nm, and the linear coefficient is 2.15×10 -4 K nm -1 , the correlation of the fitting curve is ≥0.99.

[0024] Preferably, the roughness of the silicon wafer surface is ≤10 nm.

[0025] Preferably, the scanning rate of the scanning thermal microscope is 0.1-1 Hz, and the scanning range is 1-10 μm.

[0026] Preferably, the etching time of the dry etching is 10s, 20s, 40s, 60s, 80s, 100s, and 120s, respectively, and the obtained step heights are 2-3nm, 5-6nm, 11-12nm, 24-25nm, 32-33nm, 39-40nm, and 45-46nm, respectively.

[0027] Preferably, the probe temperature difference of each height platform is the difference between the probe thermal signals on the upper surface and the lower surface of each height platform.

[0028] Preferably, electron beam exposure and dry etching are used to form multiple steps of different heights on the surface of the silicon wafer, including:

[0029] Electron beam exposure is used to form a pattern on the surface of the silicon wafer, and then dry etching is used to obtain steps of different heights;

[0030] Before patterning by electron beam exposure and before and after ion beam etching, oxygen plasma is used to clean the silicon wafer surface.

[0031] Preferably, before electron beam exposure, the surface of the silicon wafer is ultrasonically cleaned with acetone, alcohol and deionized water, and then blown dry with high-pressure nitrogen.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention first obtains a voltage load range suitable for each height step based on the influence of different voltage loads on each height step, thereby avoiding the introduction of additional effects due to excessively high voltage loads.

[0034] Then, a first working voltage load applicable to each height step is selected, and the first working voltage load is applied to each height step, so as to avoid a large influence of the voltage load on the probe temperature difference, and accurately obtain the relationship model between each height step and the probe temperature difference. Based on the set minimum temperature resolution value, the upper limit value of the step height is obtained through the relationship model between the step height and the probe temperature difference, and the test samples whose surface morphology meets the upper limit value of the step height are screened and scanned by a scanning thermal microscope, so as to suppress the "artifact" phenomenon and obtain more accurate thermal performance characterization results. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a diagram showing the characterization results of the Si surface after different Ar plasma beam etching times provided in Example 1 of the present invention;

[0036] Figure 2 A relationship diagram of different Ar plasma beam etching times and etching depths provided in Example 1 of the present invention;

[0037] Figure 3A graph showing the relationship between the step height difference and the probe temperature difference after patterned ion beam etching of the substrate provided in Example 1 of the present invention;

[0038] Figure 4 This is a characterization result diagram of the Si surface after plasma etching for 120 seconds provided in Example 1 of the present invention;

[0039] Figure 5 This is a characterization result diagram of the Si surface after plasma etching for 100 seconds provided in Example 1 of the present invention;

[0040] Figure 6 This is a graph showing the characterization results of the Si surface after 80s of plasma etching provided in Example 1 of the present invention;

[0041] Figure 7 This is a graph showing the characterization results of the Si surface after 40 seconds of plasma etching provided in Example 1 of the present invention;

[0042] Figure 8 This is a scatter plot comparison of the applied voltage and probe temperature difference under different step heights provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0043] The specific embodiments of the present invention aim to provide a method for suppressing morphological artifact effects and characterizing thermal properties using a scanning thermal microscope. By combining step height control with probe voltage optimization, a quantitative relationship model between probe temperature difference and morphological height is established, enabling high-precision thermal performance testing of samples with complex morphologies. The technical methods proposed in this invention include the following:

[0044] (1) Sample preparation of vertical step structure:

[0045] A specific embodiment of the present invention uses a commercial single-sided polished, oxide-free silicon wafer as a substrate. Since the roughness of the silicon wafer substrate is relatively low, generally less than 10 nm, and the morphology below 10 nm has little effect on the probe temperature difference, the surface of the commercial silicon wafer can be used as a benchmark to explore the step height, that is, the effect of the morphology height on the probe temperature difference. A polished silicon wafer of a fixed size is obtained by a femtosecond laser, and a rectangular pattern is first obtained by electron beam exposure. Argon ion beam etching is used to etch the microstructure. The depth of the micro-nano structure is controlled by controlling the etching time to obtain micro-nano structures with different vertical step heights.

[0046] (2) Optimize the probe applied voltage:

[0047] A scanning thermal microscope is used to apply different voltage loads to each height step through a nanothermal probe to obtain the corresponding probe temperature difference. The corresponding usage voltage load range is obtained when the detection temperature difference influence value corresponding to each height step is less than the detection temperature difference influence value threshold. The voltage loads that fall within the different usage voltage load ranges are used as the first usage voltage load.

[0048] In a specific embodiment, when the step height is 0nm to 10nm, the voltage load range is 50mV to 200mV; when the step height is 10nm to 20nm, the voltage load range is 50mV to 120mV; when the step height is 20nm to 35nm, the voltage load range is 50mV to 80mV; and when the step height is 35nm to 55nm, the voltage load range is 50mV to 60mV. It can be seen that when the step height is low, the voltage load range is very wide, and the higher the step height, the narrower the voltage load range. Therefore, in the actual scanning process, different voltages can be used based on the voltage load range according to different feature heights, thereby avoiding large errors in heat detection caused by excessive voltage load.

[0049] (3) A relationship model between the step height and the probe temperature difference is obtained, and an upper limit value of the step height is obtained through the relationship model between the step height and the probe temperature difference based on a set minimum temperature resolution value.

[0050] In a specific embodiment, the relationship model between the step height and the probe temperature difference provided in the specific embodiment of the present invention includes a no-influence zone, a transition zone and a significant influence zone; in the no-influence zone, the probe temperature difference is 0K as the step height changes, that is, the height of the step has no effect on the probe temperature difference; in the transition zone, the probe temperature difference is below 0.002K as the step height changes, and in the transition zone, the linear relationship between the step height and the probe temperature difference is weak; in the significant influence zone, the step height and the probe temperature difference are in a linear relationship, and the upper limit value of the step height is obtained through the linear relationship based on the set minimum temperature resolution value.

[0051] (4) If the maximum value of the topography height of the sample to be tested is higher than the upper limit value of the step height, the topography height of the sample to be tested is lowered; if the maximum value of the topography height of the sample to be tested is lower than the upper limit value of the step height, based on the different topography heights of the sample to be tested, a corresponding second working voltage load is selected from the corresponding working voltage load range to perform scanning thermal microscope scanning.

[0052] Example 1

[0053] This embodiment provides a method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope, including:

[0054] (1) Sample preparation of vertical step structure:

[0055] 1) Choose commercial single-sided polished silicon without oxide layer, whose surface roughness is less than 1nm, which can effectively eliminate the influence of the roughness of the sample itself on the thermal test results.

[0056] 2) A femtosecond laser was used to cut silicon wafers into a size of 1 cm × 1 cm, ultrasonically cleaned with acetone, alcohol, and deionized water for 10 min each, and then dried with high-pressure nitrogen.

[0057] 3) A rectangular pattern was obtained using electron beam exposure technology, and the step height was controlled by argon ion beam etching. The step structures with heights of 2.30 nm, 5.90 nm, 11.50 nm, 24.70 nm, 32.60 nm, 39 nm, and 45.40 nm were obtained after the argon ion beam etching time was 10 s, 20 s, 40 s, 60 s, 80 s, 100 s, and 120 s, respectively.

[0058] 4) Before the electron beam exposure patterning and before and after the ion beam etching, the Si substrate surface must be cleaned for 15 minutes using 400W O2 plasma to ensure the patterning accuracy and complete removal of the electron beam exposure glue, so as to reduce the temperature contribution of the tiny protruding structures on the plane to the entire plane. Figure 1 It can be found from the AFM morphology characterization images of (a1)-(g1) that the surface after ion beam etching is relatively flat and clean, without obvious large protrusions, which also provides a certain guarantee and premise for the accuracy of the quantitative analysis results.

[0059] (2) Establish a relationship model between topography height and probe temperature difference.

[0060] 1) Measure the relationship between the probe temperature difference and the probe height, and obtain linear variation data within the positive correlation region. Set the test parameters: scanning rate 0.3Hz, scanning range 5μm×5μm, scanning pixel size 256×256, and the first working voltage load applied by the thermal probe is 60mV. By scanning the steps of different heights, a two-dimensional colored map of the topography height and the probe temperature difference is obtained at the same time ( Figure 1 (a1)-(g1), Figure 1 (a2)-(g2)); By performing zero baseline "Flatten" processing on the upper or lower surface of the step in the AFM morphology image and the SThM thermal imaging image, a cross-sectional line scan comparison diagram of the morphology height and the probe temperature difference was obtained ( Figure 1 (a3)-(g3)); Figure 2 The relationship between etching time and etching depth is shown in Figure 2. As etching time increases, the etching depth decreases at a rate of 0.40 nm s -1The rate increases linearly, indicating that the Ar ion beam etching technology can achieve controllable step height, rapid and low surface roughness preparation.

[0061] 2) Based on the linear relationship between the probe temperature difference and the topography height, the positive correlation region is linearly extended to predict the critical step height under the temperature resolution limit (less than 0.01K). Figure 3 The relationship between the probe temperature difference and the step height is shown in the figure. When the step height is between 20nm and 50nm or higher than 50nm, the probe temperature difference and the step height show a linear positive correlation. -4 K nm -1 The correlation between the fitted curves reaches 0.99, indicating a more pronounced morphological artifact. When the step height is between 10nm and 20nm, the linear correlation weakens, resulting in a transitional region where morphological artifacts appear. When the step height is below 10nm, the probe temperature difference is virtually unaffected by the change in step height, reaching 0K, indicating an artifact-free thermal phenomenon. Based on model predictions, the maximum step height at which the effect of morphological artifacts on probe temperature measurement is insufficient to exceed the resolution (0.01K) is 63nm, indicating an upper limit on the step height.

[0062] (3) Optimize the probe applied voltage load to obtain the first working voltage load:

[0063] 1) Within the current saturation value (2.16 mA) of the nanothermal probe, set eight probe applied load test values ​​from 50 mV to 120 mV in increments of 10 mV, obtain the step height structure using the method of step (1), and perform a scanning thermal test. Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 The characterization results are respectively for step heights (etching time) of 45.40nm (120s), 39nm (100s), 32.60nm (80s) and 11.50nm (40s). In this set of figures, Figure (a) is an AFM morphology image of a 5μm scanning range at the step. In this set of figures, Figure (b) is a measurement result of the SThM thermal signal, i.e., the probe temperature, under different probe applied loads at the corresponding morphology positions. The specific test method is that when the thermal probe performs a thermal scan from bottom to top, the interval is equally divided according to the total scanning distance, thereby increasing the applied load of the probe, and all SThM thermal signal information of the probe applied load varying from 50mV to 120mV can be obtained in a square two-dimensional thermal map in the range of 5μm×5μm.

[0064] 2) Figure 8(a)-(d) are the relationship between the applied load and the probe temperature difference under different step heights. When the step height is 45.40nm, the probe temperature difference shows an almost linear increasing trend when the probe applied load exceeds 60mV; when the step height is 39nm, the probe temperature difference shows a platform-like slowly increasing trend; when the step height is reduced to 32.60nm, the probe temperature difference shows a step-by-step jump change area. Under an applied load below 80mV, the probe temperature difference hardly changes. When the applied load is further increased, the probe temperature difference suddenly increases and then slowly increases; when the step height is reduced to 11.50nm, the probe temperature difference hardly changes with the applied load and is basically stable at 10 -3 About K.

[0065] 3) Based on the experimental test results, the optimization principle of "the probe applied voltage is as small as possible and can generate a significant thermal signal" is proposed to minimize the interference of the additional thermal effect. In this embodiment, 60mV is selected as the first working voltage load.

[0066] (4) If the maximum value of the topography height of the sample to be tested is higher than the upper limit value of the step height, the topography height of the sample to be tested is lowered; if the maximum value of the topography height of the sample to be tested is lower than the upper limit value of the step height, based on the different topography heights of the sample to be tested, a corresponding second working voltage load is selected from the corresponding working voltage load range to perform scanning thermal microscope scanning.

[0067] The specific embodiment of the present invention systematically studies the relationship between the probe temperature difference and the step height, proposes a quantitative model for the influence of morphology artifacts on the SThM thermal performance measurement, and for the first time clarifies the critical step height (63nm) under the limitation of the probe temperature resolution (0.01K), providing a theoretical basis for optimizing the test accuracy and applicability of SThM.

[0068] The specific embodiment of the present invention clarifies the operating principle of "applying voltage as small as possible while being able to generate a significant thermal signal" by optimizing the method of applying voltage to the probe, thereby reducing additional effects and ensuring the authenticity of the thermal performance characterization results.

[0069] The method for characterizing thermal properties of non-flat surfaces based on scanning thermal microscopy provided in a specific embodiment of the present invention is applicable to samples with complex surface morphology or those that have not been flattened, thus expanding the application scenarios of SThM.

[0070] In response to the difficulties in characterizing the morphology "artifact" effect and complex morphology samples in the prior art, the present invention provides an optimization technology method based on the relationship between morphology height, probe applied voltage and thermal signal, so as to achieve effective suppression of morphology "artifact" effect and high-precision thermal performance characterization. The technical effects that can be achieved are as follows: 1. Through the study of the staged influence of step height, a positive correlation between probe temperature difference and morphology height is proposed, and the applicable range of transition zone and positive correlation zone is set, thereby ensuring the reliability of SThM technology at different surface heights; 2. By utilizing the quantitative relationship between step height and probe temperature signal, the critical conditions for the generation of "artifact" can be accurately identified on different morphology surfaces, ensuring the authenticity and effectiveness of SThM signal; 3. In response to the additional influence of probe applied voltage on morphology "artifact", the present invention proposes the principle of using the smallest possible applied voltage as the optimal test condition. This optimization strategy can effectively reduce the additional effect of voltage and improve the reliability of thermal signal characterization.

Claims

1. A method for characterizing thermal properties of non-flat surfaces based on scanning thermal microscopy, characterized in that: include: (1) Electron beam exposure and dry etching are used to form multiple steps of different heights on the surface of a silicon wafer, wherein the roughness of the silicon wafer surface is ≤10 nm; (2) Using a scanning thermal microscope, different voltage loads are applied to the steps of each height through a nano-thermal probe to obtain the corresponding probe temperature difference, and the corresponding working voltage load range is obtained when the detection temperature difference influence value corresponding to the step of each height is less than the detection temperature difference influence value threshold, and the voltage loads that fall within the working voltage load range corresponding to the steps of different heights are used as the first working voltage load, wherein the probe temperature difference corresponding to the step of each height is the difference between the probe thermal signals of the upper surface and the lower surface of the step of each height; (3) applying the first working voltage load to steps of different heights through a nanothermal probe to obtain corresponding probe temperature differences, thereby obtaining a relationship model between step height and probe temperature difference; Obtaining an upper limit value of the step height based on a set minimum temperature resolution value through a relationship model between the step height and the probe temperature difference; (4) If the maximum value of the topography height of the sample to be tested is higher than the upper limit value of the step height, the topography height of the sample to be tested is lowered; if the maximum value of the topography height of the sample to be tested is lower than the upper limit value of the step height, based on the different topography heights of the sample to be tested, a corresponding second working voltage load is selected from the corresponding working voltage load range to perform scanning thermal microscope scanning.

2. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 1, characterized in that: In step (2), the voltage load range corresponding to each step height is obtained as follows: When the step height is 0 nm ~ 10 nm, the voltage load range is 50 mV ~ 200 mV; When the step height is 10 nm ~ 20 nm, the voltage load range is 50 mV ~ 120 mV; When the step height is 20 nm to 35 nm, the voltage load range is 50 mV to 80 mV; When the step height is 35 nm ~ 55 nm, the voltage load range used is 50 mV ~ 60 mV.

3. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 1, wherein: The relationship model between the step height and the probe temperature difference includes a non-affected area, a transition area and a significant affected area; In the unaffected zone, the probe temperature difference is 0 K as the step height changes; In the transition region, the probe temperature difference is less than 0.002 K as the step height changes; In the obvious affected area, the step height is linearly related to the probe temperature difference, and the upper limit of the step height is obtained through the linear relationship based on the set minimum temperature resolution value.

4. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 3, wherein: When the first applied voltage load is 50-60 mV, the step height is ≤10 nm in the unaffected area; In the transition region, the step height is between 10 and 20 nm; In the obvious affected area, the step height is greater than 20 nm, and the linear coefficient is 2.15×10 -4 K ﹒ nm -1 , the correlation of the fitting curve is ≥0.

99.

5. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 1, wherein: The scanning rate of the scanning thermal microscope is 0.1 to 1 Hz, and the scanning range is 1 to 10 μm.

6. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 1, wherein: The etching time of the dry etching is 10 s, 20 s, 40 s, 60 s, 80 s, 100 s, and 120 s, respectively, and the obtained step heights are 2-3 nm, 5-6 nm, 11-12 nm, 24-25 nm, 32-33 nm, 39-40 nm, and 45-46 nm, respectively.

7. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 1, wherein: Electron beam exposure and dry etching are used to form multiple steps of different heights on the surface of the silicon wafer, including: Electron beam exposure is used to form a pattern on the surface of the silicon wafer, and then ion beam etching is used to obtain steps of different heights; Before patterning by electron beam exposure and before and after ion beam etching, oxygen plasma is used to clean the silicon wafer surface.

8. The method for characterizing thermal properties of non-flat surfaces based on a scanning thermal microscope according to claim 7, wherein: Before electron beam exposure, the silicon wafer surface was ultrasonically cleaned with acetone, alcohol and deionized water, and then dried with high-pressure nitrogen.

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