Chip sample preparation method and electrical property test method
By punching holes in the device layer of the chip sample to form detection through holes, the problem that the conductive contact holes cannot withstand high current causes the chip sample to burn, which improves the success rate of electrical testing and reduces the difficulty of testing.
Patent Information
- Application Number
- CN202510002369.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-11
AI Technical Summary
During the nanoprobe testing process, the conductive contact holes cannot withstand high current, causing the chip sample to burn, increasing the difficulty of testing.
The detection through holes are formed by punching holes in the device layer of the chip sample, exposing the substrate so that power can be directly supplied to the substrate during nanoprobe testing, avoiding direct power supply through the conductive contact holes.
It improves the overcurrent capability of chip samples, reduces the difficulty and cost of nanoprobe testing, and improves the test success rate.
Smart Images
Figure CN119805148A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip sample preparation method and an electrical property testing method. Background Art
[0002] BCD (Bipolar CMOSDMOS) is a process technology that integrates high-voltage power devices such as bipolar, CMOS, DMOS, and various resistors, capacitors, and diodes on the same chip. It combines the advantages of high transconductance and strong load driving capability of bipolar devices, high integration and low power consumption of CMOS, and the advantages of high voltage and high current driving of DMOS devices. SGT (Shielded Gate Transistor) MOSFET is a power semiconductor device that mainly reduces the chip footprint through a vertical structure, and reduces the device on-resistance through a vertical field oxide layer setting and a charge balance mechanism.
[0003] IPS (intelligent power switch) products are power chips that combine SGT devices and BCD devices. When the power chip is tested at the device level by nanoprobe, it is necessary to perform a power supply test on the substrate. At this time, the nanoprobe contacts the conductive contact holes on the surface of the substrate to achieve electrical connection between the nanoprobe and the substrate. Due to the limited overcurrent capacity of the conductive contact holes, the conductive contact holes are often unable to withstand large currents during the nanoprobe test, resulting in the burning of chip samples, which increases the difficulty of testing. Summary of the invention
[0004] The present invention provides a chip sample preparation method and an electrical property testing method, which can improve the overcurrent capability of the chip sample, thereby improving the success rate of nanoprobe testing and reducing the difficulty of nanoprobe testing.
[0005] In order to solve the above problems, the present invention provides a method for preparing a chip sample, comprising the following steps:
[0006] Providing a chip sample to be processed, the chip sample comprising a substrate, a device layer and an interconnection structure layer, wherein the device layer is arranged on one side of the substrate, the interconnection structure layer is located on the substrate and the device layer, and comprises a conductive contact hole layer and an interconnection layer in sequence from bottom to top, the interconnection layer simultaneously connects the substrate and the device layer through the conductive contact hole layer, wherein the device layer comprises a plurality of semiconductor devices;
[0007] Stripping the interconnection layer and exposing the conductive contact hole layer;
[0008] A hole is punched in the conductive contact hole layer to form a detection through hole, wherein the detection through hole is located outside the semiconductor device to be tested and the substrate is exposed through the detection through hole.
[0009] Optionally, the conductive contact hole layer includes a bottom dielectric layer and a plurality of conductive contact holes embedded in the dielectric layer.
[0010] Furthermore, the specific method of forming the detection through hole is:
[0011] Selecting at least one target semiconductor device from among all the semiconductor devices;
[0012] marking a drilling position by laser at a preset distance from each of the target semiconductor devices;
[0013] At the punching position, the bottom dielectric layer is punched by laser to form a detection through hole.
[0014] Furthermore, the detailed steps of punching holes in the bottom dielectric layer are as follows:
[0015] At the drilling position, the bottom dielectric layer is bombarded at least once by laser, and after each bombardment, a single probe short circuit test to ground is performed. When the probe detection voltage is 0-0.1V, the bombardment is stopped and a detection through hole is formed.
[0016] Optionally, the substrate includes a silicon substrate and an epitaxial layer from bottom to top, a portion of the device layer is located in the epitaxial layer, and the remaining portion is located on the epitaxial layer.
[0017] Furthermore, the detection through hole exposes the surface of the epitaxial layer; or, exposes a partial depth of the epitaxial layer; or, penetrates the epitaxial layer and exposes the surface of the silicon substrate.
[0018] Furthermore, the substrate and the epitaxial layer are both doped with N-type ions in the semiconductor device.
[0019] Optionally, the chip sample is a chip sample of an intelligent power switch platform.
[0020] On the other hand, the present invention also provides a method for testing the electrical properties of a chip sample, comprising the following steps:
[0021] Providing a chip sample, wherein the chip sample is prepared by the chip sample preparation method;
[0022] The substrate is connected to a power supply voltage, and a nanoprobe test is performed on the target semiconductor device, wherein during the nanoprobe test, the probe is connected to the substrate by directly contacting the detection through hole.
[0023] Optionally, during nanometer testing, the detection through hole is directly contacted by a first probe, and corresponding conductive contact holes in the conductive contact hole layer are contacted by a plurality of second probes.
[0024] Compared with the prior art, the present invention has the following unexpected technical effects:
[0025] The present invention provides a method for preparing a chip sample and an electrical testing method. The method for preparing a chip sample comprises the following steps: providing a chip sample to be processed, wherein the chip sample comprises a substrate, a device layer and an interconnection structure layer, wherein the device layer is arranged on one side of the substrate, and the interconnection structure layer is located on the substrate and the device layer, and comprises a conductive contact hole layer and an interconnection layer in order from bottom to top, wherein the interconnection layer simultaneously connects the substrate and the device layer through the conductive contact hole layer, wherein the device layer comprises a plurality of semiconductor devices; stripping the interconnection layer and exposing the conductive contact hole layer; punching holes in the conductive contact hole layer to form a detection through hole, wherein the detection through hole is located outside the semiconductor device to be tested, and the detection through hole exposes the substrate. The present invention prepares a detection through hole by punching holes in the device layer, wherein the detection through hole exposes the substrate, so that the substrate can be directly powered by the detection through hole during a nanoprobe test, thereby solving the problem that the conductive contact hole cannot withstand a large current and causes the chip sample to burn, thereby improving the success rate of the electrical test and reducing the difficulty of the electrical test. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a schematic diagram of the structure of a power chip sample.
[0027] Figure 2 A schematic diagram of a process for preparing a chip sample provided in one embodiment of the present invention.
[0028] Figure 3 A schematic structural diagram of a chip sample provided in one embodiment of the present invention.
[0029] Figure 4 A schematic diagram of a flow chart of a method for electrical testing of a chip sample provided by an embodiment of the present invention.
[0030] Description of reference numerals:
[0031] Figure 1 Middle: 10, 20-conductive contact holes;
[0032] Figure 3In the figure: 100 - silicon substrate; 101 - epitaxial layer; 102 - buried layer; 103 - well region; 110 - body region; 120 - source region; 130 - drain region; 200 - gate structure; 301 - detection through hole; 310 - bottom dielectric layer; 321 - first conductive contact hole; 322 - second conductive contact hole; 323 - third conductive contact hole; 324 - fourth conductive contact hole; 325 - fifth conductive contact hole. DETAILED DESCRIPTION
[0033] The following will further describe in detail a method for preparing a chip sample and an electrical testing method of the present invention. The present invention will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.
[0034] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.
[0035] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0036] like Figure 1 As shown, the current method for preparing a power chip sample is as follows: providing a power chip sample, wherein the power chip sample has a front side and a back side arranged oppositely, an NMOS device is arranged on the front side, and performing a layer removal process on the power chip sample from the front side to expose a conductive contact hole layer connected to the NMOS device, thereby completing the production of the power chip sample. The conductive contact hole layer includes a conductive contact hole layer 10 connected to the substrate and a conductive contact hole layer 20 connected to the source, drain, gate and body region of the NMOS device.
[0037] The current power chip samples need to be powered on the substrate Nsub during electrical testing and use, especially during nanoprobe testing, where the electrical connection between the test equipment and the substrate Nsub is achieved through the nanoprobe contacting the conductive contact hole 10. Since the overcurrent capacity of the nanoprobe and the conductive contact hole is limited, the power chip samples are often burned when the expected results are not seen during the nanoprobe test because the conductive contact hole cannot withstand the large current, resulting in electrical test failure, which increases the difficulty of electrical testing.
[0038] In order to solve the above problems, the back side of the substrate can be connected to the test through a nanoprobe. However, since the device-level electrical test requires the power chip sample to be fixed on the carrier, the back side of the power chip sample is set towards the carrier, and the electrical connection cannot be performed directly on the carrier surface. Therefore, it is necessary to transfer the substrate from the back side to the front side of the power chip sample through copper tape to complete the electrical connection. During the transfer process, the impedance of the copper tape itself and the connection impedance between the copper tape and the back side will be divided, especially when the connection between the copper tape and the back side is unstable, it will be divided in a large proportion, which will cause a large error in the test results.
[0039] Therefore, if Figure 2 As shown, this embodiment provides a method for preparing a chip sample, comprising the following steps:
[0040] Step S11: providing a chip sample to be processed, wherein the chip sample comprises a substrate, a device layer and an interconnection structure layer, wherein the device layer is arranged on one side of the substrate, the interconnection structure layer is located on the substrate and the device layer, and comprises a conductive contact hole layer and an interconnection layer in sequence from bottom to top, wherein the interconnection layer simultaneously connects the substrate and the device layer through the conductive contact hole layer, wherein the device layer comprises a plurality of semiconductor devices;
[0041] Step S12: stripping off the interconnection layer and exposing the conductive contact hole layer;
[0042] Step S13: drilling a hole in the conductive contact hole layer to form a detection through hole, wherein the detection through hole is located outside the semiconductor device to be tested, and the detection through hole exposes the substrate.
[0043] In this embodiment, a detection through hole is prepared by drilling in the device layer, and the detection through hole exposes the substrate, so that power can be directly supplied to the substrate through the detection through hole during electrical testing. This solves the problem of chip sample burning due to the conductive contact hole being unable to withstand large current, improves the success rate of electrical testing, and reduces the difficulty of electrical testing.
[0044] The following combination Figure 3 A method for preparing a chip sample provided in this embodiment is described in detail.
[0045] First, step S11 is performed to provide a chip sample to be processed, wherein the chip sample to be processed includes a substrate, a device layer and an interconnection structure layer, wherein the device layer is arranged on one side of the substrate, and the interconnection structure layer is located on the substrate and the device layer, and includes a conductive contact hole layer and an interconnection layer from bottom to top, wherein the interconnection layer connects the substrate and the device layer through the conductive contact hole layer, wherein the device layer includes a plurality of semiconductor devices.
[0046] The chip sample may be a power chip sample, and further, the chip sample may be a chip sample of an intelligent power switch platform. The device layer includes a plurality of semiconductor devices, and all of the semiconductor devices are arranged on one side of the substrate.
[0047] The substrate includes a silicon substrate 100 and an epitaxial layer 101 from bottom to top, a portion of the device layer is located in the epitaxial layer 101, and the remaining portion is located on the epitaxial layer 101. The substrate and the epitaxial layer are both doped with N-type ions, that is, the semiconductor device here is any semiconductor device prepared on a substrate and an epitaxial layer doped with N-type ions (i.e., an N-type substrate and an N-type epitaxial layer). The semiconductor device is, for example, at least one of an SGT process device (e.g., an SGTMOSFET transistor) or a BCD process device (e.g., a low-voltage CMOS tube, a high-voltage MOS tube, an LDMOS, a vertical NPN tube, a vertical PNP tube, a lateral PNP tube, a Schottky diode, a well resistor, a polycrystalline resistor, and a metal resistor.
[0048] The conductive contact hole layer includes a bottom dielectric layer 310 and a plurality of conductive contact holes embedded in the dielectric layer, and the bottom dielectric layer 310 covers the epitaxial layer 101 and all the semiconductor devices. These conductive contact holes are used to lead out the connection ports of all the semiconductor devices and the epitaxial layer 101 of the substrate. The interconnection structure layer leads out the connection ports of all the semiconductor devices to the surface of the chip sample through the conductive contact hole layer, and leads out the epitaxial layer 101 of the substrate to the surface of the chip sample.
[0049] like Figure 3As shown, the device layer includes an NMOS transistor as an example for explanation. At this time, a buried layer 102 is provided in the epitaxial layer 101. The buried layer 102 is in a cylindrical structure. A well region 103 is formed inside the buried layer 102, and a body region 110, a source region 120 and a drain region 130 are formed in the well region 103. The source region 120 is located between the body region 110 and the drain region 130. A gate structure 200 is provided on the surface of the epitaxial layer 101. The gate structure 200 is located between the source region 120 and the drain region 130, and covers part of the source region 120 and part of the drain region 130. The bottom dielectric layer 310 covers the gate structure 200, the epitaxial layer 101 outside the buried layer 102, the well region 103 between the gate structure 200 and the opening edge of the buried layer 102, the body region 110, and the remaining source region 120 and the drain region 130. The buried layer 102 , the well region 103 and the body region 110 are all doped with P-type ions, and the epitaxial layer 101 , the source region 120 and the drain region 130 are all doped with N-type ions.
[0050] The conductive contact hole layer includes a first conductive contact hole 321, a second conductive contact hole 322, a third conductive contact hole 323, a fourth conductive contact hole 324 and a fifth conductive contact hole 325, wherein one end of the first conductive contact hole 321 contacts the epitaxial layer 101 outside the buried layer 102 to realize substrate power supply during nanoprobe testing; one end of the second conductive contact hole 322 contacts the body region 110, one end of the third conductive contact hole 323 contacts the source region 120, one end of the fourth conductive contact hole 324 contacts the gate structure 200, one end of the fifth conductive contact hole 325 contacts the drain region 130, and the bottom dielectric layer exposes the other ends of the first conductive contact hole 321, the second conductive contact hole 322, the third conductive contact hole 323, the fourth conductive contact hole 324 and the fifth conductive contact hole 325.
[0051] The interconnection layer includes a top dielectric layer and an interconnection metal layer, wherein the interconnection metal layer is embedded in the top cutoff layer, and the top dielectric layer exposes two ends of the interconnection metal layer, one end of which is connected to each conductive contact hole in the conductive contact hole layer, and the other end is used to connect to a semiconductor device or an external circuit.
[0052] Then, step S12 is performed to strip the interconnection layer and expose the conductive contact hole layer. In detail, the chip sample is subjected to a layer stripping process by conventional operations such as a wet etching process, a dry etching process, and a grinding process to strip the interconnection layer of the interconnection structure layer and expose the conductive contact hole layer of the interconnection structure layer. This step completes the preliminary processing of the chip sample, and when the chip sample after this step is completed is subjected to a nanoprobe test, the substrate is powered through the conductive contact hole, and the conductive contact hole cannot withstand the large current, causing the chip sample to burn, resulting in the failure of the nanoprobe test, thereby increasing the difficulty of electrical testing.
[0053] Then, step S13 is performed to drill a hole in the conductive contact hole layer to form a detection through hole 301 . The detection through hole 301 is located outside the semiconductor device to be tested, and the detection through hole 301 exposes the substrate.
[0054] This step specifically includes:
[0055] First, at least one target semiconductor device is selected from all the semiconductor devices, and the target semiconductor device needs to supply power to the substrate during the nanoprobe test.
[0056] Next, a hole drilling position is marked by laser at a preset distance from each of the target semiconductor devices.
[0057] Next, at the drilling position, the bottom dielectric layer 310 is drilled by laser to form a detection through hole. In detail, at the drilling position, the bottom dielectric layer 310 is bombarded at least once by laser, and after each bombardment, a single probe short circuit test to ground is performed. When the probe detection voltage is 0 to 0.1V (i.e., when it exhibits a short circuit characteristic), the bombardment is stopped and the detection through hole 301 is formed. At this time, the detection through hole 301 exposes the substrate (i.e., the epitaxial layer or silicon substrate).
[0058] In this embodiment, the detection through hole 301 may expose the surface of the epitaxial layer 101 , may expose a portion of the depth of the epitaxial layer 101 , or may penetrate the epitaxial layer 101 and expose the surface of the silicon substrate 100 .
[0059] The detection through hole 301 can be set in the area outside the device isolation area (such as the buried layer 102 in this embodiment) of the corresponding target semiconductor device, for example, in the spacing area between the corresponding target semiconductor device and other nearby semiconductor devices, or in a non-target semiconductor device near the corresponding target semiconductor device, so that during the nanoprobe test, the detection through hole 301 and all target semiconductor devices (especially the corresponding target semiconductor device) will not interfere with each other.
[0060] The detection through hole 301 formed in this embodiment can be powered separately by the substrate on the front side of the chip sample through the probe during the nanoprobe test. Since the probe can directly act on the detection through hole 301, the substrate is not powered directly through the conductive contact hole. In this way, when encountering some longitudinal parasitic structures, there is no need to worry about excessive current causing the chip sample to burn and affecting the test results, thereby reducing the test difficulty and test cost while improving the test success rate.
[0061] like Figure 4 As shown, this embodiment also provides a method for testing the electrical properties of a chip sample, comprising the following steps:
[0062] Step S21: providing a chip sample, wherein the chip sample is prepared by the above chip sample preparation method;
[0063] Step S22: the substrate is connected to a power supply voltage, and a nanoprobe test is performed on the target semiconductor device, wherein during the nanoprobe test, the probe is connected to the substrate by directly contacting the detection through hole.
[0064] In step S22, during the nano test, the first probe is directly contacted with the detection through hole 301 to measure the power supply of the substrate, and the second probes are respectively contacted with the conductive contact holes connected to the ports of the target semiconductor device. At this time, the first probe and the second probe are both nanoprobes made of tungsten material to improve the overcurrent capability of the nanoprobe.
[0065] In this step, the nanoprobe test can measure the leakage current value, threshold voltage, saturation current, and other test items of the NMOS transistor that require power supply to the substrate.
[0066] In summary, the present invention provides a method for preparing a chip sample and an electrical testing method, the method for preparing a chip sample comprising the following steps: providing a chip sample to be processed, the chip sample comprising a substrate, a device layer and an interconnection structure layer, the device layer being arranged on one side of the substrate, the interconnection structure layer being located on the substrate and the device layer, and comprising a conductive contact hole layer and an interconnection layer from bottom to top, the interconnection layer simultaneously connecting the substrate and the device layer through the conductive contact hole layer, wherein the device layer comprises a plurality of semiconductor devices; stripping the interconnection layer and exposing the conductive contact hole layer; punching holes in the conductive contact hole layer to form a detection through hole, the detection through hole being located outside the semiconductor device to be tested, and the detection through hole exposing the substrate. The present invention prepares a detection through hole by punching holes in the device layer, the detection through hole exposing the substrate, so that the substrate can be directly powered by the detection through hole during the nanoprobe test, thus solving the problem of the chip sample being burned due to the conductive contact hole being unable to withstand a large current, improving the success rate of the electrical test, and reducing the difficulty of the electrical test.
[0067] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0068] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for preparing a chip sample, characterized in that: The following steps are involved: Providing a chip sample to be processed, the chip sample comprising a substrate, a device layer and an interconnection structure layer, wherein the device layer is arranged on one side of the substrate, the interconnection structure layer is located on the substrate and the device layer, and comprises a conductive contact hole layer and an interconnection layer in sequence from bottom to top, the interconnection layer simultaneously connects the substrate and the device layer through the conductive contact hole layer, wherein the device layer comprises a plurality of semiconductor devices; Stripping the interconnection layer and exposing the conductive contact hole layer; A hole is punched in the conductive contact hole layer to form a detection through hole, wherein the detection through hole is located outside the semiconductor device to be tested and the substrate is exposed through the detection through hole.
2. The method for preparing a chip sample according to claim 1, characterized in that: The conductive contact hole layer includes a bottom dielectric layer and a plurality of conductive contact holes embedded in the dielectric layer.
3. The method for preparing a chip sample according to claim 2, characterized in that: The specific method of forming the detection through hole is: Selecting at least one target semiconductor device from among all the semiconductor devices; marking a drilling position by laser at a preset distance from each of the target semiconductor devices; At the punching position, the bottom dielectric layer is punched by laser to form a detection through hole.
4. The method for preparing a chip sample according to claim 3, characterized in that: The detailed steps for drilling holes in the bottom dielectric layer are: At the drilling position, the bottom dielectric layer is bombarded at least once by laser, and after each bombardment, a single probe short circuit test to ground is performed. When the probe detection voltage is 0-0.1V, the bombardment is stopped and a detection through hole is formed.
5. The method for preparing a chip sample according to claim 1, characterized in that: The substrate comprises a silicon substrate and an epitaxial layer in order from bottom to top, a portion of the device layer is located in the epitaxial layer, and the remaining portion is located on the epitaxial layer.
6. The method for preparing a chip sample according to claim 5, characterized in that: The detection through hole exposes the surface of the epitaxial layer; or exposes a partial depth of the epitaxial layer; or penetrates the epitaxial layer and exposes the surface of the silicon substrate.
7. The method for preparing a chip sample according to claim 5, characterized in that: The substrate and the epitaxial layer are both doped with N-type ions.
8. The method for preparing a chip sample according to claim 1, characterized in that: The chip sample is a chip sample of an intelligent power switch platform.
9. A method for testing the electrical properties of a chip sample, characterized in that: The following steps are involved: Providing a chip sample, wherein the chip sample is prepared by the chip sample preparation method according to any one of claims 1 to 8; The substrate is connected to a power supply voltage, and a nanoprobe test is performed on the target semiconductor device, wherein during the nanoprobe test, the probe is connected to the substrate by directly contacting the detection through hole.
10. The electrical property testing method of a chip sample according to claim 9, characterized in that: During nanometer testing, the detection through hole is directly contacted by a first probe, and corresponding conductive contact holes in the conductive contact hole layer are contacted by a plurality of second probes.