Radar target echo simulation implementation system and method supporting slice forwarding

Abstract

The invention belongs to the technical field of radar target echo simulation, and particularly discloses a radar target echo simulation implementation system and method supporting slice forwarding, and the system comprises a radio frequency down-conversion module, an analog-to-digital converter, a field programmable gate array, a digital-to-analog converter and a radio frequency up-conversion module. Wherein the radio frequency down-conversion module is used for converting an input radio frequency analog signal into an analog intermediate frequency signal which can be processed by the analog-to-digital converter; the analog-to-digital converter is used for converting an analog intermediate-frequency signal into a digital intermediate-frequency signal by using eight paths of output; the field programmable gate array is used for storing the digital intermediate frequency signal, changing 0 delay, power and Doppler frequency of the digital intermediate frequency signal according to a slice forwarding mode and then sending the signal; the digital-to-analog converter is used for converting eight paths of digital intermediate-frequency signals into intermediate-frequency analog signals; and the radio frequency up-conversion module is used for converting the intermediate frequency analog signal into a radio frequency analog signal to be output.

Description

Technical Field

[0001] The present invention belongs to the technical field of radar target echo simulation, and in particular relates to a radar target echo simulation implementation system and method supporting slice forwarding. Background Art

[0002] Radar target echo simulation is a technology that stores radar signals, adds corresponding delays, changes Doppler frequency and amplitude, and forwards them. It was created due to the need for radar debugging and testing, and has been greatly developed with the emergence of technologies such as field programmable gate array (FPGA), digital radio frequency memory (DRFM), and direct frequency generation (DDS). Many existing radar system signals use radar signals with large time widths. When performing air-fed radar target echo simulation, such signals need to generate dense multi-target signals, which makes it impossible for the radar to correctly measure target parameter information. Therefore, it is urgent to propose a radar target echo simulation implementation system and method that supports slice forwarding to solve the above technical problems. Summary of the invention

[0003] The present invention provides a radar target echo simulation implementation system and method supporting slice forwarding, which is used to solve the problem that the existing radar system signal adopts a radar signal with a large time width, and when performing air-fed radar target echo simulation, dense multi-target signals are generated, so that the radar cannot correctly measure target parameter information.

[0004] In a first aspect, a radar target echo simulation implementation system supporting slice forwarding is provided, the system comprising:

[0005] RF down-conversion module, analog-to-digital converter, field programmable gate array, digital-to-analog converter and RF up-conversion module; wherein,

[0006] The RF down-conversion module is used to convert the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter;

[0007] The analog-to-digital converter is used to convert the analog intermediate frequency signal into a digital intermediate frequency signal using 8 outputs;

[0008] The field programmable gate array is used to store the digital intermediate frequency signal, and send out the signal after changing the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode;

[0009] The digital-to-analog converter is used to convert 8-channel digital intermediate frequency signals into intermediate frequency analog signals;

[0010] The radio frequency up-conversion module is used to convert the intermediate frequency analog signal into a radio frequency analog signal to be output.

[0011] In a second aspect, a method for implementing radar target echo simulation supporting slice forwarding is provided, the method comprising:

[0012] The RF down-conversion module converts the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter;

[0013] The analog-to-digital converter uses 8 outputs to convert the analog intermediate frequency signal into a digital intermediate frequency signal;

[0014] The field programmable gate array stores the digital intermediate frequency signal, and sends the signal after changing the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode;

[0015] The digital-to-analog converter converts 8-channel digital intermediate frequency signals into intermediate frequency analog signals;

[0016] The radio frequency up-conversion module converts the intermediate frequency analog signal into a radio frequency analog signal to be output.

[0017] The embodiment of the present invention provides a radar target echo simulation implementation system and method supporting slice forwarding, which realizes forwarding slice interference on the basis of a radar target echo simulator by utilizing leading edge forwarding, trailing edge forwarding, full pulse forwarding, accumulated slice forwarding and other technologies in the digital modulation stage, while taking into account the characteristics of low resource consumption rate and integration.

[0018] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 A schematic diagram of the structure of a radar target echo simulation implementation system supporting slice forwarding provided according to an embodiment of the present invention;

[0021] Figure 2 A principle block diagram of a field programmable gate array provided according to an embodiment of the present invention;

[0022] Figure 3 A principle block diagram of a power digital down-conversion module provided according to an embodiment of the present invention;

[0023] Figure 4 A principle block diagram of a modulation module provided according to an embodiment of the present invention;

[0024] Figure 5 It is a principle block diagram of a slice forwarding module provided according to an embodiment of the present invention;

[0025] Figure 6 A principle block diagram of a forwarding module provided according to an embodiment of the present invention;

[0026] Figure 7 A principle block diagram of a delay modulation module provided according to an embodiment of the present invention;

[0027] Figure 8 A principle block diagram of a power modulation module provided according to an embodiment of the present invention;

[0028] Fig. 9 A principle block diagram of a Doppler modulation module provided according to an embodiment of the present invention;

[0029] Fig.10 A principle block diagram of a power digital up-conversion module provided according to an embodiment of the present invention;

[0030] Fig.11 A schematic diagram of an implementation flow of a radar target echo simulation method supporting slice forwarding provided according to an embodiment of the present invention;

[0031] Reference numerals:

[0032] 1. RF down-conversion module 2. Analog-to-digital converter 3. Field programmable gate array

[0033] 4. Digital-to-analog converter 5. RF up-conversion module 6. Digital down-conversion module

[0034] 7. Modulation module 8. Digital up-conversion module 9. Digital down-conversion DDS module

[0035] 10. Digital down-conversion multiplier 1 module 11. Digital down-conversion multiplier 2 module

[0036] 12. Digital down-conversion extraction filter module 13. Modulation slice forwarding module 14. Modulation delay modulation module

[0037] 15. Modulation power modulation module 16. Modulation Doppler modulation module

[0038] 17. Slice forwarding pulse width period acquisition module 18. Detection processing module 19. Slice forwarding module

[0039] 20. Forwarding enable control module 21. Forwarding memory module 22. Forwarding accumulator 1 module

[0040] 23. Forwarding accumulator 2 module 24. Forwarding accumulator 3 module

[0041] 25. Delay modulation accumulator module 26. Delay modulation memory module

[0042] 27. Delay modulation adder module 28. Power modulation multiplier module

[0043] 29. Power modulation quantization module 30. Doppler modulation noise generation module

[0044] 31. Doppler modulation DDS module 32. Doppler modulation multiplier 1 module

[0045] 33. Doppler modulation multiplier 2 module 34. Doppler modulation low pass filter module

[0046] 35. Digital up-conversion DDS module 36. Digital up-conversion interpolation filter module

[0047] 37. Digital up-conversion multiplier module 38. Digital up-conversion subtractor module. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0050] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0051] In order to improve the radar's ability to accurately detect targets, an embodiment of the present invention provides a radar target echo simulation implementation system and method that supports slice forwarding.

[0052] Figure 1 FIG. 1 is a schematic diagram of a radar target echo simulation implementation system supporting slice forwarding according to an embodiment of the present invention. Figure 1 , the system comprising:

[0053] RF down-conversion module 1, analog-to-digital converter 2, field programmable gate array 3, digital-to-analog converter 4 and RF up-conversion module 5; wherein,

[0054] The RF down-conversion module 1 is used to convert the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter 2;

[0055] The analog-to-digital converter 2 is used to convert the analog intermediate frequency signal into a digital intermediate frequency signal using 8 outputs;

[0056] The field programmable gate array 3 is used to store the digital intermediate frequency signal, and send out the signal after changing the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode;

[0057] The digital-to-analog converter 4 is used to convert 8-channel digital intermediate frequency signals into intermediate frequency analog signals;

[0058] The radio frequency up-conversion module 5 is used to convert the intermediate frequency analog signal into a radio frequency analog signal to be output.

[0059] In a specific embodiment,

[0060] The field programmable gate array 3 includes a digital down-conversion module 6, a modulation module 7 and a digital up-conversion module 8; wherein,

[0061] The digital down-conversion module 6 is used to convert the digital intermediate frequency signal into a baseband signal;

[0062] The modulation module 7 is used to store the baseband signal, and perform leading edge forwarding, trailing edge forwarding, full pulse forwarding, and accumulated slice forwarding processing on the large time width signal of the baseband signal, increase the amplitude of the output signal, adjust the phase, and perform Doppler modulation before sending it out;

[0063] The digital up-conversion module 8 is used to convert the modulated baseband signal into an intermediate frequency output signal.

[0064] In a specific embodiment,

[0065] The digital down-conversion module 6 includes a down-conversion DDS module 9, a down-conversion multiplier 1 module 10, a down-conversion multiplier 2 module 11, and a down-conversion extraction filter module 12; wherein,

[0066] The down-conversion DDS module 9 is used to generate 8-channel IQ orthogonal mixing signals;

[0067] The down-conversion multiplier 1 module 10 is used to multiply the 8 I-channel mixed signals with the 8-channel digital intermediate frequency signals respectively to obtain 8 I-channel mixed signals;

[0068] The down-conversion multiplier 2 module 11 is used to multiply 8 Q-channel mixed signals with 8 digital intermediate frequency signals respectively to obtain 8 Q-channel mixed signals;

[0069] The down-conversion extraction filter module 12 is used to perform low-pass filtering on the 8 IQ mixed signals to remove high-frequency non-target signals, and then perform signal extraction to reduce the sampling rate to obtain 4 groups of IQ two-way signals.

[0070] In a specific embodiment,

[0071] The modulation module 7 includes a slice forwarding module 13, a delay modulation module 14, a power modulation module 15 and a Doppler modulation module 16; wherein,

[0072] The slice forwarding module 13 is used to obtain the pulse width period information and detection signals of the four groups of IQ two-way signals, and then perform leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding processing;

[0073] The delay modulation module 14 is used to perform corresponding signal delay according to each delay data;

[0074] The power modulation module 15 is used to adjust the signal power according to the set amplitude;

[0075] The Doppler modulation module 16 is used to control the change of the Doppler frequency according to the noise data controlled by the host computer.

[0076] In a specific embodiment,

[0077] The slice forwarding module 13 includes a detection pulse width period acquisition module 17, a detection processing module 18 and a forwarding module 19; wherein,

[0078] The detection pulse width period acquisition module 17 is used to perform power timing processing on the four groups of IQ two-way signals to obtain pulse width period data;

[0079] The detection processing module 18 is used to obtain the detection signal, the detection rising edge signal and the detection falling edge signal;

[0080] The forwarding module 19 is used to forward the input signal according to the detection signal, including leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding;

[0081] The forwarding module 19 includes an enabling control module 20, a memory module 21, an accumulator module 1 (22), an accumulator module 2 (23) and an accumulator module 3 (24);

[0082] The forwarding module 19 implements the front edge forwarding, specifically including: the enabling control module 20 gives a write enable signal when detecting the rising edge signal, so that the memory module 21 writes data, the accumulator module 1 (22) accumulates the write address, and stops accumulating after a certain period of time, and the accumulator module 2 (23) accumulates the read address, so that the memory module 21 outputs the front edge forwarding signal;

[0083] The forwarding module 19 implements trailing edge forwarding, specifically including: the enabling control module 20 gives a write enable signal when the detection signal is pulled high, so that the memory module 21 writes data, the accumulator module 1 (22) accumulates the write address, stops accumulating at the falling edge of the detection signal to complete the data storage, and after a certain period of time, the accumulator module 2 (23) accumulates the read address, so that the memory module 21 outputs a trailing edge forwarding signal;

[0084] The forwarding module 19 implements full pulse forwarding, specifically including: the enabling control module 20 gives a write enable signal when the detection signal is pulled high, so that the memory module 21 writes data, the accumulator module 1 (22) accumulates the write address, and stops accumulating after a certain period of time, and the accumulator module 2 (23) accumulates the read address, so that the memory module 21 outputs a full pulse forwarding signal;

[0085] The forwarding module 19 implements the cumulative slice forwarding, specifically including: the enable control module 20 gives a write enable signal when the detection signal is pulled high, so that the memory module 21 writes data, the accumulator module 1 (22) accumulates the write address, and stops accumulating after a certain period of time, and the accumulator module 2 (23) accumulates the read address, so that the memory module 21 outputs a signal that enters the accumulator module 3 (24), and the accumulated result is sent to the write signal of the memory module 21. After the signal accumulation is completed, it enters the accumulator module 2 (23) to accumulate the read address, so that the memory module 21 outputs the cumulative slice forwarding signal.

[0086] In a specific embodiment,

[0087] The delay modulation module 14 includes an accumulator module 25, a memory module 26 and an adder module 27, wherein:

[0088] The accumulator module 25 is used to generate a write data address for the memory module 26;

[0089] The adder module 27 is used to add each delay data to the write data address to obtain the read data address;

[0090] The memory module 26 is used to use the detection signal as a write data enable signal, store the input signal according to the write data address, and obtain the delayed output signal according to the read data address.

[0091] In a specific embodiment,

[0092] The power modulation module 15 includes a multiplier module 28 and a quantization module 29; wherein,

[0093] The multiplier module 28 is used to multiply the 16-channel amplitude data with the 16-channel delayed output signals respectively;

[0094] The quantization module 29 is used to quantize the power of the 16 multiplied signals into a power signal that can be received by a digital-to-analog converter.

[0095] In a specific embodiment,

[0096] The Doppler modulation module 16 includes a noise generation module 30, a DDS module 31, a multiplier 1 module 32, a multiplier 2 module 33 and a low-pass filter module 34; wherein,

[0097] The noise generating module 30 is used to generate corresponding noise according to the data sent by the host computer;

[0098] The DDS module 31 is used to generate orthogonal mixing signals of different frequencies according to the noise data to achieve frequency shift interference;

[0099] The multiplier 1 module 32 is used to multiply the input signal I with the signal I generated by the DDS module;

[0100] The multiplier 2 module 33 is used to multiply the input signal Q path with the Q path signal generated by the DDS module, and filter out high-frequency components through a low-pass filter.

[0101] In a specific embodiment,

[0102] The digital up-conversion module 8 includes a digital up-conversion DDS module 35, a digital up-conversion interpolation filter module 36, a digital up-conversion multiplier module 37 and a digital up-conversion subtractor module 38; wherein,

[0103] The digital up-conversion DDS module 35 is used to generate 8-channel orthogonal mixing signals;

[0104] The digital up-conversion interpolation filter module 36 is used to interpolate the input 4-channel IQ signals to obtain 8-channel IQ baseband signals, and then perform low-pass filtering to filter out high-frequency non-target signals;

[0105] The digital up-conversion multiplier module 37 is used to multiply the 8-way orthogonal mixing signal with the 8-way IQ baseband signal respectively, and then pass through the digital up-conversion subtractor module 38 to obtain the intermediate frequency target signal.

[0106] The present invention provides a radar target echo simulation implementation system supporting slice forwarding. In the signal modulation stage of radar target echo simulation, leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding are used to implement slice forwarding interference. The system has been applied to a radar interference simulation system. After testing, the working bandwidth can reach 2GHz-18GHz, the instantaneous bandwidth can reach 1GHz, the number of scattering points can reach 16, and the slice forwarding interference effect can meet the task requirements, effectively simulate the echo information of the real target, and improve the radar's accurate detection capability of the target.

[0107] Based on the same inventive concept, the present invention also provides a radar target echo simulation implementation method supporting slice forwarding, see Fig.11 , the method comprising:

[0108] S1100: The RF down-conversion module converts the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter;

[0109] S1102: The analog-to-digital converter converts the analog intermediate frequency signal into a digital intermediate frequency signal using 8 outputs;

[0110] S1104: The field programmable gate array stores the digital intermediate frequency signal, changes the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode, and then sends the signal;

[0111] S1106: The digital-to-analog converter converts the 8-channel digital intermediate frequency signals into intermediate frequency analog signals;

[0112] S1108: The RF up-conversion module converts the intermediate frequency analog signal into a RF analog signal to be output.

[0113] In a specific embodiment,

[0114] The field programmable gate array includes a digital down-conversion module, a modulation module and a digital up-conversion module; wherein,

[0115] The digital down-conversion module is used to convert the digital intermediate frequency signal into a baseband signal;

[0116] The modulation module is used to store the baseband signal, and perform leading edge forwarding, trailing edge forwarding, full pulse forwarding, and accumulated slice forwarding processing on the large time width signal of the baseband signal, increase the amplitude of the output signal, adjust the phase, and perform Doppler modulation before sending it out;

[0117] The digital up-conversion module is used to convert the modulated baseband signal into an intermediate frequency output signal.

[0118] In a specific embodiment,

[0119] The digital down-conversion module includes a down-conversion DDS module, a down-conversion multiplier 1 module, a down-conversion multiplier 2 module, and a down-conversion decimation filter module; wherein,

[0120] The down-conversion DDS module is used to generate 8-channel IQ orthogonal mixing signals;

[0121] The down-conversion multiplier 1 module is used to multiply the 8 I-channel mixed signals with the 8-channel digital intermediate frequency signals respectively to obtain 8 I-channel mixed signals;

[0122] The down-conversion multiplier 2 module is used to multiply the 8 Q-channel mixed signals with the 8-channel digital intermediate frequency signals respectively to obtain 8 Q-channel mixed signals;

[0123] The down-conversion extraction filter module is used to perform low-pass filtering on the 8 IQ mixed signals to remove high-frequency non-target signals, and then perform signal extraction to reduce the sampling rate to obtain 4 groups of IQ two-way signals.

[0124] In a specific embodiment,

[0125] The modulation module includes a slice forwarding module, a delay modulation module, a power modulation module and a Doppler modulation module; wherein,

[0126] The slice forwarding module is used to obtain the pulse width period information and detection signals of the four groups of IQ two-way signals, and then perform leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding processing;

[0127] The delay modulation module is used to perform corresponding signal delay according to each delay data;

[0128] The power modulation module is used to adjust the signal power according to the set amplitude;

[0129] The Doppler modulation module is used to control the change of the Doppler frequency according to the noise data controlled by the host computer.

[0130] In a specific embodiment,

[0131] The slice forwarding module includes a detection pulse width period acquisition module, a detection processing module and a forwarding module; wherein,

[0132] The detection pulse width period acquisition module is used to perform power timing processing on the four groups of IQ two-way signals to obtain pulse width period data;

[0133] The detection processing module is used to obtain the detection signal, the detection rising edge signal and the detection falling edge signal;

[0134] The forwarding module is used to forward the input signal according to the detection signal, including leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding;

[0135] The forwarding module includes an enabling control module, a memory module, an accumulator module 1, an accumulator module 2 and an accumulator module 3;

[0136] The forwarding module implements front-end forwarding, specifically including: the enabling control module gives a write enable signal when detecting the rising edge signal, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs a front-end forwarding signal;

[0137] The forwarding module implements trailing edge forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating at the falling edge of the detection signal to complete the data storage, and after a certain period of time, the accumulator module 2 accumulates the read address, so that the memory module outputs a trailing edge forwarding signal;

[0138] The forwarding module realizes full pulse forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs a full pulse forwarding signal;

[0139] The forwarding module realizes the cumulative slice forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs the signal into the accumulator module 3, and the accumulated result is sent to the write signal of the memory module. After the signal accumulation is completed, it enters the accumulator module 2 for read address accumulation, so that the memory module outputs the cumulative slice forwarding signal.

[0140] In a specific embodiment,

[0141] The delay modulation module includes an accumulator module, a memory module and an adder module, wherein:

[0142] The accumulator module is used to generate a write data address of the memory module;

[0143] The adder module is used to add each delay data to the write data address to obtain the read data address;

[0144] The memory module is used to use the detection signal as a write data enable signal, store the input signal according to the write data address, and obtain the delayed output signal according to the read data address.

[0145] In a specific embodiment,

[0146] The power modulation module includes a multiplier module and a quantization module; wherein,

[0147] The multiplier module is used to multiply the 16-channel amplitude data with the 16-channel delayed output signals respectively;

[0148] The quantization module is used to quantize the power of the 16 multiplied signals into a power signal that can be received by the digital-to-analog converter.

[0149] In a specific embodiment,

[0150] The Doppler modulation module includes a noise generation module, a DDS module, a multiplier 1 module, a multiplier 2 module and a low-pass filter module; wherein,

[0151] The noise generating module is used to generate corresponding noise according to the data sent by the host computer;

[0152] The DDS module is used to generate orthogonal mixing signals of different frequencies according to the noise data to achieve frequency shift interference;

[0153] The multiplier 1 module is used to multiply the input signal I with the signal I generated by the DDS module;

[0154] The multiplier 2 module is used to multiply the input signal Q path with the Q path signal generated by the DDS module, and filter out high-frequency components through a low-pass filter.

[0155] In a specific embodiment,

[0156] The digital up-conversion module includes a digital up-conversion DDS module, a digital up-conversion interpolation filter module, a digital up-conversion multiplier module and a digital up-conversion subtractor module; wherein,

[0157] The digital up-conversion DDS module is used to generate 8-channel orthogonal mixing signals;

[0158] The digital up-conversion interpolation filter module is used to interpolate the input 4-channel IQ signals to obtain 8-channel IQ baseband signals, and then perform low-pass filtering to filter out high-frequency non-target signals;

[0159] The digital up-conversion multiplier module is used to multiply 8-way orthogonal mixing signals with 8-way IQ baseband signals respectively, and then pass through the digital up-conversion subtractor module to obtain an intermediate frequency target signal.

[0160] The present invention provides a radar target echo simulation implementation method supporting slice forwarding. In the signal modulation stage of radar target echo simulation, leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding are used to implement slice forwarding interference. The method has been applied to a radar interference simulation system. After testing, the working bandwidth can reach 2GHz-18GHz, the instantaneous bandwidth can reach 1GHz, the number of scattering points can reach 16, and the slice forwarding interference effect can meet the task requirements, effectively simulate the echo information of the real target, and improve the radar's accurate detection capability of the target.

[0161] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0162] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A radar target echo simulation implementation system supporting slice forwarding, characterized in that: The system comprises: RF down-conversion module, analog-to-digital converter, field programmable gate array, digital-to-analog converter and RF up-conversion module; wherein, The RF down-conversion module is used to convert the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter; The analog-to-digital converter is used to convert the analog intermediate frequency signal into a digital intermediate frequency signal using 8 outputs; The field programmable gate array is used to store the digital intermediate frequency signal, and send out the signal after changing the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode; The digital-to-analog converter is used to convert 8-channel digital intermediate frequency signals into intermediate frequency analog signals; The radio frequency up-conversion module is used to convert the intermediate frequency analog signal into a radio frequency analog signal to be output.

2. The system according to claim 1, characterized in that The field programmable gate array includes a digital down-conversion module, a modulation module and a digital up-conversion module; wherein, The digital down-conversion module is used to convert the digital intermediate frequency signal into a baseband signal; The modulation module is used to store the baseband signal, and perform leading edge forwarding, trailing edge forwarding, full pulse forwarding, and accumulated slice forwarding processing on the large time width signal of the baseband signal, increase the amplitude of the output signal, adjust the phase, and perform Doppler modulation before sending it out; The digital up-conversion module is used to convert the modulated baseband signal into an intermediate frequency output signal.

3. The system according to claim 2, characterized in that The digital down-conversion module includes a down-conversion DDS module, a down-conversion multiplier 1 module, a down-conversion multiplier 2 module, and a down-conversion decimation filter module; wherein, The down-conversion DDS module is used to generate 8-channel IQ orthogonal mixing signals; The down-conversion multiplier 1 module is used to multiply the 8 I-channel mixed signals with the 8-channel digital intermediate frequency signals respectively to obtain 8 I-channel mixed signals; The down-conversion multiplier 2 module is used to multiply the 8 Q-channel mixed signals with the 8-channel digital intermediate frequency signals respectively to obtain 8 Q-channel mixed signals; The down-conversion extraction filter module is used to perform low-pass filtering on the 8 IQ mixed signals to remove high-frequency non-target signals, and then perform signal extraction to reduce the sampling rate to obtain 4 groups of IQ two-way signals.

4. The system according to claim 3, characterized in that The modulation module includes a slice forwarding module, a delay modulation module, a power modulation module and a Doppler modulation module; wherein, The slice forwarding module is used to obtain the pulse width period information and detection signals of the four groups of IQ two-way signals, and then perform leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding processing; The delay modulation module is used to perform corresponding signal delay according to each delay data; The power modulation module is used to adjust the signal power according to the set amplitude; The Doppler modulation module is used to control the change of the Doppler frequency according to the noise data controlled by the host computer.

5. The system according to claim 4, characterized in that The slice forwarding module includes a detection pulse width period acquisition module, a detection processing module and a forwarding module; wherein, The detection pulse width period acquisition module is used to perform power timing processing on the four groups of IQ two-way signals to obtain pulse width period data; The detection processing module is used to obtain the detection signal, the detection rising edge signal and the detection falling edge signal; The forwarding module is used to forward the input signal according to the detection signal, including leading edge forwarding, trailing edge forwarding, full pulse forwarding and accumulated slice forwarding; The forwarding module includes an enabling control module, a memory module, an accumulator module 1, an accumulator module 2 and an accumulator module 3; The forwarding module implements front-end forwarding, specifically including: the enabling control module gives a write enable signal when detecting the rising edge signal, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs a front-end forwarding signal; The forwarding module implements trailing edge forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating at the falling edge of the detection signal to complete the data storage, and after a certain period of time, the accumulator module 2 accumulates the read address, so that the memory module outputs a trailing edge forwarding signal; The forwarding module realizes full pulse forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs a full pulse forwarding signal; The forwarding module realizes the cumulative slice forwarding, specifically including: the enable control module gives a write enable signal when the detection signal is pulled high, so that the memory module writes data, the accumulator module 1 accumulates the write address, stops accumulating after a certain period of time, and the accumulator module 2 accumulates the read address, so that the memory module outputs the signal into the accumulator module 3, and the accumulated result is sent to the write signal of the memory module. After the signal accumulation is completed, it enters the accumulator module 2 for read address accumulation, so that the memory module outputs the cumulative slice forwarding signal.

6. The system according to claim 5, characterized in that The delay modulation module includes an accumulator module, a memory module and an adder module, wherein: The accumulator module is used to generate a write data address of the memory module; The adder module is used to add each delay data to the write data address to obtain the read data address; The memory module is used to use the detection signal as a write data enable signal, store the input signal according to the write data address, and obtain the delayed output signal according to the read data address.

7. The system according to claim 6, characterized in that The power modulation module includes a multiplier module and a quantization module; wherein, The multiplier module is used to multiply the 16-channel amplitude data with the 16-channel delayed output signals respectively; The quantization module is used to quantize the power of the 16 multiplied signals into a power signal that can be received by the digital-to-analog converter.

8. The system according to claim 7, characterized in that The Doppler modulation module includes a noise generation module, a DDS module, a multiplier 1 module, a multiplier 2 module and a low-pass filter module; wherein, The noise generating module is used to generate corresponding noise according to the data sent by the host computer; The DDS module is used to generate orthogonal mixing signals of different frequencies according to the noise data to achieve frequency shift interference; The multiplier 1 module is used to multiply the input signal I with the signal I generated by the DDS module; The multiplier 2 module is used to multiply the input signal Q path with the Q path signal generated by the DDS module, and filter out high-frequency components through a low-pass filter.

9. The system according to claim 8, characterized in that The digital up-conversion module includes a digital up-conversion DDS module, a digital up-conversion interpolation filter module, a digital up-conversion multiplier module and a digital up-conversion subtractor module; wherein, The digital up-conversion DDS module is used to generate 8-channel orthogonal mixing signals; The digital up-conversion interpolation filter module is used to interpolate the input 4-channel IQ signals to obtain 8-channel IQ baseband signals, and then perform low-pass filtering to filter out high-frequency non-target signals; The digital up-conversion multiplier module is used to multiply 8-way orthogonal mixing signals with 8-way IQ baseband signals respectively, and then pass through the digital up-conversion subtractor module to obtain an intermediate frequency target signal.

10. A radar target echo simulation implementation method supporting slice forwarding, characterized in that: The radar target echo simulation implementation system supporting slice forwarding according to any one of claims 1 to 9, the method comprising: The RF down-conversion module converts the input RF analog signal into an analog intermediate frequency signal that can be processed by the analog-to-digital converter; The analog-to-digital converter uses 8 outputs to convert the analog intermediate frequency signal into a digital intermediate frequency signal; The field programmable gate array stores the digital intermediate frequency signal, and sends the signal after changing the zero delay, power and Doppler frequency of the digital intermediate frequency signal according to the slice forwarding mode; The digital-to-analog converter converts 8-channel digital intermediate frequency signals into intermediate frequency analog signals; The radio frequency up-conversion module converts the intermediate frequency analog signal into a radio frequency analog signal to be output.

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