Variable optical attenuator chip and manufacturing method thereof

Abstract

The invention provides a variable optical attenuator chip and a manufacturing method, the variable optical attenuator chip comprises a waveguide core layer and at least two temperature control electrode groups, the at least two temperature control electrode groups are arranged above and / or below the waveguide core layer, and all the temperature control electrode groups are in butt joint with an external PCB; the temperature control electrode group is used for applying voltage through an external PCB to generate heat, so that the temperature of the waveguide core layer is changed to realize corresponding optical power attenuation; by arranging the plurality of temperature control electrode groups, when fixed heat is output, the power consumption of a single temperature control electrode group is reduced, and the intrinsic temperature of the single temperature control electrode group is synchronously reduced, so that the creep deformation degree of each temperature control electrode group is slowed down, and the service life of the whole device is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technology, and in particular to an adjustable optical attenuator chip and a manufacturing method thereof. Background Art

[0002] Planar optical waveguide variable optical attenuator has the advantages of simple production, good stability, small size, low cost, easy integration, and suitability for large-scale production. With the development and maturity of technology, it has become one of the most critical optical devices in optical communication systems.

[0003] At present, planar optical waveguide type variable optical attenuators are usually based on silicon-based silica technology and adopt a Mach-Zehnder interferometer structure, that is, a waveguide core layer is used to implement it. A heating electrode is arranged above the waveguide core layer. A voltage is applied to the heating electrode to make the heating electrode heat up, and the heat is transferred to the waveguide core layer and the optical power is attenuated through the thermo-optical effect of the waveguide.

[0004] The existing heating electrode 2' is as follows Figure 1 and Figure 2 As shown, it is usually a long strip of metal film with a certain thickness, and is only arranged above the waveguide core layer 1'. However, since the thermal expansion coefficient of the heating electrode 2' is much larger than that of the upper cladding layer 3' above the waveguide core layer 1', when the operating temperature rises, the heating electrode 2' will be subjected to external stress from the upper cladding layer 3'. Under the long-term effect of the stress, the heating electrode 2' will slowly creep. Among them, temperature is another important factor affecting the creep process of the heating electrode 2'. The higher the intrinsic temperature of the heating electrode 2', the more obvious the creep phenomenon of the metal film of the heating electrode 2'. As the creep degree of the metal film of the heating electrode 2' gradually increases, the metal film will eventually break. In fact, during the creep process, the corresponding device may fail prematurely and end its service life.

[0005] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. Summary of the invention

[0006] The technical problem to be solved by the present invention is how to reduce the intrinsic temperature of the heating electrode in the adjustable optical attenuator under the premise of satisfying the fixed heat, so as to reduce the creep phenomenon of the metal film of the heating electrode.

[0007] The present invention adopts the following technical solution:

[0008] In a first aspect, a variable optical attenuator chip is provided, comprising: a waveguide core layer 1 and at least two temperature-controlled electrode groups 2, wherein:

[0009] At least two temperature control electrode groups 2 are arranged above and / or below the waveguide core layer 1, and all the temperature control electrode groups 2 are connected to the external PCB board;

[0010] The temperature control electrode group 2 is used to apply voltage through an external PCB board to generate heat, thereby changing the temperature of the waveguide core layer 1 to achieve corresponding optical power attenuation.

[0011] Preferably, when at least two temperature control electrode groups 2 are arranged above the waveguide core layer 1 and at least two temperature control electrode groups 2 are arranged below the waveguide core layer 1, the at least two temperature control electrode groups 2 above the waveguide core layer 1 are connected in parallel with the at least two temperature control electrode groups 2 below the waveguide core layer 1.

[0012] Preferably, the at least two temperature control electrode groups 2 above the waveguide core layer 1 and the at least two temperature control electrode groups 2 below the waveguide core layer 1 are arranged symmetrically to each other.

[0013] Preferably, the temperature control electrode group 2 includes a heating electrode 21 and a wire electrode 22, and the heating electrode 21 is connected to an external PCB board through the wire electrode 22;

[0014] The wire electrode 22 is used to transmit the current of the PCB board to the heating electrode 21 . The heating electrode 21 is used to generate heat according to the applied voltage and transfer the heat to the waveguide core layer 1 .

[0015] Preferably, the heating electrode 21 includes an arc-shaped sub-electrode 211 and at least two strip-shaped sub-electrodes 212, wherein:

[0016] The at least two strip-shaped sub-electrodes 212 are respectively disposed at two ends of the arc-shaped sub-electrode 211 ; the width of the arc-shaped sub-electrode 211 is greater than the width of the strip-shaped sub-electrode 212 .

[0017] Preferably, the adjustable optical attenuator chip further comprises: an upper cladding layer 3, a lower cladding layer 4 and a substrate 5, wherein:

[0018] The upper cladding layer 3 is arranged above the waveguide core layer 1, the lower cladding layer 4 is arranged below the waveguide core layer 1, and the substrate 5 is arranged below the lower cladding layer 4;

[0019] The at least two temperature-controlled electrode groups 2 are arranged in the upper cladding 3 and / or the lower cladding 4 .

[0020] Preferably, the waveguide core layer 1 comprises: an input optical waveguide 11, an up-modulation optical waveguide 12, a down-modulation optical waveguide 13 and an output optical waveguide 14, wherein:

[0021] The input optical waveguide 11 is connected to the up-modulation optical waveguide 12 and the down-modulation optical waveguide 13 respectively, and the up-modulation optical waveguide 12 and the down-modulation optical waveguide 13 are both connected to the output optical waveguide 14;

[0022] At least two temperature-controlled electrode groups 2 are disposed above and / or below the upper modulation optical waveguide 12 ; at least two temperature-controlled electrode groups 2 are disposed above and / or below the lower modulation optical waveguide 13 .

[0023] In a second aspect, a method for manufacturing an adjustable optical attenuator chip is provided, and is used to manufacture the adjustable optical attenuator chip, comprising:

[0024] The number a of the temperature control electrode groups 2 below the waveguide core layer 1 and the number b of the temperature control electrode groups 2 above the waveguide core layer 1 are set, wherein a+b≥2;

[0025] Depositing a first lower cladding layer 41 on the substrate 5;

[0026] When a is greater than or equal to 1, a lower temperature control layer 6 is prepared on the first lower cladding layer 41 to deposit a layer of lower temperature control layer 6 on the first lower cladding layer 41; when a is less than 1, a second lower cladding layer 42 is deposited on the first lower cladding layer 41;

[0027] Depositing the waveguide core layer 1 on the uppermost lower temperature control layer 6 or the second lower cladding layer 42;

[0028] When b is greater than or equal to 1, a first upper cladding layer 31 is deposited on the waveguide core layer 1, and b upper temperature control layers 7 are prepared on the first upper cladding layer 31 to deposit b upper temperature control layers 7 on the waveguide core layer 1; when b is less than 1, a first upper cladding layer 31 is deposited on the waveguide core layer 1;

[0029] An anti-oxidation protection layer is deposited on the upper temperature control layer 7 or the first upper cladding layer 31 .

[0030] Preferably, when a is greater than or equal to 1, a lower temperature control layer 6 is prepared on the first lower cladding layer 41 to deposit a layer of lower temperature control layer 6 on the first lower cladding layer 41, specifically including:

[0031] When a is 1, a wire electrode 22 and a heating electrode 21 are deposited on the first lower cladding layer 41, and then a third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21 to prepare a lower temperature control layer 6;

[0032] When a is greater than 1, a wire electrode 22 and a heating electrode 21 are deposited on the first lower cladding layer 41, and then a third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21 to prepare a first lower temperature control layer 6; the preparation of the second lower temperature control layer 6 to the ath lower temperature control layer 6 is to deposit the wire electrode 22 and the heating electrode 21 on the third lower cladding layer 43 of the previous lower temperature control layer 6, and then the third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21.

[0033] Preferably, when b is greater than or equal to 1, a first upper cladding layer 31 is deposited on the waveguide core layer 1, and b upper temperature control layers 7 are prepared on the first upper cladding layer 31 to deposit b upper temperature control layers 7 on the waveguide core layer 1, specifically comprising:

[0034] When b is 1, a wire electrode 22 and a heating electrode 21 are deposited on the first upper cladding layer 31, and then a second upper cladding layer 32 is deposited on the wire electrode 22 and the heating electrode 21 to prepare an upper temperature control layer 7;

[0035] When b is greater than 1, a wire electrode 22 and a heating electrode 21 are deposited on the first upper cladding layer 31, and then a second upper cladding layer 32 is precipitated on the wire electrode 22 and the heating electrode 21 to prepare the first upper temperature control layer 7; the preparation of the second upper temperature control layer 7 to the bth upper temperature control layer 7 is to deposit the wire electrode 22 and the heating electrode on the second upper cladding layer 32 in the previous upper temperature control layer 7, and then deposit the second upper cladding layer 32 on the wire electrode 22 and the heating electrode.

[0036] The present invention provides an adjustable optical attenuator chip and a manufacturing method, comprising: a waveguide core layer 1 and at least two temperature-controlled electrode groups 2, wherein: at least two temperature-controlled electrode groups 2 are arranged above and / or below the waveguide core layer 1, and all the temperature-controlled electrode groups 2 are connected to an external PCB board; the temperature-controlled electrode group 2 is used to apply voltage through the external PCB board to generate heat, thereby changing the temperature of the waveguide core layer 1 to achieve corresponding optical power attenuation; by arranging multiple temperature-controlled electrode groups 2, when outputting fixed heat, the power consumption of a single temperature-controlled electrode group 2 is reduced, and the intrinsic temperature of a single temperature-controlled electrode group 2 is synchronously reduced, thereby slowing down the degree of creep of each temperature-controlled electrode group 2, and extending the life of the entire device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a structural schematic diagram of an existing adjustable optical attenuator chip provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of another existing adjustable optical attenuator chip provided by an embodiment of the present invention;

[0040] Figure 3 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0041] Figure 4 is a schematic structural diagram of another adjustable optical attenuator chip provided by an embodiment of the present invention;

[0042] Figure 5 is a schematic diagram of a waveguide core layer in an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0043] Figure 6 is a schematic diagram of a heating electrode in an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0044] Figure 7 It is a method flow chart of a method for manufacturing an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0045] Figure 8 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0046] Fig. 9 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0047] Fig.10 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0048] Fig.11 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0049] Fig.12 It is a structural schematic diagram of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0050] Fig.13 It is a schematic diagram of a manufacturing process of an adjustable optical attenuator chip provided by an embodiment of the present invention;

[0051] The diagram numbers are as follows:

[0052] Waveguide core layer 1'; heating electrode 2'; upper cladding layer 3'; lower cladding layer 4';

[0053] Waveguide core layer 1; input optical waveguide 11; upper modulation optical waveguide 12; lower modulation optical waveguide 13; output optical waveguide 14; temperature control electrode group 2; heating electrode 21; arc sub-electrode 211; strip sub-electrode 212; wire electrode 22; upper cladding 3; first upper cladding 31; second upper cladding 32; lower cladding 4; first lower cladding 41; second lower cladding 42; third lower cladding 43; substrate 5; lower temperature control layer 6; upper temperature control layer 7. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0055] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0056] In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" is two or more. In addition, for example, the same type of nouns may be described as two independent individuals by adding "A" and "B" at the end. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the same type of individuals for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity, i.e., the limitations of the measurement system.

[0058] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0059] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0060] Embodiment 1:

[0061] Embodiment 1 of the present invention provides an adjustable optical attenuator chip, such as Figure 3 As shown, it includes: a waveguide core layer 1, at least two temperature control electrode groups 2, wherein:

[0062] At least two temperature control electrode groups 2 are arranged above and / or below the waveguide core layer 1, and all the temperature control electrode groups 2 are connected to the external PCB board; the temperature control electrode group 2 is used to apply voltage through the external PCB board to generate heat, thereby changing the temperature of the waveguide core layer 1 to achieve corresponding optical power attenuation.

[0063] like Figure 3 and Figure 4 As shown, the waveguide core layer 1 includes an adjustable optical attenuator optical path for realizing the basic functions of the adjustable attenuator. The temperature control electrode group 2 includes a wire electrode 22 and a heating electrode 21. The heating electrode 21 is connected to an external PCB board through the wire electrode 22. The PCB board provides a corresponding voltage to the heating electrode 21 to regulate the temperature of the heating electrode 21. The heat is transferred to the waveguide core layer 1 through the heating electrode 21. The waveguide core layer 1 realizes the attenuation of optical power through the thermo-optical effect.

[0064] Since the heating electrode 21 is usually made of a metal film deposited on the waveguide core layer 1, the metal film usually creeps due to the influence of temperature. Generally, the higher the temperature, the more serious the creep of the metal film. The metal film may eventually break under long-term creep deformation, and the metal film will also greatly affect the life of the heating electrode 21 when it creeps. When it is necessary to generate fixed heat, if there is only one heating electrode 21, the power required by the heating electrode 21 is large, the temperature of the heating electrode 21 will also be high, the corresponding creep degree is greater, and the life is relatively shorter; if there are more than two heating electrodes 21, the power required by a single heating electrode 21 will be greatly reduced. Therefore, in this embodiment, the adjustable optical attenuator chip is provided with at least two temperature control electrode groups 2 to reduce the power required by each heating electrode 21. When the power consumption of a single heating electrode 21 decreases, the intrinsic temperature of the single heating electrode 21 will decrease synchronously, thereby slowing down the degree of creep of each heating electrode 21 and extending the life of the entire device.

[0065] Furthermore, in this embodiment, the optical path of the adjustable optical attenuator in the waveguide core layer 1 needs to realize the corresponding adjustable optical attenuation function, so the optical path of the adjustable optical attenuator includes the following design:

[0066] like Figure 5 As shown, the waveguide core layer 1 includes: an input optical waveguide 11, an upper modulation optical waveguide 12, a lower modulation optical waveguide 13 and an output optical waveguide 14, wherein: the input optical waveguide 11 is connected to the upper modulation optical waveguide 12 and the lower modulation optical waveguide 13 respectively, and the upper modulation optical waveguide 12 and the lower modulation optical waveguide 13 are both connected to the output optical waveguide 14; at least two temperature control electrode groups 2 are arranged above and / or below the upper modulation optical waveguide 12; at least two temperature control electrode groups 2 are arranged above and / or below the lower modulation optical waveguide 13.

[0067] At the same time, in order to meet the basic structure of the adjustable optical attenuator chip, the adjustable optical attenuator chip also includes: an upper cladding 3, a lower cladding 4 and a substrate 5, wherein: the upper cladding 3 is located above the waveguide core layer 1, the lower cladding 4 is located below the waveguide core layer 1, and the substrate 5 is arranged below the lower cladding 4; the at least two heating electrodes 21 are arranged in the upper cladding 3 and / or the lower cladding 4.

[0068] In this embodiment, the refractive index of the waveguide core layer 1 is slightly greater than the refractive index of the lower cladding layer 4 and the upper cladding layer 3, and the materials of the waveguide core layer 1, the lower cladding layer 4 and the upper cladding layer 3 can be the silicon dioxide material. The thickness of the upper cladding layer 3 and the lower cladding layer 4 can be more than three times the thickness of the waveguide core layer 1 to ensure that the optical signal is efficiently transmitted in the waveguide core layer 1, and the refractive index of the silicon dioxide in the upper cladding layer 3 is the same as the refractive index of the silicon dioxide in the lower cladding layer 4.

[0069] The heating electrode 21 may be a metal or alloy with a conductivity of 50nΩ·m to 500nΩ·m, and the wire electrode 22 may be a metal or alloy with a conductivity of 60% to 110%.

[0070] The heating electrode 21 can be made of one or any combination of titanium, tungsten, chromium and platinum; the wire electrode 22 can be made of one or any combination of gold, copper and aluminum.

[0071] An anti-oxidation protection layer is also deposited on the upper cladding layer 3. The material of the anti-oxidation protection layer may be silicon nitride or silicon dioxide to protect the heating electrode 21 and the wire electrode 22 from oxidation.

[0072] In this embodiment, the up-modulation optical waveguide 12 and the down-modulation optical waveguide 13 are respectively used as two modulation arms of the optical path of the adjustable optical attenuator. Next, the relationship between the power consumption of the heating electrode 21 and the number of the heating electrodes 21 is demonstrated as follows:

[0073] In this embodiment, in the optical path of the adjustable optical attenuator, the relationship between the modulation phase differences of the two modulation arms is:

[0074]

[0075] Among them, Δφ is the phase difference between the two modulation arms, and Transmission (P) is the transmission loss.

[0076] The Δφ is the modulation phase Δφ of all the heating electrodes 21 i The sum is:

[0077] Δφ=Δφ1+Δφ2+……+Δφ m ;

[0078] Among them, Δφ1 is the modulation phase of the first heating electrode 21, Δφ2 is the modulation phase of the second heating electrode 21, and Δφ m is the modulation phase of the mth heating electrode 21.

[0079] The modulation phase of a single heating electrode 21 satisfies the following relationship:

[0080]

[0081] Where, λ is the operating wavelength; To modulate the thermo-optic coefficient of the optical waveguide material, the thermo-optic coefficient of oxygen-silicon is determined by the waveguide material and can be 1.1×10 -5 K -1 ; L is the length of the heating electrode 21, and ΔTi is the temperature change of the waveguide core layer 1 caused by the heating of the heating electrode 21.

[0082] The ΔTi satisfies the following relationship:

[0083]

[0084] Where k is the temperature correlation coefficient, C p is the heat capacity of the modulated optical waveguide material, m is the mass of the modulated optical waveguide material, P i is the loading power consumption of a single heating electrode 21.

[0085] Through the above formula, we can get:

[0086]

[0087] It can be seen from the above formula that the phase difference Δφ between the two modulation arms is the sum of the modulation phases of each heating electrode 21 . When the length L of the heating electrode 21 remains unchanged, the phase difference is proportional to the total power consumption of all the heating electrodes 21 .

[0088] Therefore, when only one heating electrode 21 is working, the total power consumption required to load the phase difference Δφ of the two modulation arms is P, and the total power consumption is borne by the working heating electrode 21; when i heating electrodes 21 are working at the same time, the total power consumption required to load the phase difference Δφ of the two modulation arms is P = P1 + P2 + ... + P i , where for a single heating electrode 21, for example, the power consumption of the i-th heating electrode 21 is P i , obviously, P i <P, therefore, under the premise of generating the same total power consumption, if multiple heating electrodes 21 are set to work simultaneously, the power consumption of a single heating electrode 21 will be greatly reduced, and the intrinsic temperature of a single heating electrode 21 will also be lower. The following is the relationship between the creep of the metal film of the heating electrode 21 and the intrinsic temperature T:

[0089]

[0090] Where R(T) is the reaction rate at temperature T, A is the frequency factor, and E a is the activation energy, k is the Boltzmann constant, M is the device working state, and t is the lifetime of the device under normal operation.

[0091] Simplifying the above formula, we get:

[0092]

[0093] Among them, a is a constant, and the logarithm of the life span t is linearly related to the derivative of the temperature T. Therefore, it can be seen that the lower the temperature, the longer the life span.

[0094] Furthermore, in this embodiment, in order to ensure the stress balance and polarization coherence loss of the heating electrode 21 in the variable optical attenuator chip, the following designs are also involved:

[0095] When at least two temperature-controlled electrode groups 2 are disposed above the waveguide core layer 1, and at least two temperature-controlled electrode groups 2 are disposed below the waveguide core layer 1, the at least two temperature-controlled electrode groups 2 above the waveguide core layer 1 are connected in parallel with the at least two temperature-controlled electrode groups 2 below the waveguide core layer 1. Further, the at least two temperature-controlled electrode groups 2 above the waveguide core layer 1 and the at least two temperature-controlled electrode groups 2 below the waveguide core layer 1 are arranged symmetrically to each other.

[0096] In this embodiment, by arranging the same number of temperature control electrode groups 2 above and below the waveguide core layer 1 and symmetrically arranging them, the stress balance of the heating electrode 21 in the variable optical attenuator chip is ensured and excessive polarization coherence loss is avoided.

[0097] Furthermore, in addition to creep affecting the life of the metal film of the heating electrode 21, electromigration on the electrode is also one of the factors that restrict the life. Usually, due to the large power consumption of the heating electrode 21 and the micron-level width of the heating electrode 21, the cross-sectional area of ​​the heating electrode 21 is small, and the current density is large, electromigration will occur even at low temperatures. The median life of failure due to electromigration is inversely proportional to the current density and temperature. Therefore, the greater the current density, the shorter the electrode life. Therefore, in order to further improve the electrode life, it is necessary to reduce the current density. Therefore, this embodiment also involves the following designs:

[0098] like Figure 5 and Figure 6 As shown, the heating electrode 21 includes an arc-shaped sub-electrode 211 and at least two strip-shaped sub-electrodes 212, wherein: the at least two strip-shaped sub-electrodes 212 are respectively arranged at both ends of the arc-shaped sub-electrode 211; the width of the arc-shaped sub-electrode 211 is greater than the width of the strip-shaped sub-electrode 212. The maximum width of the arc-shaped sub-electrode 211 is 378±1um, and the length of the heating electrode 21 is 3000±1um.

[0099] Furthermore, the relationship between the current density in the heating electrode 21 and the life of the heating electrode 21 is demonstrated as follows:

[0100] Median lifetime to failure due to electromigration tMTF It can be expressed by the black equation as follows:

[0101]

[0102] The above formula can be further transformed into:

[0103]

[0104] Among them, A, p and q are empirical constants, W is the line width, L is the length, A dc is a constant related to line width, J is current density, m is a constant between 1 and 3, and E a is the activation energy, T is the electrode intrinsic temperature, and k is the Boltzmann constant.

[0105] It can be seen from the above formula that electromigration is related to current density and electrode intrinsic temperature. When the current density is smaller, the electromigration ability is weaker and the median life is longer.

[0106] In this embodiment, the heating electrode 21 is designed to be arc-shaped, thereby increasing the width of the heating electrode 21 and increasing the cross-sectional area of ​​the heating electrode 21, thereby reducing the current density, weakening the electromigration phenomenon, and extending the life of the electrode.

[0107] In this embodiment, if at least two temperature control electrode groups 2 are provided above and below the waveguide core layer 1, the process for manufacturing the temperature control electrode groups 2 is also the same to ensure that each temperature control electrode group 2 balances the stress on the waveguide core layer 1 during operation.

[0108] Embodiment 2:

[0109] Embodiment 2 of the present invention provides a method for manufacturing an adjustable optical attenuator chip based on embodiment 1, which is used to manufacture the adjustable optical attenuator chip described in embodiment 1. Figure 7 and Figure 8 As shown, including:

[0110] In step 101 , the number a of the temperature control electrode groups 2 below the waveguide core layer 1 and the number b of the temperature control electrode groups 2 above the waveguide core layer 1 are set, wherein a+b≥2.

[0111] In step 102 , a first lower cladding layer 41 is deposited on the substrate 5 .

[0112] It should be noted that, in order to clearly demonstrate the manufacturing process, the lower cladding layer 4 in Example 1 is divided into a first lower cladding layer 41, a second lower cladding layer 42 and a third lower cladding layer 43 for ease of description. The materials and manufacturing processes of the first lower cladding layer 41, the second lower cladding layer 42 and the third lower cladding layer 43 can be the same.

[0113] In step 103, when a is greater than or equal to 1, a lower temperature control layer 6 is prepared on the first lower cladding layer 41 to deposit a layer of lower temperature control layer 6 on the first lower cladding layer 41; when a is less than 1, a second lower cladding layer 42 is deposited on the first lower cladding layer 41.

[0114] Fig. 9 It is shown that at least one lower temperature control layer 6 is deposited on the first lower cladding layer 41; Fig.10 It is shown that the lower temperature control layer 6 is not deposited on the first lower cladding layer 41, but the second lower cladding layer 42 is directly produced.

[0115] The second lower cladding layer 42 is used to fill the layer between the first lower cladding layer 41 and the waveguide core layer 1 when the temperature control electrode group 2 is not provided in the lower cladding layer 4, so as to ensure the thickness of the whole chip.

[0116] The lower temperature control layer 6 is prepared specifically as follows: when a is 1, a wire electrode 22 and a heating electrode 21 are deposited on the first lower cladding layer 41 , and then a third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21 to prepare the lower temperature control layer 6 .

[0117] like Fig. 9 As shown, when a is greater than 1, a wire electrode 22 and a heating electrode 21 are deposited on the first lower cladding layer 41, and then a third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21 to prepare a first lower temperature control layer 6; the preparation of the second lower temperature control layer 6 to the ath lower temperature control layer 6 is to deposit the wire electrode 22 and the heating electrode 21 on the third lower cladding layer 43 of the previous lower temperature control layer 6, and then the third lower cladding layer 43 is deposited on the wire electrode 22 and the heating electrode 21.

[0118] Among them, the first lower cladding 41, the second lower cladding 42 and the third lower cladding 43 can be deposited by chemical vapor deposition, the wire electrode 22 and the heating electrode 21 can be deposited on the lower cladding 4 by physical vapor deposition, and the waveguide core layer 1 can be deposited on the second lower cladding 42 or the uppermost third lower cladding 43 by chemical vapor deposition.

[0119] In step 104 , a waveguide core layer 1 is deposited on the uppermost lower temperature control layer 6 or the second lower cladding layer 42 .

[0120] The optical path of the variable optical attenuator is formed on the waveguide core layer 1 by using reactive etching technology.

[0121] In step 105, when b is greater than or equal to 1, a first upper cladding layer 31 is deposited on the waveguide core layer 1, and b upper temperature control layers 7 are prepared on the first upper cladding layer 31 to deposit b upper temperature control layers 7 on the waveguide core layer 1; when b is less than 1, a first upper cladding layer 31 is deposited on the waveguide core layer 1.

[0122] Fig.11 It is shown that at least one upper temperature control layer 7 is deposited on the first upper cladding layer 31; Fig.12 It is shown that no temperature control layer 7 is deposited on the waveguide core layer 1, but only the first upper cladding layer 31 is produced.

[0123] It should be noted that, in order to clearly illustrate the manufacturing process, the upper cladding layer 3 in Example 1 is divided into a first upper cladding layer 31 and a second upper cladding layer 32 for ease of description. The materials and manufacturing processes of the first upper cladding layer 31 and the second upper cladding layer 32 can be the same.

[0124] The first upper cladding layer 31 is: when the temperature control electrode group 2 is not provided in the upper cladding layer 3, it is used to fill the layer above the waveguide core layer 1 to ensure the thickness of the entire chip.

[0125] The upper temperature control layer 7 is prepared specifically as follows: when b is 1, a wire electrode 22 and a heating electrode 21 are deposited on the first upper cladding layer 31 , and then a second upper cladding layer 32 is deposited on the wire electrode 22 and the heating electrode 21 to prepare the upper temperature control layer 7 .

[0126] like Fig.11 , when b is greater than 1, a wire electrode 22 and a heating electrode 21 are deposited on the first upper cladding layer 31, and then a second upper cladding layer 32 is deposited on the wire electrode 22 and the heating electrode 21 to prepare a first upper temperature control layer 7; the preparation of the second upper temperature control layer 7 to the bth upper temperature control layer 7 is to deposit a wire electrode 22 and a heating electrode on the second upper cladding layer 32 in the previous upper temperature control layer 7, and then deposit a second upper cladding layer 32 on the wire electrode 22 and the heating electrode.

[0127] The first upper cladding layer 31 and the second upper cladding layer 32 can be deposited by chemical vapor deposition, and the wire electrode 22 and the heating electrode 21 can be obtained by physical vapor deposition.

[0128] In step 106 , an anti-oxidation protection layer is deposited on the upper temperature control layer 7 or the first upper cladding layer 31 .

[0129] The anti-oxidation protection layer may be formed by a plasma chemical vapor deposition process, and then the wafer is processed by high temperature annealing and high pressure treatment, and finally the adjustable optical attenuator chip is manufactured by dicing the wafer.

[0130] Embodiment 3:

[0131] Based on the above embodiments, this embodiment provides an example of a manufacturing process of an adjustable optical attenuator chip. In this embodiment, all upper cladding layers are referred to as upper cladding layers 3, and all lower cladding layers are referred to as lower cladding layers 4, without any subdivision.

[0132] by Fig.13 Take the structure in as an example, Fig.13 Two temperature control electrode groups 2 are arranged above and below the middle waveguide core layer 1, and all temperature control electrode groups 2 are located on one side of the upper modulation optical waveguide 12. Fig.13 The steps for making the structure in are as follows:

[0133] First, a lower cladding layer 4 is deposited on the substrate 5 by chemical vapor deposition.

[0134] The wire electrode 22 and the heater electrode 21 are deposited on the lower cladding layer 4 by physical vapor deposition.

[0135] A lower cladding layer 4 is deposited on the wire electrode 22 and the heater electrode 21 by chemical vapor deposition.

[0136] The wire electrode 22 and the heater electrode 21 are deposited on the lower cladding layer 4 by physical vapor deposition.

[0137] A lower cladding layer 4 is deposited on the wire electrode 22 and the heater electrode 21 by chemical vapor deposition.

[0138] The waveguide core layer 1 is deposited on the lower cladding layer 4 by chemical vapor deposition, and the optical path of the adjustable optical attenuator is formed on the waveguide core layer 1 by reactive etching technology.

[0139] An upper cladding layer 3 is formed on the waveguide core layer 1 by chemical vapor deposition.

[0140] The wire electrode 22 and the heater electrode 21 are deposited on the upper cladding layer 3 by physical vapor deposition.

[0141] The upper cladding layer 3 is deposited on the wire electrode 22 and the heater electrode 21 by chemical vapor deposition.

[0142] The wire electrode 22 and the heater electrode 21 are deposited on the upper cladding layer 3 by physical vapor deposition.

[0143] The upper cladding layer 3 is deposited on the wire electrode 22 and the heating electrode 21 by chemical vapor deposition, and an anti-oxidation protection layer is deposited on the upper cladding layer 3 .

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An adjustable optical attenuator chip, characterized in that: include: A waveguide core layer (1) and at least two temperature control electrode groups (2), wherein: At least two temperature control electrode groups (2) are arranged above and / or below the waveguide core layer (1), and all the temperature control electrode groups (2) are connected to an external PCB board; The temperature control electrode group (2) is used to apply voltage through an external PCB board to generate heat, thereby changing the temperature of the waveguide core layer (1) to achieve corresponding optical power attenuation.

2. The adjustable optical attenuator chip according to claim 1, characterized in that: When at least two temperature control electrode groups (2) are arranged above the waveguide core layer (1) and at least two temperature control electrode groups (2) are arranged below the waveguide core layer (1), the at least two temperature control electrode groups (2) above the waveguide core layer (1) are connected in parallel with the at least two temperature control electrode groups (2) below the waveguide core layer (1).

3. The adjustable optical attenuator chip according to claim 2, characterized in that: The at least two temperature control electrode groups (2) above the waveguide core layer (1) and the at least two temperature control electrode groups (2) below the waveguide core layer (1) are arranged symmetrically to each other.

4. The adjustable optical attenuator chip according to claim 1, characterized in that: The temperature control electrode group (2) comprises a heating electrode (21) and a wire electrode (22), and the heating electrode (21) is connected to an external PCB board via the wire electrode (22); The wire electrode (22) is used to transmit the current of the PCB board to the heating electrode (21); the heating electrode (21) is used to generate heat according to the applied voltage and transfer the heat to the waveguide core layer (1).

5. The adjustable optical attenuator chip according to claim 4, characterized in that: The heating electrode (21) comprises an arc-shaped sub-electrode (211) and at least two strip-shaped sub-electrodes (212), wherein: The at least two strip-shaped sub-electrodes (212) are respectively arranged at two ends of the arc-shaped sub-electrode (211); and the width of the arc-shaped sub-electrode (211) is greater than the width of the strip-shaped sub-electrode (212).

6. The adjustable optical attenuator chip according to claim 1, characterized in that: The adjustable optical attenuator chip further comprises: an upper cladding layer (3), a lower cladding layer (4) and a substrate (5), wherein: The upper cladding layer (3) is arranged above the waveguide core layer (1), the lower cladding layer (4) is arranged below the waveguide core layer (1), and the substrate (5) is arranged below the lower cladding layer (4); The at least two temperature-controlled electrode groups (2) are arranged in the upper cladding (3) and / or the lower cladding (4).

7. The adjustable optical attenuator chip according to claim 1, characterized in that: The waveguide core layer (1) comprises: an input optical waveguide (11), an up-modulation optical waveguide (12), a down-modulation optical waveguide (13) and an output optical waveguide (14), wherein: The input optical waveguide (11) is connected to the up-modulation optical waveguide (12) and the down-modulation optical waveguide (13) respectively, and the up-modulation optical waveguide (12) and the down-modulation optical waveguide (13) are both connected to the output optical waveguide (14); At least two temperature control electrode groups (2) are arranged above and / or below the upper modulation optical waveguide (12); and at least two temperature control electrode groups (2) are arranged above and / or below the lower modulation optical waveguide (13).

8. A method for manufacturing an adjustable optical attenuator chip, used for manufacturing the adjustable optical attenuator chip as claimed in any one of claims 1 to 7, characterized in that: include: The number a of the temperature control electrode groups (2) below the waveguide core layer (1) and the number b of the temperature control electrode groups (2) above the waveguide core layer (1) are set, wherein a+b≥2; Depositing a first lower cladding layer (41) on the substrate (5); When a is greater than or equal to 1, a lower temperature control layer (6) is prepared on the first lower cladding layer (41) to deposit a layer of lower temperature control layer (6) on the first lower cladding layer (41); when a is less than 1, a second lower cladding layer (42) is deposited on the first lower cladding layer (41); Depositing a waveguide core layer (1) on the uppermost lower temperature control layer (6) or the second lower cladding layer (42); When b is greater than or equal to 1, a first upper cladding layer (31) is deposited on the waveguide core layer (1), and b upper temperature control layers (7) are prepared on the first upper cladding layer (31) to deposit b upper temperature control layers (7) on the waveguide core layer (1); when b is less than 1, a first upper cladding layer (31) is deposited on the waveguide core layer (1); An anti-oxidation protective layer is deposited on the upper temperature control layer (7) or the first upper cladding layer (31).

9. The method for manufacturing the variable optical attenuator chip according to claim 8, characterized in that: When a is greater than or equal to 1, a lower temperature control layer (6) is prepared on the first lower cladding layer (41) to deposit a layer of lower temperature control layer (6) on the first lower cladding layer (41), specifically comprising: When a is 1, a wire electrode (22) and a heating electrode (21) are deposited on the first lower cladding layer (41), and then a third lower cladding layer (43) is deposited on the wire electrode (22) and the heating electrode (21) to prepare a lower temperature control layer (6); When a is greater than 1, a wire electrode (22) and a heating electrode (21) are deposited on the first lower cladding layer (41), and then a third lower cladding layer (43) is deposited on the wire electrode (22) and the heating electrode (21) to prepare a first lower temperature control layer (6); the preparation of the second lower temperature control layer (6) to the ath lower temperature control layer (6) is to deposit a wire electrode (22) and a heating electrode (21) on the third lower cladding layer (43) of the previous lower temperature control layer (6), and then the third lower cladding layer (43) is deposited on the wire electrode (22) and the heating electrode (21).

10. The method for manufacturing the variable optical attenuator chip according to claim 8, characterized in that: When b is greater than or equal to 1, a first upper cladding layer (31) is deposited on the waveguide core layer (1), and b upper temperature control layers (7) are prepared on the first upper cladding layer (31) to deposit b upper temperature control layers (7) on the waveguide core layer (1), specifically comprising: When b is 1, a wire electrode (22) and a heating electrode (21) are deposited on the first upper cladding layer (31), and then a second upper cladding layer (32) is deposited on the wire electrode (22) and the heating electrode (21) to prepare an upper temperature control layer (7); When b is greater than 1, a wire electrode (22) and a heating electrode (21) are deposited on the first upper cladding layer (31), and then a second upper cladding layer (32) is deposited on the wire electrode (22) and the heating electrode (21) to prepare a first upper temperature control layer (7); the preparation of the second upper temperature control layer (7) to the bth upper temperature control layer (7) is to deposit a wire electrode (22) and a heating electrode on the second upper cladding layer (32) in the previous upper temperature control layer (7), and then deposit the second upper cladding layer (32) on the wire electrode (22) and the heating electrode.

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