Electronic device and manufacturing method thereof
By using a two-stage yellow light process in the manufacturing of electronic devices, the shape of the patterned photoresist layer is improved, and the problems of photoresist layer peeling and wire breaking are solved, which significantly improves the yield of the electronic device.
Patent Information
- Application Number
- CN202510015771.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-12
- Filing Date
- 2025-01-06
- Publication Date
- 2025-04-11
AI Technical Summary
In the existing electronic device manufacturing methods, it is difficult to avoid insufficient coverage of the photoresist layer at a specific position in a single yellow light process stage, resulting in wire breakage problems; and when two yellow light process stages are adopted, more complex processing patterns are prone to invasion and peeling of the photoresist layer by water vapor, reducing the integrity of the conductive layer.
Using a two-stage yellow light process, a first patterned photoresist layer is formed through a first mask, and a portion of the conductive layer is removed correspondingly to expose the insulating layer; then a second patterned photoresist layer is formed using a second mask, and portions of the insulating layer are exposed and removed to improve the shape of the photoresist layer and avoid peeling.
The problem of photoresist layer peeling and wire breakage is effectively avoided, and the yield of electronic devices is greatly improved.
Smart Images
Figure CN119805852A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to an electronic device and a manufacturing method thereof. Background Art
[0002] In the existing electronic device manufacturing method, only a single yellow light process stage is used to process the stacked structure, in which the wires may be broken because the coverage of the photoresist at some specific positions is low. Although the use of two yellow light process stages can solve the above problem, for more complex processing patterns, the patterned photoresist layer may be invaded by moisture and peeled off, reducing the integrity of the patterned conductive layer formed by the subsequent process, and ultimately causing wire breakage in the electronic device. Summary of the invention
[0003] The invention provides an electronic device and a manufacturing method thereof, which effectively avoids the problem of photoresist layer peeling during the process and improves the yield of the electronic device.
[0004] According to one embodiment of the present invention, an electronic device is provided, comprising a substrate, an insulating layer and a conductive layer stacked in sequence. The insulating layer comprises a first portion, a second portion and a third portion. The second portion is located on a side of the first portion away from the conductive layer, and the third portion is located on a side of the second portion away from the conductive layer. The first portion, the second portion and the third portion are continuously distributed. The top surface of the conductive layer away from the substrate is higher than the top surface of the insulating layer. The top surface of the first portion is higher than the top surface of the second portion, and the top surface of the third portion is higher than the top surface of the second portion.
[0005] According to another embodiment of the present invention, a method for manufacturing an electronic device is provided, including sequentially stacking an insulating layer and a conductive layer on a substrate; forming a first patterned photoresist layer using a first mask; removing a portion of the conductive layer to expose the insulating layer corresponding to the pattern of the first patterned photoresist layer; forming a second patterned photoresist layer using a second mask, wherein the second patterned photoresist layer exposes a portion of the insulating layer; and removing the portion of the insulating layer.
[0006] Based on the above, the method for manufacturing an electronic device provided by the embodiment of the present invention utilizes a two-stage yellow light process to manufacture the electronic device and improves the shape of the patterned photoresist layer to avoid the problem of photoresist layer peeling and wire breakage, thereby greatly improving the yield of the electronic device.
[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figures 1A to 1F A schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present invention is shown.
[0009] Figure 1G Show Figure 1A Schematic diagram of the mask in the photolithography process shown.
[0010] Figure 1H Show Figure 1D Schematic diagram of the mask in the photolithography process shown.
[0011] FIG. 2A to FIG. 2F A schematic diagram of a method for manufacturing an electronic device according to a comparative example is shown.
[0012] Figure 2G Show Figure 2A Schematic diagram of the mask in the photolithography process shown.
[0013] Figure 2H Show Figure 2D Schematic diagram of the mask in the photolithography process shown.
[0014] Description of reference numerals:
[0015] 1: Substrate
[0016] 10, 20, 30, 40: Mask
[0017] 10C, 20C, 20D, 30C, 40C, 40D: Pattern
[0018] 100: Insulation layer
[0019] 200, 200': Conductive layer
[0020] 300, 400: Patterned photoresist layer
[0021] 1000, 2000: Electronic devices
[0022] T1, T2, T3: Top surface DETAILED DESCRIPTION
[0023] Figures 1A to 1F A schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present invention is shown. Figures 1A to 1F Only a partial cross-sectional view during the manufacturing process is shown, wherein Figures 1A to 1C The steps shown are the first stage of yellow light process. Figures 1D to 1F The steps shown are the second stage yellow light process. Figure 1G Show Figure 1A Schematic diagram of the mask in the photolithography process shown. Figure 1A The section line AD is a straight line formed by the line segment AC, the line segment CE' and the line segment E'D. Figure 1G It is shown in Figure 1A The dashed line corresponding to the section line AD is marked on it. Figure 1AThe endpoints A, C, E' and D of the line segments correspond to positions a, c, e' and d respectively. Figure 1H Show Figure 1D Schematic diagram of the mask in the photolithography process shown. Figure 1D The section line AD is a straight line formed by the line segments AB, BC, CE' and E'D. Figure 1H It is shown in Figure 1D The dashed line corresponding to the section line AD is marked on it. Figure 1D The endpoints A, B, C, E' and D of the line segments correspond to the positions a, b, c, e' and d.
[0024] exist Figure 1A In the steps shown, an insulating layer 100 and a conductive layer 200 are sequentially stacked on a substrate 1, and a conductive layer 200 is formed by using Figure 1G The mask 10 shown is subjected to a photolithography process to form a patterned photoresist layer 300 corresponding to the pattern of the mask 10 on the conductive layer 200 , wherein the mask 10 includes a plurality of patterns 10C.
[0025] exist Figure 1B In the step shown, an etching process is performed, wherein the area on line segment AC is the etching area, corresponding to Figure 1G The pattern 10C shown is formed accordingly Figure 1C The patterned conductive layer 200 is shown. Figure 1C The patterned conductive layer 200 has Figure 1G The patterns 10C shown correspond to multiple patterns. It should be noted that although Figure 1G The patterns 10C are circular, but the present invention is not limited thereto. In some embodiments of the present invention, the patterns 10C do not have an angle less than or equal to 75 degrees.
[0026] exist Figure 1D In the steps shown, use Figure 1H The mask 20 shown is subjected to a photolithography process to form a patterned photoresist layer 400 corresponding to the pattern of the mask 20 on the insulating layer 100 and the patterned conductive layer 200. Figure 1E In the steps shown, an etching process is performed to produce Figure 1F The electronic device 1000 shown includes a substrate 1 , an insulating layer 100 , and a patterned conductive layer 200 ′.
[0027] Figure 1FThe patterned conductive layer 200' can be used as a conductive wire in the manufactured electronic device 1000, and its top surface away from the substrate 1 is higher than the top surface of the insulating layer 100 substrate 1. In addition, no conductive wire is set on the insulating layer 100 corresponding to the line segment CE', the line segment BC and the line segment AB, and can be used as a light transmission area in the manufactured electronic device 1000, but not limited to this. Through the above-mentioned process, the top surface T1 of the partial insulating layer 100 (first partial insulating layer) on the line segment CE' will be higher than the top surface T2 of the partial insulating layer 100 (second partial insulating layer) on the line segment BC relative to the substrate 1, and the top surface T3 of the partial insulating layer 100 (third partial insulating layer) on the line segment AB will be higher than the top surface T2 of the partial insulating layer 100 (second partial insulating layer) on the line segment BC relative to the substrate 1.
[0028] It should be noted that Figure 1H The mask 20 shown includes a pattern 20C and a pattern 20D, wherein the pattern 20C corresponds to Figure 1D as well as Figure 1E The patterned photoresist layer 400 is located on the insulating layer 100, and the pattern 20D corresponds to Figure 1D as well as Figure 1E The patterned photoresist layer 400 is located on the patterned conductive layer 200. By configuring the pattern 20C on the mask 20 to form the patterned photoresist layer 400 on the insulating layer 100, the product in the process can be prevented from adhering to the surface of the insulating layer 100, which is beneficial to improve the yield of subsequent processes.
[0029] It should also be noted that for the sake of ease of understanding, Figure 1H The pattern 10C of the mask 10 in the aforementioned process step is indicated by a dotted line. Therefore, it can be seen that the diameter of the pattern 20C of the mask 20 is smaller than the diameter of the pattern 10C of the mask 10. In addition, although Figure 1H The patterns 20C in the figure are circular, but the present invention is not limited thereto. In some embodiments of the present invention, the patterns 20C do not have an angle less than or equal to 75 degrees. In other words, Figure 1D In the illustrated step, there is no angle less than or equal to 75 degrees on the patterned photoresist layer 400 corresponding to the pattern 20C formed.
[0030] Please also refer to Figure 1E as well as Figure 1H Since the patterned photoresist layer 400 ( Figure 1E ) corresponds to pattern 20C ( Figure 1H ) and has a gap with the patterned conductive layer 200, wherein the gap corresponds to the line segment BC. Therefore, the top surface T2 of the portion of the insulating layer 100 (the second portion of the insulating layer) on the line segment BC is formed into a concave surface (such as Figure 1FIn addition, as mentioned above, the patterned conductive layer 200 has the same Figure 1G ) corresponding pattern, so in a top view, Figure 1F The top surface T2 shown will be formed to be Figure 1H The pattern 10C and the pattern 20C shown are annular patterns corresponding to each other. In other words, the vertical projection of the top surface T2 on the substrate 1 will form an annular pattern. The annular pattern includes a first contour corresponding to the pattern 20C and a second contour corresponding to the pattern 10C, the first contour is surrounded by the second contour, and there is no angle less than or equal to 75 degrees on the first contour and the second contour. In some embodiments, the first contour is conformal to the second contour, for example, both contours are circular, but not limited to this. In some embodiments, the first contour and the second contour may not be conformal, for example, one contour is circular and the other contour is hexagonal.
[0031] FIG. 2A to FIG. 2F A schematic diagram of a method for manufacturing an electronic device according to a comparative example is shown. Figure 2G Show Figure 2A Schematic diagram of the mask in the photolithography process shown. Figure 2A The section line AD is a straight line formed by the line segment AC, the line segment CE' and the line segment E'D. Figure 2G It is shown in Figure 2A The dashed line corresponding to the section line AD is marked on it. Figure 2A The endpoints A, C, E' and D of the line segments correspond to positions a, c, e' and d respectively. Figure 2H Show Figure 2D Schematic diagram of the mask in the photolithography process shown. Figure 2D The section line AD is a straight line formed by the line segments AB, BC, CE' and E'D. Figure 2H It is shown in Figure 2D The dashed line corresponding to the section line AD is marked on it. Figure 2D The endpoints A, B, C, E' and D of the line segments correspond to the positions a, b, c, e' and d.
[0032] exist Figure 2A In the steps shown, an insulating layer 100 and a conductive layer 200 are sequentially stacked on a substrate 1, and a conductive layer 200 is formed by using Figure 2G The mask 30 shown is subjected to a photolithography process to form a patterned photoresist layer 300 corresponding to the pattern of the mask 30 on the conductive layer 200 , wherein the mask 30 includes a plurality of patterns 30C.
[0033] exist Figure 2B In the step shown, an etching process is performed, wherein the area on line segment AE' is the etching area, corresponding to Figure 2GThe pattern 30C shown is formed accordingly Figure 2C The patterned conductive layer 200 is shown. Figure 2C The patterned conductive layer 200 has Figure 2G The patterns 30C shown correspond to multiple patterns. It should be noted that there are multiple angles less than or equal to 75 degrees on the patterns 30C, such as at position e'.
[0034] exist Figure 2D In the steps shown, use Figure 2H The mask 40 shown is subjected to a photolithography process to form a patterned photoresist layer 400 corresponding to the pattern of the mask 40 on the insulating layer 100 and the patterned conductive layer 200 . Figure 2H The mask 40 shown includes a pattern 40C and a pattern 40D, wherein the pattern 40C corresponds to Figure 2D as well as Figure 2E The patterned photoresist layer 400 is located on the insulating layer 100, and the pattern 40D corresponds to Figure 2D as well as Figure 2E The patterned photoresist layer 400 is located on the patterned conductive layer 200.
[0035] exist Figure 2E In the steps shown, an etching process is performed to produce Figure 2F The electronic device 2000 shown includes a substrate 1 , an insulating layer 100 , and a patterned conductive layer 200 ′, wherein the patterned conductive layer 200 ′ can be used as a conductive wire in the manufactured electronic device 2000 .
[0036] However, it should be noted that due to the pattern 30C (see Figure 2G ) at position e' there is an angle less than or equal to 75 degrees, Figure 2C The patterned conductive layer 200 formed in the step shown in FIG. 1 will have an obtuse angle corresponding to the above-mentioned angle. Further, when Figure 2D In the steps shown, a patterned photoresist layer 400 is formed. The patterned photoresist layer 400 forms a structure with an angle less than or equal to 75 degrees at the junction with the patterned conductive layer 200 (corresponding to the end point E'). In this way, the patterned photoresist layer 400 is difficult to adhere to at this location and is easily invaded by water vapor. In this case, the patterned photoresist layer 400 may be partially peeled off, which further affects the Figure 2F The integrity of the patterned conductive layer 200' formed in the steps shown in the figure is damaged, which eventually leads to the wire breakage in the electronic device 2000. Figures 1A to 1H In the embodiment shown, there is no structure on the patterns 10C and 20C having an angle less than or equal to 75 degrees, so that the problems of photoresist layer peeling and wire breakage in the comparative example can be avoided.
[0037] In summary, the method for manufacturing an electronic device provided by the embodiment of the present invention utilizes a two-stage yellow light process to manufacture the electronic device, improves the shape of the patterned photoresist layer to avoid the problem of photoresist layer peeling and wire breakage, and greatly improves the yield of the electronic device.
Claims
1. An electronic device comprising a substrate, an insulating layer and a conductive layer stacked in sequence, wherein The insulating layer includes a first portion, a second portion and a third portion, the second portion is located at a side of the first portion away from the conductive layer, the third portion is located at a side of the second portion away from the conductive layer, and the first portion, the second portion and the third portion are continuously distributed. The top surface of the conductive layer away from the substrate is higher than the top surface of the insulating layer, the top surface of the first portion is higher than the top surface of the second portion, and the top surface of the third portion is higher than the top surface of the second portion. 2 . The electronic device of claim 1 , wherein a vertical projection of the top surface of the second portion on the substrate is formed into a ring pattern. 3 . The electronic device as claimed in claim 2 , wherein the annular pattern comprises a first outline and a second outline, the first outline is surrounded by the second outline, and the first outline and the second outline are conformal. 4 . The electronic device as claimed in claim 2 , wherein the annular pattern comprises a first contour and a second contour, the first contour is surrounded by the second contour, and the first contour and the second contour are not conformal. 5 . The electronic device as claimed in claim 2 , wherein the annular pattern comprises a first outline and a second outline, the first outline is surrounded by the second outline, and there is no angle less than or equal to 75 degrees between the first outline and the second outline. 6 . The electronic device as claimed in claim 1 , wherein the conductive layer is not disposed on the first portion, the second portion, and the third portion.
7. A method for manufacturing an electronic device, comprising: stacking an insulating layer and a conductive layer in sequence on a substrate; forming a first patterned photoresist layer using a first mask; Corresponding to the pattern of the first patterned photoresist layer, removing a portion of the conductive layer to expose the insulating layer; forming a second patterned photoresist layer using a second mask, wherein the second patterned photoresist layer exposes a portion of the insulating layer; as well as The portion of the insulating layer is removed.
8. The method for manufacturing an electronic device according to claim 7, further comprising: A ring pattern is formed on a top surface of the insulating layer away from the substrate. 9 . The method for manufacturing an electronic device as claimed in claim 8 , wherein the annular pattern comprises a first contour and a second contour, the first contour is surrounded by the second contour, and there is no angle less than or equal to 75 degrees between the first contour and the second contour. 10 . The method for manufacturing an electronic device as claimed in claim 8 , wherein the annular pattern comprises a first contour and a second contour, the first contour is surrounded by the second contour, and the first contour and the second contour are conformal. 11 . The method for manufacturing an electronic device as claimed in claim 8 , wherein the annular pattern comprises a first contour and a second contour, the first contour is surrounded by the second contour, and the first contour and the second contour are not conformal.